1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /** 3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer 4 * 5 * Copyright (C) 2014 Chen-Zhi (Roger Chen) 6 * 7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> 8 */ 9 10 #include <linux/stmmac.h> 11 #include <linux/bitops.h> 12 #include <linux/clk.h> 13 #include <linux/phy.h> 14 #include <linux/of_net.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/delay.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/regmap.h> 22 #include <linux/pm_runtime.h> 23 24 #include "stmmac_platform.h" 25 26 struct rk_priv_data; 27 struct rk_gmac_ops { 28 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, 29 int tx_delay, int rx_delay); 30 void (*set_to_rmii)(struct rk_priv_data *bsp_priv); 31 void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed); 32 void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed); 33 void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, 34 bool enable); 35 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); 36 bool regs_valid; 37 u32 regs[]; 38 }; 39 40 static const char * const rk_clocks[] = { 41 "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed", 42 }; 43 44 static const char * const rk_rmii_clocks[] = { 45 "mac_clk_rx", "clk_mac_ref", "clk_mac_refout", 46 }; 47 48 enum rk_clocks_index { 49 RK_ACLK_MAC = 0, 50 RK_PCLK_MAC, 51 RK_MAC_CLK_TX, 52 RK_CLK_MAC_SPEED, 53 RK_MAC_CLK_RX, 54 RK_CLK_MAC_REF, 55 RK_CLK_MAC_REFOUT, 56 }; 57 58 struct rk_priv_data { 59 struct platform_device *pdev; 60 phy_interface_t phy_iface; 61 int id; 62 struct regulator *regulator; 63 bool suspended; 64 const struct rk_gmac_ops *ops; 65 66 bool clk_enabled; 67 bool clock_input; 68 bool integrated_phy; 69 70 struct clk_bulk_data *clks; 71 int num_clks; 72 struct clk *clk_mac; 73 struct clk *clk_phy; 74 75 struct reset_control *phy_reset; 76 77 int tx_delay; 78 int rx_delay; 79 80 struct regmap *grf; 81 struct regmap *php_grf; 82 }; 83 84 #define HIWORD_UPDATE(val, mask, shift) \ 85 ((val) << (shift) | (mask) << ((shift) + 16)) 86 87 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 88 #define GRF_CLR_BIT(nr) (BIT(nr+16)) 89 90 #define DELAY_ENABLE(soc, tx, rx) \ 91 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ 92 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) 93 94 #define PX30_GRF_GMAC_CON1 0x0904 95 96 /* PX30_GRF_GMAC_CON1 */ 97 #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 98 GRF_BIT(6)) 99 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2) 100 #define PX30_GMAC_SPEED_100M GRF_BIT(2) 101 102 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) 103 { 104 struct device *dev = &bsp_priv->pdev->dev; 105 106 if (IS_ERR(bsp_priv->grf)) { 107 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 108 return; 109 } 110 111 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 112 PX30_GMAC_PHY_INTF_SEL_RMII); 113 } 114 115 static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 116 { 117 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 118 struct device *dev = &bsp_priv->pdev->dev; 119 int ret; 120 121 if (!clk_mac_speed) { 122 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__); 123 return; 124 } 125 126 if (speed == 10) { 127 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 128 PX30_GMAC_SPEED_10M); 129 130 ret = clk_set_rate(clk_mac_speed, 2500000); 131 if (ret) 132 dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n", 133 __func__, ret); 134 } else if (speed == 100) { 135 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 136 PX30_GMAC_SPEED_100M); 137 138 ret = clk_set_rate(clk_mac_speed, 25000000); 139 if (ret) 140 dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n", 141 __func__, ret); 142 143 } else { 144 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 145 } 146 } 147 148 static const struct rk_gmac_ops px30_ops = { 149 .set_to_rmii = px30_set_to_rmii, 150 .set_rmii_speed = px30_set_rmii_speed, 151 }; 152 153 #define RK3128_GRF_MAC_CON0 0x0168 154 #define RK3128_GRF_MAC_CON1 0x016c 155 156 /* RK3128_GRF_MAC_CON0 */ 157 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 158 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 159 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 160 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 161 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 162 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 163 164 /* RK3128_GRF_MAC_CON1 */ 165 #define RK3128_GMAC_PHY_INTF_SEL_RGMII \ 166 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8)) 167 #define RK3128_GMAC_PHY_INTF_SEL_RMII \ 168 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8)) 169 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9) 170 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 171 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10) 172 #define RK3128_GMAC_SPEED_100M GRF_BIT(10) 173 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11) 174 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 175 #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 176 #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 177 #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 178 #define RK3128_GMAC_RMII_MODE GRF_BIT(14) 179 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 180 181 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, 182 int tx_delay, int rx_delay) 183 { 184 struct device *dev = &bsp_priv->pdev->dev; 185 186 if (IS_ERR(bsp_priv->grf)) { 187 dev_err(dev, "Missing rockchip,grf property\n"); 188 return; 189 } 190 191 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 192 RK3128_GMAC_PHY_INTF_SEL_RGMII | 193 RK3128_GMAC_RMII_MODE_CLR); 194 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0, 195 DELAY_ENABLE(RK3128, tx_delay, rx_delay) | 196 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) | 197 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay)); 198 } 199 200 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) 201 { 202 struct device *dev = &bsp_priv->pdev->dev; 203 204 if (IS_ERR(bsp_priv->grf)) { 205 dev_err(dev, "Missing rockchip,grf property\n"); 206 return; 207 } 208 209 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 210 RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE); 211 } 212 213 static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 214 { 215 struct device *dev = &bsp_priv->pdev->dev; 216 217 if (IS_ERR(bsp_priv->grf)) { 218 dev_err(dev, "Missing rockchip,grf property\n"); 219 return; 220 } 221 222 if (speed == 10) 223 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 224 RK3128_GMAC_CLK_2_5M); 225 else if (speed == 100) 226 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 227 RK3128_GMAC_CLK_25M); 228 else if (speed == 1000) 229 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 230 RK3128_GMAC_CLK_125M); 231 else 232 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 233 } 234 235 static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 236 { 237 struct device *dev = &bsp_priv->pdev->dev; 238 239 if (IS_ERR(bsp_priv->grf)) { 240 dev_err(dev, "Missing rockchip,grf property\n"); 241 return; 242 } 243 244 if (speed == 10) { 245 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 246 RK3128_GMAC_RMII_CLK_2_5M | 247 RK3128_GMAC_SPEED_10M); 248 } else if (speed == 100) { 249 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 250 RK3128_GMAC_RMII_CLK_25M | 251 RK3128_GMAC_SPEED_100M); 252 } else { 253 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 254 } 255 } 256 257 static const struct rk_gmac_ops rk3128_ops = { 258 .set_to_rgmii = rk3128_set_to_rgmii, 259 .set_to_rmii = rk3128_set_to_rmii, 260 .set_rgmii_speed = rk3128_set_rgmii_speed, 261 .set_rmii_speed = rk3128_set_rmii_speed, 262 }; 263 264 #define RK3228_GRF_MAC_CON0 0x0900 265 #define RK3228_GRF_MAC_CON1 0x0904 266 267 #define RK3228_GRF_CON_MUX 0x50 268 269 /* RK3228_GRF_MAC_CON0 */ 270 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 271 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 272 273 /* RK3228_GRF_MAC_CON1 */ 274 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ 275 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 276 #define RK3228_GMAC_PHY_INTF_SEL_RMII \ 277 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 278 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) 279 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 280 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) 281 #define RK3228_GMAC_SPEED_100M GRF_BIT(2) 282 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) 283 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 284 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) 285 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) 286 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) 287 #define RK3228_GMAC_RMII_MODE GRF_BIT(10) 288 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) 289 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 290 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 291 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 292 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 293 294 /* RK3228_GRF_COM_MUX */ 295 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15) 296 297 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, 298 int tx_delay, int rx_delay) 299 { 300 struct device *dev = &bsp_priv->pdev->dev; 301 302 if (IS_ERR(bsp_priv->grf)) { 303 dev_err(dev, "Missing rockchip,grf property\n"); 304 return; 305 } 306 307 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 308 RK3228_GMAC_PHY_INTF_SEL_RGMII | 309 RK3228_GMAC_RMII_MODE_CLR | 310 DELAY_ENABLE(RK3228, tx_delay, rx_delay)); 311 312 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, 313 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | 314 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); 315 } 316 317 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) 318 { 319 struct device *dev = &bsp_priv->pdev->dev; 320 321 if (IS_ERR(bsp_priv->grf)) { 322 dev_err(dev, "Missing rockchip,grf property\n"); 323 return; 324 } 325 326 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 327 RK3228_GMAC_PHY_INTF_SEL_RMII | 328 RK3228_GMAC_RMII_MODE); 329 330 /* set MAC to RMII mode */ 331 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); 332 } 333 334 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 335 { 336 struct device *dev = &bsp_priv->pdev->dev; 337 338 if (IS_ERR(bsp_priv->grf)) { 339 dev_err(dev, "Missing rockchip,grf property\n"); 340 return; 341 } 342 343 if (speed == 10) 344 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 345 RK3228_GMAC_CLK_2_5M); 346 else if (speed == 100) 347 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 348 RK3228_GMAC_CLK_25M); 349 else if (speed == 1000) 350 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 351 RK3228_GMAC_CLK_125M); 352 else 353 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 354 } 355 356 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 357 { 358 struct device *dev = &bsp_priv->pdev->dev; 359 360 if (IS_ERR(bsp_priv->grf)) { 361 dev_err(dev, "Missing rockchip,grf property\n"); 362 return; 363 } 364 365 if (speed == 10) 366 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 367 RK3228_GMAC_RMII_CLK_2_5M | 368 RK3228_GMAC_SPEED_10M); 369 else if (speed == 100) 370 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 371 RK3228_GMAC_RMII_CLK_25M | 372 RK3228_GMAC_SPEED_100M); 373 else 374 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 375 } 376 377 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) 378 { 379 regmap_write(priv->grf, RK3228_GRF_CON_MUX, 380 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 381 } 382 383 static const struct rk_gmac_ops rk3228_ops = { 384 .set_to_rgmii = rk3228_set_to_rgmii, 385 .set_to_rmii = rk3228_set_to_rmii, 386 .set_rgmii_speed = rk3228_set_rgmii_speed, 387 .set_rmii_speed = rk3228_set_rmii_speed, 388 .integrated_phy_powerup = rk3228_integrated_phy_powerup, 389 }; 390 391 #define RK3288_GRF_SOC_CON1 0x0248 392 #define RK3288_GRF_SOC_CON3 0x0250 393 394 /*RK3288_GRF_SOC_CON1*/ 395 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ 396 GRF_CLR_BIT(8)) 397 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ 398 GRF_BIT(8)) 399 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) 400 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 401 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) 402 #define RK3288_GMAC_SPEED_100M GRF_BIT(10) 403 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) 404 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 405 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 406 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 407 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 408 #define RK3288_GMAC_RMII_MODE GRF_BIT(14) 409 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 410 411 /*RK3288_GRF_SOC_CON3*/ 412 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 413 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 414 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 415 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 416 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 417 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 418 419 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 420 int tx_delay, int rx_delay) 421 { 422 struct device *dev = &bsp_priv->pdev->dev; 423 424 if (IS_ERR(bsp_priv->grf)) { 425 dev_err(dev, "Missing rockchip,grf property\n"); 426 return; 427 } 428 429 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 430 RK3288_GMAC_PHY_INTF_SEL_RGMII | 431 RK3288_GMAC_RMII_MODE_CLR); 432 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 433 DELAY_ENABLE(RK3288, tx_delay, rx_delay) | 434 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | 435 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); 436 } 437 438 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 439 { 440 struct device *dev = &bsp_priv->pdev->dev; 441 442 if (IS_ERR(bsp_priv->grf)) { 443 dev_err(dev, "Missing rockchip,grf property\n"); 444 return; 445 } 446 447 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 448 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); 449 } 450 451 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 452 { 453 struct device *dev = &bsp_priv->pdev->dev; 454 455 if (IS_ERR(bsp_priv->grf)) { 456 dev_err(dev, "Missing rockchip,grf property\n"); 457 return; 458 } 459 460 if (speed == 10) 461 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 462 RK3288_GMAC_CLK_2_5M); 463 else if (speed == 100) 464 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 465 RK3288_GMAC_CLK_25M); 466 else if (speed == 1000) 467 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 468 RK3288_GMAC_CLK_125M); 469 else 470 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 471 } 472 473 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 474 { 475 struct device *dev = &bsp_priv->pdev->dev; 476 477 if (IS_ERR(bsp_priv->grf)) { 478 dev_err(dev, "Missing rockchip,grf property\n"); 479 return; 480 } 481 482 if (speed == 10) { 483 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 484 RK3288_GMAC_RMII_CLK_2_5M | 485 RK3288_GMAC_SPEED_10M); 486 } else if (speed == 100) { 487 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 488 RK3288_GMAC_RMII_CLK_25M | 489 RK3288_GMAC_SPEED_100M); 490 } else { 491 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 492 } 493 } 494 495 static const struct rk_gmac_ops rk3288_ops = { 496 .set_to_rgmii = rk3288_set_to_rgmii, 497 .set_to_rmii = rk3288_set_to_rmii, 498 .set_rgmii_speed = rk3288_set_rgmii_speed, 499 .set_rmii_speed = rk3288_set_rmii_speed, 500 }; 501 502 #define RK3308_GRF_MAC_CON0 0x04a0 503 504 /* RK3308_GRF_MAC_CON0 */ 505 #define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \ 506 GRF_BIT(4)) 507 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3) 508 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 509 #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0) 510 #define RK3308_GMAC_SPEED_100M GRF_BIT(0) 511 512 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) 513 { 514 struct device *dev = &bsp_priv->pdev->dev; 515 516 if (IS_ERR(bsp_priv->grf)) { 517 dev_err(dev, "Missing rockchip,grf property\n"); 518 return; 519 } 520 521 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 522 RK3308_GMAC_PHY_INTF_SEL_RMII); 523 } 524 525 static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 526 { 527 struct device *dev = &bsp_priv->pdev->dev; 528 529 if (IS_ERR(bsp_priv->grf)) { 530 dev_err(dev, "Missing rockchip,grf property\n"); 531 return; 532 } 533 534 if (speed == 10) { 535 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 536 RK3308_GMAC_SPEED_10M); 537 } else if (speed == 100) { 538 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 539 RK3308_GMAC_SPEED_100M); 540 } else { 541 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 542 } 543 } 544 545 static const struct rk_gmac_ops rk3308_ops = { 546 .set_to_rmii = rk3308_set_to_rmii, 547 .set_rmii_speed = rk3308_set_rmii_speed, 548 }; 549 550 #define RK3328_GRF_MAC_CON0 0x0900 551 #define RK3328_GRF_MAC_CON1 0x0904 552 #define RK3328_GRF_MAC_CON2 0x0908 553 #define RK3328_GRF_MACPHY_CON1 0xb04 554 555 /* RK3328_GRF_MAC_CON0 */ 556 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 557 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 558 559 /* RK3328_GRF_MAC_CON1 */ 560 #define RK3328_GMAC_PHY_INTF_SEL_RGMII \ 561 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 562 #define RK3328_GMAC_PHY_INTF_SEL_RMII \ 563 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 564 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) 565 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 566 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) 567 #define RK3328_GMAC_SPEED_100M GRF_BIT(2) 568 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) 569 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 570 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12)) 571 #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12)) 572 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12)) 573 #define RK3328_GMAC_RMII_MODE GRF_BIT(9) 574 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) 575 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 576 #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 577 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 578 #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0) 579 580 /* RK3328_GRF_MACPHY_CON1 */ 581 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9) 582 583 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, 584 int tx_delay, int rx_delay) 585 { 586 struct device *dev = &bsp_priv->pdev->dev; 587 588 if (IS_ERR(bsp_priv->grf)) { 589 dev_err(dev, "Missing rockchip,grf property\n"); 590 return; 591 } 592 593 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 594 RK3328_GMAC_PHY_INTF_SEL_RGMII | 595 RK3328_GMAC_RMII_MODE_CLR | 596 RK3328_GMAC_RXCLK_DLY_ENABLE | 597 RK3328_GMAC_TXCLK_DLY_ENABLE); 598 599 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0, 600 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) | 601 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); 602 } 603 604 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) 605 { 606 struct device *dev = &bsp_priv->pdev->dev; 607 unsigned int reg; 608 609 if (IS_ERR(bsp_priv->grf)) { 610 dev_err(dev, "Missing rockchip,grf property\n"); 611 return; 612 } 613 614 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : 615 RK3328_GRF_MAC_CON1; 616 617 regmap_write(bsp_priv->grf, reg, 618 RK3328_GMAC_PHY_INTF_SEL_RMII | 619 RK3328_GMAC_RMII_MODE); 620 } 621 622 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 623 { 624 struct device *dev = &bsp_priv->pdev->dev; 625 626 if (IS_ERR(bsp_priv->grf)) { 627 dev_err(dev, "Missing rockchip,grf property\n"); 628 return; 629 } 630 631 if (speed == 10) 632 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 633 RK3328_GMAC_CLK_2_5M); 634 else if (speed == 100) 635 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 636 RK3328_GMAC_CLK_25M); 637 else if (speed == 1000) 638 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 639 RK3328_GMAC_CLK_125M); 640 else 641 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 642 } 643 644 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 645 { 646 struct device *dev = &bsp_priv->pdev->dev; 647 unsigned int reg; 648 649 if (IS_ERR(bsp_priv->grf)) { 650 dev_err(dev, "Missing rockchip,grf property\n"); 651 return; 652 } 653 654 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : 655 RK3328_GRF_MAC_CON1; 656 657 if (speed == 10) 658 regmap_write(bsp_priv->grf, reg, 659 RK3328_GMAC_RMII_CLK_2_5M | 660 RK3328_GMAC_SPEED_10M); 661 else if (speed == 100) 662 regmap_write(bsp_priv->grf, reg, 663 RK3328_GMAC_RMII_CLK_25M | 664 RK3328_GMAC_SPEED_100M); 665 else 666 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 667 } 668 669 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) 670 { 671 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, 672 RK3328_MACPHY_RMII_MODE); 673 } 674 675 static const struct rk_gmac_ops rk3328_ops = { 676 .set_to_rgmii = rk3328_set_to_rgmii, 677 .set_to_rmii = rk3328_set_to_rmii, 678 .set_rgmii_speed = rk3328_set_rgmii_speed, 679 .set_rmii_speed = rk3328_set_rmii_speed, 680 .integrated_phy_powerup = rk3328_integrated_phy_powerup, 681 }; 682 683 #define RK3366_GRF_SOC_CON6 0x0418 684 #define RK3366_GRF_SOC_CON7 0x041c 685 686 /* RK3366_GRF_SOC_CON6 */ 687 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 688 GRF_CLR_BIT(11)) 689 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 690 GRF_BIT(11)) 691 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) 692 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 693 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) 694 #define RK3366_GMAC_SPEED_100M GRF_BIT(7) 695 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) 696 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 697 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 698 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 699 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 700 #define RK3366_GMAC_RMII_MODE GRF_BIT(6) 701 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 702 703 /* RK3366_GRF_SOC_CON7 */ 704 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 705 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 706 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 707 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 708 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 709 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 710 711 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 712 int tx_delay, int rx_delay) 713 { 714 struct device *dev = &bsp_priv->pdev->dev; 715 716 if (IS_ERR(bsp_priv->grf)) { 717 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 718 return; 719 } 720 721 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 722 RK3366_GMAC_PHY_INTF_SEL_RGMII | 723 RK3366_GMAC_RMII_MODE_CLR); 724 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, 725 DELAY_ENABLE(RK3366, tx_delay, rx_delay) | 726 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | 727 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); 728 } 729 730 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 731 { 732 struct device *dev = &bsp_priv->pdev->dev; 733 734 if (IS_ERR(bsp_priv->grf)) { 735 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 736 return; 737 } 738 739 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 740 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); 741 } 742 743 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 744 { 745 struct device *dev = &bsp_priv->pdev->dev; 746 747 if (IS_ERR(bsp_priv->grf)) { 748 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 749 return; 750 } 751 752 if (speed == 10) 753 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 754 RK3366_GMAC_CLK_2_5M); 755 else if (speed == 100) 756 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 757 RK3366_GMAC_CLK_25M); 758 else if (speed == 1000) 759 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 760 RK3366_GMAC_CLK_125M); 761 else 762 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 763 } 764 765 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 766 { 767 struct device *dev = &bsp_priv->pdev->dev; 768 769 if (IS_ERR(bsp_priv->grf)) { 770 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 771 return; 772 } 773 774 if (speed == 10) { 775 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 776 RK3366_GMAC_RMII_CLK_2_5M | 777 RK3366_GMAC_SPEED_10M); 778 } else if (speed == 100) { 779 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 780 RK3366_GMAC_RMII_CLK_25M | 781 RK3366_GMAC_SPEED_100M); 782 } else { 783 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 784 } 785 } 786 787 static const struct rk_gmac_ops rk3366_ops = { 788 .set_to_rgmii = rk3366_set_to_rgmii, 789 .set_to_rmii = rk3366_set_to_rmii, 790 .set_rgmii_speed = rk3366_set_rgmii_speed, 791 .set_rmii_speed = rk3366_set_rmii_speed, 792 }; 793 794 #define RK3368_GRF_SOC_CON15 0x043c 795 #define RK3368_GRF_SOC_CON16 0x0440 796 797 /* RK3368_GRF_SOC_CON15 */ 798 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 799 GRF_CLR_BIT(11)) 800 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 801 GRF_BIT(11)) 802 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) 803 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 804 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) 805 #define RK3368_GMAC_SPEED_100M GRF_BIT(7) 806 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) 807 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 808 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 809 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 810 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 811 #define RK3368_GMAC_RMII_MODE GRF_BIT(6) 812 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 813 814 /* RK3368_GRF_SOC_CON16 */ 815 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 816 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 817 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 818 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 819 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 820 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 821 822 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 823 int tx_delay, int rx_delay) 824 { 825 struct device *dev = &bsp_priv->pdev->dev; 826 827 if (IS_ERR(bsp_priv->grf)) { 828 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 829 return; 830 } 831 832 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 833 RK3368_GMAC_PHY_INTF_SEL_RGMII | 834 RK3368_GMAC_RMII_MODE_CLR); 835 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, 836 DELAY_ENABLE(RK3368, tx_delay, rx_delay) | 837 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | 838 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); 839 } 840 841 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 842 { 843 struct device *dev = &bsp_priv->pdev->dev; 844 845 if (IS_ERR(bsp_priv->grf)) { 846 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 847 return; 848 } 849 850 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 851 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); 852 } 853 854 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 855 { 856 struct device *dev = &bsp_priv->pdev->dev; 857 858 if (IS_ERR(bsp_priv->grf)) { 859 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 860 return; 861 } 862 863 if (speed == 10) 864 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 865 RK3368_GMAC_CLK_2_5M); 866 else if (speed == 100) 867 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 868 RK3368_GMAC_CLK_25M); 869 else if (speed == 1000) 870 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 871 RK3368_GMAC_CLK_125M); 872 else 873 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 874 } 875 876 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 877 { 878 struct device *dev = &bsp_priv->pdev->dev; 879 880 if (IS_ERR(bsp_priv->grf)) { 881 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 882 return; 883 } 884 885 if (speed == 10) { 886 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 887 RK3368_GMAC_RMII_CLK_2_5M | 888 RK3368_GMAC_SPEED_10M); 889 } else if (speed == 100) { 890 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 891 RK3368_GMAC_RMII_CLK_25M | 892 RK3368_GMAC_SPEED_100M); 893 } else { 894 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 895 } 896 } 897 898 static const struct rk_gmac_ops rk3368_ops = { 899 .set_to_rgmii = rk3368_set_to_rgmii, 900 .set_to_rmii = rk3368_set_to_rmii, 901 .set_rgmii_speed = rk3368_set_rgmii_speed, 902 .set_rmii_speed = rk3368_set_rmii_speed, 903 }; 904 905 #define RK3399_GRF_SOC_CON5 0xc214 906 #define RK3399_GRF_SOC_CON6 0xc218 907 908 /* RK3399_GRF_SOC_CON5 */ 909 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 910 GRF_CLR_BIT(11)) 911 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 912 GRF_BIT(11)) 913 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) 914 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 915 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) 916 #define RK3399_GMAC_SPEED_100M GRF_BIT(7) 917 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) 918 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 919 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 920 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 921 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 922 #define RK3399_GMAC_RMII_MODE GRF_BIT(6) 923 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 924 925 /* RK3399_GRF_SOC_CON6 */ 926 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 927 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 928 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 929 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 930 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 931 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 932 933 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 934 int tx_delay, int rx_delay) 935 { 936 struct device *dev = &bsp_priv->pdev->dev; 937 938 if (IS_ERR(bsp_priv->grf)) { 939 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 940 return; 941 } 942 943 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 944 RK3399_GMAC_PHY_INTF_SEL_RGMII | 945 RK3399_GMAC_RMII_MODE_CLR); 946 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, 947 DELAY_ENABLE(RK3399, tx_delay, rx_delay) | 948 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | 949 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); 950 } 951 952 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 953 { 954 struct device *dev = &bsp_priv->pdev->dev; 955 956 if (IS_ERR(bsp_priv->grf)) { 957 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 958 return; 959 } 960 961 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 962 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); 963 } 964 965 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 966 { 967 struct device *dev = &bsp_priv->pdev->dev; 968 969 if (IS_ERR(bsp_priv->grf)) { 970 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 971 return; 972 } 973 974 if (speed == 10) 975 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 976 RK3399_GMAC_CLK_2_5M); 977 else if (speed == 100) 978 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 979 RK3399_GMAC_CLK_25M); 980 else if (speed == 1000) 981 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 982 RK3399_GMAC_CLK_125M); 983 else 984 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 985 } 986 987 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 988 { 989 struct device *dev = &bsp_priv->pdev->dev; 990 991 if (IS_ERR(bsp_priv->grf)) { 992 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 993 return; 994 } 995 996 if (speed == 10) { 997 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 998 RK3399_GMAC_RMII_CLK_2_5M | 999 RK3399_GMAC_SPEED_10M); 1000 } else if (speed == 100) { 1001 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 1002 RK3399_GMAC_RMII_CLK_25M | 1003 RK3399_GMAC_SPEED_100M); 1004 } else { 1005 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 1006 } 1007 } 1008 1009 static const struct rk_gmac_ops rk3399_ops = { 1010 .set_to_rgmii = rk3399_set_to_rgmii, 1011 .set_to_rmii = rk3399_set_to_rmii, 1012 .set_rgmii_speed = rk3399_set_rgmii_speed, 1013 .set_rmii_speed = rk3399_set_rmii_speed, 1014 }; 1015 1016 #define RK3568_GRF_GMAC0_CON0 0x0380 1017 #define RK3568_GRF_GMAC0_CON1 0x0384 1018 #define RK3568_GRF_GMAC1_CON0 0x0388 1019 #define RK3568_GRF_GMAC1_CON1 0x038c 1020 1021 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ 1022 #define RK3568_GMAC_PHY_INTF_SEL_RGMII \ 1023 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 1024 #define RK3568_GMAC_PHY_INTF_SEL_RMII \ 1025 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 1026 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) 1027 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 1028 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 1029 #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 1030 #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 1031 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 1032 1033 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ 1034 #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1035 #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1036 1037 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, 1038 int tx_delay, int rx_delay) 1039 { 1040 struct device *dev = &bsp_priv->pdev->dev; 1041 u32 con0, con1; 1042 1043 if (IS_ERR(bsp_priv->grf)) { 1044 dev_err(dev, "Missing rockchip,grf property\n"); 1045 return; 1046 } 1047 1048 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 : 1049 RK3568_GRF_GMAC0_CON0; 1050 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 1051 RK3568_GRF_GMAC0_CON1; 1052 1053 regmap_write(bsp_priv->grf, con0, 1054 RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) | 1055 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay)); 1056 1057 regmap_write(bsp_priv->grf, con1, 1058 RK3568_GMAC_PHY_INTF_SEL_RGMII | 1059 RK3568_GMAC_RXCLK_DLY_ENABLE | 1060 RK3568_GMAC_TXCLK_DLY_ENABLE); 1061 } 1062 1063 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) 1064 { 1065 struct device *dev = &bsp_priv->pdev->dev; 1066 u32 con1; 1067 1068 if (IS_ERR(bsp_priv->grf)) { 1069 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 1070 return; 1071 } 1072 1073 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 1074 RK3568_GRF_GMAC0_CON1; 1075 regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII); 1076 } 1077 1078 static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) 1079 { 1080 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 1081 struct device *dev = &bsp_priv->pdev->dev; 1082 long rate; 1083 int ret; 1084 1085 rate = rgmii_clock(speed); 1086 if (rate < 0) { 1087 dev_err(dev, "unknown speed value for GMAC speed=%d", speed); 1088 return; 1089 } 1090 1091 ret = clk_set_rate(clk_mac_speed, rate); 1092 if (ret) 1093 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n", 1094 __func__, rate, ret); 1095 } 1096 1097 static const struct rk_gmac_ops rk3568_ops = { 1098 .set_to_rgmii = rk3568_set_to_rgmii, 1099 .set_to_rmii = rk3568_set_to_rmii, 1100 .set_rgmii_speed = rk3568_set_gmac_speed, 1101 .set_rmii_speed = rk3568_set_gmac_speed, 1102 .regs_valid = true, 1103 .regs = { 1104 0xfe2a0000, /* gmac0 */ 1105 0xfe010000, /* gmac1 */ 1106 0x0, /* sentinel */ 1107 }, 1108 }; 1109 1110 /* VCCIO0_1_3_IOC */ 1111 #define RK3576_VCCIO0_1_3_IOC_CON2 0X6408 1112 #define RK3576_VCCIO0_1_3_IOC_CON3 0X640c 1113 #define RK3576_VCCIO0_1_3_IOC_CON4 0X6410 1114 #define RK3576_VCCIO0_1_3_IOC_CON5 0X6414 1115 1116 #define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 1117 #define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 1118 #define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 1119 #define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 1120 1121 #define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1122 #define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1123 1124 /* SDGMAC_GRF */ 1125 #define RK3576_GRF_GMAC_CON0 0X0020 1126 #define RK3576_GRF_GMAC_CON1 0X0024 1127 1128 #define RK3576_GMAC_RMII_MODE GRF_BIT(3) 1129 #define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3) 1130 1131 #define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7) 1132 #define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7) 1133 1134 #define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5) 1135 #define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5) 1136 1137 #define RK3576_GMAC_CLK_RGMII_DIV1 \ 1138 (GRF_CLR_BIT(6) | GRF_CLR_BIT(5)) 1139 #define RK3576_GMAC_CLK_RGMII_DIV5 \ 1140 (GRF_BIT(6) | GRF_BIT(5)) 1141 #define RK3576_GMAC_CLK_RGMII_DIV50 \ 1142 (GRF_BIT(6) | GRF_CLR_BIT(5)) 1143 1144 #define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) 1145 #define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) 1146 1147 static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv, 1148 int tx_delay, int rx_delay) 1149 { 1150 struct device *dev = &bsp_priv->pdev->dev; 1151 unsigned int offset_con; 1152 1153 if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) { 1154 dev_err(dev, "Missing rockchip,grf or rockchip,php-grf property\n"); 1155 return; 1156 } 1157 1158 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1159 RK3576_GRF_GMAC_CON0; 1160 1161 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE); 1162 1163 offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 : 1164 RK3576_VCCIO0_1_3_IOC_CON2; 1165 1166 /* m0 && m1 delay enabled */ 1167 regmap_write(bsp_priv->php_grf, offset_con, 1168 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 1169 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 1170 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 1171 1172 /* m0 && m1 delay value */ 1173 regmap_write(bsp_priv->php_grf, offset_con, 1174 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 1175 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 1176 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 1177 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 1178 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 1179 } 1180 1181 static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv) 1182 { 1183 struct device *dev = &bsp_priv->pdev->dev; 1184 unsigned int offset_con; 1185 1186 if (IS_ERR(bsp_priv->grf)) { 1187 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 1188 return; 1189 } 1190 1191 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1192 RK3576_GRF_GMAC_CON0; 1193 1194 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE); 1195 } 1196 1197 static void rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) 1198 { 1199 struct device *dev = &bsp_priv->pdev->dev; 1200 unsigned int val = 0, offset_con; 1201 1202 switch (speed) { 1203 case 10: 1204 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 1205 val = RK3576_GMAC_CLK_RMII_DIV20; 1206 else 1207 val = RK3576_GMAC_CLK_RGMII_DIV50; 1208 break; 1209 case 100: 1210 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 1211 val = RK3576_GMAC_CLK_RMII_DIV2; 1212 else 1213 val = RK3576_GMAC_CLK_RGMII_DIV5; 1214 break; 1215 case 1000: 1216 if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII) 1217 val = RK3576_GMAC_CLK_RGMII_DIV1; 1218 else 1219 goto err; 1220 break; 1221 default: 1222 goto err; 1223 } 1224 1225 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1226 RK3576_GRF_GMAC_CON0; 1227 1228 regmap_write(bsp_priv->grf, offset_con, val); 1229 1230 return; 1231 err: 1232 dev_err(dev, "unknown speed value for GMAC speed=%d", speed); 1233 } 1234 1235 static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1236 bool enable) 1237 { 1238 unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO : 1239 RK3576_GMAC_CLK_SELECT_CRU; 1240 unsigned int offset_con; 1241 1242 val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE : 1243 RK3576_GMAC_CLK_RMII_GATE; 1244 1245 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1246 RK3576_GRF_GMAC_CON0; 1247 1248 regmap_write(bsp_priv->grf, offset_con, val); 1249 } 1250 1251 static const struct rk_gmac_ops rk3576_ops = { 1252 .set_to_rgmii = rk3576_set_to_rgmii, 1253 .set_to_rmii = rk3576_set_to_rmii, 1254 .set_rgmii_speed = rk3576_set_gmac_speed, 1255 .set_rmii_speed = rk3576_set_gmac_speed, 1256 .set_clock_selection = rk3576_set_clock_selection, 1257 .regs_valid = true, 1258 .regs = { 1259 0x2a220000, /* gmac0 */ 1260 0x2a230000, /* gmac1 */ 1261 0x0, /* sentinel */ 1262 }, 1263 }; 1264 1265 /* sys_grf */ 1266 #define RK3588_GRF_GMAC_CON7 0X031c 1267 #define RK3588_GRF_GMAC_CON8 0X0320 1268 #define RK3588_GRF_GMAC_CON9 0X0324 1269 1270 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3) 1271 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3) 1272 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2) 1273 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2) 1274 1275 #define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) 1276 #define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) 1277 1278 /* php_grf */ 1279 #define RK3588_GRF_GMAC_CON0 0X0008 1280 #define RK3588_GRF_CLK_CON1 0X0070 1281 1282 #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \ 1283 (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6)) 1284 #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \ 1285 (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6)) 1286 1287 #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) 1288 #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id)) 1289 1290 #define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4) 1291 #define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4) 1292 1293 #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2) 1294 #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2) 1295 1296 #define RK3588_GMAC_CLK_RGMII_DIV1(id) \ 1297 (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3)) 1298 #define RK3588_GMAC_CLK_RGMII_DIV5(id) \ 1299 (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1300 #define RK3588_GMAC_CLK_RGMII_DIV50(id) \ 1301 (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1302 1303 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) 1304 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1) 1305 1306 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv, 1307 int tx_delay, int rx_delay) 1308 { 1309 struct device *dev = &bsp_priv->pdev->dev; 1310 u32 offset_con, id = bsp_priv->id; 1311 1312 if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) { 1313 dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n"); 1314 return; 1315 } 1316 1317 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 : 1318 RK3588_GRF_GMAC_CON8; 1319 1320 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1321 RK3588_GMAC_PHY_INTF_SEL_RGMII(id)); 1322 1323 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1324 RK3588_GMAC_CLK_RGMII_MODE(id)); 1325 1326 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7, 1327 RK3588_GMAC_RXCLK_DLY_ENABLE(id) | 1328 RK3588_GMAC_TXCLK_DLY_ENABLE(id)); 1329 1330 regmap_write(bsp_priv->grf, offset_con, 1331 RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) | 1332 RK3588_GMAC_CLK_TX_DL_CFG(tx_delay)); 1333 } 1334 1335 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv) 1336 { 1337 struct device *dev = &bsp_priv->pdev->dev; 1338 1339 if (IS_ERR(bsp_priv->php_grf)) { 1340 dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__); 1341 return; 1342 } 1343 1344 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1345 RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id)); 1346 1347 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1348 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id)); 1349 } 1350 1351 static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) 1352 { 1353 struct device *dev = &bsp_priv->pdev->dev; 1354 unsigned int val = 0, id = bsp_priv->id; 1355 1356 switch (speed) { 1357 case 10: 1358 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 1359 val = RK3588_GMA_CLK_RMII_DIV20(id); 1360 else 1361 val = RK3588_GMAC_CLK_RGMII_DIV50(id); 1362 break; 1363 case 100: 1364 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 1365 val = RK3588_GMA_CLK_RMII_DIV2(id); 1366 else 1367 val = RK3588_GMAC_CLK_RGMII_DIV5(id); 1368 break; 1369 case 1000: 1370 if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII) 1371 val = RK3588_GMAC_CLK_RGMII_DIV1(id); 1372 else 1373 goto err; 1374 break; 1375 default: 1376 goto err; 1377 } 1378 1379 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1380 1381 return; 1382 err: 1383 dev_err(dev, "unknown speed value for GMAC speed=%d", speed); 1384 } 1385 1386 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1387 bool enable) 1388 { 1389 unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) : 1390 RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id); 1391 1392 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) : 1393 RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id); 1394 1395 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1396 } 1397 1398 static const struct rk_gmac_ops rk3588_ops = { 1399 .set_to_rgmii = rk3588_set_to_rgmii, 1400 .set_to_rmii = rk3588_set_to_rmii, 1401 .set_rgmii_speed = rk3588_set_gmac_speed, 1402 .set_rmii_speed = rk3588_set_gmac_speed, 1403 .set_clock_selection = rk3588_set_clock_selection, 1404 .regs_valid = true, 1405 .regs = { 1406 0xfe1b0000, /* gmac0 */ 1407 0xfe1c0000, /* gmac1 */ 1408 0x0, /* sentinel */ 1409 }, 1410 }; 1411 1412 #define RV1108_GRF_GMAC_CON0 0X0900 1413 1414 /* RV1108_GRF_GMAC_CON0 */ 1415 #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 1416 GRF_BIT(6)) 1417 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) 1418 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 1419 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2) 1420 #define RV1108_GMAC_SPEED_100M GRF_BIT(2) 1421 #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7) 1422 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 1423 1424 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) 1425 { 1426 struct device *dev = &bsp_priv->pdev->dev; 1427 1428 if (IS_ERR(bsp_priv->grf)) { 1429 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 1430 return; 1431 } 1432 1433 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1434 RV1108_GMAC_PHY_INTF_SEL_RMII); 1435 } 1436 1437 static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 1438 { 1439 struct device *dev = &bsp_priv->pdev->dev; 1440 1441 if (IS_ERR(bsp_priv->grf)) { 1442 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 1443 return; 1444 } 1445 1446 if (speed == 10) { 1447 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1448 RV1108_GMAC_RMII_CLK_2_5M | 1449 RV1108_GMAC_SPEED_10M); 1450 } else if (speed == 100) { 1451 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1452 RV1108_GMAC_RMII_CLK_25M | 1453 RV1108_GMAC_SPEED_100M); 1454 } else { 1455 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 1456 } 1457 } 1458 1459 static const struct rk_gmac_ops rv1108_ops = { 1460 .set_to_rmii = rv1108_set_to_rmii, 1461 .set_rmii_speed = rv1108_set_rmii_speed, 1462 }; 1463 1464 #define RV1126_GRF_GMAC_CON0 0X0070 1465 #define RV1126_GRF_GMAC_CON1 0X0074 1466 #define RV1126_GRF_GMAC_CON2 0X0078 1467 1468 /* RV1126_GRF_GMAC_CON0 */ 1469 #define RV1126_GMAC_PHY_INTF_SEL_RGMII \ 1470 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 1471 #define RV1126_GMAC_PHY_INTF_SEL_RMII \ 1472 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 1473 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7) 1474 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7) 1475 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1) 1476 #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 1477 #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0) 1478 #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 1479 #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3) 1480 #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3) 1481 #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2) 1482 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2) 1483 1484 /* RV1126_GRF_GMAC_CON1 */ 1485 #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1486 #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1487 /* RV1126_GRF_GMAC_CON2 */ 1488 #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1489 #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1490 1491 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv, 1492 int tx_delay, int rx_delay) 1493 { 1494 struct device *dev = &bsp_priv->pdev->dev; 1495 1496 if (IS_ERR(bsp_priv->grf)) { 1497 dev_err(dev, "Missing rockchip,grf property\n"); 1498 return; 1499 } 1500 1501 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1502 RV1126_GMAC_PHY_INTF_SEL_RGMII | 1503 RV1126_GMAC_M0_RXCLK_DLY_ENABLE | 1504 RV1126_GMAC_M0_TXCLK_DLY_ENABLE | 1505 RV1126_GMAC_M1_RXCLK_DLY_ENABLE | 1506 RV1126_GMAC_M1_TXCLK_DLY_ENABLE); 1507 1508 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1, 1509 RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) | 1510 RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay)); 1511 1512 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2, 1513 RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) | 1514 RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay)); 1515 } 1516 1517 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) 1518 { 1519 struct device *dev = &bsp_priv->pdev->dev; 1520 1521 if (IS_ERR(bsp_priv->grf)) { 1522 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 1523 return; 1524 } 1525 1526 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1527 RV1126_GMAC_PHY_INTF_SEL_RMII); 1528 } 1529 1530 static void rv1126_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 1531 { 1532 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 1533 struct device *dev = &bsp_priv->pdev->dev; 1534 long rate; 1535 int ret; 1536 1537 rate = rgmii_clock(speed); 1538 if (rate < 0) { 1539 dev_err(dev, "unknown speed value for RGMII speed=%d", speed); 1540 return; 1541 } 1542 1543 ret = clk_set_rate(clk_mac_speed, rate); 1544 if (ret) 1545 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n", 1546 __func__, rate, ret); 1547 } 1548 1549 static void rv1126_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 1550 { 1551 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 1552 struct device *dev = &bsp_priv->pdev->dev; 1553 unsigned long rate; 1554 int ret; 1555 1556 switch (speed) { 1557 case 10: 1558 rate = 2500000; 1559 break; 1560 case 100: 1561 rate = 25000000; 1562 break; 1563 default: 1564 dev_err(dev, "unknown speed value for RGMII speed=%d", speed); 1565 return; 1566 } 1567 1568 ret = clk_set_rate(clk_mac_speed, rate); 1569 if (ret) 1570 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n", 1571 __func__, rate, ret); 1572 } 1573 1574 static const struct rk_gmac_ops rv1126_ops = { 1575 .set_to_rgmii = rv1126_set_to_rgmii, 1576 .set_to_rmii = rv1126_set_to_rmii, 1577 .set_rgmii_speed = rv1126_set_rgmii_speed, 1578 .set_rmii_speed = rv1126_set_rmii_speed, 1579 }; 1580 1581 #define RK_GRF_MACPHY_CON0 0xb00 1582 #define RK_GRF_MACPHY_CON1 0xb04 1583 #define RK_GRF_MACPHY_CON2 0xb08 1584 #define RK_GRF_MACPHY_CON3 0xb0c 1585 1586 #define RK_MACPHY_ENABLE GRF_BIT(0) 1587 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0) 1588 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) 1589 #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) 1590 #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) 1591 #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) 1592 1593 static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) 1594 { 1595 if (priv->ops->integrated_phy_powerup) 1596 priv->ops->integrated_phy_powerup(priv); 1597 1598 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); 1599 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); 1600 1601 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); 1602 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); 1603 1604 if (priv->phy_reset) { 1605 /* PHY needs to be disabled before trying to reset it */ 1606 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 1607 if (priv->phy_reset) 1608 reset_control_assert(priv->phy_reset); 1609 usleep_range(10, 20); 1610 if (priv->phy_reset) 1611 reset_control_deassert(priv->phy_reset); 1612 usleep_range(10, 20); 1613 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); 1614 msleep(30); 1615 } 1616 } 1617 1618 static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) 1619 { 1620 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 1621 if (priv->phy_reset) 1622 reset_control_assert(priv->phy_reset); 1623 } 1624 1625 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) 1626 { 1627 struct rk_priv_data *bsp_priv = plat->bsp_priv; 1628 struct device *dev = &bsp_priv->pdev->dev; 1629 int phy_iface = bsp_priv->phy_iface; 1630 int i, j, ret; 1631 1632 bsp_priv->clk_enabled = false; 1633 1634 bsp_priv->num_clks = ARRAY_SIZE(rk_clocks); 1635 if (phy_iface == PHY_INTERFACE_MODE_RMII) 1636 bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks); 1637 1638 bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks, 1639 sizeof(*bsp_priv->clks), GFP_KERNEL); 1640 if (!bsp_priv->clks) 1641 return -ENOMEM; 1642 1643 for (i = 0; i < ARRAY_SIZE(rk_clocks); i++) 1644 bsp_priv->clks[i].id = rk_clocks[i]; 1645 1646 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1647 for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++) 1648 bsp_priv->clks[i++].id = rk_rmii_clocks[j]; 1649 } 1650 1651 ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks, 1652 bsp_priv->clks); 1653 if (ret) 1654 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1655 1656 /* "stmmaceth" will be enabled by the core */ 1657 bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth"); 1658 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_mac); 1659 if (ret) 1660 return dev_err_probe(dev, ret, "Cannot get stmmaceth clock\n"); 1661 1662 if (bsp_priv->clock_input) { 1663 dev_info(dev, "clock input from PHY\n"); 1664 } else if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1665 clk_set_rate(bsp_priv->clk_mac, 50000000); 1666 } 1667 1668 if (plat->phy_node && bsp_priv->integrated_phy) { 1669 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); 1670 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy); 1671 if (ret) 1672 return dev_err_probe(dev, ret, "Cannot get PHY clock\n"); 1673 clk_set_rate(bsp_priv->clk_phy, 50000000); 1674 } 1675 1676 return 0; 1677 } 1678 1679 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 1680 { 1681 int ret; 1682 1683 if (enable) { 1684 if (!bsp_priv->clk_enabled) { 1685 ret = clk_bulk_prepare_enable(bsp_priv->num_clks, 1686 bsp_priv->clks); 1687 if (ret) 1688 return ret; 1689 1690 ret = clk_prepare_enable(bsp_priv->clk_phy); 1691 if (ret) 1692 return ret; 1693 1694 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1695 bsp_priv->ops->set_clock_selection(bsp_priv, 1696 bsp_priv->clock_input, true); 1697 1698 mdelay(5); 1699 bsp_priv->clk_enabled = true; 1700 } 1701 } else { 1702 if (bsp_priv->clk_enabled) { 1703 clk_bulk_disable_unprepare(bsp_priv->num_clks, 1704 bsp_priv->clks); 1705 clk_disable_unprepare(bsp_priv->clk_phy); 1706 1707 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1708 bsp_priv->ops->set_clock_selection(bsp_priv, 1709 bsp_priv->clock_input, false); 1710 1711 bsp_priv->clk_enabled = false; 1712 } 1713 } 1714 1715 return 0; 1716 } 1717 1718 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) 1719 { 1720 struct regulator *ldo = bsp_priv->regulator; 1721 int ret; 1722 struct device *dev = &bsp_priv->pdev->dev; 1723 1724 if (enable) { 1725 ret = regulator_enable(ldo); 1726 if (ret) 1727 dev_err(dev, "fail to enable phy-supply\n"); 1728 } else { 1729 ret = regulator_disable(ldo); 1730 if (ret) 1731 dev_err(dev, "fail to disable phy-supply\n"); 1732 } 1733 1734 return 0; 1735 } 1736 1737 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, 1738 struct plat_stmmacenet_data *plat, 1739 const struct rk_gmac_ops *ops) 1740 { 1741 struct rk_priv_data *bsp_priv; 1742 struct device *dev = &pdev->dev; 1743 struct resource *res; 1744 int ret; 1745 const char *strings = NULL; 1746 int value; 1747 1748 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); 1749 if (!bsp_priv) 1750 return ERR_PTR(-ENOMEM); 1751 1752 of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface); 1753 bsp_priv->ops = ops; 1754 1755 /* Some SoCs have multiple MAC controllers, which need 1756 * to be distinguished. 1757 */ 1758 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1759 if (res && ops->regs_valid) { 1760 int i = 0; 1761 1762 while (ops->regs[i]) { 1763 if (ops->regs[i] == res->start) { 1764 bsp_priv->id = i; 1765 break; 1766 } 1767 i++; 1768 } 1769 } 1770 1771 bsp_priv->regulator = devm_regulator_get(dev, "phy"); 1772 if (IS_ERR(bsp_priv->regulator)) { 1773 ret = PTR_ERR(bsp_priv->regulator); 1774 dev_err_probe(dev, ret, "failed to get phy regulator\n"); 1775 return ERR_PTR(ret); 1776 } 1777 1778 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); 1779 if (ret) { 1780 dev_err(dev, "Can not read property: clock_in_out.\n"); 1781 bsp_priv->clock_input = true; 1782 } else { 1783 dev_info(dev, "clock input or output? (%s).\n", 1784 strings); 1785 if (!strcmp(strings, "input")) 1786 bsp_priv->clock_input = true; 1787 else 1788 bsp_priv->clock_input = false; 1789 } 1790 1791 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); 1792 if (ret) { 1793 bsp_priv->tx_delay = 0x30; 1794 dev_err(dev, "Can not read property: tx_delay."); 1795 dev_err(dev, "set tx_delay to 0x%x\n", 1796 bsp_priv->tx_delay); 1797 } else { 1798 dev_info(dev, "TX delay(0x%x).\n", value); 1799 bsp_priv->tx_delay = value; 1800 } 1801 1802 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); 1803 if (ret) { 1804 bsp_priv->rx_delay = 0x10; 1805 dev_err(dev, "Can not read property: rx_delay."); 1806 dev_err(dev, "set rx_delay to 0x%x\n", 1807 bsp_priv->rx_delay); 1808 } else { 1809 dev_info(dev, "RX delay(0x%x).\n", value); 1810 bsp_priv->rx_delay = value; 1811 } 1812 1813 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 1814 "rockchip,grf"); 1815 bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node, 1816 "rockchip,php-grf"); 1817 1818 if (plat->phy_node) { 1819 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, 1820 "phy-is-integrated"); 1821 if (bsp_priv->integrated_phy) { 1822 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL); 1823 if (IS_ERR(bsp_priv->phy_reset)) { 1824 dev_err(&pdev->dev, "No PHY reset control found.\n"); 1825 bsp_priv->phy_reset = NULL; 1826 } 1827 } 1828 } 1829 dev_info(dev, "integrated PHY? (%s).\n", 1830 bsp_priv->integrated_phy ? "yes" : "no"); 1831 1832 bsp_priv->pdev = pdev; 1833 1834 return bsp_priv; 1835 } 1836 1837 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv) 1838 { 1839 switch (bsp_priv->phy_iface) { 1840 case PHY_INTERFACE_MODE_RGMII: 1841 case PHY_INTERFACE_MODE_RGMII_ID: 1842 case PHY_INTERFACE_MODE_RGMII_RXID: 1843 case PHY_INTERFACE_MODE_RGMII_TXID: 1844 if (!bsp_priv->ops->set_to_rgmii) 1845 return -EINVAL; 1846 break; 1847 case PHY_INTERFACE_MODE_RMII: 1848 if (!bsp_priv->ops->set_to_rmii) 1849 return -EINVAL; 1850 break; 1851 default: 1852 dev_err(&bsp_priv->pdev->dev, 1853 "unsupported interface %d", bsp_priv->phy_iface); 1854 } 1855 return 0; 1856 } 1857 1858 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) 1859 { 1860 int ret; 1861 struct device *dev = &bsp_priv->pdev->dev; 1862 1863 ret = rk_gmac_check_ops(bsp_priv); 1864 if (ret) 1865 return ret; 1866 1867 ret = gmac_clk_enable(bsp_priv, true); 1868 if (ret) 1869 return ret; 1870 1871 /*rmii or rgmii*/ 1872 switch (bsp_priv->phy_iface) { 1873 case PHY_INTERFACE_MODE_RGMII: 1874 dev_info(dev, "init for RGMII\n"); 1875 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 1876 bsp_priv->rx_delay); 1877 break; 1878 case PHY_INTERFACE_MODE_RGMII_ID: 1879 dev_info(dev, "init for RGMII_ID\n"); 1880 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); 1881 break; 1882 case PHY_INTERFACE_MODE_RGMII_RXID: 1883 dev_info(dev, "init for RGMII_RXID\n"); 1884 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); 1885 break; 1886 case PHY_INTERFACE_MODE_RGMII_TXID: 1887 dev_info(dev, "init for RGMII_TXID\n"); 1888 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); 1889 break; 1890 case PHY_INTERFACE_MODE_RMII: 1891 dev_info(dev, "init for RMII\n"); 1892 bsp_priv->ops->set_to_rmii(bsp_priv); 1893 break; 1894 default: 1895 dev_err(dev, "NO interface defined!\n"); 1896 } 1897 1898 ret = phy_power_on(bsp_priv, true); 1899 if (ret) { 1900 gmac_clk_enable(bsp_priv, false); 1901 return ret; 1902 } 1903 1904 pm_runtime_get_sync(dev); 1905 1906 if (bsp_priv->integrated_phy) 1907 rk_gmac_integrated_phy_powerup(bsp_priv); 1908 1909 return 0; 1910 } 1911 1912 static void rk_gmac_powerdown(struct rk_priv_data *gmac) 1913 { 1914 if (gmac->integrated_phy) 1915 rk_gmac_integrated_phy_powerdown(gmac); 1916 1917 pm_runtime_put_sync(&gmac->pdev->dev); 1918 1919 phy_power_on(gmac, false); 1920 gmac_clk_enable(gmac, false); 1921 } 1922 1923 static void rk_fix_speed(void *priv, unsigned int speed, unsigned int mode) 1924 { 1925 struct rk_priv_data *bsp_priv = priv; 1926 struct device *dev = &bsp_priv->pdev->dev; 1927 1928 switch (bsp_priv->phy_iface) { 1929 case PHY_INTERFACE_MODE_RGMII: 1930 case PHY_INTERFACE_MODE_RGMII_ID: 1931 case PHY_INTERFACE_MODE_RGMII_RXID: 1932 case PHY_INTERFACE_MODE_RGMII_TXID: 1933 if (bsp_priv->ops->set_rgmii_speed) 1934 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed); 1935 break; 1936 case PHY_INTERFACE_MODE_RMII: 1937 if (bsp_priv->ops->set_rmii_speed) 1938 bsp_priv->ops->set_rmii_speed(bsp_priv, speed); 1939 break; 1940 default: 1941 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface); 1942 } 1943 } 1944 1945 static int rk_gmac_probe(struct platform_device *pdev) 1946 { 1947 struct plat_stmmacenet_data *plat_dat; 1948 struct stmmac_resources stmmac_res; 1949 const struct rk_gmac_ops *data; 1950 int ret; 1951 1952 data = of_device_get_match_data(&pdev->dev); 1953 if (!data) { 1954 dev_err(&pdev->dev, "no of match data provided\n"); 1955 return -EINVAL; 1956 } 1957 1958 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1959 if (ret) 1960 return ret; 1961 1962 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 1963 if (IS_ERR(plat_dat)) 1964 return PTR_ERR(plat_dat); 1965 1966 /* If the stmmac is not already selected as gmac4, 1967 * then make sure we fallback to gmac. 1968 */ 1969 if (!plat_dat->has_gmac4) 1970 plat_dat->has_gmac = true; 1971 plat_dat->fix_mac_speed = rk_fix_speed; 1972 1973 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data); 1974 if (IS_ERR(plat_dat->bsp_priv)) 1975 return PTR_ERR(plat_dat->bsp_priv); 1976 1977 ret = rk_gmac_clk_init(plat_dat); 1978 if (ret) 1979 return ret; 1980 1981 ret = rk_gmac_powerup(plat_dat->bsp_priv); 1982 if (ret) 1983 return ret; 1984 1985 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1986 if (ret) 1987 goto err_gmac_powerdown; 1988 1989 return 0; 1990 1991 err_gmac_powerdown: 1992 rk_gmac_powerdown(plat_dat->bsp_priv); 1993 1994 return ret; 1995 } 1996 1997 static void rk_gmac_remove(struct platform_device *pdev) 1998 { 1999 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev); 2000 2001 stmmac_dvr_remove(&pdev->dev); 2002 2003 rk_gmac_powerdown(bsp_priv); 2004 } 2005 2006 #ifdef CONFIG_PM_SLEEP 2007 static int rk_gmac_suspend(struct device *dev) 2008 { 2009 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 2010 int ret = stmmac_suspend(dev); 2011 2012 /* Keep the PHY up if we use Wake-on-Lan. */ 2013 if (!device_may_wakeup(dev)) { 2014 rk_gmac_powerdown(bsp_priv); 2015 bsp_priv->suspended = true; 2016 } 2017 2018 return ret; 2019 } 2020 2021 static int rk_gmac_resume(struct device *dev) 2022 { 2023 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 2024 2025 /* The PHY was up for Wake-on-Lan. */ 2026 if (bsp_priv->suspended) { 2027 rk_gmac_powerup(bsp_priv); 2028 bsp_priv->suspended = false; 2029 } 2030 2031 return stmmac_resume(dev); 2032 } 2033 #endif /* CONFIG_PM_SLEEP */ 2034 2035 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume); 2036 2037 static const struct of_device_id rk_gmac_dwmac_match[] = { 2038 { .compatible = "rockchip,px30-gmac", .data = &px30_ops }, 2039 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops }, 2040 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops }, 2041 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops }, 2042 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops }, 2043 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops }, 2044 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, 2045 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, 2046 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, 2047 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops }, 2048 { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops }, 2049 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops }, 2050 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops }, 2051 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops }, 2052 { } 2053 }; 2054 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); 2055 2056 static struct platform_driver rk_gmac_dwmac_driver = { 2057 .probe = rk_gmac_probe, 2058 .remove = rk_gmac_remove, 2059 .driver = { 2060 .name = "rk_gmac-dwmac", 2061 .pm = &rk_gmac_pm_ops, 2062 .of_match_table = rk_gmac_dwmac_match, 2063 }, 2064 }; 2065 module_platform_driver(rk_gmac_dwmac_driver); 2066 2067 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>"); 2068 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer"); 2069 MODULE_LICENSE("GPL"); 2070