1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /** 3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer 4 * 5 * Copyright (C) 2014 Chen-Zhi (Roger Chen) 6 * 7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> 8 */ 9 10 #include <linux/stmmac.h> 11 #include <linux/bitops.h> 12 #include <linux/clk.h> 13 #include <linux/phy.h> 14 #include <linux/of_net.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/delay.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/regmap.h> 22 #include <linux/pm_runtime.h> 23 24 #include "stmmac_platform.h" 25 26 struct rk_priv_data; 27 28 struct rk_reg_speed_data { 29 unsigned int rgmii_10; 30 unsigned int rgmii_100; 31 unsigned int rgmii_1000; 32 unsigned int rmii_10; 33 unsigned int rmii_100; 34 }; 35 36 struct rk_gmac_ops { 37 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, 38 int tx_delay, int rx_delay); 39 void (*set_to_rmii)(struct rk_priv_data *bsp_priv); 40 int (*set_speed)(struct rk_priv_data *bsp_priv, 41 phy_interface_t interface, int speed); 42 void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, 43 bool enable); 44 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); 45 void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv); 46 bool php_grf_required; 47 bool regs_valid; 48 u32 regs[]; 49 }; 50 51 static const char * const rk_clocks[] = { 52 "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed", 53 }; 54 55 static const char * const rk_rmii_clocks[] = { 56 "mac_clk_rx", "clk_mac_ref", "clk_mac_refout", 57 }; 58 59 enum rk_clocks_index { 60 RK_ACLK_MAC = 0, 61 RK_PCLK_MAC, 62 RK_MAC_CLK_TX, 63 RK_CLK_MAC_SPEED, 64 RK_MAC_CLK_RX, 65 RK_CLK_MAC_REF, 66 RK_CLK_MAC_REFOUT, 67 }; 68 69 struct rk_priv_data { 70 struct device *dev; 71 phy_interface_t phy_iface; 72 int id; 73 struct regulator *regulator; 74 const struct rk_gmac_ops *ops; 75 76 bool clk_enabled; 77 bool clock_input; 78 bool integrated_phy; 79 80 struct clk_bulk_data *clks; 81 int num_clks; 82 struct clk *clk_phy; 83 84 struct reset_control *phy_reset; 85 86 int tx_delay; 87 int rx_delay; 88 89 struct regmap *grf; 90 struct regmap *php_grf; 91 }; 92 93 static int rk_set_reg_speed(struct rk_priv_data *bsp_priv, 94 const struct rk_reg_speed_data *rsd, 95 unsigned int reg, phy_interface_t interface, 96 int speed) 97 { 98 unsigned int val; 99 100 if (phy_interface_mode_is_rgmii(interface)) { 101 if (speed == SPEED_10) { 102 val = rsd->rgmii_10; 103 } else if (speed == SPEED_100) { 104 val = rsd->rgmii_100; 105 } else if (speed == SPEED_1000) { 106 val = rsd->rgmii_1000; 107 } else { 108 /* Phylink will not allow inappropriate speeds for 109 * interface modes, so this should never happen. 110 */ 111 return -EINVAL; 112 } 113 } else if (interface == PHY_INTERFACE_MODE_RMII) { 114 if (speed == SPEED_10) { 115 val = rsd->rmii_10; 116 } else if (speed == SPEED_100) { 117 val = rsd->rmii_100; 118 } else { 119 /* Phylink will not allow inappropriate speeds for 120 * interface modes, so this should never happen. 121 */ 122 return -EINVAL; 123 } 124 } else { 125 /* This should never happen, as .get_interfaces() limits 126 * the interface modes that are supported to RGMII and/or 127 * RMII. 128 */ 129 return -EINVAL; 130 } 131 132 regmap_write(bsp_priv->grf, reg, val); 133 134 return 0; 135 136 } 137 138 static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv, 139 phy_interface_t interface, int speed) 140 { 141 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 142 long rate; 143 144 rate = rgmii_clock(speed); 145 if (rate < 0) 146 return rate; 147 148 return clk_set_rate(clk_mac_speed, rate); 149 } 150 151 #define HIWORD_UPDATE(val, mask, shift) \ 152 ((val) << (shift) | (mask) << ((shift) + 16)) 153 154 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 155 #define GRF_CLR_BIT(nr) (BIT(nr+16)) 156 157 #define DELAY_ENABLE(soc, tx, rx) \ 158 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ 159 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) 160 161 #define RK_GRF_MACPHY_CON0 0xb00 162 #define RK_GRF_MACPHY_CON1 0xb04 163 #define RK_GRF_MACPHY_CON2 0xb08 164 #define RK_GRF_MACPHY_CON3 0xb0c 165 166 #define RK_MACPHY_ENABLE GRF_BIT(0) 167 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0) 168 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) 169 #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) 170 #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) 171 #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) 172 173 static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv) 174 { 175 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); 176 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); 177 178 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); 179 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); 180 181 if (priv->phy_reset) { 182 /* PHY needs to be disabled before trying to reset it */ 183 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 184 if (priv->phy_reset) 185 reset_control_assert(priv->phy_reset); 186 usleep_range(10, 20); 187 if (priv->phy_reset) 188 reset_control_deassert(priv->phy_reset); 189 usleep_range(10, 20); 190 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); 191 msleep(30); 192 } 193 } 194 195 static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv) 196 { 197 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 198 if (priv->phy_reset) 199 reset_control_assert(priv->phy_reset); 200 } 201 202 #define RK_FEPHY_SHUTDOWN GRF_BIT(1) 203 #define RK_FEPHY_POWERUP GRF_CLR_BIT(1) 204 #define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6) 205 #define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9)) 206 #define RK_FEPHY_PHY_ID GRF_BIT(11) 207 208 static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv, 209 unsigned int reg) 210 { 211 reset_control_assert(priv->phy_reset); 212 usleep_range(20, 30); 213 214 regmap_write(priv->grf, reg, 215 RK_FEPHY_POWERUP | 216 RK_FEPHY_INTERNAL_RMII_SEL | 217 RK_FEPHY_24M_CLK_SEL | 218 RK_FEPHY_PHY_ID); 219 usleep_range(10000, 12000); 220 221 reset_control_deassert(priv->phy_reset); 222 usleep_range(50000, 60000); 223 } 224 225 static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv, 226 unsigned int reg) 227 { 228 regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN); 229 } 230 231 #define PX30_GRF_GMAC_CON1 0x0904 232 233 /* PX30_GRF_GMAC_CON1 */ 234 #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 235 GRF_BIT(6)) 236 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2) 237 #define PX30_GMAC_SPEED_100M GRF_BIT(2) 238 239 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) 240 { 241 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 242 PX30_GMAC_PHY_INTF_SEL_RMII); 243 } 244 245 static int px30_set_speed(struct rk_priv_data *bsp_priv, 246 phy_interface_t interface, int speed) 247 { 248 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 249 struct device *dev = bsp_priv->dev; 250 unsigned int con1; 251 long rate; 252 253 if (!clk_mac_speed) { 254 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__); 255 return -EINVAL; 256 } 257 258 if (speed == 10) { 259 con1 = PX30_GMAC_SPEED_10M; 260 rate = 2500000; 261 } else if (speed == 100) { 262 con1 = PX30_GMAC_SPEED_100M; 263 rate = 25000000; 264 } else { 265 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 266 return -EINVAL; 267 } 268 269 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, con1); 270 271 return clk_set_rate(clk_mac_speed, rate); 272 } 273 274 static const struct rk_gmac_ops px30_ops = { 275 .set_to_rmii = px30_set_to_rmii, 276 .set_speed = px30_set_speed, 277 }; 278 279 #define RK3128_GRF_MAC_CON0 0x0168 280 #define RK3128_GRF_MAC_CON1 0x016c 281 282 /* RK3128_GRF_MAC_CON0 */ 283 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 284 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 285 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 286 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 287 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 288 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 289 290 /* RK3128_GRF_MAC_CON1 */ 291 #define RK3128_GMAC_PHY_INTF_SEL_RGMII \ 292 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8)) 293 #define RK3128_GMAC_PHY_INTF_SEL_RMII \ 294 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8)) 295 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9) 296 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 297 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10) 298 #define RK3128_GMAC_SPEED_100M GRF_BIT(10) 299 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11) 300 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 301 #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 302 #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 303 #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 304 #define RK3128_GMAC_RMII_MODE GRF_BIT(14) 305 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 306 307 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, 308 int tx_delay, int rx_delay) 309 { 310 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 311 RK3128_GMAC_PHY_INTF_SEL_RGMII | 312 RK3128_GMAC_RMII_MODE_CLR); 313 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0, 314 DELAY_ENABLE(RK3128, tx_delay, rx_delay) | 315 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) | 316 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay)); 317 } 318 319 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) 320 { 321 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 322 RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE); 323 } 324 325 static const struct rk_reg_speed_data rk3128_reg_speed_data = { 326 .rgmii_10 = RK3128_GMAC_CLK_2_5M, 327 .rgmii_100 = RK3128_GMAC_CLK_25M, 328 .rgmii_1000 = RK3128_GMAC_CLK_125M, 329 .rmii_10 = RK3128_GMAC_RMII_CLK_2_5M | RK3128_GMAC_SPEED_10M, 330 .rmii_100 = RK3128_GMAC_RMII_CLK_25M | RK3128_GMAC_SPEED_100M, 331 }; 332 333 static int rk3128_set_speed(struct rk_priv_data *bsp_priv, 334 phy_interface_t interface, int speed) 335 { 336 return rk_set_reg_speed(bsp_priv, &rk3128_reg_speed_data, 337 RK3128_GRF_MAC_CON1, interface, speed); 338 } 339 340 static const struct rk_gmac_ops rk3128_ops = { 341 .set_to_rgmii = rk3128_set_to_rgmii, 342 .set_to_rmii = rk3128_set_to_rmii, 343 .set_speed = rk3128_set_speed, 344 }; 345 346 #define RK3228_GRF_MAC_CON0 0x0900 347 #define RK3228_GRF_MAC_CON1 0x0904 348 349 #define RK3228_GRF_CON_MUX 0x50 350 351 /* RK3228_GRF_MAC_CON0 */ 352 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 353 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 354 355 /* RK3228_GRF_MAC_CON1 */ 356 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ 357 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 358 #define RK3228_GMAC_PHY_INTF_SEL_RMII \ 359 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 360 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) 361 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 362 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) 363 #define RK3228_GMAC_SPEED_100M GRF_BIT(2) 364 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) 365 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 366 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) 367 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) 368 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) 369 #define RK3228_GMAC_RMII_MODE GRF_BIT(10) 370 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) 371 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 372 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 373 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 374 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 375 376 /* RK3228_GRF_COM_MUX */ 377 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15) 378 379 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, 380 int tx_delay, int rx_delay) 381 { 382 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 383 RK3228_GMAC_PHY_INTF_SEL_RGMII | 384 RK3228_GMAC_RMII_MODE_CLR | 385 DELAY_ENABLE(RK3228, tx_delay, rx_delay)); 386 387 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, 388 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | 389 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); 390 } 391 392 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) 393 { 394 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 395 RK3228_GMAC_PHY_INTF_SEL_RMII | 396 RK3228_GMAC_RMII_MODE); 397 398 /* set MAC to RMII mode */ 399 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); 400 } 401 402 static const struct rk_reg_speed_data rk3228_reg_speed_data = { 403 .rgmii_10 = RK3228_GMAC_CLK_2_5M, 404 .rgmii_100 = RK3228_GMAC_CLK_25M, 405 .rgmii_1000 = RK3228_GMAC_CLK_125M, 406 .rmii_10 = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_SPEED_10M, 407 .rmii_100 = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_SPEED_100M, 408 }; 409 410 static int rk3228_set_speed(struct rk_priv_data *bsp_priv, 411 phy_interface_t interface, int speed) 412 { 413 return rk_set_reg_speed(bsp_priv, &rk3228_reg_speed_data, 414 RK3228_GRF_MAC_CON1, interface, speed); 415 } 416 417 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) 418 { 419 regmap_write(priv->grf, RK3228_GRF_CON_MUX, 420 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 421 422 rk_gmac_integrated_ephy_powerup(priv); 423 } 424 425 static const struct rk_gmac_ops rk3228_ops = { 426 .set_to_rgmii = rk3228_set_to_rgmii, 427 .set_to_rmii = rk3228_set_to_rmii, 428 .set_speed = rk3228_set_speed, 429 .integrated_phy_powerup = rk3228_integrated_phy_powerup, 430 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, 431 }; 432 433 #define RK3288_GRF_SOC_CON1 0x0248 434 #define RK3288_GRF_SOC_CON3 0x0250 435 436 /*RK3288_GRF_SOC_CON1*/ 437 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ 438 GRF_CLR_BIT(8)) 439 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ 440 GRF_BIT(8)) 441 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) 442 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 443 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) 444 #define RK3288_GMAC_SPEED_100M GRF_BIT(10) 445 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) 446 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 447 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 448 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 449 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 450 #define RK3288_GMAC_RMII_MODE GRF_BIT(14) 451 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 452 453 /*RK3288_GRF_SOC_CON3*/ 454 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 455 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 456 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 457 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 458 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 459 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 460 461 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 462 int tx_delay, int rx_delay) 463 { 464 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 465 RK3288_GMAC_PHY_INTF_SEL_RGMII | 466 RK3288_GMAC_RMII_MODE_CLR); 467 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 468 DELAY_ENABLE(RK3288, tx_delay, rx_delay) | 469 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | 470 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); 471 } 472 473 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 474 { 475 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 476 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); 477 } 478 479 static const struct rk_reg_speed_data rk3288_reg_speed_data = { 480 .rgmii_10 = RK3288_GMAC_CLK_2_5M, 481 .rgmii_100 = RK3288_GMAC_CLK_25M, 482 .rgmii_1000 = RK3288_GMAC_CLK_125M, 483 .rmii_10 = RK3288_GMAC_RMII_CLK_2_5M | RK3288_GMAC_SPEED_10M, 484 .rmii_100 = RK3288_GMAC_RMII_CLK_25M | RK3288_GMAC_SPEED_100M, 485 }; 486 487 static int rk3288_set_speed(struct rk_priv_data *bsp_priv, 488 phy_interface_t interface, int speed) 489 { 490 return rk_set_reg_speed(bsp_priv, &rk3288_reg_speed_data, 491 RK3288_GRF_SOC_CON1, interface, speed); 492 } 493 494 static const struct rk_gmac_ops rk3288_ops = { 495 .set_to_rgmii = rk3288_set_to_rgmii, 496 .set_to_rmii = rk3288_set_to_rmii, 497 .set_speed = rk3288_set_speed, 498 }; 499 500 #define RK3308_GRF_MAC_CON0 0x04a0 501 502 /* RK3308_GRF_MAC_CON0 */ 503 #define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \ 504 GRF_BIT(4)) 505 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3) 506 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 507 #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0) 508 #define RK3308_GMAC_SPEED_100M GRF_BIT(0) 509 510 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) 511 { 512 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 513 RK3308_GMAC_PHY_INTF_SEL_RMII); 514 } 515 516 static const struct rk_reg_speed_data rk3308_reg_speed_data = { 517 .rmii_10 = RK3308_GMAC_SPEED_10M, 518 .rmii_100 = RK3308_GMAC_SPEED_100M, 519 }; 520 521 static int rk3308_set_speed(struct rk_priv_data *bsp_priv, 522 phy_interface_t interface, int speed) 523 { 524 return rk_set_reg_speed(bsp_priv, &rk3308_reg_speed_data, 525 RK3308_GRF_MAC_CON0, interface, speed); 526 } 527 528 static const struct rk_gmac_ops rk3308_ops = { 529 .set_to_rmii = rk3308_set_to_rmii, 530 .set_speed = rk3308_set_speed, 531 }; 532 533 #define RK3328_GRF_MAC_CON0 0x0900 534 #define RK3328_GRF_MAC_CON1 0x0904 535 #define RK3328_GRF_MAC_CON2 0x0908 536 #define RK3328_GRF_MACPHY_CON1 0xb04 537 538 /* RK3328_GRF_MAC_CON0 */ 539 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 540 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 541 542 /* RK3328_GRF_MAC_CON1 */ 543 #define RK3328_GMAC_PHY_INTF_SEL_RGMII \ 544 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 545 #define RK3328_GMAC_PHY_INTF_SEL_RMII \ 546 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 547 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) 548 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 549 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) 550 #define RK3328_GMAC_SPEED_100M GRF_BIT(2) 551 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) 552 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 553 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12)) 554 #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12)) 555 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12)) 556 #define RK3328_GMAC_RMII_MODE GRF_BIT(9) 557 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) 558 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 559 #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 560 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 561 #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0) 562 563 /* RK3328_GRF_MACPHY_CON1 */ 564 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9) 565 566 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, 567 int tx_delay, int rx_delay) 568 { 569 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 570 RK3328_GMAC_PHY_INTF_SEL_RGMII | 571 RK3328_GMAC_RMII_MODE_CLR | 572 RK3328_GMAC_RXCLK_DLY_ENABLE | 573 RK3328_GMAC_TXCLK_DLY_ENABLE); 574 575 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0, 576 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) | 577 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); 578 } 579 580 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) 581 { 582 unsigned int reg; 583 584 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : 585 RK3328_GRF_MAC_CON1; 586 587 regmap_write(bsp_priv->grf, reg, 588 RK3328_GMAC_PHY_INTF_SEL_RMII | 589 RK3328_GMAC_RMII_MODE); 590 } 591 592 static const struct rk_reg_speed_data rk3328_reg_speed_data = { 593 .rgmii_10 = RK3328_GMAC_CLK_2_5M, 594 .rgmii_100 = RK3328_GMAC_CLK_25M, 595 .rgmii_1000 = RK3328_GMAC_CLK_125M, 596 .rmii_10 = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_SPEED_10M, 597 .rmii_100 = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_SPEED_100M, 598 }; 599 600 static int rk3328_set_speed(struct rk_priv_data *bsp_priv, 601 phy_interface_t interface, int speed) 602 { 603 unsigned int reg; 604 605 if (interface == PHY_INTERFACE_MODE_RMII && bsp_priv->integrated_phy) 606 reg = RK3328_GRF_MAC_CON2; 607 else 608 reg = RK3328_GRF_MAC_CON1; 609 610 return rk_set_reg_speed(bsp_priv, &rk3328_reg_speed_data, reg, 611 interface, speed); 612 } 613 614 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) 615 { 616 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, 617 RK3328_MACPHY_RMII_MODE); 618 619 rk_gmac_integrated_ephy_powerup(priv); 620 } 621 622 static const struct rk_gmac_ops rk3328_ops = { 623 .set_to_rgmii = rk3328_set_to_rgmii, 624 .set_to_rmii = rk3328_set_to_rmii, 625 .set_speed = rk3328_set_speed, 626 .integrated_phy_powerup = rk3328_integrated_phy_powerup, 627 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, 628 }; 629 630 #define RK3366_GRF_SOC_CON6 0x0418 631 #define RK3366_GRF_SOC_CON7 0x041c 632 633 /* RK3366_GRF_SOC_CON6 */ 634 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 635 GRF_CLR_BIT(11)) 636 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 637 GRF_BIT(11)) 638 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) 639 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 640 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) 641 #define RK3366_GMAC_SPEED_100M GRF_BIT(7) 642 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) 643 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 644 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 645 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 646 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 647 #define RK3366_GMAC_RMII_MODE GRF_BIT(6) 648 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 649 650 /* RK3366_GRF_SOC_CON7 */ 651 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 652 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 653 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 654 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 655 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 656 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 657 658 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 659 int tx_delay, int rx_delay) 660 { 661 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 662 RK3366_GMAC_PHY_INTF_SEL_RGMII | 663 RK3366_GMAC_RMII_MODE_CLR); 664 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, 665 DELAY_ENABLE(RK3366, tx_delay, rx_delay) | 666 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | 667 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); 668 } 669 670 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 671 { 672 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 673 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); 674 } 675 676 static const struct rk_reg_speed_data rk3366_reg_speed_data = { 677 .rgmii_10 = RK3366_GMAC_CLK_2_5M, 678 .rgmii_100 = RK3366_GMAC_CLK_25M, 679 .rgmii_1000 = RK3366_GMAC_CLK_125M, 680 .rmii_10 = RK3366_GMAC_RMII_CLK_2_5M | RK3366_GMAC_SPEED_10M, 681 .rmii_100 = RK3366_GMAC_RMII_CLK_25M | RK3366_GMAC_SPEED_100M, 682 }; 683 684 static int rk3366_set_speed(struct rk_priv_data *bsp_priv, 685 phy_interface_t interface, int speed) 686 { 687 return rk_set_reg_speed(bsp_priv, &rk3366_reg_speed_data, 688 RK3366_GRF_SOC_CON6, interface, speed); 689 } 690 691 static const struct rk_gmac_ops rk3366_ops = { 692 .set_to_rgmii = rk3366_set_to_rgmii, 693 .set_to_rmii = rk3366_set_to_rmii, 694 .set_speed = rk3366_set_speed, 695 }; 696 697 #define RK3368_GRF_SOC_CON15 0x043c 698 #define RK3368_GRF_SOC_CON16 0x0440 699 700 /* RK3368_GRF_SOC_CON15 */ 701 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 702 GRF_CLR_BIT(11)) 703 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 704 GRF_BIT(11)) 705 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) 706 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 707 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) 708 #define RK3368_GMAC_SPEED_100M GRF_BIT(7) 709 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) 710 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 711 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 712 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 713 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 714 #define RK3368_GMAC_RMII_MODE GRF_BIT(6) 715 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 716 717 /* RK3368_GRF_SOC_CON16 */ 718 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 719 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 720 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 721 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 722 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 723 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 724 725 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 726 int tx_delay, int rx_delay) 727 { 728 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 729 RK3368_GMAC_PHY_INTF_SEL_RGMII | 730 RK3368_GMAC_RMII_MODE_CLR); 731 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, 732 DELAY_ENABLE(RK3368, tx_delay, rx_delay) | 733 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | 734 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); 735 } 736 737 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 738 { 739 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 740 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); 741 } 742 743 static const struct rk_reg_speed_data rk3368_reg_speed_data = { 744 .rgmii_10 = RK3368_GMAC_CLK_2_5M, 745 .rgmii_100 = RK3368_GMAC_CLK_25M, 746 .rgmii_1000 = RK3368_GMAC_CLK_125M, 747 .rmii_10 = RK3368_GMAC_RMII_CLK_2_5M | RK3368_GMAC_SPEED_10M, 748 .rmii_100 = RK3368_GMAC_RMII_CLK_25M | RK3368_GMAC_SPEED_100M, 749 }; 750 751 static int rk3368_set_speed(struct rk_priv_data *bsp_priv, 752 phy_interface_t interface, int speed) 753 { 754 return rk_set_reg_speed(bsp_priv, &rk3368_reg_speed_data, 755 RK3368_GRF_SOC_CON15, interface, speed); 756 } 757 758 static const struct rk_gmac_ops rk3368_ops = { 759 .set_to_rgmii = rk3368_set_to_rgmii, 760 .set_to_rmii = rk3368_set_to_rmii, 761 .set_speed = rk3368_set_speed, 762 }; 763 764 #define RK3399_GRF_SOC_CON5 0xc214 765 #define RK3399_GRF_SOC_CON6 0xc218 766 767 /* RK3399_GRF_SOC_CON5 */ 768 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 769 GRF_CLR_BIT(11)) 770 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 771 GRF_BIT(11)) 772 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) 773 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 774 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) 775 #define RK3399_GMAC_SPEED_100M GRF_BIT(7) 776 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) 777 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 778 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 779 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 780 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 781 #define RK3399_GMAC_RMII_MODE GRF_BIT(6) 782 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 783 784 /* RK3399_GRF_SOC_CON6 */ 785 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 786 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 787 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 788 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 789 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 790 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 791 792 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 793 int tx_delay, int rx_delay) 794 { 795 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 796 RK3399_GMAC_PHY_INTF_SEL_RGMII | 797 RK3399_GMAC_RMII_MODE_CLR); 798 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, 799 DELAY_ENABLE(RK3399, tx_delay, rx_delay) | 800 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | 801 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); 802 } 803 804 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 805 { 806 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 807 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); 808 } 809 810 static const struct rk_reg_speed_data rk3399_reg_speed_data = { 811 .rgmii_10 = RK3399_GMAC_CLK_2_5M, 812 .rgmii_100 = RK3399_GMAC_CLK_25M, 813 .rgmii_1000 = RK3399_GMAC_CLK_125M, 814 .rmii_10 = RK3399_GMAC_RMII_CLK_2_5M | RK3399_GMAC_SPEED_10M, 815 .rmii_100 = RK3399_GMAC_RMII_CLK_25M | RK3399_GMAC_SPEED_100M, 816 }; 817 818 static int rk3399_set_speed(struct rk_priv_data *bsp_priv, 819 phy_interface_t interface, int speed) 820 { 821 return rk_set_reg_speed(bsp_priv, &rk3399_reg_speed_data, 822 RK3399_GRF_SOC_CON5, interface, speed); 823 } 824 825 static const struct rk_gmac_ops rk3399_ops = { 826 .set_to_rgmii = rk3399_set_to_rgmii, 827 .set_to_rmii = rk3399_set_to_rmii, 828 .set_speed = rk3399_set_speed, 829 }; 830 831 #define RK3528_VO_GRF_GMAC_CON 0x0018 832 #define RK3528_VO_GRF_MACPHY_CON0 0x001c 833 #define RK3528_VO_GRF_MACPHY_CON1 0x0020 834 #define RK3528_VPU_GRF_GMAC_CON5 0x0018 835 #define RK3528_VPU_GRF_GMAC_CON6 0x001c 836 837 #define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 838 #define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 839 #define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 840 #define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 841 842 #define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) 843 #define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) 844 845 #define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1) 846 #define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8) 847 #define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8) 848 849 #define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12) 850 #define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12) 851 852 #define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3) 853 #define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3) 854 #define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10) 855 #define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10) 856 857 #define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10)) 858 #define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10)) 859 #define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10)) 860 861 #define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) 862 #define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) 863 #define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9) 864 #define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9) 865 866 static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv, 867 int tx_delay, int rx_delay) 868 { 869 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 870 RK3528_GMAC1_PHY_INTF_SEL_RGMII); 871 872 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 873 DELAY_ENABLE(RK3528, tx_delay, rx_delay)); 874 875 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6, 876 RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) | 877 RK3528_GMAC_CLK_TX_DL_CFG(tx_delay)); 878 } 879 880 static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv) 881 { 882 if (bsp_priv->id == 1) 883 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 884 RK3528_GMAC1_PHY_INTF_SEL_RMII); 885 else 886 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, 887 RK3528_GMAC0_PHY_INTF_SEL_RMII | 888 RK3528_GMAC0_CLK_RMII_DIV2); 889 } 890 891 static const struct rk_reg_speed_data rk3528_gmac0_reg_speed_data = { 892 .rmii_10 = RK3528_GMAC0_CLK_RMII_DIV20, 893 .rmii_100 = RK3528_GMAC0_CLK_RMII_DIV2, 894 }; 895 896 static const struct rk_reg_speed_data rk3528_gmac1_reg_speed_data = { 897 .rgmii_10 = RK3528_GMAC1_CLK_RGMII_DIV50, 898 .rgmii_100 = RK3528_GMAC1_CLK_RGMII_DIV5, 899 .rgmii_1000 = RK3528_GMAC1_CLK_RGMII_DIV1, 900 .rmii_10 = RK3528_GMAC1_CLK_RMII_DIV20, 901 .rmii_100 = RK3528_GMAC1_CLK_RMII_DIV2, 902 }; 903 904 static int rk3528_set_speed(struct rk_priv_data *bsp_priv, 905 phy_interface_t interface, int speed) 906 { 907 const struct rk_reg_speed_data *rsd; 908 unsigned int reg; 909 910 if (bsp_priv->id == 1) { 911 rsd = &rk3528_gmac1_reg_speed_data; 912 reg = RK3528_VPU_GRF_GMAC_CON5; 913 } else { 914 rsd = &rk3528_gmac0_reg_speed_data; 915 reg = RK3528_VO_GRF_GMAC_CON; 916 } 917 918 return rk_set_reg_speed(bsp_priv, rsd, reg, interface, speed); 919 } 920 921 static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv, 922 bool input, bool enable) 923 { 924 unsigned int val; 925 926 if (bsp_priv->id == 1) { 927 val = input ? RK3528_GMAC1_CLK_SELECT_IO : 928 RK3528_GMAC1_CLK_SELECT_CRU; 929 val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE : 930 RK3528_GMAC1_CLK_RMII_GATE; 931 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val); 932 } else { 933 val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE : 934 RK3528_GMAC0_CLK_RMII_GATE; 935 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val); 936 } 937 } 938 939 static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv) 940 { 941 rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); 942 } 943 944 static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv) 945 { 946 rk_gmac_integrated_fephy_powerdown(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); 947 } 948 949 static const struct rk_gmac_ops rk3528_ops = { 950 .set_to_rgmii = rk3528_set_to_rgmii, 951 .set_to_rmii = rk3528_set_to_rmii, 952 .set_speed = rk3528_set_speed, 953 .set_clock_selection = rk3528_set_clock_selection, 954 .integrated_phy_powerup = rk3528_integrated_phy_powerup, 955 .integrated_phy_powerdown = rk3528_integrated_phy_powerdown, 956 .regs_valid = true, 957 .regs = { 958 0xffbd0000, /* gmac0 */ 959 0xffbe0000, /* gmac1 */ 960 0x0, /* sentinel */ 961 }, 962 }; 963 964 #define RK3568_GRF_GMAC0_CON0 0x0380 965 #define RK3568_GRF_GMAC0_CON1 0x0384 966 #define RK3568_GRF_GMAC1_CON0 0x0388 967 #define RK3568_GRF_GMAC1_CON1 0x038c 968 969 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ 970 #define RK3568_GMAC_PHY_INTF_SEL_RGMII \ 971 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 972 #define RK3568_GMAC_PHY_INTF_SEL_RMII \ 973 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 974 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) 975 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 976 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 977 #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 978 #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 979 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 980 981 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ 982 #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 983 #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 984 985 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, 986 int tx_delay, int rx_delay) 987 { 988 u32 con0, con1; 989 990 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 : 991 RK3568_GRF_GMAC0_CON0; 992 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 993 RK3568_GRF_GMAC0_CON1; 994 995 regmap_write(bsp_priv->grf, con0, 996 RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) | 997 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay)); 998 999 regmap_write(bsp_priv->grf, con1, 1000 RK3568_GMAC_PHY_INTF_SEL_RGMII | 1001 RK3568_GMAC_RXCLK_DLY_ENABLE | 1002 RK3568_GMAC_TXCLK_DLY_ENABLE); 1003 } 1004 1005 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) 1006 { 1007 u32 con1; 1008 1009 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 1010 RK3568_GRF_GMAC0_CON1; 1011 regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII); 1012 } 1013 1014 static const struct rk_gmac_ops rk3568_ops = { 1015 .set_to_rgmii = rk3568_set_to_rgmii, 1016 .set_to_rmii = rk3568_set_to_rmii, 1017 .set_speed = rk_set_clk_mac_speed, 1018 .regs_valid = true, 1019 .regs = { 1020 0xfe2a0000, /* gmac0 */ 1021 0xfe010000, /* gmac1 */ 1022 0x0, /* sentinel */ 1023 }, 1024 }; 1025 1026 /* VCCIO0_1_3_IOC */ 1027 #define RK3576_VCCIO0_1_3_IOC_CON2 0X6408 1028 #define RK3576_VCCIO0_1_3_IOC_CON3 0X640c 1029 #define RK3576_VCCIO0_1_3_IOC_CON4 0X6410 1030 #define RK3576_VCCIO0_1_3_IOC_CON5 0X6414 1031 1032 #define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 1033 #define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 1034 #define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 1035 #define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 1036 1037 #define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1038 #define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1039 1040 /* SDGMAC_GRF */ 1041 #define RK3576_GRF_GMAC_CON0 0X0020 1042 #define RK3576_GRF_GMAC_CON1 0X0024 1043 1044 #define RK3576_GMAC_RMII_MODE GRF_BIT(3) 1045 #define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3) 1046 1047 #define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7) 1048 #define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7) 1049 1050 #define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5) 1051 #define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5) 1052 1053 #define RK3576_GMAC_CLK_RGMII_DIV1 \ 1054 (GRF_CLR_BIT(6) | GRF_CLR_BIT(5)) 1055 #define RK3576_GMAC_CLK_RGMII_DIV5 \ 1056 (GRF_BIT(6) | GRF_BIT(5)) 1057 #define RK3576_GMAC_CLK_RGMII_DIV50 \ 1058 (GRF_BIT(6) | GRF_CLR_BIT(5)) 1059 1060 #define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) 1061 #define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) 1062 1063 static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv, 1064 int tx_delay, int rx_delay) 1065 { 1066 unsigned int offset_con; 1067 1068 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1069 RK3576_GRF_GMAC_CON0; 1070 1071 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE); 1072 1073 offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 : 1074 RK3576_VCCIO0_1_3_IOC_CON2; 1075 1076 /* m0 && m1 delay enabled */ 1077 regmap_write(bsp_priv->php_grf, offset_con, 1078 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 1079 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 1080 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 1081 1082 /* m0 && m1 delay value */ 1083 regmap_write(bsp_priv->php_grf, offset_con, 1084 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 1085 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 1086 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 1087 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 1088 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 1089 } 1090 1091 static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv) 1092 { 1093 unsigned int offset_con; 1094 1095 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1096 RK3576_GRF_GMAC_CON0; 1097 1098 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE); 1099 } 1100 1101 static const struct rk_reg_speed_data rk3578_reg_speed_data = { 1102 .rgmii_10 = RK3576_GMAC_CLK_RGMII_DIV50, 1103 .rgmii_100 = RK3576_GMAC_CLK_RGMII_DIV5, 1104 .rgmii_1000 = RK3576_GMAC_CLK_RGMII_DIV1, 1105 .rmii_10 = RK3576_GMAC_CLK_RMII_DIV20, 1106 .rmii_100 = RK3576_GMAC_CLK_RMII_DIV2, 1107 }; 1108 1109 static int rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, 1110 phy_interface_t interface, int speed) 1111 { 1112 unsigned int offset_con; 1113 1114 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1115 RK3576_GRF_GMAC_CON0; 1116 1117 return rk_set_reg_speed(bsp_priv, &rk3578_reg_speed_data, offset_con, 1118 interface, speed); 1119 } 1120 1121 static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1122 bool enable) 1123 { 1124 unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO : 1125 RK3576_GMAC_CLK_SELECT_CRU; 1126 unsigned int offset_con; 1127 1128 val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE : 1129 RK3576_GMAC_CLK_RMII_GATE; 1130 1131 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1132 RK3576_GRF_GMAC_CON0; 1133 1134 regmap_write(bsp_priv->grf, offset_con, val); 1135 } 1136 1137 static const struct rk_gmac_ops rk3576_ops = { 1138 .set_to_rgmii = rk3576_set_to_rgmii, 1139 .set_to_rmii = rk3576_set_to_rmii, 1140 .set_speed = rk3576_set_gmac_speed, 1141 .set_clock_selection = rk3576_set_clock_selection, 1142 .php_grf_required = true, 1143 .regs_valid = true, 1144 .regs = { 1145 0x2a220000, /* gmac0 */ 1146 0x2a230000, /* gmac1 */ 1147 0x0, /* sentinel */ 1148 }, 1149 }; 1150 1151 /* sys_grf */ 1152 #define RK3588_GRF_GMAC_CON7 0X031c 1153 #define RK3588_GRF_GMAC_CON8 0X0320 1154 #define RK3588_GRF_GMAC_CON9 0X0324 1155 1156 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3) 1157 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3) 1158 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2) 1159 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2) 1160 1161 #define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) 1162 #define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) 1163 1164 /* php_grf */ 1165 #define RK3588_GRF_GMAC_CON0 0X0008 1166 #define RK3588_GRF_CLK_CON1 0X0070 1167 1168 #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \ 1169 (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6)) 1170 #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \ 1171 (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6)) 1172 1173 #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) 1174 #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id)) 1175 1176 #define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4) 1177 #define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4) 1178 1179 #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2) 1180 #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2) 1181 1182 #define RK3588_GMAC_CLK_RGMII_DIV1(id) \ 1183 (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3)) 1184 #define RK3588_GMAC_CLK_RGMII_DIV5(id) \ 1185 (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1186 #define RK3588_GMAC_CLK_RGMII_DIV50(id) \ 1187 (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1188 1189 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) 1190 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1) 1191 1192 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv, 1193 int tx_delay, int rx_delay) 1194 { 1195 u32 offset_con, id = bsp_priv->id; 1196 1197 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 : 1198 RK3588_GRF_GMAC_CON8; 1199 1200 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1201 RK3588_GMAC_PHY_INTF_SEL_RGMII(id)); 1202 1203 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1204 RK3588_GMAC_CLK_RGMII_MODE(id)); 1205 1206 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7, 1207 RK3588_GMAC_RXCLK_DLY_ENABLE(id) | 1208 RK3588_GMAC_TXCLK_DLY_ENABLE(id)); 1209 1210 regmap_write(bsp_priv->grf, offset_con, 1211 RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) | 1212 RK3588_GMAC_CLK_TX_DL_CFG(tx_delay)); 1213 } 1214 1215 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv) 1216 { 1217 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1218 RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id)); 1219 1220 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1221 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id)); 1222 } 1223 1224 static int rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, 1225 phy_interface_t interface, int speed) 1226 { 1227 unsigned int val = 0, id = bsp_priv->id; 1228 1229 switch (speed) { 1230 case 10: 1231 if (interface == PHY_INTERFACE_MODE_RMII) 1232 val = RK3588_GMA_CLK_RMII_DIV20(id); 1233 else 1234 val = RK3588_GMAC_CLK_RGMII_DIV50(id); 1235 break; 1236 case 100: 1237 if (interface == PHY_INTERFACE_MODE_RMII) 1238 val = RK3588_GMA_CLK_RMII_DIV2(id); 1239 else 1240 val = RK3588_GMAC_CLK_RGMII_DIV5(id); 1241 break; 1242 case 1000: 1243 if (interface != PHY_INTERFACE_MODE_RMII) 1244 val = RK3588_GMAC_CLK_RGMII_DIV1(id); 1245 else 1246 goto err; 1247 break; 1248 default: 1249 goto err; 1250 } 1251 1252 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1253 1254 return 0; 1255 err: 1256 return -EINVAL; 1257 } 1258 1259 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1260 bool enable) 1261 { 1262 unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) : 1263 RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id); 1264 1265 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) : 1266 RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id); 1267 1268 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1269 } 1270 1271 static const struct rk_gmac_ops rk3588_ops = { 1272 .set_to_rgmii = rk3588_set_to_rgmii, 1273 .set_to_rmii = rk3588_set_to_rmii, 1274 .set_speed = rk3588_set_gmac_speed, 1275 .set_clock_selection = rk3588_set_clock_selection, 1276 .php_grf_required = true, 1277 .regs_valid = true, 1278 .regs = { 1279 0xfe1b0000, /* gmac0 */ 1280 0xfe1c0000, /* gmac1 */ 1281 0x0, /* sentinel */ 1282 }, 1283 }; 1284 1285 #define RV1108_GRF_GMAC_CON0 0X0900 1286 1287 /* RV1108_GRF_GMAC_CON0 */ 1288 #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 1289 GRF_BIT(6)) 1290 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) 1291 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 1292 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2) 1293 #define RV1108_GMAC_SPEED_100M GRF_BIT(2) 1294 #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7) 1295 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 1296 1297 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) 1298 { 1299 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1300 RV1108_GMAC_PHY_INTF_SEL_RMII); 1301 } 1302 1303 static const struct rk_reg_speed_data rv1108_reg_speed_data = { 1304 .rmii_10 = RV1108_GMAC_RMII_CLK_2_5M | RV1108_GMAC_SPEED_10M, 1305 .rmii_100 = RV1108_GMAC_RMII_CLK_25M | RV1108_GMAC_SPEED_100M, 1306 }; 1307 1308 static int rv1108_set_speed(struct rk_priv_data *bsp_priv, 1309 phy_interface_t interface, int speed) 1310 { 1311 return rk_set_reg_speed(bsp_priv, &rv1108_reg_speed_data, 1312 RV1108_GRF_GMAC_CON0, interface, speed); 1313 } 1314 1315 static const struct rk_gmac_ops rv1108_ops = { 1316 .set_to_rmii = rv1108_set_to_rmii, 1317 .set_speed = rv1108_set_speed, 1318 }; 1319 1320 #define RV1126_GRF_GMAC_CON0 0X0070 1321 #define RV1126_GRF_GMAC_CON1 0X0074 1322 #define RV1126_GRF_GMAC_CON2 0X0078 1323 1324 /* RV1126_GRF_GMAC_CON0 */ 1325 #define RV1126_GMAC_PHY_INTF_SEL_RGMII \ 1326 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 1327 #define RV1126_GMAC_PHY_INTF_SEL_RMII \ 1328 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 1329 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7) 1330 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7) 1331 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1) 1332 #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 1333 #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0) 1334 #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 1335 #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3) 1336 #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3) 1337 #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2) 1338 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2) 1339 1340 /* RV1126_GRF_GMAC_CON1 */ 1341 #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1342 #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1343 /* RV1126_GRF_GMAC_CON2 */ 1344 #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1345 #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1346 1347 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv, 1348 int tx_delay, int rx_delay) 1349 { 1350 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1351 RV1126_GMAC_PHY_INTF_SEL_RGMII | 1352 RV1126_GMAC_M0_RXCLK_DLY_ENABLE | 1353 RV1126_GMAC_M0_TXCLK_DLY_ENABLE | 1354 RV1126_GMAC_M1_RXCLK_DLY_ENABLE | 1355 RV1126_GMAC_M1_TXCLK_DLY_ENABLE); 1356 1357 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1, 1358 RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) | 1359 RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay)); 1360 1361 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2, 1362 RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) | 1363 RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay)); 1364 } 1365 1366 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) 1367 { 1368 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1369 RV1126_GMAC_PHY_INTF_SEL_RMII); 1370 } 1371 1372 static const struct rk_gmac_ops rv1126_ops = { 1373 .set_to_rgmii = rv1126_set_to_rgmii, 1374 .set_to_rmii = rv1126_set_to_rmii, 1375 .set_speed = rk_set_clk_mac_speed, 1376 }; 1377 1378 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) 1379 { 1380 struct rk_priv_data *bsp_priv = plat->bsp_priv; 1381 int phy_iface = bsp_priv->phy_iface; 1382 struct device *dev = bsp_priv->dev; 1383 int i, j, ret; 1384 1385 bsp_priv->clk_enabled = false; 1386 1387 bsp_priv->num_clks = ARRAY_SIZE(rk_clocks); 1388 if (phy_iface == PHY_INTERFACE_MODE_RMII) 1389 bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks); 1390 1391 bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks, 1392 sizeof(*bsp_priv->clks), GFP_KERNEL); 1393 if (!bsp_priv->clks) 1394 return -ENOMEM; 1395 1396 for (i = 0; i < ARRAY_SIZE(rk_clocks); i++) 1397 bsp_priv->clks[i].id = rk_clocks[i]; 1398 1399 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1400 for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++) 1401 bsp_priv->clks[i++].id = rk_rmii_clocks[j]; 1402 } 1403 1404 ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks, 1405 bsp_priv->clks); 1406 if (ret) 1407 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1408 1409 if (bsp_priv->clock_input) { 1410 dev_info(dev, "clock input from PHY\n"); 1411 } else if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1412 clk_set_rate(plat->stmmac_clk, 50000000); 1413 } 1414 1415 if (plat->phy_node && bsp_priv->integrated_phy) { 1416 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); 1417 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy); 1418 if (ret) 1419 return dev_err_probe(dev, ret, "Cannot get PHY clock\n"); 1420 clk_set_rate(bsp_priv->clk_phy, 50000000); 1421 } 1422 1423 return 0; 1424 } 1425 1426 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 1427 { 1428 int ret; 1429 1430 if (enable) { 1431 if (!bsp_priv->clk_enabled) { 1432 ret = clk_bulk_prepare_enable(bsp_priv->num_clks, 1433 bsp_priv->clks); 1434 if (ret) 1435 return ret; 1436 1437 ret = clk_prepare_enable(bsp_priv->clk_phy); 1438 if (ret) 1439 return ret; 1440 1441 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1442 bsp_priv->ops->set_clock_selection(bsp_priv, 1443 bsp_priv->clock_input, true); 1444 1445 mdelay(5); 1446 bsp_priv->clk_enabled = true; 1447 } 1448 } else { 1449 if (bsp_priv->clk_enabled) { 1450 clk_bulk_disable_unprepare(bsp_priv->num_clks, 1451 bsp_priv->clks); 1452 clk_disable_unprepare(bsp_priv->clk_phy); 1453 1454 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1455 bsp_priv->ops->set_clock_selection(bsp_priv, 1456 bsp_priv->clock_input, false); 1457 1458 bsp_priv->clk_enabled = false; 1459 } 1460 } 1461 1462 return 0; 1463 } 1464 1465 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) 1466 { 1467 struct regulator *ldo = bsp_priv->regulator; 1468 struct device *dev = bsp_priv->dev; 1469 int ret; 1470 1471 if (enable) { 1472 ret = regulator_enable(ldo); 1473 if (ret) 1474 dev_err(dev, "fail to enable phy-supply\n"); 1475 } else { 1476 ret = regulator_disable(ldo); 1477 if (ret) 1478 dev_err(dev, "fail to disable phy-supply\n"); 1479 } 1480 1481 return 0; 1482 } 1483 1484 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, 1485 struct plat_stmmacenet_data *plat, 1486 const struct rk_gmac_ops *ops) 1487 { 1488 struct rk_priv_data *bsp_priv; 1489 struct device *dev = &pdev->dev; 1490 struct resource *res; 1491 int ret; 1492 const char *strings = NULL; 1493 int value; 1494 1495 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); 1496 if (!bsp_priv) 1497 return ERR_PTR(-ENOMEM); 1498 1499 bsp_priv->phy_iface = plat->phy_interface; 1500 bsp_priv->ops = ops; 1501 1502 /* Some SoCs have multiple MAC controllers, which need 1503 * to be distinguished. 1504 */ 1505 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1506 if (res && ops->regs_valid) { 1507 int i = 0; 1508 1509 while (ops->regs[i]) { 1510 if (ops->regs[i] == res->start) { 1511 bsp_priv->id = i; 1512 break; 1513 } 1514 i++; 1515 } 1516 } 1517 1518 bsp_priv->regulator = devm_regulator_get(dev, "phy"); 1519 if (IS_ERR(bsp_priv->regulator)) { 1520 ret = PTR_ERR(bsp_priv->regulator); 1521 dev_err_probe(dev, ret, "failed to get phy regulator\n"); 1522 return ERR_PTR(ret); 1523 } 1524 1525 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); 1526 if (ret) { 1527 dev_err(dev, "Can not read property: clock_in_out.\n"); 1528 bsp_priv->clock_input = true; 1529 } else { 1530 dev_info(dev, "clock input or output? (%s).\n", 1531 strings); 1532 if (!strcmp(strings, "input")) 1533 bsp_priv->clock_input = true; 1534 else 1535 bsp_priv->clock_input = false; 1536 } 1537 1538 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); 1539 if (ret) { 1540 bsp_priv->tx_delay = 0x30; 1541 dev_err(dev, "Can not read property: tx_delay."); 1542 dev_err(dev, "set tx_delay to 0x%x\n", 1543 bsp_priv->tx_delay); 1544 } else { 1545 dev_info(dev, "TX delay(0x%x).\n", value); 1546 bsp_priv->tx_delay = value; 1547 } 1548 1549 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); 1550 if (ret) { 1551 bsp_priv->rx_delay = 0x10; 1552 dev_err(dev, "Can not read property: rx_delay."); 1553 dev_err(dev, "set rx_delay to 0x%x\n", 1554 bsp_priv->rx_delay); 1555 } else { 1556 dev_info(dev, "RX delay(0x%x).\n", value); 1557 bsp_priv->rx_delay = value; 1558 } 1559 1560 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 1561 "rockchip,grf"); 1562 if (IS_ERR(bsp_priv->grf)) { 1563 dev_err_probe(dev, PTR_ERR(bsp_priv->grf), 1564 "failed to lookup rockchip,grf\n"); 1565 return ERR_CAST(bsp_priv->grf); 1566 } 1567 1568 if (ops->php_grf_required) { 1569 bsp_priv->php_grf = 1570 syscon_regmap_lookup_by_phandle(dev->of_node, 1571 "rockchip,php-grf"); 1572 if (IS_ERR(bsp_priv->php_grf)) { 1573 dev_err_probe(dev, PTR_ERR(bsp_priv->php_grf), 1574 "failed to lookup rockchip,php-grf\n"); 1575 return ERR_CAST(bsp_priv->php_grf); 1576 } 1577 } 1578 1579 if (plat->phy_node) { 1580 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, 1581 "phy-is-integrated"); 1582 if (bsp_priv->integrated_phy) { 1583 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL); 1584 if (IS_ERR(bsp_priv->phy_reset)) { 1585 dev_err(&pdev->dev, "No PHY reset control found.\n"); 1586 bsp_priv->phy_reset = NULL; 1587 } 1588 } 1589 } 1590 dev_info(dev, "integrated PHY? (%s).\n", 1591 bsp_priv->integrated_phy ? "yes" : "no"); 1592 1593 bsp_priv->dev = dev; 1594 1595 return bsp_priv; 1596 } 1597 1598 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv) 1599 { 1600 switch (bsp_priv->phy_iface) { 1601 case PHY_INTERFACE_MODE_RGMII: 1602 case PHY_INTERFACE_MODE_RGMII_ID: 1603 case PHY_INTERFACE_MODE_RGMII_RXID: 1604 case PHY_INTERFACE_MODE_RGMII_TXID: 1605 if (!bsp_priv->ops->set_to_rgmii) 1606 return -EINVAL; 1607 break; 1608 case PHY_INTERFACE_MODE_RMII: 1609 if (!bsp_priv->ops->set_to_rmii) 1610 return -EINVAL; 1611 break; 1612 default: 1613 dev_err(bsp_priv->dev, 1614 "unsupported interface %d", bsp_priv->phy_iface); 1615 } 1616 return 0; 1617 } 1618 1619 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) 1620 { 1621 struct device *dev = bsp_priv->dev; 1622 int ret; 1623 1624 ret = rk_gmac_check_ops(bsp_priv); 1625 if (ret) 1626 return ret; 1627 1628 ret = gmac_clk_enable(bsp_priv, true); 1629 if (ret) 1630 return ret; 1631 1632 /*rmii or rgmii*/ 1633 switch (bsp_priv->phy_iface) { 1634 case PHY_INTERFACE_MODE_RGMII: 1635 dev_info(dev, "init for RGMII\n"); 1636 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 1637 bsp_priv->rx_delay); 1638 break; 1639 case PHY_INTERFACE_MODE_RGMII_ID: 1640 dev_info(dev, "init for RGMII_ID\n"); 1641 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); 1642 break; 1643 case PHY_INTERFACE_MODE_RGMII_RXID: 1644 dev_info(dev, "init for RGMII_RXID\n"); 1645 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); 1646 break; 1647 case PHY_INTERFACE_MODE_RGMII_TXID: 1648 dev_info(dev, "init for RGMII_TXID\n"); 1649 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); 1650 break; 1651 case PHY_INTERFACE_MODE_RMII: 1652 dev_info(dev, "init for RMII\n"); 1653 bsp_priv->ops->set_to_rmii(bsp_priv); 1654 break; 1655 default: 1656 dev_err(dev, "NO interface defined!\n"); 1657 } 1658 1659 ret = phy_power_on(bsp_priv, true); 1660 if (ret) { 1661 gmac_clk_enable(bsp_priv, false); 1662 return ret; 1663 } 1664 1665 pm_runtime_get_sync(dev); 1666 1667 if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup) 1668 bsp_priv->ops->integrated_phy_powerup(bsp_priv); 1669 1670 return 0; 1671 } 1672 1673 static void rk_gmac_powerdown(struct rk_priv_data *gmac) 1674 { 1675 if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown) 1676 gmac->ops->integrated_phy_powerdown(gmac); 1677 1678 pm_runtime_put_sync(gmac->dev); 1679 1680 phy_power_on(gmac, false); 1681 gmac_clk_enable(gmac, false); 1682 } 1683 1684 static void rk_get_interfaces(struct stmmac_priv *priv, void *bsp_priv, 1685 unsigned long *interfaces) 1686 { 1687 struct rk_priv_data *rk = bsp_priv; 1688 1689 if (rk->ops->set_to_rgmii) 1690 phy_interface_set_rgmii(interfaces); 1691 1692 if (rk->ops->set_to_rmii) 1693 __set_bit(PHY_INTERFACE_MODE_RMII, interfaces); 1694 } 1695 1696 static int rk_set_clk_tx_rate(void *bsp_priv_, struct clk *clk_tx_i, 1697 phy_interface_t interface, int speed) 1698 { 1699 struct rk_priv_data *bsp_priv = bsp_priv_; 1700 1701 if (bsp_priv->ops->set_speed) 1702 return bsp_priv->ops->set_speed(bsp_priv, bsp_priv->phy_iface, 1703 speed); 1704 1705 return -EINVAL; 1706 } 1707 1708 static int rk_gmac_suspend(struct device *dev, void *bsp_priv_) 1709 { 1710 struct rk_priv_data *bsp_priv = bsp_priv_; 1711 1712 /* Keep the PHY up if we use Wake-on-Lan. */ 1713 if (!device_may_wakeup(dev)) 1714 rk_gmac_powerdown(bsp_priv); 1715 1716 return 0; 1717 } 1718 1719 static int rk_gmac_resume(struct device *dev, void *bsp_priv_) 1720 { 1721 struct rk_priv_data *bsp_priv = bsp_priv_; 1722 1723 /* The PHY was up for Wake-on-Lan. */ 1724 if (!device_may_wakeup(dev)) 1725 rk_gmac_powerup(bsp_priv); 1726 1727 return 0; 1728 } 1729 1730 static int rk_gmac_probe(struct platform_device *pdev) 1731 { 1732 struct plat_stmmacenet_data *plat_dat; 1733 struct stmmac_resources stmmac_res; 1734 const struct rk_gmac_ops *data; 1735 int ret; 1736 1737 data = of_device_get_match_data(&pdev->dev); 1738 if (!data) { 1739 dev_err(&pdev->dev, "no of match data provided\n"); 1740 return -EINVAL; 1741 } 1742 1743 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1744 if (ret) 1745 return ret; 1746 1747 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 1748 if (IS_ERR(plat_dat)) 1749 return PTR_ERR(plat_dat); 1750 1751 /* If the stmmac is not already selected as gmac4, 1752 * then make sure we fallback to gmac. 1753 */ 1754 if (!plat_dat->has_gmac4) { 1755 plat_dat->has_gmac = true; 1756 plat_dat->rx_fifo_size = 4096; 1757 plat_dat->tx_fifo_size = 2048; 1758 } 1759 1760 plat_dat->get_interfaces = rk_get_interfaces; 1761 plat_dat->set_clk_tx_rate = rk_set_clk_tx_rate; 1762 plat_dat->suspend = rk_gmac_suspend; 1763 plat_dat->resume = rk_gmac_resume; 1764 1765 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data); 1766 if (IS_ERR(plat_dat->bsp_priv)) 1767 return PTR_ERR(plat_dat->bsp_priv); 1768 1769 ret = rk_gmac_clk_init(plat_dat); 1770 if (ret) 1771 return ret; 1772 1773 ret = rk_gmac_powerup(plat_dat->bsp_priv); 1774 if (ret) 1775 return ret; 1776 1777 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1778 if (ret) 1779 goto err_gmac_powerdown; 1780 1781 return 0; 1782 1783 err_gmac_powerdown: 1784 rk_gmac_powerdown(plat_dat->bsp_priv); 1785 1786 return ret; 1787 } 1788 1789 static void rk_gmac_remove(struct platform_device *pdev) 1790 { 1791 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev); 1792 1793 stmmac_dvr_remove(&pdev->dev); 1794 1795 rk_gmac_powerdown(bsp_priv); 1796 } 1797 1798 static const struct of_device_id rk_gmac_dwmac_match[] = { 1799 { .compatible = "rockchip,px30-gmac", .data = &px30_ops }, 1800 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops }, 1801 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops }, 1802 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops }, 1803 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops }, 1804 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops }, 1805 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, 1806 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, 1807 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, 1808 { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops }, 1809 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops }, 1810 { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops }, 1811 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops }, 1812 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops }, 1813 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops }, 1814 { } 1815 }; 1816 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); 1817 1818 static struct platform_driver rk_gmac_dwmac_driver = { 1819 .probe = rk_gmac_probe, 1820 .remove = rk_gmac_remove, 1821 .driver = { 1822 .name = "rk_gmac-dwmac", 1823 .pm = &stmmac_simple_pm_ops, 1824 .of_match_table = rk_gmac_dwmac_match, 1825 }, 1826 }; 1827 module_platform_driver(rk_gmac_dwmac_driver); 1828 1829 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>"); 1830 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer"); 1831 MODULE_LICENSE("GPL"); 1832