1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /** 3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer 4 * 5 * Copyright (C) 2014 Chen-Zhi (Roger Chen) 6 * 7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> 8 */ 9 10 #include <linux/stmmac.h> 11 #include <linux/hw_bitfield.h> 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/phy.h> 15 #include <linux/of_net.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/delay.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/regmap.h> 23 #include <linux/pm_runtime.h> 24 25 #include "stmmac_platform.h" 26 27 struct rk_priv_data; 28 29 struct rk_reg_speed_data { 30 unsigned int rgmii_10; 31 unsigned int rgmii_100; 32 unsigned int rgmii_1000; 33 unsigned int rmii_10; 34 unsigned int rmii_100; 35 }; 36 37 struct rk_gmac_ops { 38 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, 39 int tx_delay, int rx_delay); 40 void (*set_to_rmii)(struct rk_priv_data *bsp_priv); 41 int (*set_speed)(struct rk_priv_data *bsp_priv, 42 phy_interface_t interface, int speed); 43 void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, 44 bool enable); 45 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); 46 void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv); 47 bool php_grf_required; 48 bool regs_valid; 49 u32 regs[]; 50 }; 51 52 static const char * const rk_clocks[] = { 53 "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed", 54 }; 55 56 static const char * const rk_rmii_clocks[] = { 57 "mac_clk_rx", "clk_mac_ref", "clk_mac_refout", 58 }; 59 60 enum rk_clocks_index { 61 RK_ACLK_MAC = 0, 62 RK_PCLK_MAC, 63 RK_MAC_CLK_TX, 64 RK_CLK_MAC_SPEED, 65 RK_MAC_CLK_RX, 66 RK_CLK_MAC_REF, 67 RK_CLK_MAC_REFOUT, 68 }; 69 70 struct rk_priv_data { 71 struct device *dev; 72 phy_interface_t phy_iface; 73 int id; 74 struct regulator *regulator; 75 bool suspended; 76 const struct rk_gmac_ops *ops; 77 78 bool clk_enabled; 79 bool clock_input; 80 bool integrated_phy; 81 82 struct clk_bulk_data *clks; 83 int num_clks; 84 struct clk *clk_phy; 85 86 struct reset_control *phy_reset; 87 88 int tx_delay; 89 int rx_delay; 90 91 struct regmap *grf; 92 struct regmap *php_grf; 93 }; 94 95 static int rk_set_reg_speed(struct rk_priv_data *bsp_priv, 96 const struct rk_reg_speed_data *rsd, 97 unsigned int reg, phy_interface_t interface, 98 int speed) 99 { 100 unsigned int val; 101 102 if (phy_interface_mode_is_rgmii(interface)) { 103 if (speed == SPEED_10) { 104 val = rsd->rgmii_10; 105 } else if (speed == SPEED_100) { 106 val = rsd->rgmii_100; 107 } else if (speed == SPEED_1000) { 108 val = rsd->rgmii_1000; 109 } else { 110 /* Phylink will not allow inappropriate speeds for 111 * interface modes, so this should never happen. 112 */ 113 return -EINVAL; 114 } 115 } else if (interface == PHY_INTERFACE_MODE_RMII) { 116 if (speed == SPEED_10) { 117 val = rsd->rmii_10; 118 } else if (speed == SPEED_100) { 119 val = rsd->rmii_100; 120 } else { 121 /* Phylink will not allow inappropriate speeds for 122 * interface modes, so this should never happen. 123 */ 124 return -EINVAL; 125 } 126 } else { 127 /* This should never happen, as .get_interfaces() limits 128 * the interface modes that are supported to RGMII and/or 129 * RMII. 130 */ 131 return -EINVAL; 132 } 133 134 regmap_write(bsp_priv->grf, reg, val); 135 136 return 0; 137 138 } 139 140 static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv, 141 phy_interface_t interface, int speed) 142 { 143 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 144 long rate; 145 146 rate = rgmii_clock(speed); 147 if (rate < 0) 148 return rate; 149 150 return clk_set_rate(clk_mac_speed, rate); 151 } 152 153 #define HIWORD_UPDATE(val, mask, shift) \ 154 (FIELD_PREP_WM16((mask) << (shift), (val))) 155 156 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 157 #define GRF_CLR_BIT(nr) (BIT(nr+16)) 158 159 #define DELAY_ENABLE(soc, tx, rx) \ 160 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ 161 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) 162 163 #define RK_GRF_MACPHY_CON0 0xb00 164 #define RK_GRF_MACPHY_CON1 0xb04 165 #define RK_GRF_MACPHY_CON2 0xb08 166 #define RK_GRF_MACPHY_CON3 0xb0c 167 168 #define RK_MACPHY_ENABLE GRF_BIT(0) 169 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0) 170 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) 171 #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) 172 #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) 173 #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) 174 175 static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv) 176 { 177 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); 178 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); 179 180 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); 181 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); 182 183 if (priv->phy_reset) { 184 /* PHY needs to be disabled before trying to reset it */ 185 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 186 if (priv->phy_reset) 187 reset_control_assert(priv->phy_reset); 188 usleep_range(10, 20); 189 if (priv->phy_reset) 190 reset_control_deassert(priv->phy_reset); 191 usleep_range(10, 20); 192 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); 193 msleep(30); 194 } 195 } 196 197 static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv) 198 { 199 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 200 if (priv->phy_reset) 201 reset_control_assert(priv->phy_reset); 202 } 203 204 #define RK_FEPHY_SHUTDOWN GRF_BIT(1) 205 #define RK_FEPHY_POWERUP GRF_CLR_BIT(1) 206 #define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6) 207 #define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9)) 208 #define RK_FEPHY_PHY_ID GRF_BIT(11) 209 210 static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv, 211 unsigned int reg) 212 { 213 reset_control_assert(priv->phy_reset); 214 usleep_range(20, 30); 215 216 regmap_write(priv->grf, reg, 217 RK_FEPHY_POWERUP | 218 RK_FEPHY_INTERNAL_RMII_SEL | 219 RK_FEPHY_24M_CLK_SEL | 220 RK_FEPHY_PHY_ID); 221 usleep_range(10000, 12000); 222 223 reset_control_deassert(priv->phy_reset); 224 usleep_range(50000, 60000); 225 } 226 227 static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv, 228 unsigned int reg) 229 { 230 regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN); 231 } 232 233 #define PX30_GRF_GMAC_CON1 0x0904 234 235 /* PX30_GRF_GMAC_CON1 */ 236 #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 237 GRF_BIT(6)) 238 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2) 239 #define PX30_GMAC_SPEED_100M GRF_BIT(2) 240 241 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) 242 { 243 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 244 PX30_GMAC_PHY_INTF_SEL_RMII); 245 } 246 247 static int px30_set_speed(struct rk_priv_data *bsp_priv, 248 phy_interface_t interface, int speed) 249 { 250 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 251 struct device *dev = bsp_priv->dev; 252 unsigned int con1; 253 long rate; 254 255 if (!clk_mac_speed) { 256 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__); 257 return -EINVAL; 258 } 259 260 if (speed == 10) { 261 con1 = PX30_GMAC_SPEED_10M; 262 rate = 2500000; 263 } else if (speed == 100) { 264 con1 = PX30_GMAC_SPEED_100M; 265 rate = 25000000; 266 } else { 267 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 268 return -EINVAL; 269 } 270 271 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, con1); 272 273 return clk_set_rate(clk_mac_speed, rate); 274 } 275 276 static const struct rk_gmac_ops px30_ops = { 277 .set_to_rmii = px30_set_to_rmii, 278 .set_speed = px30_set_speed, 279 }; 280 281 #define RK3128_GRF_MAC_CON0 0x0168 282 #define RK3128_GRF_MAC_CON1 0x016c 283 284 /* RK3128_GRF_MAC_CON0 */ 285 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 286 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 287 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 288 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 289 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 290 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 291 292 /* RK3128_GRF_MAC_CON1 */ 293 #define RK3128_GMAC_PHY_INTF_SEL_RGMII \ 294 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8)) 295 #define RK3128_GMAC_PHY_INTF_SEL_RMII \ 296 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8)) 297 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9) 298 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 299 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10) 300 #define RK3128_GMAC_SPEED_100M GRF_BIT(10) 301 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11) 302 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 303 #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 304 #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 305 #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 306 #define RK3128_GMAC_RMII_MODE GRF_BIT(14) 307 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 308 309 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, 310 int tx_delay, int rx_delay) 311 { 312 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 313 RK3128_GMAC_PHY_INTF_SEL_RGMII | 314 RK3128_GMAC_RMII_MODE_CLR); 315 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0, 316 DELAY_ENABLE(RK3128, tx_delay, rx_delay) | 317 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) | 318 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay)); 319 } 320 321 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) 322 { 323 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 324 RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE); 325 } 326 327 static const struct rk_reg_speed_data rk3128_reg_speed_data = { 328 .rgmii_10 = RK3128_GMAC_CLK_2_5M, 329 .rgmii_100 = RK3128_GMAC_CLK_25M, 330 .rgmii_1000 = RK3128_GMAC_CLK_125M, 331 .rmii_10 = RK3128_GMAC_RMII_CLK_2_5M | RK3128_GMAC_SPEED_10M, 332 .rmii_100 = RK3128_GMAC_RMII_CLK_25M | RK3128_GMAC_SPEED_100M, 333 }; 334 335 static int rk3128_set_speed(struct rk_priv_data *bsp_priv, 336 phy_interface_t interface, int speed) 337 { 338 return rk_set_reg_speed(bsp_priv, &rk3128_reg_speed_data, 339 RK3128_GRF_MAC_CON1, interface, speed); 340 } 341 342 static const struct rk_gmac_ops rk3128_ops = { 343 .set_to_rgmii = rk3128_set_to_rgmii, 344 .set_to_rmii = rk3128_set_to_rmii, 345 .set_speed = rk3128_set_speed, 346 }; 347 348 #define RK3228_GRF_MAC_CON0 0x0900 349 #define RK3228_GRF_MAC_CON1 0x0904 350 351 #define RK3228_GRF_CON_MUX 0x50 352 353 /* RK3228_GRF_MAC_CON0 */ 354 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 355 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 356 357 /* RK3228_GRF_MAC_CON1 */ 358 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ 359 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 360 #define RK3228_GMAC_PHY_INTF_SEL_RMII \ 361 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 362 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) 363 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 364 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) 365 #define RK3228_GMAC_SPEED_100M GRF_BIT(2) 366 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) 367 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 368 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) 369 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) 370 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) 371 #define RK3228_GMAC_RMII_MODE GRF_BIT(10) 372 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) 373 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 374 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 375 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 376 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 377 378 /* RK3228_GRF_COM_MUX */ 379 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15) 380 381 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, 382 int tx_delay, int rx_delay) 383 { 384 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 385 RK3228_GMAC_PHY_INTF_SEL_RGMII | 386 RK3228_GMAC_RMII_MODE_CLR | 387 DELAY_ENABLE(RK3228, tx_delay, rx_delay)); 388 389 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, 390 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | 391 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); 392 } 393 394 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) 395 { 396 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 397 RK3228_GMAC_PHY_INTF_SEL_RMII | 398 RK3228_GMAC_RMII_MODE); 399 400 /* set MAC to RMII mode */ 401 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); 402 } 403 404 static const struct rk_reg_speed_data rk3228_reg_speed_data = { 405 .rgmii_10 = RK3228_GMAC_CLK_2_5M, 406 .rgmii_100 = RK3228_GMAC_CLK_25M, 407 .rgmii_1000 = RK3228_GMAC_CLK_125M, 408 .rmii_10 = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_SPEED_10M, 409 .rmii_100 = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_SPEED_100M, 410 }; 411 412 static int rk3228_set_speed(struct rk_priv_data *bsp_priv, 413 phy_interface_t interface, int speed) 414 { 415 return rk_set_reg_speed(bsp_priv, &rk3228_reg_speed_data, 416 RK3228_GRF_MAC_CON1, interface, speed); 417 } 418 419 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) 420 { 421 regmap_write(priv->grf, RK3228_GRF_CON_MUX, 422 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 423 424 rk_gmac_integrated_ephy_powerup(priv); 425 } 426 427 static const struct rk_gmac_ops rk3228_ops = { 428 .set_to_rgmii = rk3228_set_to_rgmii, 429 .set_to_rmii = rk3228_set_to_rmii, 430 .set_speed = rk3228_set_speed, 431 .integrated_phy_powerup = rk3228_integrated_phy_powerup, 432 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, 433 }; 434 435 #define RK3288_GRF_SOC_CON1 0x0248 436 #define RK3288_GRF_SOC_CON3 0x0250 437 438 /*RK3288_GRF_SOC_CON1*/ 439 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ 440 GRF_CLR_BIT(8)) 441 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ 442 GRF_BIT(8)) 443 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) 444 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 445 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) 446 #define RK3288_GMAC_SPEED_100M GRF_BIT(10) 447 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) 448 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 449 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 450 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 451 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 452 #define RK3288_GMAC_RMII_MODE GRF_BIT(14) 453 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 454 455 /*RK3288_GRF_SOC_CON3*/ 456 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 457 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 458 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 459 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 460 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 461 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 462 463 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 464 int tx_delay, int rx_delay) 465 { 466 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 467 RK3288_GMAC_PHY_INTF_SEL_RGMII | 468 RK3288_GMAC_RMII_MODE_CLR); 469 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 470 DELAY_ENABLE(RK3288, tx_delay, rx_delay) | 471 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | 472 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); 473 } 474 475 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 476 { 477 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 478 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); 479 } 480 481 static const struct rk_reg_speed_data rk3288_reg_speed_data = { 482 .rgmii_10 = RK3288_GMAC_CLK_2_5M, 483 .rgmii_100 = RK3288_GMAC_CLK_25M, 484 .rgmii_1000 = RK3288_GMAC_CLK_125M, 485 .rmii_10 = RK3288_GMAC_RMII_CLK_2_5M | RK3288_GMAC_SPEED_10M, 486 .rmii_100 = RK3288_GMAC_RMII_CLK_25M | RK3288_GMAC_SPEED_100M, 487 }; 488 489 static int rk3288_set_speed(struct rk_priv_data *bsp_priv, 490 phy_interface_t interface, int speed) 491 { 492 return rk_set_reg_speed(bsp_priv, &rk3288_reg_speed_data, 493 RK3288_GRF_SOC_CON1, interface, speed); 494 } 495 496 static const struct rk_gmac_ops rk3288_ops = { 497 .set_to_rgmii = rk3288_set_to_rgmii, 498 .set_to_rmii = rk3288_set_to_rmii, 499 .set_speed = rk3288_set_speed, 500 }; 501 502 #define RK3308_GRF_MAC_CON0 0x04a0 503 504 /* RK3308_GRF_MAC_CON0 */ 505 #define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \ 506 GRF_BIT(4)) 507 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3) 508 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 509 #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0) 510 #define RK3308_GMAC_SPEED_100M GRF_BIT(0) 511 512 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) 513 { 514 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 515 RK3308_GMAC_PHY_INTF_SEL_RMII); 516 } 517 518 static const struct rk_reg_speed_data rk3308_reg_speed_data = { 519 .rmii_10 = RK3308_GMAC_SPEED_10M, 520 .rmii_100 = RK3308_GMAC_SPEED_100M, 521 }; 522 523 static int rk3308_set_speed(struct rk_priv_data *bsp_priv, 524 phy_interface_t interface, int speed) 525 { 526 return rk_set_reg_speed(bsp_priv, &rk3308_reg_speed_data, 527 RK3308_GRF_MAC_CON0, interface, speed); 528 } 529 530 static const struct rk_gmac_ops rk3308_ops = { 531 .set_to_rmii = rk3308_set_to_rmii, 532 .set_speed = rk3308_set_speed, 533 }; 534 535 #define RK3328_GRF_MAC_CON0 0x0900 536 #define RK3328_GRF_MAC_CON1 0x0904 537 #define RK3328_GRF_MAC_CON2 0x0908 538 #define RK3328_GRF_MACPHY_CON1 0xb04 539 540 /* RK3328_GRF_MAC_CON0 */ 541 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 542 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 543 544 /* RK3328_GRF_MAC_CON1 */ 545 #define RK3328_GMAC_PHY_INTF_SEL_RGMII \ 546 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 547 #define RK3328_GMAC_PHY_INTF_SEL_RMII \ 548 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 549 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) 550 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 551 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) 552 #define RK3328_GMAC_SPEED_100M GRF_BIT(2) 553 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) 554 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 555 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12)) 556 #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12)) 557 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12)) 558 #define RK3328_GMAC_RMII_MODE GRF_BIT(9) 559 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) 560 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 561 #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 562 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 563 #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0) 564 565 /* RK3328_GRF_MACPHY_CON1 */ 566 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9) 567 568 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, 569 int tx_delay, int rx_delay) 570 { 571 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 572 RK3328_GMAC_PHY_INTF_SEL_RGMII | 573 RK3328_GMAC_RMII_MODE_CLR | 574 RK3328_GMAC_RXCLK_DLY_ENABLE | 575 RK3328_GMAC_TXCLK_DLY_ENABLE); 576 577 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0, 578 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) | 579 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); 580 } 581 582 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) 583 { 584 unsigned int reg; 585 586 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : 587 RK3328_GRF_MAC_CON1; 588 589 regmap_write(bsp_priv->grf, reg, 590 RK3328_GMAC_PHY_INTF_SEL_RMII | 591 RK3328_GMAC_RMII_MODE); 592 } 593 594 static const struct rk_reg_speed_data rk3328_reg_speed_data = { 595 .rgmii_10 = RK3328_GMAC_CLK_2_5M, 596 .rgmii_100 = RK3328_GMAC_CLK_25M, 597 .rgmii_1000 = RK3328_GMAC_CLK_125M, 598 .rmii_10 = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_SPEED_10M, 599 .rmii_100 = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_SPEED_100M, 600 }; 601 602 static int rk3328_set_speed(struct rk_priv_data *bsp_priv, 603 phy_interface_t interface, int speed) 604 { 605 unsigned int reg; 606 607 if (interface == PHY_INTERFACE_MODE_RMII && bsp_priv->integrated_phy) 608 reg = RK3328_GRF_MAC_CON2; 609 else 610 reg = RK3328_GRF_MAC_CON1; 611 612 return rk_set_reg_speed(bsp_priv, &rk3328_reg_speed_data, reg, 613 interface, speed); 614 } 615 616 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) 617 { 618 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, 619 RK3328_MACPHY_RMII_MODE); 620 621 rk_gmac_integrated_ephy_powerup(priv); 622 } 623 624 static const struct rk_gmac_ops rk3328_ops = { 625 .set_to_rgmii = rk3328_set_to_rgmii, 626 .set_to_rmii = rk3328_set_to_rmii, 627 .set_speed = rk3328_set_speed, 628 .integrated_phy_powerup = rk3328_integrated_phy_powerup, 629 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, 630 }; 631 632 #define RK3366_GRF_SOC_CON6 0x0418 633 #define RK3366_GRF_SOC_CON7 0x041c 634 635 /* RK3366_GRF_SOC_CON6 */ 636 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 637 GRF_CLR_BIT(11)) 638 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 639 GRF_BIT(11)) 640 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) 641 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 642 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) 643 #define RK3366_GMAC_SPEED_100M GRF_BIT(7) 644 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) 645 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 646 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 647 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 648 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 649 #define RK3366_GMAC_RMII_MODE GRF_BIT(6) 650 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 651 652 /* RK3366_GRF_SOC_CON7 */ 653 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 654 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 655 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 656 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 657 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 658 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 659 660 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 661 int tx_delay, int rx_delay) 662 { 663 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 664 RK3366_GMAC_PHY_INTF_SEL_RGMII | 665 RK3366_GMAC_RMII_MODE_CLR); 666 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, 667 DELAY_ENABLE(RK3366, tx_delay, rx_delay) | 668 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | 669 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); 670 } 671 672 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 673 { 674 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 675 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); 676 } 677 678 static const struct rk_reg_speed_data rk3366_reg_speed_data = { 679 .rgmii_10 = RK3366_GMAC_CLK_2_5M, 680 .rgmii_100 = RK3366_GMAC_CLK_25M, 681 .rgmii_1000 = RK3366_GMAC_CLK_125M, 682 .rmii_10 = RK3366_GMAC_RMII_CLK_2_5M | RK3366_GMAC_SPEED_10M, 683 .rmii_100 = RK3366_GMAC_RMII_CLK_25M | RK3366_GMAC_SPEED_100M, 684 }; 685 686 static int rk3366_set_speed(struct rk_priv_data *bsp_priv, 687 phy_interface_t interface, int speed) 688 { 689 return rk_set_reg_speed(bsp_priv, &rk3366_reg_speed_data, 690 RK3366_GRF_SOC_CON6, interface, speed); 691 } 692 693 static const struct rk_gmac_ops rk3366_ops = { 694 .set_to_rgmii = rk3366_set_to_rgmii, 695 .set_to_rmii = rk3366_set_to_rmii, 696 .set_speed = rk3366_set_speed, 697 }; 698 699 #define RK3368_GRF_SOC_CON15 0x043c 700 #define RK3368_GRF_SOC_CON16 0x0440 701 702 /* RK3368_GRF_SOC_CON15 */ 703 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 704 GRF_CLR_BIT(11)) 705 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 706 GRF_BIT(11)) 707 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) 708 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 709 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) 710 #define RK3368_GMAC_SPEED_100M GRF_BIT(7) 711 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) 712 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 713 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 714 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 715 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 716 #define RK3368_GMAC_RMII_MODE GRF_BIT(6) 717 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 718 719 /* RK3368_GRF_SOC_CON16 */ 720 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 721 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 722 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 723 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 724 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 725 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 726 727 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 728 int tx_delay, int rx_delay) 729 { 730 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 731 RK3368_GMAC_PHY_INTF_SEL_RGMII | 732 RK3368_GMAC_RMII_MODE_CLR); 733 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, 734 DELAY_ENABLE(RK3368, tx_delay, rx_delay) | 735 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | 736 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); 737 } 738 739 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 740 { 741 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 742 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); 743 } 744 745 static const struct rk_reg_speed_data rk3368_reg_speed_data = { 746 .rgmii_10 = RK3368_GMAC_CLK_2_5M, 747 .rgmii_100 = RK3368_GMAC_CLK_25M, 748 .rgmii_1000 = RK3368_GMAC_CLK_125M, 749 .rmii_10 = RK3368_GMAC_RMII_CLK_2_5M | RK3368_GMAC_SPEED_10M, 750 .rmii_100 = RK3368_GMAC_RMII_CLK_25M | RK3368_GMAC_SPEED_100M, 751 }; 752 753 static int rk3368_set_speed(struct rk_priv_data *bsp_priv, 754 phy_interface_t interface, int speed) 755 { 756 return rk_set_reg_speed(bsp_priv, &rk3368_reg_speed_data, 757 RK3368_GRF_SOC_CON15, interface, speed); 758 } 759 760 static const struct rk_gmac_ops rk3368_ops = { 761 .set_to_rgmii = rk3368_set_to_rgmii, 762 .set_to_rmii = rk3368_set_to_rmii, 763 .set_speed = rk3368_set_speed, 764 }; 765 766 #define RK3399_GRF_SOC_CON5 0xc214 767 #define RK3399_GRF_SOC_CON6 0xc218 768 769 /* RK3399_GRF_SOC_CON5 */ 770 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 771 GRF_CLR_BIT(11)) 772 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 773 GRF_BIT(11)) 774 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) 775 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 776 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) 777 #define RK3399_GMAC_SPEED_100M GRF_BIT(7) 778 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) 779 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 780 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 781 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 782 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 783 #define RK3399_GMAC_RMII_MODE GRF_BIT(6) 784 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 785 786 /* RK3399_GRF_SOC_CON6 */ 787 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 788 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 789 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 790 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 791 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 792 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 793 794 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 795 int tx_delay, int rx_delay) 796 { 797 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 798 RK3399_GMAC_PHY_INTF_SEL_RGMII | 799 RK3399_GMAC_RMII_MODE_CLR); 800 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, 801 DELAY_ENABLE(RK3399, tx_delay, rx_delay) | 802 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | 803 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); 804 } 805 806 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 807 { 808 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 809 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); 810 } 811 812 static const struct rk_reg_speed_data rk3399_reg_speed_data = { 813 .rgmii_10 = RK3399_GMAC_CLK_2_5M, 814 .rgmii_100 = RK3399_GMAC_CLK_25M, 815 .rgmii_1000 = RK3399_GMAC_CLK_125M, 816 .rmii_10 = RK3399_GMAC_RMII_CLK_2_5M | RK3399_GMAC_SPEED_10M, 817 .rmii_100 = RK3399_GMAC_RMII_CLK_25M | RK3399_GMAC_SPEED_100M, 818 }; 819 820 static int rk3399_set_speed(struct rk_priv_data *bsp_priv, 821 phy_interface_t interface, int speed) 822 { 823 return rk_set_reg_speed(bsp_priv, &rk3399_reg_speed_data, 824 RK3399_GRF_SOC_CON5, interface, speed); 825 } 826 827 static const struct rk_gmac_ops rk3399_ops = { 828 .set_to_rgmii = rk3399_set_to_rgmii, 829 .set_to_rmii = rk3399_set_to_rmii, 830 .set_speed = rk3399_set_speed, 831 }; 832 833 #define RK3528_VO_GRF_GMAC_CON 0x0018 834 #define RK3528_VO_GRF_MACPHY_CON0 0x001c 835 #define RK3528_VO_GRF_MACPHY_CON1 0x0020 836 #define RK3528_VPU_GRF_GMAC_CON5 0x0018 837 #define RK3528_VPU_GRF_GMAC_CON6 0x001c 838 839 #define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 840 #define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 841 #define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 842 #define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 843 844 #define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) 845 #define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) 846 847 #define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1) 848 #define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8) 849 #define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8) 850 851 #define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12) 852 #define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12) 853 854 #define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3) 855 #define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3) 856 #define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10) 857 #define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10) 858 859 #define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10)) 860 #define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10)) 861 #define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10)) 862 863 #define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) 864 #define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) 865 #define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9) 866 #define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9) 867 868 static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv, 869 int tx_delay, int rx_delay) 870 { 871 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 872 RK3528_GMAC1_PHY_INTF_SEL_RGMII); 873 874 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 875 DELAY_ENABLE(RK3528, tx_delay, rx_delay)); 876 877 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6, 878 RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) | 879 RK3528_GMAC_CLK_TX_DL_CFG(tx_delay)); 880 } 881 882 static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv) 883 { 884 if (bsp_priv->id == 1) 885 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 886 RK3528_GMAC1_PHY_INTF_SEL_RMII); 887 else 888 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, 889 RK3528_GMAC0_PHY_INTF_SEL_RMII | 890 RK3528_GMAC0_CLK_RMII_DIV2); 891 } 892 893 static const struct rk_reg_speed_data rk3528_gmac0_reg_speed_data = { 894 .rmii_10 = RK3528_GMAC0_CLK_RMII_DIV20, 895 .rmii_100 = RK3528_GMAC0_CLK_RMII_DIV2, 896 }; 897 898 static const struct rk_reg_speed_data rk3528_gmac1_reg_speed_data = { 899 .rgmii_10 = RK3528_GMAC1_CLK_RGMII_DIV50, 900 .rgmii_100 = RK3528_GMAC1_CLK_RGMII_DIV5, 901 .rgmii_1000 = RK3528_GMAC1_CLK_RGMII_DIV1, 902 .rmii_10 = RK3528_GMAC1_CLK_RMII_DIV20, 903 .rmii_100 = RK3528_GMAC1_CLK_RMII_DIV2, 904 }; 905 906 static int rk3528_set_speed(struct rk_priv_data *bsp_priv, 907 phy_interface_t interface, int speed) 908 { 909 const struct rk_reg_speed_data *rsd; 910 unsigned int reg; 911 912 if (bsp_priv->id == 1) { 913 rsd = &rk3528_gmac1_reg_speed_data; 914 reg = RK3528_VPU_GRF_GMAC_CON5; 915 } else { 916 rsd = &rk3528_gmac0_reg_speed_data; 917 reg = RK3528_VO_GRF_GMAC_CON; 918 } 919 920 return rk_set_reg_speed(bsp_priv, rsd, reg, interface, speed); 921 } 922 923 static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv, 924 bool input, bool enable) 925 { 926 unsigned int val; 927 928 if (bsp_priv->id == 1) { 929 val = input ? RK3528_GMAC1_CLK_SELECT_IO : 930 RK3528_GMAC1_CLK_SELECT_CRU; 931 val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE : 932 RK3528_GMAC1_CLK_RMII_GATE; 933 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val); 934 } else { 935 val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE : 936 RK3528_GMAC0_CLK_RMII_GATE; 937 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val); 938 } 939 } 940 941 static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv) 942 { 943 rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); 944 } 945 946 static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv) 947 { 948 rk_gmac_integrated_fephy_powerdown(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); 949 } 950 951 static const struct rk_gmac_ops rk3528_ops = { 952 .set_to_rgmii = rk3528_set_to_rgmii, 953 .set_to_rmii = rk3528_set_to_rmii, 954 .set_speed = rk3528_set_speed, 955 .set_clock_selection = rk3528_set_clock_selection, 956 .integrated_phy_powerup = rk3528_integrated_phy_powerup, 957 .integrated_phy_powerdown = rk3528_integrated_phy_powerdown, 958 .regs_valid = true, 959 .regs = { 960 0xffbd0000, /* gmac0 */ 961 0xffbe0000, /* gmac1 */ 962 0x0, /* sentinel */ 963 }, 964 }; 965 966 #define RK3568_GRF_GMAC0_CON0 0x0380 967 #define RK3568_GRF_GMAC0_CON1 0x0384 968 #define RK3568_GRF_GMAC1_CON0 0x0388 969 #define RK3568_GRF_GMAC1_CON1 0x038c 970 971 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ 972 #define RK3568_GMAC_PHY_INTF_SEL_RGMII \ 973 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 974 #define RK3568_GMAC_PHY_INTF_SEL_RMII \ 975 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 976 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) 977 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 978 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 979 #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 980 #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 981 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 982 983 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ 984 #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 985 #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 986 987 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, 988 int tx_delay, int rx_delay) 989 { 990 u32 con0, con1; 991 992 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 : 993 RK3568_GRF_GMAC0_CON0; 994 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 995 RK3568_GRF_GMAC0_CON1; 996 997 regmap_write(bsp_priv->grf, con0, 998 RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) | 999 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay)); 1000 1001 regmap_write(bsp_priv->grf, con1, 1002 RK3568_GMAC_PHY_INTF_SEL_RGMII | 1003 RK3568_GMAC_RXCLK_DLY_ENABLE | 1004 RK3568_GMAC_TXCLK_DLY_ENABLE); 1005 } 1006 1007 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) 1008 { 1009 u32 con1; 1010 1011 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 1012 RK3568_GRF_GMAC0_CON1; 1013 regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII); 1014 } 1015 1016 static const struct rk_gmac_ops rk3568_ops = { 1017 .set_to_rgmii = rk3568_set_to_rgmii, 1018 .set_to_rmii = rk3568_set_to_rmii, 1019 .set_speed = rk_set_clk_mac_speed, 1020 .regs_valid = true, 1021 .regs = { 1022 0xfe2a0000, /* gmac0 */ 1023 0xfe010000, /* gmac1 */ 1024 0x0, /* sentinel */ 1025 }, 1026 }; 1027 1028 /* VCCIO0_1_3_IOC */ 1029 #define RK3576_VCCIO0_1_3_IOC_CON2 0X6408 1030 #define RK3576_VCCIO0_1_3_IOC_CON3 0X640c 1031 #define RK3576_VCCIO0_1_3_IOC_CON4 0X6410 1032 #define RK3576_VCCIO0_1_3_IOC_CON5 0X6414 1033 1034 #define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 1035 #define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 1036 #define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 1037 #define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 1038 1039 #define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1040 #define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1041 1042 /* SDGMAC_GRF */ 1043 #define RK3576_GRF_GMAC_CON0 0X0020 1044 #define RK3576_GRF_GMAC_CON1 0X0024 1045 1046 #define RK3576_GMAC_RMII_MODE GRF_BIT(3) 1047 #define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3) 1048 1049 #define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7) 1050 #define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7) 1051 1052 #define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5) 1053 #define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5) 1054 1055 #define RK3576_GMAC_CLK_RGMII_DIV1 \ 1056 (GRF_CLR_BIT(6) | GRF_CLR_BIT(5)) 1057 #define RK3576_GMAC_CLK_RGMII_DIV5 \ 1058 (GRF_BIT(6) | GRF_BIT(5)) 1059 #define RK3576_GMAC_CLK_RGMII_DIV50 \ 1060 (GRF_BIT(6) | GRF_CLR_BIT(5)) 1061 1062 #define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) 1063 #define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) 1064 1065 static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv, 1066 int tx_delay, int rx_delay) 1067 { 1068 unsigned int offset_con; 1069 1070 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1071 RK3576_GRF_GMAC_CON0; 1072 1073 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE); 1074 1075 offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 : 1076 RK3576_VCCIO0_1_3_IOC_CON2; 1077 1078 /* m0 && m1 delay enabled */ 1079 regmap_write(bsp_priv->php_grf, offset_con, 1080 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 1081 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 1082 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 1083 1084 /* m0 && m1 delay value */ 1085 regmap_write(bsp_priv->php_grf, offset_con, 1086 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 1087 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 1088 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 1089 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 1090 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 1091 } 1092 1093 static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv) 1094 { 1095 unsigned int offset_con; 1096 1097 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1098 RK3576_GRF_GMAC_CON0; 1099 1100 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE); 1101 } 1102 1103 static const struct rk_reg_speed_data rk3578_reg_speed_data = { 1104 .rgmii_10 = RK3576_GMAC_CLK_RGMII_DIV50, 1105 .rgmii_100 = RK3576_GMAC_CLK_RGMII_DIV5, 1106 .rgmii_1000 = RK3576_GMAC_CLK_RGMII_DIV1, 1107 .rmii_10 = RK3576_GMAC_CLK_RMII_DIV20, 1108 .rmii_100 = RK3576_GMAC_CLK_RMII_DIV2, 1109 }; 1110 1111 static int rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, 1112 phy_interface_t interface, int speed) 1113 { 1114 unsigned int offset_con; 1115 1116 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1117 RK3576_GRF_GMAC_CON0; 1118 1119 return rk_set_reg_speed(bsp_priv, &rk3578_reg_speed_data, offset_con, 1120 interface, speed); 1121 } 1122 1123 static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1124 bool enable) 1125 { 1126 unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO : 1127 RK3576_GMAC_CLK_SELECT_CRU; 1128 unsigned int offset_con; 1129 1130 val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE : 1131 RK3576_GMAC_CLK_RMII_GATE; 1132 1133 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1134 RK3576_GRF_GMAC_CON0; 1135 1136 regmap_write(bsp_priv->grf, offset_con, val); 1137 } 1138 1139 static const struct rk_gmac_ops rk3576_ops = { 1140 .set_to_rgmii = rk3576_set_to_rgmii, 1141 .set_to_rmii = rk3576_set_to_rmii, 1142 .set_speed = rk3576_set_gmac_speed, 1143 .set_clock_selection = rk3576_set_clock_selection, 1144 .php_grf_required = true, 1145 .regs_valid = true, 1146 .regs = { 1147 0x2a220000, /* gmac0 */ 1148 0x2a230000, /* gmac1 */ 1149 0x0, /* sentinel */ 1150 }, 1151 }; 1152 1153 /* sys_grf */ 1154 #define RK3588_GRF_GMAC_CON7 0X031c 1155 #define RK3588_GRF_GMAC_CON8 0X0320 1156 #define RK3588_GRF_GMAC_CON9 0X0324 1157 1158 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3) 1159 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3) 1160 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2) 1161 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2) 1162 1163 #define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) 1164 #define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) 1165 1166 /* php_grf */ 1167 #define RK3588_GRF_GMAC_CON0 0X0008 1168 #define RK3588_GRF_CLK_CON1 0X0070 1169 1170 #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \ 1171 (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6)) 1172 #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \ 1173 (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6)) 1174 1175 #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) 1176 #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id)) 1177 1178 #define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4) 1179 #define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4) 1180 1181 #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2) 1182 #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2) 1183 1184 #define RK3588_GMAC_CLK_RGMII_DIV1(id) \ 1185 (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3)) 1186 #define RK3588_GMAC_CLK_RGMII_DIV5(id) \ 1187 (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1188 #define RK3588_GMAC_CLK_RGMII_DIV50(id) \ 1189 (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1190 1191 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) 1192 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1) 1193 1194 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv, 1195 int tx_delay, int rx_delay) 1196 { 1197 u32 offset_con, id = bsp_priv->id; 1198 1199 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 : 1200 RK3588_GRF_GMAC_CON8; 1201 1202 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1203 RK3588_GMAC_PHY_INTF_SEL_RGMII(id)); 1204 1205 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1206 RK3588_GMAC_CLK_RGMII_MODE(id)); 1207 1208 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7, 1209 RK3588_GMAC_RXCLK_DLY_ENABLE(id) | 1210 RK3588_GMAC_TXCLK_DLY_ENABLE(id)); 1211 1212 regmap_write(bsp_priv->grf, offset_con, 1213 RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) | 1214 RK3588_GMAC_CLK_TX_DL_CFG(tx_delay)); 1215 } 1216 1217 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv) 1218 { 1219 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1220 RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id)); 1221 1222 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1223 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id)); 1224 } 1225 1226 static int rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, 1227 phy_interface_t interface, int speed) 1228 { 1229 unsigned int val = 0, id = bsp_priv->id; 1230 1231 switch (speed) { 1232 case 10: 1233 if (interface == PHY_INTERFACE_MODE_RMII) 1234 val = RK3588_GMA_CLK_RMII_DIV20(id); 1235 else 1236 val = RK3588_GMAC_CLK_RGMII_DIV50(id); 1237 break; 1238 case 100: 1239 if (interface == PHY_INTERFACE_MODE_RMII) 1240 val = RK3588_GMA_CLK_RMII_DIV2(id); 1241 else 1242 val = RK3588_GMAC_CLK_RGMII_DIV5(id); 1243 break; 1244 case 1000: 1245 if (interface != PHY_INTERFACE_MODE_RMII) 1246 val = RK3588_GMAC_CLK_RGMII_DIV1(id); 1247 else 1248 goto err; 1249 break; 1250 default: 1251 goto err; 1252 } 1253 1254 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1255 1256 return 0; 1257 err: 1258 return -EINVAL; 1259 } 1260 1261 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1262 bool enable) 1263 { 1264 unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) : 1265 RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id); 1266 1267 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) : 1268 RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id); 1269 1270 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1271 } 1272 1273 static const struct rk_gmac_ops rk3588_ops = { 1274 .set_to_rgmii = rk3588_set_to_rgmii, 1275 .set_to_rmii = rk3588_set_to_rmii, 1276 .set_speed = rk3588_set_gmac_speed, 1277 .set_clock_selection = rk3588_set_clock_selection, 1278 .php_grf_required = true, 1279 .regs_valid = true, 1280 .regs = { 1281 0xfe1b0000, /* gmac0 */ 1282 0xfe1c0000, /* gmac1 */ 1283 0x0, /* sentinel */ 1284 }, 1285 }; 1286 1287 #define RV1108_GRF_GMAC_CON0 0X0900 1288 1289 /* RV1108_GRF_GMAC_CON0 */ 1290 #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 1291 GRF_BIT(6)) 1292 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) 1293 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 1294 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2) 1295 #define RV1108_GMAC_SPEED_100M GRF_BIT(2) 1296 #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7) 1297 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 1298 1299 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) 1300 { 1301 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1302 RV1108_GMAC_PHY_INTF_SEL_RMII); 1303 } 1304 1305 static const struct rk_reg_speed_data rv1108_reg_speed_data = { 1306 .rmii_10 = RV1108_GMAC_RMII_CLK_2_5M | RV1108_GMAC_SPEED_10M, 1307 .rmii_100 = RV1108_GMAC_RMII_CLK_25M | RV1108_GMAC_SPEED_100M, 1308 }; 1309 1310 static int rv1108_set_speed(struct rk_priv_data *bsp_priv, 1311 phy_interface_t interface, int speed) 1312 { 1313 return rk_set_reg_speed(bsp_priv, &rv1108_reg_speed_data, 1314 RV1108_GRF_GMAC_CON0, interface, speed); 1315 } 1316 1317 static const struct rk_gmac_ops rv1108_ops = { 1318 .set_to_rmii = rv1108_set_to_rmii, 1319 .set_speed = rv1108_set_speed, 1320 }; 1321 1322 #define RV1126_GRF_GMAC_CON0 0X0070 1323 #define RV1126_GRF_GMAC_CON1 0X0074 1324 #define RV1126_GRF_GMAC_CON2 0X0078 1325 1326 /* RV1126_GRF_GMAC_CON0 */ 1327 #define RV1126_GMAC_PHY_INTF_SEL_RGMII \ 1328 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 1329 #define RV1126_GMAC_PHY_INTF_SEL_RMII \ 1330 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 1331 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7) 1332 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7) 1333 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1) 1334 #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 1335 #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0) 1336 #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 1337 #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3) 1338 #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3) 1339 #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2) 1340 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2) 1341 1342 /* RV1126_GRF_GMAC_CON1 */ 1343 #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1344 #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1345 /* RV1126_GRF_GMAC_CON2 */ 1346 #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1347 #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1348 1349 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv, 1350 int tx_delay, int rx_delay) 1351 { 1352 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1353 RV1126_GMAC_PHY_INTF_SEL_RGMII | 1354 RV1126_GMAC_M0_RXCLK_DLY_ENABLE | 1355 RV1126_GMAC_M0_TXCLK_DLY_ENABLE | 1356 RV1126_GMAC_M1_RXCLK_DLY_ENABLE | 1357 RV1126_GMAC_M1_TXCLK_DLY_ENABLE); 1358 1359 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1, 1360 RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) | 1361 RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay)); 1362 1363 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2, 1364 RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) | 1365 RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay)); 1366 } 1367 1368 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) 1369 { 1370 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1371 RV1126_GMAC_PHY_INTF_SEL_RMII); 1372 } 1373 1374 static const struct rk_gmac_ops rv1126_ops = { 1375 .set_to_rgmii = rv1126_set_to_rgmii, 1376 .set_to_rmii = rv1126_set_to_rmii, 1377 .set_speed = rk_set_clk_mac_speed, 1378 }; 1379 1380 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) 1381 { 1382 struct rk_priv_data *bsp_priv = plat->bsp_priv; 1383 int phy_iface = bsp_priv->phy_iface; 1384 struct device *dev = bsp_priv->dev; 1385 int i, j, ret; 1386 1387 bsp_priv->clk_enabled = false; 1388 1389 bsp_priv->num_clks = ARRAY_SIZE(rk_clocks); 1390 if (phy_iface == PHY_INTERFACE_MODE_RMII) 1391 bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks); 1392 1393 bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks, 1394 sizeof(*bsp_priv->clks), GFP_KERNEL); 1395 if (!bsp_priv->clks) 1396 return -ENOMEM; 1397 1398 for (i = 0; i < ARRAY_SIZE(rk_clocks); i++) 1399 bsp_priv->clks[i].id = rk_clocks[i]; 1400 1401 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1402 for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++) 1403 bsp_priv->clks[i++].id = rk_rmii_clocks[j]; 1404 } 1405 1406 ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks, 1407 bsp_priv->clks); 1408 if (ret) 1409 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1410 1411 if (bsp_priv->clock_input) { 1412 dev_info(dev, "clock input from PHY\n"); 1413 } else if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1414 clk_set_rate(plat->stmmac_clk, 50000000); 1415 } 1416 1417 if (plat->phy_node && bsp_priv->integrated_phy) { 1418 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); 1419 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy); 1420 if (ret) 1421 return dev_err_probe(dev, ret, "Cannot get PHY clock\n"); 1422 clk_set_rate(bsp_priv->clk_phy, 50000000); 1423 } 1424 1425 return 0; 1426 } 1427 1428 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 1429 { 1430 int ret; 1431 1432 if (enable) { 1433 if (!bsp_priv->clk_enabled) { 1434 ret = clk_bulk_prepare_enable(bsp_priv->num_clks, 1435 bsp_priv->clks); 1436 if (ret) 1437 return ret; 1438 1439 ret = clk_prepare_enable(bsp_priv->clk_phy); 1440 if (ret) 1441 return ret; 1442 1443 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1444 bsp_priv->ops->set_clock_selection(bsp_priv, 1445 bsp_priv->clock_input, true); 1446 1447 mdelay(5); 1448 bsp_priv->clk_enabled = true; 1449 } 1450 } else { 1451 if (bsp_priv->clk_enabled) { 1452 clk_bulk_disable_unprepare(bsp_priv->num_clks, 1453 bsp_priv->clks); 1454 clk_disable_unprepare(bsp_priv->clk_phy); 1455 1456 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1457 bsp_priv->ops->set_clock_selection(bsp_priv, 1458 bsp_priv->clock_input, false); 1459 1460 bsp_priv->clk_enabled = false; 1461 } 1462 } 1463 1464 return 0; 1465 } 1466 1467 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) 1468 { 1469 struct regulator *ldo = bsp_priv->regulator; 1470 struct device *dev = bsp_priv->dev; 1471 int ret; 1472 1473 if (enable) { 1474 ret = regulator_enable(ldo); 1475 if (ret) 1476 dev_err(dev, "fail to enable phy-supply\n"); 1477 } else { 1478 ret = regulator_disable(ldo); 1479 if (ret) 1480 dev_err(dev, "fail to disable phy-supply\n"); 1481 } 1482 1483 return 0; 1484 } 1485 1486 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, 1487 struct plat_stmmacenet_data *plat, 1488 const struct rk_gmac_ops *ops) 1489 { 1490 struct rk_priv_data *bsp_priv; 1491 struct device *dev = &pdev->dev; 1492 struct resource *res; 1493 int ret; 1494 const char *strings = NULL; 1495 int value; 1496 1497 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); 1498 if (!bsp_priv) 1499 return ERR_PTR(-ENOMEM); 1500 1501 bsp_priv->phy_iface = plat->phy_interface; 1502 bsp_priv->ops = ops; 1503 1504 /* Some SoCs have multiple MAC controllers, which need 1505 * to be distinguished. 1506 */ 1507 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1508 if (res && ops->regs_valid) { 1509 int i = 0; 1510 1511 while (ops->regs[i]) { 1512 if (ops->regs[i] == res->start) { 1513 bsp_priv->id = i; 1514 break; 1515 } 1516 i++; 1517 } 1518 } 1519 1520 bsp_priv->regulator = devm_regulator_get(dev, "phy"); 1521 if (IS_ERR(bsp_priv->regulator)) { 1522 ret = PTR_ERR(bsp_priv->regulator); 1523 dev_err_probe(dev, ret, "failed to get phy regulator\n"); 1524 return ERR_PTR(ret); 1525 } 1526 1527 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); 1528 if (ret) { 1529 dev_err(dev, "Can not read property: clock_in_out.\n"); 1530 bsp_priv->clock_input = true; 1531 } else { 1532 dev_info(dev, "clock input or output? (%s).\n", 1533 strings); 1534 if (!strcmp(strings, "input")) 1535 bsp_priv->clock_input = true; 1536 else 1537 bsp_priv->clock_input = false; 1538 } 1539 1540 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); 1541 if (ret) { 1542 bsp_priv->tx_delay = 0x30; 1543 dev_err(dev, "Can not read property: tx_delay."); 1544 dev_err(dev, "set tx_delay to 0x%x\n", 1545 bsp_priv->tx_delay); 1546 } else { 1547 dev_info(dev, "TX delay(0x%x).\n", value); 1548 bsp_priv->tx_delay = value; 1549 } 1550 1551 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); 1552 if (ret) { 1553 bsp_priv->rx_delay = 0x10; 1554 dev_err(dev, "Can not read property: rx_delay."); 1555 dev_err(dev, "set rx_delay to 0x%x\n", 1556 bsp_priv->rx_delay); 1557 } else { 1558 dev_info(dev, "RX delay(0x%x).\n", value); 1559 bsp_priv->rx_delay = value; 1560 } 1561 1562 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 1563 "rockchip,grf"); 1564 if (IS_ERR(bsp_priv->grf)) { 1565 dev_err_probe(dev, PTR_ERR(bsp_priv->grf), 1566 "failed to lookup rockchip,grf\n"); 1567 return ERR_CAST(bsp_priv->grf); 1568 } 1569 1570 if (ops->php_grf_required) { 1571 bsp_priv->php_grf = 1572 syscon_regmap_lookup_by_phandle(dev->of_node, 1573 "rockchip,php-grf"); 1574 if (IS_ERR(bsp_priv->php_grf)) { 1575 dev_err_probe(dev, PTR_ERR(bsp_priv->php_grf), 1576 "failed to lookup rockchip,php-grf\n"); 1577 return ERR_CAST(bsp_priv->php_grf); 1578 } 1579 } 1580 1581 if (plat->phy_node) { 1582 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, 1583 "phy-is-integrated"); 1584 if (bsp_priv->integrated_phy) { 1585 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL); 1586 if (IS_ERR(bsp_priv->phy_reset)) { 1587 dev_err(&pdev->dev, "No PHY reset control found.\n"); 1588 bsp_priv->phy_reset = NULL; 1589 } 1590 } 1591 } 1592 dev_info(dev, "integrated PHY? (%s).\n", 1593 bsp_priv->integrated_phy ? "yes" : "no"); 1594 1595 bsp_priv->dev = dev; 1596 1597 return bsp_priv; 1598 } 1599 1600 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv) 1601 { 1602 switch (bsp_priv->phy_iface) { 1603 case PHY_INTERFACE_MODE_RGMII: 1604 case PHY_INTERFACE_MODE_RGMII_ID: 1605 case PHY_INTERFACE_MODE_RGMII_RXID: 1606 case PHY_INTERFACE_MODE_RGMII_TXID: 1607 if (!bsp_priv->ops->set_to_rgmii) 1608 return -EINVAL; 1609 break; 1610 case PHY_INTERFACE_MODE_RMII: 1611 if (!bsp_priv->ops->set_to_rmii) 1612 return -EINVAL; 1613 break; 1614 default: 1615 dev_err(bsp_priv->dev, 1616 "unsupported interface %d", bsp_priv->phy_iface); 1617 } 1618 return 0; 1619 } 1620 1621 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) 1622 { 1623 struct device *dev = bsp_priv->dev; 1624 int ret; 1625 1626 ret = rk_gmac_check_ops(bsp_priv); 1627 if (ret) 1628 return ret; 1629 1630 ret = gmac_clk_enable(bsp_priv, true); 1631 if (ret) 1632 return ret; 1633 1634 /*rmii or rgmii*/ 1635 switch (bsp_priv->phy_iface) { 1636 case PHY_INTERFACE_MODE_RGMII: 1637 dev_info(dev, "init for RGMII\n"); 1638 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 1639 bsp_priv->rx_delay); 1640 break; 1641 case PHY_INTERFACE_MODE_RGMII_ID: 1642 dev_info(dev, "init for RGMII_ID\n"); 1643 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); 1644 break; 1645 case PHY_INTERFACE_MODE_RGMII_RXID: 1646 dev_info(dev, "init for RGMII_RXID\n"); 1647 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); 1648 break; 1649 case PHY_INTERFACE_MODE_RGMII_TXID: 1650 dev_info(dev, "init for RGMII_TXID\n"); 1651 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); 1652 break; 1653 case PHY_INTERFACE_MODE_RMII: 1654 dev_info(dev, "init for RMII\n"); 1655 bsp_priv->ops->set_to_rmii(bsp_priv); 1656 break; 1657 default: 1658 dev_err(dev, "NO interface defined!\n"); 1659 } 1660 1661 ret = phy_power_on(bsp_priv, true); 1662 if (ret) { 1663 gmac_clk_enable(bsp_priv, false); 1664 return ret; 1665 } 1666 1667 pm_runtime_get_sync(dev); 1668 1669 if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup) 1670 bsp_priv->ops->integrated_phy_powerup(bsp_priv); 1671 1672 return 0; 1673 } 1674 1675 static void rk_gmac_powerdown(struct rk_priv_data *gmac) 1676 { 1677 if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown) 1678 gmac->ops->integrated_phy_powerdown(gmac); 1679 1680 pm_runtime_put_sync(gmac->dev); 1681 1682 phy_power_on(gmac, false); 1683 gmac_clk_enable(gmac, false); 1684 } 1685 1686 static void rk_get_interfaces(struct stmmac_priv *priv, void *bsp_priv, 1687 unsigned long *interfaces) 1688 { 1689 struct rk_priv_data *rk = bsp_priv; 1690 1691 if (rk->ops->set_to_rgmii) 1692 phy_interface_set_rgmii(interfaces); 1693 1694 if (rk->ops->set_to_rmii) 1695 __set_bit(PHY_INTERFACE_MODE_RMII, interfaces); 1696 } 1697 1698 static int rk_set_clk_tx_rate(void *bsp_priv_, struct clk *clk_tx_i, 1699 phy_interface_t interface, int speed) 1700 { 1701 struct rk_priv_data *bsp_priv = bsp_priv_; 1702 1703 if (bsp_priv->ops->set_speed) 1704 return bsp_priv->ops->set_speed(bsp_priv, bsp_priv->phy_iface, 1705 speed); 1706 1707 return -EINVAL; 1708 } 1709 1710 static int rk_gmac_probe(struct platform_device *pdev) 1711 { 1712 struct plat_stmmacenet_data *plat_dat; 1713 struct stmmac_resources stmmac_res; 1714 const struct rk_gmac_ops *data; 1715 int ret; 1716 1717 data = of_device_get_match_data(&pdev->dev); 1718 if (!data) { 1719 dev_err(&pdev->dev, "no of match data provided\n"); 1720 return -EINVAL; 1721 } 1722 1723 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1724 if (ret) 1725 return ret; 1726 1727 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 1728 if (IS_ERR(plat_dat)) 1729 return PTR_ERR(plat_dat); 1730 1731 /* If the stmmac is not already selected as gmac4, 1732 * then make sure we fallback to gmac. 1733 */ 1734 if (!plat_dat->has_gmac4) { 1735 plat_dat->has_gmac = true; 1736 plat_dat->rx_fifo_size = 4096; 1737 plat_dat->tx_fifo_size = 2048; 1738 } 1739 1740 plat_dat->get_interfaces = rk_get_interfaces; 1741 plat_dat->set_clk_tx_rate = rk_set_clk_tx_rate; 1742 1743 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data); 1744 if (IS_ERR(plat_dat->bsp_priv)) 1745 return PTR_ERR(plat_dat->bsp_priv); 1746 1747 ret = rk_gmac_clk_init(plat_dat); 1748 if (ret) 1749 return ret; 1750 1751 ret = rk_gmac_powerup(plat_dat->bsp_priv); 1752 if (ret) 1753 return ret; 1754 1755 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1756 if (ret) 1757 goto err_gmac_powerdown; 1758 1759 return 0; 1760 1761 err_gmac_powerdown: 1762 rk_gmac_powerdown(plat_dat->bsp_priv); 1763 1764 return ret; 1765 } 1766 1767 static void rk_gmac_remove(struct platform_device *pdev) 1768 { 1769 struct stmmac_priv *priv = netdev_priv(platform_get_drvdata(pdev)); 1770 struct rk_priv_data *bsp_priv = priv->plat->bsp_priv; 1771 1772 stmmac_dvr_remove(&pdev->dev); 1773 1774 rk_gmac_powerdown(bsp_priv); 1775 1776 if (priv->plat->phy_node && bsp_priv->integrated_phy) 1777 clk_put(bsp_priv->clk_phy); 1778 } 1779 1780 #ifdef CONFIG_PM_SLEEP 1781 static int rk_gmac_suspend(struct device *dev) 1782 { 1783 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 1784 int ret = stmmac_suspend(dev); 1785 1786 /* Keep the PHY up if we use Wake-on-Lan. */ 1787 if (!device_may_wakeup(dev)) { 1788 rk_gmac_powerdown(bsp_priv); 1789 bsp_priv->suspended = true; 1790 } 1791 1792 return ret; 1793 } 1794 1795 static int rk_gmac_resume(struct device *dev) 1796 { 1797 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 1798 1799 /* The PHY was up for Wake-on-Lan. */ 1800 if (bsp_priv->suspended) { 1801 rk_gmac_powerup(bsp_priv); 1802 bsp_priv->suspended = false; 1803 } 1804 1805 return stmmac_resume(dev); 1806 } 1807 #endif /* CONFIG_PM_SLEEP */ 1808 1809 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume); 1810 1811 static const struct of_device_id rk_gmac_dwmac_match[] = { 1812 { .compatible = "rockchip,px30-gmac", .data = &px30_ops }, 1813 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops }, 1814 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops }, 1815 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops }, 1816 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops }, 1817 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops }, 1818 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, 1819 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, 1820 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, 1821 { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops }, 1822 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops }, 1823 { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops }, 1824 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops }, 1825 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops }, 1826 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops }, 1827 { } 1828 }; 1829 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); 1830 1831 static struct platform_driver rk_gmac_dwmac_driver = { 1832 .probe = rk_gmac_probe, 1833 .remove = rk_gmac_remove, 1834 .driver = { 1835 .name = "rk_gmac-dwmac", 1836 .pm = &rk_gmac_pm_ops, 1837 .of_match_table = rk_gmac_dwmac_match, 1838 }, 1839 }; 1840 module_platform_driver(rk_gmac_dwmac_driver); 1841 1842 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>"); 1843 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer"); 1844 MODULE_LICENSE("GPL"); 1845