1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /** 3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer 4 * 5 * Copyright (C) 2014 Chen-Zhi (Roger Chen) 6 * 7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> 8 */ 9 10 #include <linux/stmmac.h> 11 #include <linux/hw_bitfield.h> 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/phy.h> 15 #include <linux/of_net.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/delay.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/regmap.h> 23 #include <linux/pm_runtime.h> 24 25 #include "stmmac_platform.h" 26 27 struct rk_priv_data; 28 29 struct rk_reg_speed_data { 30 unsigned int rgmii_10; 31 unsigned int rgmii_100; 32 unsigned int rgmii_1000; 33 unsigned int rmii_10; 34 unsigned int rmii_100; 35 }; 36 37 struct rk_gmac_ops { 38 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, 39 int tx_delay, int rx_delay); 40 void (*set_to_rmii)(struct rk_priv_data *bsp_priv); 41 int (*set_speed)(struct rk_priv_data *bsp_priv, 42 phy_interface_t interface, int speed); 43 void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, 44 bool enable); 45 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); 46 void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv); 47 bool php_grf_required; 48 bool regs_valid; 49 u32 regs[]; 50 }; 51 52 static const char * const rk_clocks[] = { 53 "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed", 54 }; 55 56 static const char * const rk_rmii_clocks[] = { 57 "mac_clk_rx", "clk_mac_ref", "clk_mac_refout", 58 }; 59 60 enum rk_clocks_index { 61 RK_ACLK_MAC = 0, 62 RK_PCLK_MAC, 63 RK_MAC_CLK_TX, 64 RK_CLK_MAC_SPEED, 65 RK_MAC_CLK_RX, 66 RK_CLK_MAC_REF, 67 RK_CLK_MAC_REFOUT, 68 }; 69 70 struct rk_priv_data { 71 struct device *dev; 72 phy_interface_t phy_iface; 73 int id; 74 struct regulator *regulator; 75 const struct rk_gmac_ops *ops; 76 77 bool clk_enabled; 78 bool clock_input; 79 bool integrated_phy; 80 81 struct clk_bulk_data *clks; 82 int num_clks; 83 struct clk *clk_phy; 84 85 struct reset_control *phy_reset; 86 87 int tx_delay; 88 int rx_delay; 89 90 struct regmap *grf; 91 struct regmap *php_grf; 92 }; 93 94 static int rk_set_reg_speed(struct rk_priv_data *bsp_priv, 95 const struct rk_reg_speed_data *rsd, 96 unsigned int reg, phy_interface_t interface, 97 int speed) 98 { 99 unsigned int val; 100 101 if (phy_interface_mode_is_rgmii(interface)) { 102 if (speed == SPEED_10) { 103 val = rsd->rgmii_10; 104 } else if (speed == SPEED_100) { 105 val = rsd->rgmii_100; 106 } else if (speed == SPEED_1000) { 107 val = rsd->rgmii_1000; 108 } else { 109 /* Phylink will not allow inappropriate speeds for 110 * interface modes, so this should never happen. 111 */ 112 return -EINVAL; 113 } 114 } else if (interface == PHY_INTERFACE_MODE_RMII) { 115 if (speed == SPEED_10) { 116 val = rsd->rmii_10; 117 } else if (speed == SPEED_100) { 118 val = rsd->rmii_100; 119 } else { 120 /* Phylink will not allow inappropriate speeds for 121 * interface modes, so this should never happen. 122 */ 123 return -EINVAL; 124 } 125 } else { 126 /* This should never happen, as .get_interfaces() limits 127 * the interface modes that are supported to RGMII and/or 128 * RMII. 129 */ 130 return -EINVAL; 131 } 132 133 regmap_write(bsp_priv->grf, reg, val); 134 135 return 0; 136 137 } 138 139 static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv, 140 phy_interface_t interface, int speed) 141 { 142 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 143 long rate; 144 145 rate = rgmii_clock(speed); 146 if (rate < 0) 147 return rate; 148 149 return clk_set_rate(clk_mac_speed, rate); 150 } 151 152 #define HIWORD_UPDATE(val, mask, shift) \ 153 (FIELD_PREP_WM16((mask) << (shift), (val))) 154 155 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 156 #define GRF_CLR_BIT(nr) (BIT(nr+16)) 157 158 #define DELAY_ENABLE(soc, tx, rx) \ 159 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ 160 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) 161 162 #define RK_GRF_MACPHY_CON0 0xb00 163 #define RK_GRF_MACPHY_CON1 0xb04 164 #define RK_GRF_MACPHY_CON2 0xb08 165 #define RK_GRF_MACPHY_CON3 0xb0c 166 167 #define RK_MACPHY_ENABLE GRF_BIT(0) 168 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0) 169 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) 170 #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) 171 #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) 172 #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) 173 174 static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv) 175 { 176 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); 177 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); 178 179 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); 180 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); 181 182 if (priv->phy_reset) { 183 /* PHY needs to be disabled before trying to reset it */ 184 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 185 if (priv->phy_reset) 186 reset_control_assert(priv->phy_reset); 187 usleep_range(10, 20); 188 if (priv->phy_reset) 189 reset_control_deassert(priv->phy_reset); 190 usleep_range(10, 20); 191 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); 192 msleep(30); 193 } 194 } 195 196 static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv) 197 { 198 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 199 if (priv->phy_reset) 200 reset_control_assert(priv->phy_reset); 201 } 202 203 #define RK_FEPHY_SHUTDOWN GRF_BIT(1) 204 #define RK_FEPHY_POWERUP GRF_CLR_BIT(1) 205 #define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6) 206 #define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9)) 207 #define RK_FEPHY_PHY_ID GRF_BIT(11) 208 209 static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv, 210 unsigned int reg) 211 { 212 reset_control_assert(priv->phy_reset); 213 usleep_range(20, 30); 214 215 regmap_write(priv->grf, reg, 216 RK_FEPHY_POWERUP | 217 RK_FEPHY_INTERNAL_RMII_SEL | 218 RK_FEPHY_24M_CLK_SEL | 219 RK_FEPHY_PHY_ID); 220 usleep_range(10000, 12000); 221 222 reset_control_deassert(priv->phy_reset); 223 usleep_range(50000, 60000); 224 } 225 226 static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv, 227 unsigned int reg) 228 { 229 regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN); 230 } 231 232 #define PX30_GRF_GMAC_CON1 0x0904 233 234 /* PX30_GRF_GMAC_CON1 */ 235 #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 236 GRF_BIT(6)) 237 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2) 238 #define PX30_GMAC_SPEED_100M GRF_BIT(2) 239 240 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) 241 { 242 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 243 PX30_GMAC_PHY_INTF_SEL_RMII); 244 } 245 246 static int px30_set_speed(struct rk_priv_data *bsp_priv, 247 phy_interface_t interface, int speed) 248 { 249 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 250 struct device *dev = bsp_priv->dev; 251 unsigned int con1; 252 long rate; 253 254 if (!clk_mac_speed) { 255 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__); 256 return -EINVAL; 257 } 258 259 if (speed == 10) { 260 con1 = PX30_GMAC_SPEED_10M; 261 rate = 2500000; 262 } else if (speed == 100) { 263 con1 = PX30_GMAC_SPEED_100M; 264 rate = 25000000; 265 } else { 266 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 267 return -EINVAL; 268 } 269 270 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, con1); 271 272 return clk_set_rate(clk_mac_speed, rate); 273 } 274 275 static const struct rk_gmac_ops px30_ops = { 276 .set_to_rmii = px30_set_to_rmii, 277 .set_speed = px30_set_speed, 278 }; 279 280 #define RK3128_GRF_MAC_CON0 0x0168 281 #define RK3128_GRF_MAC_CON1 0x016c 282 283 /* RK3128_GRF_MAC_CON0 */ 284 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 285 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 286 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 287 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 288 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 289 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 290 291 /* RK3128_GRF_MAC_CON1 */ 292 #define RK3128_GMAC_PHY_INTF_SEL_RGMII \ 293 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8)) 294 #define RK3128_GMAC_PHY_INTF_SEL_RMII \ 295 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8)) 296 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9) 297 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 298 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10) 299 #define RK3128_GMAC_SPEED_100M GRF_BIT(10) 300 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11) 301 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 302 #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 303 #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 304 #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 305 #define RK3128_GMAC_RMII_MODE GRF_BIT(14) 306 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 307 308 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, 309 int tx_delay, int rx_delay) 310 { 311 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 312 RK3128_GMAC_PHY_INTF_SEL_RGMII | 313 RK3128_GMAC_RMII_MODE_CLR); 314 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0, 315 DELAY_ENABLE(RK3128, tx_delay, rx_delay) | 316 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) | 317 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay)); 318 } 319 320 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) 321 { 322 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 323 RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE); 324 } 325 326 static const struct rk_reg_speed_data rk3128_reg_speed_data = { 327 .rgmii_10 = RK3128_GMAC_CLK_2_5M, 328 .rgmii_100 = RK3128_GMAC_CLK_25M, 329 .rgmii_1000 = RK3128_GMAC_CLK_125M, 330 .rmii_10 = RK3128_GMAC_RMII_CLK_2_5M | RK3128_GMAC_SPEED_10M, 331 .rmii_100 = RK3128_GMAC_RMII_CLK_25M | RK3128_GMAC_SPEED_100M, 332 }; 333 334 static int rk3128_set_speed(struct rk_priv_data *bsp_priv, 335 phy_interface_t interface, int speed) 336 { 337 return rk_set_reg_speed(bsp_priv, &rk3128_reg_speed_data, 338 RK3128_GRF_MAC_CON1, interface, speed); 339 } 340 341 static const struct rk_gmac_ops rk3128_ops = { 342 .set_to_rgmii = rk3128_set_to_rgmii, 343 .set_to_rmii = rk3128_set_to_rmii, 344 .set_speed = rk3128_set_speed, 345 }; 346 347 #define RK3228_GRF_MAC_CON0 0x0900 348 #define RK3228_GRF_MAC_CON1 0x0904 349 350 #define RK3228_GRF_CON_MUX 0x50 351 352 /* RK3228_GRF_MAC_CON0 */ 353 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 354 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 355 356 /* RK3228_GRF_MAC_CON1 */ 357 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ 358 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 359 #define RK3228_GMAC_PHY_INTF_SEL_RMII \ 360 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 361 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) 362 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 363 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) 364 #define RK3228_GMAC_SPEED_100M GRF_BIT(2) 365 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) 366 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 367 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) 368 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) 369 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) 370 #define RK3228_GMAC_RMII_MODE GRF_BIT(10) 371 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) 372 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 373 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 374 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 375 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 376 377 /* RK3228_GRF_COM_MUX */ 378 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15) 379 380 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, 381 int tx_delay, int rx_delay) 382 { 383 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 384 RK3228_GMAC_PHY_INTF_SEL_RGMII | 385 RK3228_GMAC_RMII_MODE_CLR | 386 DELAY_ENABLE(RK3228, tx_delay, rx_delay)); 387 388 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, 389 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | 390 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); 391 } 392 393 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) 394 { 395 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 396 RK3228_GMAC_PHY_INTF_SEL_RMII | 397 RK3228_GMAC_RMII_MODE); 398 399 /* set MAC to RMII mode */ 400 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); 401 } 402 403 static const struct rk_reg_speed_data rk3228_reg_speed_data = { 404 .rgmii_10 = RK3228_GMAC_CLK_2_5M, 405 .rgmii_100 = RK3228_GMAC_CLK_25M, 406 .rgmii_1000 = RK3228_GMAC_CLK_125M, 407 .rmii_10 = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_SPEED_10M, 408 .rmii_100 = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_SPEED_100M, 409 }; 410 411 static int rk3228_set_speed(struct rk_priv_data *bsp_priv, 412 phy_interface_t interface, int speed) 413 { 414 return rk_set_reg_speed(bsp_priv, &rk3228_reg_speed_data, 415 RK3228_GRF_MAC_CON1, interface, speed); 416 } 417 418 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) 419 { 420 regmap_write(priv->grf, RK3228_GRF_CON_MUX, 421 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 422 423 rk_gmac_integrated_ephy_powerup(priv); 424 } 425 426 static const struct rk_gmac_ops rk3228_ops = { 427 .set_to_rgmii = rk3228_set_to_rgmii, 428 .set_to_rmii = rk3228_set_to_rmii, 429 .set_speed = rk3228_set_speed, 430 .integrated_phy_powerup = rk3228_integrated_phy_powerup, 431 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, 432 }; 433 434 #define RK3288_GRF_SOC_CON1 0x0248 435 #define RK3288_GRF_SOC_CON3 0x0250 436 437 /*RK3288_GRF_SOC_CON1*/ 438 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ 439 GRF_CLR_BIT(8)) 440 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ 441 GRF_BIT(8)) 442 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) 443 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 444 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) 445 #define RK3288_GMAC_SPEED_100M GRF_BIT(10) 446 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) 447 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 448 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 449 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 450 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 451 #define RK3288_GMAC_RMII_MODE GRF_BIT(14) 452 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 453 454 /*RK3288_GRF_SOC_CON3*/ 455 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 456 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 457 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 458 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 459 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 460 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 461 462 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 463 int tx_delay, int rx_delay) 464 { 465 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 466 RK3288_GMAC_PHY_INTF_SEL_RGMII | 467 RK3288_GMAC_RMII_MODE_CLR); 468 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 469 DELAY_ENABLE(RK3288, tx_delay, rx_delay) | 470 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | 471 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); 472 } 473 474 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 475 { 476 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 477 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); 478 } 479 480 static const struct rk_reg_speed_data rk3288_reg_speed_data = { 481 .rgmii_10 = RK3288_GMAC_CLK_2_5M, 482 .rgmii_100 = RK3288_GMAC_CLK_25M, 483 .rgmii_1000 = RK3288_GMAC_CLK_125M, 484 .rmii_10 = RK3288_GMAC_RMII_CLK_2_5M | RK3288_GMAC_SPEED_10M, 485 .rmii_100 = RK3288_GMAC_RMII_CLK_25M | RK3288_GMAC_SPEED_100M, 486 }; 487 488 static int rk3288_set_speed(struct rk_priv_data *bsp_priv, 489 phy_interface_t interface, int speed) 490 { 491 return rk_set_reg_speed(bsp_priv, &rk3288_reg_speed_data, 492 RK3288_GRF_SOC_CON1, interface, speed); 493 } 494 495 static const struct rk_gmac_ops rk3288_ops = { 496 .set_to_rgmii = rk3288_set_to_rgmii, 497 .set_to_rmii = rk3288_set_to_rmii, 498 .set_speed = rk3288_set_speed, 499 }; 500 501 #define RK3308_GRF_MAC_CON0 0x04a0 502 503 /* RK3308_GRF_MAC_CON0 */ 504 #define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \ 505 GRF_BIT(4)) 506 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3) 507 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 508 #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0) 509 #define RK3308_GMAC_SPEED_100M GRF_BIT(0) 510 511 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) 512 { 513 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 514 RK3308_GMAC_PHY_INTF_SEL_RMII); 515 } 516 517 static const struct rk_reg_speed_data rk3308_reg_speed_data = { 518 .rmii_10 = RK3308_GMAC_SPEED_10M, 519 .rmii_100 = RK3308_GMAC_SPEED_100M, 520 }; 521 522 static int rk3308_set_speed(struct rk_priv_data *bsp_priv, 523 phy_interface_t interface, int speed) 524 { 525 return rk_set_reg_speed(bsp_priv, &rk3308_reg_speed_data, 526 RK3308_GRF_MAC_CON0, interface, speed); 527 } 528 529 static const struct rk_gmac_ops rk3308_ops = { 530 .set_to_rmii = rk3308_set_to_rmii, 531 .set_speed = rk3308_set_speed, 532 }; 533 534 #define RK3328_GRF_MAC_CON0 0x0900 535 #define RK3328_GRF_MAC_CON1 0x0904 536 #define RK3328_GRF_MAC_CON2 0x0908 537 #define RK3328_GRF_MACPHY_CON1 0xb04 538 539 /* RK3328_GRF_MAC_CON0 */ 540 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 541 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 542 543 /* RK3328_GRF_MAC_CON1 */ 544 #define RK3328_GMAC_PHY_INTF_SEL_RGMII \ 545 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 546 #define RK3328_GMAC_PHY_INTF_SEL_RMII \ 547 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 548 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) 549 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 550 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) 551 #define RK3328_GMAC_SPEED_100M GRF_BIT(2) 552 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) 553 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 554 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12)) 555 #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12)) 556 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12)) 557 #define RK3328_GMAC_RMII_MODE GRF_BIT(9) 558 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) 559 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 560 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 561 562 /* RK3328_GRF_MACPHY_CON1 */ 563 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9) 564 565 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, 566 int tx_delay, int rx_delay) 567 { 568 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 569 RK3328_GMAC_PHY_INTF_SEL_RGMII | 570 RK3328_GMAC_RMII_MODE_CLR | 571 RK3328_GMAC_RXCLK_DLY_ENABLE | 572 RK3328_GMAC_TXCLK_DLY_ENABLE); 573 574 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0, 575 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) | 576 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); 577 } 578 579 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) 580 { 581 unsigned int reg; 582 583 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : 584 RK3328_GRF_MAC_CON1; 585 586 regmap_write(bsp_priv->grf, reg, 587 RK3328_GMAC_PHY_INTF_SEL_RMII | 588 RK3328_GMAC_RMII_MODE); 589 } 590 591 static const struct rk_reg_speed_data rk3328_reg_speed_data = { 592 .rgmii_10 = RK3328_GMAC_CLK_2_5M, 593 .rgmii_100 = RK3328_GMAC_CLK_25M, 594 .rgmii_1000 = RK3328_GMAC_CLK_125M, 595 .rmii_10 = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_SPEED_10M, 596 .rmii_100 = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_SPEED_100M, 597 }; 598 599 static int rk3328_set_speed(struct rk_priv_data *bsp_priv, 600 phy_interface_t interface, int speed) 601 { 602 unsigned int reg; 603 604 if (interface == PHY_INTERFACE_MODE_RMII && bsp_priv->integrated_phy) 605 reg = RK3328_GRF_MAC_CON2; 606 else 607 reg = RK3328_GRF_MAC_CON1; 608 609 return rk_set_reg_speed(bsp_priv, &rk3328_reg_speed_data, reg, 610 interface, speed); 611 } 612 613 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) 614 { 615 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, 616 RK3328_MACPHY_RMII_MODE); 617 618 rk_gmac_integrated_ephy_powerup(priv); 619 } 620 621 static const struct rk_gmac_ops rk3328_ops = { 622 .set_to_rgmii = rk3328_set_to_rgmii, 623 .set_to_rmii = rk3328_set_to_rmii, 624 .set_speed = rk3328_set_speed, 625 .integrated_phy_powerup = rk3328_integrated_phy_powerup, 626 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, 627 }; 628 629 #define RK3366_GRF_SOC_CON6 0x0418 630 #define RK3366_GRF_SOC_CON7 0x041c 631 632 /* RK3366_GRF_SOC_CON6 */ 633 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 634 GRF_CLR_BIT(11)) 635 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 636 GRF_BIT(11)) 637 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) 638 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 639 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) 640 #define RK3366_GMAC_SPEED_100M GRF_BIT(7) 641 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) 642 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 643 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 644 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 645 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 646 #define RK3366_GMAC_RMII_MODE GRF_BIT(6) 647 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 648 649 /* RK3366_GRF_SOC_CON7 */ 650 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 651 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 652 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 653 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 654 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 655 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 656 657 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 658 int tx_delay, int rx_delay) 659 { 660 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 661 RK3366_GMAC_PHY_INTF_SEL_RGMII | 662 RK3366_GMAC_RMII_MODE_CLR); 663 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, 664 DELAY_ENABLE(RK3366, tx_delay, rx_delay) | 665 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | 666 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); 667 } 668 669 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 670 { 671 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 672 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); 673 } 674 675 static const struct rk_reg_speed_data rk3366_reg_speed_data = { 676 .rgmii_10 = RK3366_GMAC_CLK_2_5M, 677 .rgmii_100 = RK3366_GMAC_CLK_25M, 678 .rgmii_1000 = RK3366_GMAC_CLK_125M, 679 .rmii_10 = RK3366_GMAC_RMII_CLK_2_5M | RK3366_GMAC_SPEED_10M, 680 .rmii_100 = RK3366_GMAC_RMII_CLK_25M | RK3366_GMAC_SPEED_100M, 681 }; 682 683 static int rk3366_set_speed(struct rk_priv_data *bsp_priv, 684 phy_interface_t interface, int speed) 685 { 686 return rk_set_reg_speed(bsp_priv, &rk3366_reg_speed_data, 687 RK3366_GRF_SOC_CON6, interface, speed); 688 } 689 690 static const struct rk_gmac_ops rk3366_ops = { 691 .set_to_rgmii = rk3366_set_to_rgmii, 692 .set_to_rmii = rk3366_set_to_rmii, 693 .set_speed = rk3366_set_speed, 694 }; 695 696 #define RK3368_GRF_SOC_CON15 0x043c 697 #define RK3368_GRF_SOC_CON16 0x0440 698 699 /* RK3368_GRF_SOC_CON15 */ 700 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 701 GRF_CLR_BIT(11)) 702 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 703 GRF_BIT(11)) 704 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) 705 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 706 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) 707 #define RK3368_GMAC_SPEED_100M GRF_BIT(7) 708 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) 709 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 710 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 711 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 712 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 713 #define RK3368_GMAC_RMII_MODE GRF_BIT(6) 714 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 715 716 /* RK3368_GRF_SOC_CON16 */ 717 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 718 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 719 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 720 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 721 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 722 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 723 724 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 725 int tx_delay, int rx_delay) 726 { 727 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 728 RK3368_GMAC_PHY_INTF_SEL_RGMII | 729 RK3368_GMAC_RMII_MODE_CLR); 730 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, 731 DELAY_ENABLE(RK3368, tx_delay, rx_delay) | 732 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | 733 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); 734 } 735 736 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 737 { 738 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 739 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); 740 } 741 742 static const struct rk_reg_speed_data rk3368_reg_speed_data = { 743 .rgmii_10 = RK3368_GMAC_CLK_2_5M, 744 .rgmii_100 = RK3368_GMAC_CLK_25M, 745 .rgmii_1000 = RK3368_GMAC_CLK_125M, 746 .rmii_10 = RK3368_GMAC_RMII_CLK_2_5M | RK3368_GMAC_SPEED_10M, 747 .rmii_100 = RK3368_GMAC_RMII_CLK_25M | RK3368_GMAC_SPEED_100M, 748 }; 749 750 static int rk3368_set_speed(struct rk_priv_data *bsp_priv, 751 phy_interface_t interface, int speed) 752 { 753 return rk_set_reg_speed(bsp_priv, &rk3368_reg_speed_data, 754 RK3368_GRF_SOC_CON15, interface, speed); 755 } 756 757 static const struct rk_gmac_ops rk3368_ops = { 758 .set_to_rgmii = rk3368_set_to_rgmii, 759 .set_to_rmii = rk3368_set_to_rmii, 760 .set_speed = rk3368_set_speed, 761 }; 762 763 #define RK3399_GRF_SOC_CON5 0xc214 764 #define RK3399_GRF_SOC_CON6 0xc218 765 766 /* RK3399_GRF_SOC_CON5 */ 767 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 768 GRF_CLR_BIT(11)) 769 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 770 GRF_BIT(11)) 771 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) 772 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 773 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) 774 #define RK3399_GMAC_SPEED_100M GRF_BIT(7) 775 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) 776 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 777 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 778 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 779 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 780 #define RK3399_GMAC_RMII_MODE GRF_BIT(6) 781 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 782 783 /* RK3399_GRF_SOC_CON6 */ 784 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 785 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 786 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 787 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 788 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 789 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 790 791 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 792 int tx_delay, int rx_delay) 793 { 794 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 795 RK3399_GMAC_PHY_INTF_SEL_RGMII | 796 RK3399_GMAC_RMII_MODE_CLR); 797 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, 798 DELAY_ENABLE(RK3399, tx_delay, rx_delay) | 799 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | 800 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); 801 } 802 803 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 804 { 805 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 806 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); 807 } 808 809 static const struct rk_reg_speed_data rk3399_reg_speed_data = { 810 .rgmii_10 = RK3399_GMAC_CLK_2_5M, 811 .rgmii_100 = RK3399_GMAC_CLK_25M, 812 .rgmii_1000 = RK3399_GMAC_CLK_125M, 813 .rmii_10 = RK3399_GMAC_RMII_CLK_2_5M | RK3399_GMAC_SPEED_10M, 814 .rmii_100 = RK3399_GMAC_RMII_CLK_25M | RK3399_GMAC_SPEED_100M, 815 }; 816 817 static int rk3399_set_speed(struct rk_priv_data *bsp_priv, 818 phy_interface_t interface, int speed) 819 { 820 return rk_set_reg_speed(bsp_priv, &rk3399_reg_speed_data, 821 RK3399_GRF_SOC_CON5, interface, speed); 822 } 823 824 static const struct rk_gmac_ops rk3399_ops = { 825 .set_to_rgmii = rk3399_set_to_rgmii, 826 .set_to_rmii = rk3399_set_to_rmii, 827 .set_speed = rk3399_set_speed, 828 }; 829 830 #define RK3528_VO_GRF_GMAC_CON 0x0018 831 #define RK3528_VO_GRF_MACPHY_CON0 0x001c 832 #define RK3528_VO_GRF_MACPHY_CON1 0x0020 833 #define RK3528_VPU_GRF_GMAC_CON5 0x0018 834 #define RK3528_VPU_GRF_GMAC_CON6 0x001c 835 836 #define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 837 #define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 838 #define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 839 #define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 840 841 #define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) 842 #define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) 843 844 #define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1) 845 #define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8) 846 #define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8) 847 848 #define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12) 849 #define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12) 850 851 #define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3) 852 #define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3) 853 #define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10) 854 #define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10) 855 856 #define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10)) 857 #define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10)) 858 #define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10)) 859 860 #define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) 861 #define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) 862 #define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9) 863 #define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9) 864 865 static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv, 866 int tx_delay, int rx_delay) 867 { 868 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 869 RK3528_GMAC1_PHY_INTF_SEL_RGMII); 870 871 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 872 DELAY_ENABLE(RK3528, tx_delay, rx_delay)); 873 874 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6, 875 RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) | 876 RK3528_GMAC_CLK_TX_DL_CFG(tx_delay)); 877 } 878 879 static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv) 880 { 881 if (bsp_priv->id == 1) 882 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 883 RK3528_GMAC1_PHY_INTF_SEL_RMII); 884 else 885 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, 886 RK3528_GMAC0_PHY_INTF_SEL_RMII | 887 RK3528_GMAC0_CLK_RMII_DIV2); 888 } 889 890 static const struct rk_reg_speed_data rk3528_gmac0_reg_speed_data = { 891 .rmii_10 = RK3528_GMAC0_CLK_RMII_DIV20, 892 .rmii_100 = RK3528_GMAC0_CLK_RMII_DIV2, 893 }; 894 895 static const struct rk_reg_speed_data rk3528_gmac1_reg_speed_data = { 896 .rgmii_10 = RK3528_GMAC1_CLK_RGMII_DIV50, 897 .rgmii_100 = RK3528_GMAC1_CLK_RGMII_DIV5, 898 .rgmii_1000 = RK3528_GMAC1_CLK_RGMII_DIV1, 899 .rmii_10 = RK3528_GMAC1_CLK_RMII_DIV20, 900 .rmii_100 = RK3528_GMAC1_CLK_RMII_DIV2, 901 }; 902 903 static int rk3528_set_speed(struct rk_priv_data *bsp_priv, 904 phy_interface_t interface, int speed) 905 { 906 const struct rk_reg_speed_data *rsd; 907 unsigned int reg; 908 909 if (bsp_priv->id == 1) { 910 rsd = &rk3528_gmac1_reg_speed_data; 911 reg = RK3528_VPU_GRF_GMAC_CON5; 912 } else { 913 rsd = &rk3528_gmac0_reg_speed_data; 914 reg = RK3528_VO_GRF_GMAC_CON; 915 } 916 917 return rk_set_reg_speed(bsp_priv, rsd, reg, interface, speed); 918 } 919 920 static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv, 921 bool input, bool enable) 922 { 923 unsigned int val; 924 925 if (bsp_priv->id == 1) { 926 val = input ? RK3528_GMAC1_CLK_SELECT_IO : 927 RK3528_GMAC1_CLK_SELECT_CRU; 928 val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE : 929 RK3528_GMAC1_CLK_RMII_GATE; 930 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val); 931 } else { 932 val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE : 933 RK3528_GMAC0_CLK_RMII_GATE; 934 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val); 935 } 936 } 937 938 static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv) 939 { 940 rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); 941 } 942 943 static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv) 944 { 945 rk_gmac_integrated_fephy_powerdown(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); 946 } 947 948 static const struct rk_gmac_ops rk3528_ops = { 949 .set_to_rgmii = rk3528_set_to_rgmii, 950 .set_to_rmii = rk3528_set_to_rmii, 951 .set_speed = rk3528_set_speed, 952 .set_clock_selection = rk3528_set_clock_selection, 953 .integrated_phy_powerup = rk3528_integrated_phy_powerup, 954 .integrated_phy_powerdown = rk3528_integrated_phy_powerdown, 955 .regs_valid = true, 956 .regs = { 957 0xffbd0000, /* gmac0 */ 958 0xffbe0000, /* gmac1 */ 959 0x0, /* sentinel */ 960 }, 961 }; 962 963 #define RK3568_GRF_GMAC0_CON0 0x0380 964 #define RK3568_GRF_GMAC0_CON1 0x0384 965 #define RK3568_GRF_GMAC1_CON0 0x0388 966 #define RK3568_GRF_GMAC1_CON1 0x038c 967 968 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ 969 #define RK3568_GMAC_PHY_INTF_SEL_RGMII \ 970 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 971 #define RK3568_GMAC_PHY_INTF_SEL_RMII \ 972 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 973 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) 974 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 975 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 976 #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 977 #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 978 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 979 980 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ 981 #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 982 #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 983 984 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, 985 int tx_delay, int rx_delay) 986 { 987 u32 con0, con1; 988 989 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 : 990 RK3568_GRF_GMAC0_CON0; 991 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 992 RK3568_GRF_GMAC0_CON1; 993 994 regmap_write(bsp_priv->grf, con0, 995 RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) | 996 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay)); 997 998 regmap_write(bsp_priv->grf, con1, 999 RK3568_GMAC_PHY_INTF_SEL_RGMII | 1000 RK3568_GMAC_RXCLK_DLY_ENABLE | 1001 RK3568_GMAC_TXCLK_DLY_ENABLE); 1002 } 1003 1004 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) 1005 { 1006 u32 con1; 1007 1008 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 1009 RK3568_GRF_GMAC0_CON1; 1010 regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII); 1011 } 1012 1013 static const struct rk_gmac_ops rk3568_ops = { 1014 .set_to_rgmii = rk3568_set_to_rgmii, 1015 .set_to_rmii = rk3568_set_to_rmii, 1016 .set_speed = rk_set_clk_mac_speed, 1017 .regs_valid = true, 1018 .regs = { 1019 0xfe2a0000, /* gmac0 */ 1020 0xfe010000, /* gmac1 */ 1021 0x0, /* sentinel */ 1022 }, 1023 }; 1024 1025 /* VCCIO0_1_3_IOC */ 1026 #define RK3576_VCCIO0_1_3_IOC_CON2 0X6408 1027 #define RK3576_VCCIO0_1_3_IOC_CON3 0X640c 1028 #define RK3576_VCCIO0_1_3_IOC_CON4 0X6410 1029 #define RK3576_VCCIO0_1_3_IOC_CON5 0X6414 1030 1031 #define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 1032 #define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 1033 #define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 1034 #define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 1035 1036 #define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1037 #define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1038 1039 /* SDGMAC_GRF */ 1040 #define RK3576_GRF_GMAC_CON0 0X0020 1041 #define RK3576_GRF_GMAC_CON1 0X0024 1042 1043 #define RK3576_GMAC_RMII_MODE GRF_BIT(3) 1044 #define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3) 1045 1046 #define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7) 1047 #define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7) 1048 1049 #define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5) 1050 #define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5) 1051 1052 #define RK3576_GMAC_CLK_RGMII_DIV1 \ 1053 (GRF_CLR_BIT(6) | GRF_CLR_BIT(5)) 1054 #define RK3576_GMAC_CLK_RGMII_DIV5 \ 1055 (GRF_BIT(6) | GRF_BIT(5)) 1056 #define RK3576_GMAC_CLK_RGMII_DIV50 \ 1057 (GRF_BIT(6) | GRF_CLR_BIT(5)) 1058 1059 #define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) 1060 #define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) 1061 1062 static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv, 1063 int tx_delay, int rx_delay) 1064 { 1065 unsigned int offset_con; 1066 1067 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1068 RK3576_GRF_GMAC_CON0; 1069 1070 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE); 1071 1072 offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 : 1073 RK3576_VCCIO0_1_3_IOC_CON2; 1074 1075 /* m0 && m1 delay enabled */ 1076 regmap_write(bsp_priv->php_grf, offset_con, 1077 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 1078 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 1079 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 1080 1081 /* m0 && m1 delay value */ 1082 regmap_write(bsp_priv->php_grf, offset_con, 1083 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 1084 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 1085 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 1086 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 1087 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 1088 } 1089 1090 static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv) 1091 { 1092 unsigned int offset_con; 1093 1094 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1095 RK3576_GRF_GMAC_CON0; 1096 1097 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE); 1098 } 1099 1100 static const struct rk_reg_speed_data rk3578_reg_speed_data = { 1101 .rgmii_10 = RK3576_GMAC_CLK_RGMII_DIV50, 1102 .rgmii_100 = RK3576_GMAC_CLK_RGMII_DIV5, 1103 .rgmii_1000 = RK3576_GMAC_CLK_RGMII_DIV1, 1104 .rmii_10 = RK3576_GMAC_CLK_RMII_DIV20, 1105 .rmii_100 = RK3576_GMAC_CLK_RMII_DIV2, 1106 }; 1107 1108 static int rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, 1109 phy_interface_t interface, int speed) 1110 { 1111 unsigned int offset_con; 1112 1113 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1114 RK3576_GRF_GMAC_CON0; 1115 1116 return rk_set_reg_speed(bsp_priv, &rk3578_reg_speed_data, offset_con, 1117 interface, speed); 1118 } 1119 1120 static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1121 bool enable) 1122 { 1123 unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO : 1124 RK3576_GMAC_CLK_SELECT_CRU; 1125 unsigned int offset_con; 1126 1127 val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE : 1128 RK3576_GMAC_CLK_RMII_GATE; 1129 1130 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1131 RK3576_GRF_GMAC_CON0; 1132 1133 regmap_write(bsp_priv->grf, offset_con, val); 1134 } 1135 1136 static const struct rk_gmac_ops rk3576_ops = { 1137 .set_to_rgmii = rk3576_set_to_rgmii, 1138 .set_to_rmii = rk3576_set_to_rmii, 1139 .set_speed = rk3576_set_gmac_speed, 1140 .set_clock_selection = rk3576_set_clock_selection, 1141 .php_grf_required = true, 1142 .regs_valid = true, 1143 .regs = { 1144 0x2a220000, /* gmac0 */ 1145 0x2a230000, /* gmac1 */ 1146 0x0, /* sentinel */ 1147 }, 1148 }; 1149 1150 /* sys_grf */ 1151 #define RK3588_GRF_GMAC_CON7 0X031c 1152 #define RK3588_GRF_GMAC_CON8 0X0320 1153 #define RK3588_GRF_GMAC_CON9 0X0324 1154 1155 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3) 1156 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3) 1157 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2) 1158 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2) 1159 1160 #define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) 1161 #define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) 1162 1163 /* php_grf */ 1164 #define RK3588_GRF_GMAC_CON0 0X0008 1165 #define RK3588_GRF_CLK_CON1 0X0070 1166 1167 #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \ 1168 (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6)) 1169 #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \ 1170 (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6)) 1171 1172 #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) 1173 #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id)) 1174 1175 #define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4) 1176 #define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4) 1177 1178 #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2) 1179 #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2) 1180 1181 #define RK3588_GMAC_CLK_RGMII_DIV1(id) \ 1182 (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3)) 1183 #define RK3588_GMAC_CLK_RGMII_DIV5(id) \ 1184 (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1185 #define RK3588_GMAC_CLK_RGMII_DIV50(id) \ 1186 (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1187 1188 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) 1189 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1) 1190 1191 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv, 1192 int tx_delay, int rx_delay) 1193 { 1194 u32 offset_con, id = bsp_priv->id; 1195 1196 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 : 1197 RK3588_GRF_GMAC_CON8; 1198 1199 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1200 RK3588_GMAC_PHY_INTF_SEL_RGMII(id)); 1201 1202 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1203 RK3588_GMAC_CLK_RGMII_MODE(id)); 1204 1205 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7, 1206 RK3588_GMAC_RXCLK_DLY_ENABLE(id) | 1207 RK3588_GMAC_TXCLK_DLY_ENABLE(id)); 1208 1209 regmap_write(bsp_priv->grf, offset_con, 1210 RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) | 1211 RK3588_GMAC_CLK_TX_DL_CFG(tx_delay)); 1212 } 1213 1214 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv) 1215 { 1216 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1217 RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id)); 1218 1219 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1220 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id)); 1221 } 1222 1223 static int rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, 1224 phy_interface_t interface, int speed) 1225 { 1226 unsigned int val = 0, id = bsp_priv->id; 1227 1228 switch (speed) { 1229 case 10: 1230 if (interface == PHY_INTERFACE_MODE_RMII) 1231 val = RK3588_GMA_CLK_RMII_DIV20(id); 1232 else 1233 val = RK3588_GMAC_CLK_RGMII_DIV50(id); 1234 break; 1235 case 100: 1236 if (interface == PHY_INTERFACE_MODE_RMII) 1237 val = RK3588_GMA_CLK_RMII_DIV2(id); 1238 else 1239 val = RK3588_GMAC_CLK_RGMII_DIV5(id); 1240 break; 1241 case 1000: 1242 if (interface != PHY_INTERFACE_MODE_RMII) 1243 val = RK3588_GMAC_CLK_RGMII_DIV1(id); 1244 else 1245 goto err; 1246 break; 1247 default: 1248 goto err; 1249 } 1250 1251 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1252 1253 return 0; 1254 err: 1255 return -EINVAL; 1256 } 1257 1258 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1259 bool enable) 1260 { 1261 unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) : 1262 RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id); 1263 1264 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) : 1265 RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id); 1266 1267 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1268 } 1269 1270 static const struct rk_gmac_ops rk3588_ops = { 1271 .set_to_rgmii = rk3588_set_to_rgmii, 1272 .set_to_rmii = rk3588_set_to_rmii, 1273 .set_speed = rk3588_set_gmac_speed, 1274 .set_clock_selection = rk3588_set_clock_selection, 1275 .php_grf_required = true, 1276 .regs_valid = true, 1277 .regs = { 1278 0xfe1b0000, /* gmac0 */ 1279 0xfe1c0000, /* gmac1 */ 1280 0x0, /* sentinel */ 1281 }, 1282 }; 1283 1284 #define RV1108_GRF_GMAC_CON0 0X0900 1285 1286 /* RV1108_GRF_GMAC_CON0 */ 1287 #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 1288 GRF_BIT(6)) 1289 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) 1290 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 1291 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2) 1292 #define RV1108_GMAC_SPEED_100M GRF_BIT(2) 1293 #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7) 1294 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 1295 1296 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) 1297 { 1298 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1299 RV1108_GMAC_PHY_INTF_SEL_RMII); 1300 } 1301 1302 static const struct rk_reg_speed_data rv1108_reg_speed_data = { 1303 .rmii_10 = RV1108_GMAC_RMII_CLK_2_5M | RV1108_GMAC_SPEED_10M, 1304 .rmii_100 = RV1108_GMAC_RMII_CLK_25M | RV1108_GMAC_SPEED_100M, 1305 }; 1306 1307 static int rv1108_set_speed(struct rk_priv_data *bsp_priv, 1308 phy_interface_t interface, int speed) 1309 { 1310 return rk_set_reg_speed(bsp_priv, &rv1108_reg_speed_data, 1311 RV1108_GRF_GMAC_CON0, interface, speed); 1312 } 1313 1314 static const struct rk_gmac_ops rv1108_ops = { 1315 .set_to_rmii = rv1108_set_to_rmii, 1316 .set_speed = rv1108_set_speed, 1317 }; 1318 1319 #define RV1126_GRF_GMAC_CON0 0X0070 1320 #define RV1126_GRF_GMAC_CON1 0X0074 1321 #define RV1126_GRF_GMAC_CON2 0X0078 1322 1323 /* RV1126_GRF_GMAC_CON0 */ 1324 #define RV1126_GMAC_PHY_INTF_SEL_RGMII \ 1325 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 1326 #define RV1126_GMAC_PHY_INTF_SEL_RMII \ 1327 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 1328 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7) 1329 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7) 1330 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1) 1331 #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 1332 #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0) 1333 #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 1334 #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3) 1335 #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3) 1336 #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2) 1337 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2) 1338 1339 /* RV1126_GRF_GMAC_CON1 */ 1340 #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1341 #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1342 /* RV1126_GRF_GMAC_CON2 */ 1343 #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1344 #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1345 1346 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv, 1347 int tx_delay, int rx_delay) 1348 { 1349 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1350 RV1126_GMAC_PHY_INTF_SEL_RGMII | 1351 RV1126_GMAC_M0_RXCLK_DLY_ENABLE | 1352 RV1126_GMAC_M0_TXCLK_DLY_ENABLE | 1353 RV1126_GMAC_M1_RXCLK_DLY_ENABLE | 1354 RV1126_GMAC_M1_TXCLK_DLY_ENABLE); 1355 1356 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1, 1357 RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) | 1358 RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay)); 1359 1360 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2, 1361 RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) | 1362 RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay)); 1363 } 1364 1365 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) 1366 { 1367 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1368 RV1126_GMAC_PHY_INTF_SEL_RMII); 1369 } 1370 1371 static const struct rk_gmac_ops rv1126_ops = { 1372 .set_to_rgmii = rv1126_set_to_rgmii, 1373 .set_to_rmii = rv1126_set_to_rmii, 1374 .set_speed = rk_set_clk_mac_speed, 1375 }; 1376 1377 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) 1378 { 1379 struct rk_priv_data *bsp_priv = plat->bsp_priv; 1380 int phy_iface = bsp_priv->phy_iface; 1381 struct device *dev = bsp_priv->dev; 1382 int i, j, ret; 1383 1384 bsp_priv->clk_enabled = false; 1385 1386 bsp_priv->num_clks = ARRAY_SIZE(rk_clocks); 1387 if (phy_iface == PHY_INTERFACE_MODE_RMII) 1388 bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks); 1389 1390 bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks, 1391 sizeof(*bsp_priv->clks), GFP_KERNEL); 1392 if (!bsp_priv->clks) 1393 return -ENOMEM; 1394 1395 for (i = 0; i < ARRAY_SIZE(rk_clocks); i++) 1396 bsp_priv->clks[i].id = rk_clocks[i]; 1397 1398 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1399 for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++) 1400 bsp_priv->clks[i++].id = rk_rmii_clocks[j]; 1401 } 1402 1403 ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks, 1404 bsp_priv->clks); 1405 if (ret) 1406 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1407 1408 if (bsp_priv->clock_input) { 1409 dev_info(dev, "clock input from PHY\n"); 1410 } else if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1411 clk_set_rate(plat->stmmac_clk, 50000000); 1412 } 1413 1414 if (plat->phy_node && bsp_priv->integrated_phy) { 1415 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); 1416 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy); 1417 if (ret) 1418 return dev_err_probe(dev, ret, "Cannot get PHY clock\n"); 1419 clk_set_rate(bsp_priv->clk_phy, 50000000); 1420 } 1421 1422 return 0; 1423 } 1424 1425 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 1426 { 1427 int ret; 1428 1429 if (enable) { 1430 if (!bsp_priv->clk_enabled) { 1431 ret = clk_bulk_prepare_enable(bsp_priv->num_clks, 1432 bsp_priv->clks); 1433 if (ret) 1434 return ret; 1435 1436 ret = clk_prepare_enable(bsp_priv->clk_phy); 1437 if (ret) 1438 return ret; 1439 1440 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1441 bsp_priv->ops->set_clock_selection(bsp_priv, 1442 bsp_priv->clock_input, true); 1443 1444 mdelay(5); 1445 bsp_priv->clk_enabled = true; 1446 } 1447 } else { 1448 if (bsp_priv->clk_enabled) { 1449 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) { 1450 bsp_priv->ops->set_clock_selection(bsp_priv, 1451 bsp_priv->clock_input, false); 1452 } 1453 1454 clk_bulk_disable_unprepare(bsp_priv->num_clks, 1455 bsp_priv->clks); 1456 clk_disable_unprepare(bsp_priv->clk_phy); 1457 1458 bsp_priv->clk_enabled = false; 1459 } 1460 } 1461 1462 return 0; 1463 } 1464 1465 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) 1466 { 1467 struct regulator *ldo = bsp_priv->regulator; 1468 struct device *dev = bsp_priv->dev; 1469 int ret; 1470 1471 if (enable) { 1472 ret = regulator_enable(ldo); 1473 if (ret) 1474 dev_err(dev, "fail to enable phy-supply\n"); 1475 } else { 1476 ret = regulator_disable(ldo); 1477 if (ret) 1478 dev_err(dev, "fail to disable phy-supply\n"); 1479 } 1480 1481 return 0; 1482 } 1483 1484 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, 1485 struct plat_stmmacenet_data *plat, 1486 const struct rk_gmac_ops *ops) 1487 { 1488 struct rk_priv_data *bsp_priv; 1489 struct device *dev = &pdev->dev; 1490 struct resource *res; 1491 int ret; 1492 const char *strings = NULL; 1493 int value; 1494 1495 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); 1496 if (!bsp_priv) 1497 return ERR_PTR(-ENOMEM); 1498 1499 bsp_priv->phy_iface = plat->phy_interface; 1500 bsp_priv->ops = ops; 1501 1502 /* Some SoCs have multiple MAC controllers, which need 1503 * to be distinguished. 1504 */ 1505 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1506 if (res && ops->regs_valid) { 1507 int i = 0; 1508 1509 while (ops->regs[i]) { 1510 if (ops->regs[i] == res->start) { 1511 bsp_priv->id = i; 1512 break; 1513 } 1514 i++; 1515 } 1516 } 1517 1518 bsp_priv->regulator = devm_regulator_get(dev, "phy"); 1519 if (IS_ERR(bsp_priv->regulator)) { 1520 ret = PTR_ERR(bsp_priv->regulator); 1521 dev_err_probe(dev, ret, "failed to get phy regulator\n"); 1522 return ERR_PTR(ret); 1523 } 1524 1525 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); 1526 if (ret) { 1527 dev_err(dev, "Can not read property: clock_in_out.\n"); 1528 bsp_priv->clock_input = true; 1529 } else { 1530 dev_info(dev, "clock input or output? (%s).\n", 1531 strings); 1532 if (!strcmp(strings, "input")) 1533 bsp_priv->clock_input = true; 1534 else 1535 bsp_priv->clock_input = false; 1536 } 1537 1538 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); 1539 if (ret) { 1540 bsp_priv->tx_delay = 0x30; 1541 dev_err(dev, "Can not read property: tx_delay."); 1542 dev_err(dev, "set tx_delay to 0x%x\n", 1543 bsp_priv->tx_delay); 1544 } else { 1545 dev_info(dev, "TX delay(0x%x).\n", value); 1546 bsp_priv->tx_delay = value; 1547 } 1548 1549 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); 1550 if (ret) { 1551 bsp_priv->rx_delay = 0x10; 1552 dev_err(dev, "Can not read property: rx_delay."); 1553 dev_err(dev, "set rx_delay to 0x%x\n", 1554 bsp_priv->rx_delay); 1555 } else { 1556 dev_info(dev, "RX delay(0x%x).\n", value); 1557 bsp_priv->rx_delay = value; 1558 } 1559 1560 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 1561 "rockchip,grf"); 1562 if (IS_ERR(bsp_priv->grf)) { 1563 dev_err_probe(dev, PTR_ERR(bsp_priv->grf), 1564 "failed to lookup rockchip,grf\n"); 1565 return ERR_CAST(bsp_priv->grf); 1566 } 1567 1568 if (ops->php_grf_required) { 1569 bsp_priv->php_grf = 1570 syscon_regmap_lookup_by_phandle(dev->of_node, 1571 "rockchip,php-grf"); 1572 if (IS_ERR(bsp_priv->php_grf)) { 1573 dev_err_probe(dev, PTR_ERR(bsp_priv->php_grf), 1574 "failed to lookup rockchip,php-grf\n"); 1575 return ERR_CAST(bsp_priv->php_grf); 1576 } 1577 } 1578 1579 if (plat->phy_node) { 1580 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, 1581 "phy-is-integrated"); 1582 if (bsp_priv->integrated_phy) { 1583 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL); 1584 if (IS_ERR(bsp_priv->phy_reset)) { 1585 dev_err(&pdev->dev, "No PHY reset control found.\n"); 1586 bsp_priv->phy_reset = NULL; 1587 } 1588 } 1589 } 1590 dev_info(dev, "integrated PHY? (%s).\n", 1591 bsp_priv->integrated_phy ? "yes" : "no"); 1592 1593 bsp_priv->dev = dev; 1594 1595 return bsp_priv; 1596 } 1597 1598 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv) 1599 { 1600 switch (bsp_priv->phy_iface) { 1601 case PHY_INTERFACE_MODE_RGMII: 1602 case PHY_INTERFACE_MODE_RGMII_ID: 1603 case PHY_INTERFACE_MODE_RGMII_RXID: 1604 case PHY_INTERFACE_MODE_RGMII_TXID: 1605 if (!bsp_priv->ops->set_to_rgmii) 1606 return -EINVAL; 1607 break; 1608 case PHY_INTERFACE_MODE_RMII: 1609 if (!bsp_priv->ops->set_to_rmii) 1610 return -EINVAL; 1611 break; 1612 default: 1613 dev_err(bsp_priv->dev, 1614 "unsupported interface %d", bsp_priv->phy_iface); 1615 } 1616 return 0; 1617 } 1618 1619 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) 1620 { 1621 struct device *dev = bsp_priv->dev; 1622 int ret; 1623 1624 ret = rk_gmac_check_ops(bsp_priv); 1625 if (ret) 1626 return ret; 1627 1628 ret = gmac_clk_enable(bsp_priv, true); 1629 if (ret) 1630 return ret; 1631 1632 /*rmii or rgmii*/ 1633 switch (bsp_priv->phy_iface) { 1634 case PHY_INTERFACE_MODE_RGMII: 1635 dev_info(dev, "init for RGMII\n"); 1636 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 1637 bsp_priv->rx_delay); 1638 break; 1639 case PHY_INTERFACE_MODE_RGMII_ID: 1640 dev_info(dev, "init for RGMII_ID\n"); 1641 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); 1642 break; 1643 case PHY_INTERFACE_MODE_RGMII_RXID: 1644 dev_info(dev, "init for RGMII_RXID\n"); 1645 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); 1646 break; 1647 case PHY_INTERFACE_MODE_RGMII_TXID: 1648 dev_info(dev, "init for RGMII_TXID\n"); 1649 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); 1650 break; 1651 case PHY_INTERFACE_MODE_RMII: 1652 dev_info(dev, "init for RMII\n"); 1653 bsp_priv->ops->set_to_rmii(bsp_priv); 1654 break; 1655 default: 1656 dev_err(dev, "NO interface defined!\n"); 1657 } 1658 1659 ret = phy_power_on(bsp_priv, true); 1660 if (ret) { 1661 gmac_clk_enable(bsp_priv, false); 1662 return ret; 1663 } 1664 1665 pm_runtime_get_sync(dev); 1666 1667 if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup) 1668 bsp_priv->ops->integrated_phy_powerup(bsp_priv); 1669 1670 return 0; 1671 } 1672 1673 static void rk_gmac_powerdown(struct rk_priv_data *gmac) 1674 { 1675 if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown) 1676 gmac->ops->integrated_phy_powerdown(gmac); 1677 1678 pm_runtime_put_sync(gmac->dev); 1679 1680 phy_power_on(gmac, false); 1681 gmac_clk_enable(gmac, false); 1682 } 1683 1684 static void rk_get_interfaces(struct stmmac_priv *priv, void *bsp_priv, 1685 unsigned long *interfaces) 1686 { 1687 struct rk_priv_data *rk = bsp_priv; 1688 1689 if (rk->ops->set_to_rgmii) 1690 phy_interface_set_rgmii(interfaces); 1691 1692 if (rk->ops->set_to_rmii) 1693 __set_bit(PHY_INTERFACE_MODE_RMII, interfaces); 1694 } 1695 1696 static int rk_set_clk_tx_rate(void *bsp_priv_, struct clk *clk_tx_i, 1697 phy_interface_t interface, int speed) 1698 { 1699 struct rk_priv_data *bsp_priv = bsp_priv_; 1700 1701 if (bsp_priv->ops->set_speed) 1702 return bsp_priv->ops->set_speed(bsp_priv, bsp_priv->phy_iface, 1703 speed); 1704 1705 return -EINVAL; 1706 } 1707 1708 static int rk_gmac_suspend(struct device *dev, void *bsp_priv_) 1709 { 1710 struct rk_priv_data *bsp_priv = bsp_priv_; 1711 1712 /* Keep the PHY up if we use Wake-on-Lan. */ 1713 if (!device_may_wakeup(dev)) 1714 rk_gmac_powerdown(bsp_priv); 1715 1716 return 0; 1717 } 1718 1719 static int rk_gmac_resume(struct device *dev, void *bsp_priv_) 1720 { 1721 struct rk_priv_data *bsp_priv = bsp_priv_; 1722 1723 /* The PHY was up for Wake-on-Lan. */ 1724 if (!device_may_wakeup(dev)) 1725 rk_gmac_powerup(bsp_priv); 1726 1727 return 0; 1728 } 1729 1730 static int rk_gmac_probe(struct platform_device *pdev) 1731 { 1732 struct plat_stmmacenet_data *plat_dat; 1733 struct stmmac_resources stmmac_res; 1734 const struct rk_gmac_ops *data; 1735 int ret; 1736 1737 data = of_device_get_match_data(&pdev->dev); 1738 if (!data) { 1739 dev_err(&pdev->dev, "no of match data provided\n"); 1740 return -EINVAL; 1741 } 1742 1743 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1744 if (ret) 1745 return ret; 1746 1747 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 1748 if (IS_ERR(plat_dat)) 1749 return PTR_ERR(plat_dat); 1750 1751 /* If the stmmac is not already selected as gmac4, 1752 * then make sure we fallback to gmac. 1753 */ 1754 if (!plat_dat->has_gmac4) { 1755 plat_dat->has_gmac = true; 1756 plat_dat->rx_fifo_size = 4096; 1757 plat_dat->tx_fifo_size = 2048; 1758 } 1759 1760 plat_dat->get_interfaces = rk_get_interfaces; 1761 plat_dat->set_clk_tx_rate = rk_set_clk_tx_rate; 1762 plat_dat->suspend = rk_gmac_suspend; 1763 plat_dat->resume = rk_gmac_resume; 1764 1765 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data); 1766 if (IS_ERR(plat_dat->bsp_priv)) 1767 return PTR_ERR(plat_dat->bsp_priv); 1768 1769 ret = rk_gmac_clk_init(plat_dat); 1770 if (ret) 1771 return ret; 1772 1773 ret = rk_gmac_powerup(plat_dat->bsp_priv); 1774 if (ret) 1775 return ret; 1776 1777 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1778 if (ret) 1779 goto err_gmac_powerdown; 1780 1781 return 0; 1782 1783 err_gmac_powerdown: 1784 rk_gmac_powerdown(plat_dat->bsp_priv); 1785 1786 return ret; 1787 } 1788 1789 static void rk_gmac_remove(struct platform_device *pdev) 1790 { 1791 struct stmmac_priv *priv = netdev_priv(platform_get_drvdata(pdev)); 1792 struct rk_priv_data *bsp_priv = priv->plat->bsp_priv; 1793 1794 stmmac_dvr_remove(&pdev->dev); 1795 1796 rk_gmac_powerdown(bsp_priv); 1797 1798 if (priv->plat->phy_node && bsp_priv->integrated_phy) 1799 clk_put(bsp_priv->clk_phy); 1800 } 1801 1802 static const struct of_device_id rk_gmac_dwmac_match[] = { 1803 { .compatible = "rockchip,px30-gmac", .data = &px30_ops }, 1804 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops }, 1805 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops }, 1806 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops }, 1807 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops }, 1808 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops }, 1809 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, 1810 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, 1811 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, 1812 { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops }, 1813 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops }, 1814 { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops }, 1815 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops }, 1816 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops }, 1817 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops }, 1818 { } 1819 }; 1820 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); 1821 1822 static struct platform_driver rk_gmac_dwmac_driver = { 1823 .probe = rk_gmac_probe, 1824 .remove = rk_gmac_remove, 1825 .driver = { 1826 .name = "rk_gmac-dwmac", 1827 .pm = &stmmac_simple_pm_ops, 1828 .of_match_table = rk_gmac_dwmac_match, 1829 }, 1830 }; 1831 module_platform_driver(rk_gmac_dwmac_driver); 1832 1833 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>"); 1834 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer"); 1835 MODULE_LICENSE("GPL"); 1836