1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2018-19, Linaro Limited 3 4 #include <linux/module.h> 5 #include <linux/of.h> 6 #include <linux/of_net.h> 7 #include <linux/platform_device.h> 8 #include <linux/phy.h> 9 #include <linux/phy/phy.h> 10 11 #include "stmmac.h" 12 #include "stmmac_platform.h" 13 14 #define RGMII_IO_MACRO_CONFIG 0x0 15 #define SDCC_HC_REG_DLL_CONFIG 0x4 16 #define SDCC_TEST_CTL 0x8 17 #define SDCC_HC_REG_DDR_CONFIG 0xC 18 #define SDCC_HC_REG_DLL_CONFIG2 0x10 19 #define SDC4_STATUS 0x14 20 #define SDCC_USR_CTL 0x18 21 #define RGMII_IO_MACRO_CONFIG2 0x1C 22 #define RGMII_IO_MACRO_DEBUG1 0x20 23 #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28 24 25 /* RGMII_IO_MACRO_CONFIG fields */ 26 #define RGMII_CONFIG_FUNC_CLK_EN BIT(30) 27 #define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) 28 #define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20) 29 #define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17) 30 #define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8) 31 #define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6) 32 #define RGMII_CONFIG_INTF_SEL GENMASK(5, 4) 33 #define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) 34 #define RGMII_CONFIG_LOOPBACK_EN BIT(2) 35 #define RGMII_CONFIG_PROG_SWAP BIT(1) 36 #define RGMII_CONFIG_DDR_MODE BIT(0) 37 #define RGMII_CONFIG_SGMII_CLK_DVDR GENMASK(18, 10) 38 39 /* SDCC_HC_REG_DLL_CONFIG fields */ 40 #define SDCC_DLL_CONFIG_DLL_RST BIT(30) 41 #define SDCC_DLL_CONFIG_PDN BIT(29) 42 #define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24) 43 #define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20) 44 #define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) 45 #define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) 46 #define SDCC_DLL_CONFIG_CDR_EN BIT(17) 47 #define SDCC_DLL_CONFIG_DLL_EN BIT(16) 48 #define SDCC_DLL_MCLK_GATING_EN BIT(5) 49 #define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2) 50 51 /* SDCC_HC_REG_DDR_CONFIG fields */ 52 #define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) 53 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21) 54 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27) 55 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) 56 #define SDCC_DDR_CONFIG_TCXO_CYCLES_CNT GENMASK(11, 9) 57 #define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0) 58 59 /* SDCC_HC_REG_DLL_CONFIG2 fields */ 60 #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) 61 #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10) 62 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2) 63 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) 64 #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) 65 66 /* SDC4_STATUS bits */ 67 #define SDC4_STATUS_DLL_LOCK BIT(7) 68 69 /* RGMII_IO_MACRO_CONFIG2 fields */ 70 #define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17) 71 #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) 72 #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) 73 #define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) 74 #define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) 75 #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) 76 #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) 77 78 /* MAC_CTRL_REG bits */ 79 #define ETHQOS_MAC_CTRL_SPEED_MODE BIT(14) 80 #define ETHQOS_MAC_CTRL_PORT_SEL BIT(15) 81 82 #define SGMII_10M_RX_CLK_DVDR 0x31 83 84 struct ethqos_emac_por { 85 unsigned int offset; 86 unsigned int value; 87 }; 88 89 struct ethqos_emac_driver_data { 90 const struct ethqos_emac_por *por; 91 unsigned int num_por; 92 bool rgmii_config_loopback_en; 93 bool has_emac_ge_3; 94 const char *link_clk_name; 95 bool has_integrated_pcs; 96 u32 dma_addr_width; 97 struct dwmac4_addrs dwmac4_addrs; 98 }; 99 100 struct qcom_ethqos { 101 struct platform_device *pdev; 102 void __iomem *rgmii_base; 103 void __iomem *mac_base; 104 int (*configure_func)(struct qcom_ethqos *ethqos); 105 106 unsigned int link_clk_rate; 107 struct clk *link_clk; 108 struct phy *serdes_phy; 109 unsigned int speed; 110 int serdes_speed; 111 phy_interface_t phy_mode; 112 113 const struct ethqos_emac_por *por; 114 unsigned int num_por; 115 bool rgmii_config_loopback_en; 116 bool has_emac_ge_3; 117 }; 118 119 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) 120 { 121 return readl(ethqos->rgmii_base + offset); 122 } 123 124 static void rgmii_writel(struct qcom_ethqos *ethqos, 125 int value, unsigned int offset) 126 { 127 writel(value, ethqos->rgmii_base + offset); 128 } 129 130 static void rgmii_updatel(struct qcom_ethqos *ethqos, 131 int mask, int val, unsigned int offset) 132 { 133 unsigned int temp; 134 135 temp = rgmii_readl(ethqos, offset); 136 temp = (temp & ~(mask)) | val; 137 rgmii_writel(ethqos, temp, offset); 138 } 139 140 static void rgmii_dump(void *priv) 141 { 142 struct qcom_ethqos *ethqos = priv; 143 struct device *dev = ðqos->pdev->dev; 144 145 dev_dbg(dev, "Rgmii register dump\n"); 146 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %x\n", 147 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG)); 148 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %x\n", 149 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG)); 150 dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %x\n", 151 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG)); 152 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n", 153 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2)); 154 dev_dbg(dev, "SDC4_STATUS: %x\n", 155 rgmii_readl(ethqos, SDC4_STATUS)); 156 dev_dbg(dev, "SDCC_USR_CTL: %x\n", 157 rgmii_readl(ethqos, SDCC_USR_CTL)); 158 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %x\n", 159 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2)); 160 dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %x\n", 161 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1)); 162 dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n", 163 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG)); 164 } 165 166 /* Clock rates */ 167 #define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL) 168 #define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL) 169 #define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL) 170 171 static void 172 ethqos_update_link_clk(struct qcom_ethqos *ethqos, unsigned int speed) 173 { 174 if (!phy_interface_mode_is_rgmii(ethqos->phy_mode)) 175 return; 176 177 switch (speed) { 178 case SPEED_1000: 179 ethqos->link_clk_rate = RGMII_1000_NOM_CLK_FREQ; 180 break; 181 182 case SPEED_100: 183 ethqos->link_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ; 184 break; 185 186 case SPEED_10: 187 ethqos->link_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ; 188 break; 189 } 190 191 clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate); 192 } 193 194 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) 195 { 196 rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN, 197 RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); 198 } 199 200 static const struct ethqos_emac_por emac_v2_3_0_por[] = { 201 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, 202 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 203 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 204 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 205 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 206 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 207 }; 208 209 static const struct ethqos_emac_driver_data emac_v2_3_0_data = { 210 .por = emac_v2_3_0_por, 211 .num_por = ARRAY_SIZE(emac_v2_3_0_por), 212 .rgmii_config_loopback_en = true, 213 .has_emac_ge_3 = false, 214 }; 215 216 static const struct ethqos_emac_por emac_v2_1_0_por[] = { 217 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 }, 218 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 219 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 220 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 221 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 222 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 223 }; 224 225 static const struct ethqos_emac_driver_data emac_v2_1_0_data = { 226 .por = emac_v2_1_0_por, 227 .num_por = ARRAY_SIZE(emac_v2_1_0_por), 228 .rgmii_config_loopback_en = false, 229 .has_emac_ge_3 = false, 230 }; 231 232 static const struct ethqos_emac_por emac_v3_0_0_por[] = { 233 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 }, 234 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c }, 235 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 }, 236 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 237 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 238 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 239 }; 240 241 static const struct ethqos_emac_driver_data emac_v3_0_0_data = { 242 .por = emac_v3_0_0_por, 243 .num_por = ARRAY_SIZE(emac_v3_0_0_por), 244 .rgmii_config_loopback_en = false, 245 .has_emac_ge_3 = true, 246 .dwmac4_addrs = { 247 .dma_chan = 0x00008100, 248 .dma_chan_offset = 0x1000, 249 .mtl_chan = 0x00008000, 250 .mtl_chan_offset = 0x1000, 251 .mtl_ets_ctrl = 0x00008010, 252 .mtl_ets_ctrl_offset = 0x1000, 253 .mtl_txq_weight = 0x00008018, 254 .mtl_txq_weight_offset = 0x1000, 255 .mtl_send_slp_cred = 0x0000801c, 256 .mtl_send_slp_cred_offset = 0x1000, 257 .mtl_high_cred = 0x00008020, 258 .mtl_high_cred_offset = 0x1000, 259 .mtl_low_cred = 0x00008024, 260 .mtl_low_cred_offset = 0x1000, 261 }, 262 }; 263 264 static const struct ethqos_emac_por emac_v4_0_0_por[] = { 265 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 }, 266 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c }, 267 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 }, 268 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 269 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 270 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 271 }; 272 273 static const struct ethqos_emac_driver_data emac_v4_0_0_data = { 274 .por = emac_v4_0_0_por, 275 .num_por = ARRAY_SIZE(emac_v3_0_0_por), 276 .rgmii_config_loopback_en = false, 277 .has_emac_ge_3 = true, 278 .link_clk_name = "phyaux", 279 .has_integrated_pcs = true, 280 .dma_addr_width = 36, 281 .dwmac4_addrs = { 282 .dma_chan = 0x00008100, 283 .dma_chan_offset = 0x1000, 284 .mtl_chan = 0x00008000, 285 .mtl_chan_offset = 0x1000, 286 .mtl_ets_ctrl = 0x00008010, 287 .mtl_ets_ctrl_offset = 0x1000, 288 .mtl_txq_weight = 0x00008018, 289 .mtl_txq_weight_offset = 0x1000, 290 .mtl_send_slp_cred = 0x0000801c, 291 .mtl_send_slp_cred_offset = 0x1000, 292 .mtl_high_cred = 0x00008020, 293 .mtl_high_cred_offset = 0x1000, 294 .mtl_low_cred = 0x00008024, 295 .mtl_low_cred_offset = 0x1000, 296 }, 297 }; 298 299 static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 300 { 301 struct device *dev = ðqos->pdev->dev; 302 unsigned int val; 303 int retry = 1000; 304 305 /* Set CDR_EN */ 306 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN, 307 SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG); 308 309 /* Set CDR_EXT_EN */ 310 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN, 311 SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG); 312 313 /* Clear CK_OUT_EN */ 314 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 315 0, SDCC_HC_REG_DLL_CONFIG); 316 317 /* Set DLL_EN */ 318 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 319 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 320 321 if (!ethqos->has_emac_ge_3) { 322 rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN, 323 0, SDCC_HC_REG_DLL_CONFIG); 324 325 rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE, 326 0, SDCC_HC_REG_DLL_CONFIG); 327 } 328 329 /* Wait for CK_OUT_EN clear */ 330 do { 331 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 332 val &= SDCC_DLL_CONFIG_CK_OUT_EN; 333 if (!val) 334 break; 335 mdelay(1); 336 retry--; 337 } while (retry > 0); 338 if (!retry) 339 dev_err(dev, "Clear CK_OUT_EN timedout\n"); 340 341 /* Set CK_OUT_EN */ 342 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 343 SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG); 344 345 /* Wait for CK_OUT_EN set */ 346 retry = 1000; 347 do { 348 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 349 val &= SDCC_DLL_CONFIG_CK_OUT_EN; 350 if (val) 351 break; 352 mdelay(1); 353 retry--; 354 } while (retry > 0); 355 if (!retry) 356 dev_err(dev, "Set CK_OUT_EN timedout\n"); 357 358 /* Set DDR_CAL_EN */ 359 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN, 360 SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2); 361 362 if (!ethqos->has_emac_ge_3) { 363 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS, 364 0, SDCC_HC_REG_DLL_CONFIG2); 365 366 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, 367 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2); 368 369 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, 370 BIT(2), SDCC_HC_REG_DLL_CONFIG2); 371 372 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 373 SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 374 SDCC_HC_REG_DLL_CONFIG2); 375 } 376 377 return 0; 378 } 379 380 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 381 { 382 struct device *dev = ðqos->pdev->dev; 383 int phase_shift; 384 int loopback; 385 386 /* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */ 387 if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID || 388 ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID) 389 phase_shift = 0; 390 else 391 phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN; 392 393 /* Disable loopback mode */ 394 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN, 395 0, RGMII_IO_MACRO_CONFIG2); 396 397 /* Determine if this platform wants loopback enabled after programming */ 398 if (ethqos->rgmii_config_loopback_en) 399 loopback = RGMII_CONFIG_LOOPBACK_EN; 400 else 401 loopback = 0; 402 403 /* Select RGMII, write 0 to interface select */ 404 rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL, 405 0, RGMII_IO_MACRO_CONFIG); 406 407 switch (ethqos->speed) { 408 case SPEED_1000: 409 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 410 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 411 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 412 0, RGMII_IO_MACRO_CONFIG); 413 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 414 RGMII_CONFIG_POS_NEG_DATA_SEL, 415 RGMII_IO_MACRO_CONFIG); 416 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 417 RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG); 418 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 419 0, RGMII_IO_MACRO_CONFIG2); 420 421 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 422 phase_shift, RGMII_IO_MACRO_CONFIG2); 423 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 424 0, RGMII_IO_MACRO_CONFIG2); 425 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 426 RGMII_CONFIG2_RX_PROG_SWAP, 427 RGMII_IO_MACRO_CONFIG2); 428 429 /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns, 430 * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns 431 */ 432 if (ethqos->has_emac_ge_3) { 433 /* 0.9 ns */ 434 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 435 115, SDCC_HC_REG_DDR_CONFIG); 436 } else { 437 /* 1.8 ns */ 438 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 439 57, SDCC_HC_REG_DDR_CONFIG); 440 } 441 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN, 442 SDCC_DDR_CONFIG_PRG_DLY_EN, 443 SDCC_HC_REG_DDR_CONFIG); 444 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 445 loopback, RGMII_IO_MACRO_CONFIG); 446 break; 447 448 case SPEED_100: 449 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 450 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 451 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 452 RGMII_CONFIG_BYPASS_TX_ID_EN, 453 RGMII_IO_MACRO_CONFIG); 454 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 455 0, RGMII_IO_MACRO_CONFIG); 456 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 457 0, RGMII_IO_MACRO_CONFIG); 458 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 459 0, RGMII_IO_MACRO_CONFIG2); 460 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 461 phase_shift, RGMII_IO_MACRO_CONFIG2); 462 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2, 463 BIT(6), RGMII_IO_MACRO_CONFIG); 464 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 465 0, RGMII_IO_MACRO_CONFIG2); 466 467 if (ethqos->has_emac_ge_3) 468 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 469 RGMII_CONFIG2_RX_PROG_SWAP, 470 RGMII_IO_MACRO_CONFIG2); 471 else 472 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 473 0, RGMII_IO_MACRO_CONFIG2); 474 475 /* Write 0x5 to PRG_RCLK_DLY_CODE */ 476 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 477 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 478 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 479 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 480 SDCC_HC_REG_DDR_CONFIG); 481 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 482 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 483 SDCC_HC_REG_DDR_CONFIG); 484 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 485 loopback, RGMII_IO_MACRO_CONFIG); 486 break; 487 488 case SPEED_10: 489 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 490 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 491 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 492 RGMII_CONFIG_BYPASS_TX_ID_EN, 493 RGMII_IO_MACRO_CONFIG); 494 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 495 0, RGMII_IO_MACRO_CONFIG); 496 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 497 0, RGMII_IO_MACRO_CONFIG); 498 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 499 0, RGMII_IO_MACRO_CONFIG2); 500 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 501 phase_shift, RGMII_IO_MACRO_CONFIG2); 502 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9, 503 BIT(12) | GENMASK(9, 8), 504 RGMII_IO_MACRO_CONFIG); 505 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 506 0, RGMII_IO_MACRO_CONFIG2); 507 if (ethqos->has_emac_ge_3) 508 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 509 RGMII_CONFIG2_RX_PROG_SWAP, 510 RGMII_IO_MACRO_CONFIG2); 511 else 512 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 513 0, RGMII_IO_MACRO_CONFIG2); 514 /* Write 0x5 to PRG_RCLK_DLY_CODE */ 515 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 516 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 517 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 518 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 519 SDCC_HC_REG_DDR_CONFIG); 520 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 521 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 522 SDCC_HC_REG_DDR_CONFIG); 523 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 524 loopback, RGMII_IO_MACRO_CONFIG); 525 break; 526 default: 527 dev_err(dev, "Invalid speed %d\n", ethqos->speed); 528 return -EINVAL; 529 } 530 531 return 0; 532 } 533 534 static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos) 535 { 536 struct device *dev = ðqos->pdev->dev; 537 volatile unsigned int dll_lock; 538 unsigned int i, retry = 1000; 539 540 /* Reset to POR values and enable clk */ 541 for (i = 0; i < ethqos->num_por; i++) 542 rgmii_writel(ethqos, ethqos->por[i].value, 543 ethqos->por[i].offset); 544 ethqos_set_func_clk_en(ethqos); 545 546 /* Initialize the DLL first */ 547 548 /* Set DLL_RST */ 549 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 550 SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG); 551 552 /* Set PDN */ 553 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 554 SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG); 555 556 if (ethqos->has_emac_ge_3) { 557 if (ethqos->speed == SPEED_1000) { 558 rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL); 559 rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL); 560 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 561 } else { 562 rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL); 563 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 564 } 565 } 566 567 /* Clear DLL_RST */ 568 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0, 569 SDCC_HC_REG_DLL_CONFIG); 570 571 /* Clear PDN */ 572 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0, 573 SDCC_HC_REG_DLL_CONFIG); 574 575 if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) { 576 /* Set DLL_EN */ 577 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 578 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 579 580 /* Set CK_OUT_EN */ 581 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 582 SDCC_DLL_CONFIG_CK_OUT_EN, 583 SDCC_HC_REG_DLL_CONFIG); 584 585 /* Set USR_CTL bit 26 with mask of 3 bits */ 586 if (!ethqos->has_emac_ge_3) 587 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), 588 SDCC_USR_CTL); 589 590 /* wait for DLL LOCK */ 591 do { 592 mdelay(1); 593 dll_lock = rgmii_readl(ethqos, SDC4_STATUS); 594 if (dll_lock & SDC4_STATUS_DLL_LOCK) 595 break; 596 retry--; 597 } while (retry > 0); 598 if (!retry) 599 dev_err(dev, "Timeout while waiting for DLL lock\n"); 600 } 601 602 if (ethqos->speed == SPEED_1000) 603 ethqos_dll_configure(ethqos); 604 605 ethqos_rgmii_macro_init(ethqos); 606 607 return 0; 608 } 609 610 /* On interface toggle MAC registers gets reset. 611 * Configure MAC block for SGMII on ethernet phy link up 612 */ 613 static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos) 614 { 615 struct net_device *dev = platform_get_drvdata(ethqos->pdev); 616 struct stmmac_priv *priv = netdev_priv(dev); 617 int val; 618 619 val = readl(ethqos->mac_base + MAC_CTRL_REG); 620 621 switch (ethqos->speed) { 622 case SPEED_2500: 623 val &= ~ETHQOS_MAC_CTRL_PORT_SEL; 624 rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG, 625 RGMII_CONFIG2_RGMII_CLK_SEL_CFG, 626 RGMII_IO_MACRO_CONFIG2); 627 if (ethqos->serdes_speed != SPEED_2500) 628 phy_set_speed(ethqos->serdes_phy, SPEED_2500); 629 ethqos->serdes_speed = SPEED_2500; 630 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 0, 0, 0); 631 break; 632 case SPEED_1000: 633 val &= ~ETHQOS_MAC_CTRL_PORT_SEL; 634 rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG, 635 RGMII_CONFIG2_RGMII_CLK_SEL_CFG, 636 RGMII_IO_MACRO_CONFIG2); 637 if (ethqos->serdes_speed != SPEED_1000) 638 phy_set_speed(ethqos->serdes_phy, SPEED_1000); 639 ethqos->serdes_speed = SPEED_1000; 640 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, 0, 0); 641 break; 642 case SPEED_100: 643 val |= ETHQOS_MAC_CTRL_PORT_SEL | ETHQOS_MAC_CTRL_SPEED_MODE; 644 if (ethqos->serdes_speed != SPEED_1000) 645 phy_set_speed(ethqos->serdes_phy, SPEED_1000); 646 ethqos->serdes_speed = SPEED_1000; 647 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, 0, 0); 648 break; 649 case SPEED_10: 650 val |= ETHQOS_MAC_CTRL_PORT_SEL; 651 val &= ~ETHQOS_MAC_CTRL_SPEED_MODE; 652 rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR, 653 FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR, 654 SGMII_10M_RX_CLK_DVDR), 655 RGMII_IO_MACRO_CONFIG); 656 if (ethqos->serdes_speed != SPEED_1000) 657 phy_set_speed(ethqos->serdes_phy, ethqos->speed); 658 ethqos->serdes_speed = SPEED_1000; 659 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, 0, 0); 660 break; 661 } 662 663 writel(val, ethqos->mac_base + MAC_CTRL_REG); 664 665 return val; 666 } 667 668 static int ethqos_configure(struct qcom_ethqos *ethqos) 669 { 670 return ethqos->configure_func(ethqos); 671 } 672 673 static void ethqos_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode) 674 { 675 struct qcom_ethqos *ethqos = priv; 676 677 ethqos->speed = speed; 678 ethqos_update_link_clk(ethqos, speed); 679 ethqos_configure(ethqos); 680 } 681 682 static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv) 683 { 684 struct qcom_ethqos *ethqos = priv; 685 int ret; 686 687 ret = phy_init(ethqos->serdes_phy); 688 if (ret) 689 return ret; 690 691 ret = phy_power_on(ethqos->serdes_phy); 692 if (ret) 693 return ret; 694 695 return phy_set_speed(ethqos->serdes_phy, ethqos->speed); 696 } 697 698 static void qcom_ethqos_serdes_powerdown(struct net_device *ndev, void *priv) 699 { 700 struct qcom_ethqos *ethqos = priv; 701 702 phy_power_off(ethqos->serdes_phy); 703 phy_exit(ethqos->serdes_phy); 704 } 705 706 static int ethqos_clks_config(void *priv, bool enabled) 707 { 708 struct qcom_ethqos *ethqos = priv; 709 int ret = 0; 710 711 if (enabled) { 712 ret = clk_prepare_enable(ethqos->link_clk); 713 if (ret) { 714 dev_err(ðqos->pdev->dev, "link_clk enable failed\n"); 715 return ret; 716 } 717 718 /* Enable functional clock to prevent DMA reset to timeout due 719 * to lacking PHY clock after the hardware block has been power 720 * cycled. The actual configuration will be adjusted once 721 * ethqos_fix_mac_speed() is invoked. 722 */ 723 ethqos_set_func_clk_en(ethqos); 724 } else { 725 clk_disable_unprepare(ethqos->link_clk); 726 } 727 728 return ret; 729 } 730 731 static void ethqos_clks_disable(void *data) 732 { 733 ethqos_clks_config(data, false); 734 } 735 736 static void ethqos_ptp_clk_freq_config(struct stmmac_priv *priv) 737 { 738 struct plat_stmmacenet_data *plat_dat = priv->plat; 739 int err; 740 741 if (!plat_dat->clk_ptp_ref) 742 return; 743 744 /* Max the PTP ref clock out to get the best resolution possible */ 745 err = clk_set_rate(plat_dat->clk_ptp_ref, ULONG_MAX); 746 if (err) 747 netdev_err(priv->dev, "Failed to max out clk_ptp_ref: %d\n", err); 748 plat_dat->clk_ptp_rate = clk_get_rate(plat_dat->clk_ptp_ref); 749 750 netdev_dbg(priv->dev, "PTP rate %d\n", plat_dat->clk_ptp_rate); 751 } 752 753 static int qcom_ethqos_probe(struct platform_device *pdev) 754 { 755 struct device_node *np = pdev->dev.of_node; 756 const struct ethqos_emac_driver_data *data; 757 struct plat_stmmacenet_data *plat_dat; 758 struct stmmac_resources stmmac_res; 759 struct device *dev = &pdev->dev; 760 struct qcom_ethqos *ethqos; 761 int ret, i; 762 763 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 764 if (ret) 765 return dev_err_probe(dev, ret, 766 "Failed to get platform resources\n"); 767 768 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 769 if (IS_ERR(plat_dat)) { 770 return dev_err_probe(dev, PTR_ERR(plat_dat), 771 "dt configuration failed\n"); 772 } 773 774 plat_dat->clks_config = ethqos_clks_config; 775 776 ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL); 777 if (!ethqos) 778 return -ENOMEM; 779 780 ret = of_get_phy_mode(np, ðqos->phy_mode); 781 if (ret) 782 return dev_err_probe(dev, ret, "Failed to get phy mode\n"); 783 switch (ethqos->phy_mode) { 784 case PHY_INTERFACE_MODE_RGMII: 785 case PHY_INTERFACE_MODE_RGMII_ID: 786 case PHY_INTERFACE_MODE_RGMII_RXID: 787 case PHY_INTERFACE_MODE_RGMII_TXID: 788 ethqos->configure_func = ethqos_configure_rgmii; 789 break; 790 case PHY_INTERFACE_MODE_SGMII: 791 ethqos->configure_func = ethqos_configure_sgmii; 792 break; 793 default: 794 dev_err(dev, "Unsupported phy mode %s\n", 795 phy_modes(ethqos->phy_mode)); 796 return -EINVAL; 797 } 798 799 ethqos->pdev = pdev; 800 ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); 801 if (IS_ERR(ethqos->rgmii_base)) 802 return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base), 803 "Failed to map rgmii resource\n"); 804 805 ethqos->mac_base = stmmac_res.addr; 806 807 data = of_device_get_match_data(dev); 808 ethqos->por = data->por; 809 ethqos->num_por = data->num_por; 810 ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en; 811 ethqos->has_emac_ge_3 = data->has_emac_ge_3; 812 813 ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii"); 814 if (IS_ERR(ethqos->link_clk)) 815 return dev_err_probe(dev, PTR_ERR(ethqos->link_clk), 816 "Failed to get link_clk\n"); 817 818 ret = ethqos_clks_config(ethqos, true); 819 if (ret) 820 return ret; 821 822 ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); 823 if (ret) 824 return ret; 825 826 ethqos->serdes_phy = devm_phy_optional_get(dev, "serdes"); 827 if (IS_ERR(ethqos->serdes_phy)) 828 return dev_err_probe(dev, PTR_ERR(ethqos->serdes_phy), 829 "Failed to get serdes phy\n"); 830 831 ethqos->speed = SPEED_1000; 832 ethqos->serdes_speed = SPEED_1000; 833 ethqos_update_link_clk(ethqos, SPEED_1000); 834 ethqos_set_func_clk_en(ethqos); 835 836 plat_dat->bsp_priv = ethqos; 837 plat_dat->fix_mac_speed = ethqos_fix_mac_speed; 838 plat_dat->dump_debug_regs = rgmii_dump; 839 plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config; 840 plat_dat->has_gmac4 = 1; 841 if (ethqos->has_emac_ge_3) 842 plat_dat->dwmac4_addrs = &data->dwmac4_addrs; 843 plat_dat->pmt = 1; 844 if (of_property_read_bool(np, "snps,tso")) 845 plat_dat->flags |= STMMAC_FLAG_TSO_EN; 846 if (of_device_is_compatible(np, "qcom,qcs404-ethqos")) 847 plat_dat->flags |= STMMAC_FLAG_RX_CLK_RUNS_IN_LPI; 848 if (data->has_integrated_pcs) 849 plat_dat->flags |= STMMAC_FLAG_HAS_INTEGRATED_PCS; 850 if (data->dma_addr_width) 851 plat_dat->host_dma_width = data->dma_addr_width; 852 853 if (ethqos->serdes_phy) { 854 plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup; 855 plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown; 856 } 857 858 /* Enable TSO on queue0 and enable TBS on rest of the queues */ 859 for (i = 1; i < plat_dat->tx_queues_to_use; i++) 860 plat_dat->tx_queues_cfg[i].tbs_en = 1; 861 862 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); 863 } 864 865 static const struct of_device_id qcom_ethqos_match[] = { 866 { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, 867 { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data}, 868 { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data}, 869 { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data}, 870 { } 871 }; 872 MODULE_DEVICE_TABLE(of, qcom_ethqos_match); 873 874 static struct platform_driver qcom_ethqos_driver = { 875 .probe = qcom_ethqos_probe, 876 .driver = { 877 .name = "qcom-ethqos", 878 .pm = &stmmac_pltfr_pm_ops, 879 .of_match_table = qcom_ethqos_match, 880 }, 881 }; 882 module_platform_driver(qcom_ethqos_driver); 883 884 MODULE_DESCRIPTION("Qualcomm ETHQOS driver"); 885 MODULE_LICENSE("GPL v2"); 886