1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2018-19, Linaro Limited 3 4 #include <linux/module.h> 5 #include <linux/of.h> 6 #include <linux/of_net.h> 7 #include <linux/platform_device.h> 8 #include <linux/phy.h> 9 #include <linux/phy/phy.h> 10 11 #include "stmmac.h" 12 #include "stmmac_platform.h" 13 14 #define RGMII_IO_MACRO_CONFIG 0x0 15 #define SDCC_HC_REG_DLL_CONFIG 0x4 16 #define SDCC_TEST_CTL 0x8 17 #define SDCC_HC_REG_DDR_CONFIG 0xC 18 #define SDCC_HC_REG_DLL_CONFIG2 0x10 19 #define SDC4_STATUS 0x14 20 #define SDCC_USR_CTL 0x18 21 #define RGMII_IO_MACRO_CONFIG2 0x1C 22 #define RGMII_IO_MACRO_DEBUG1 0x20 23 #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28 24 25 /* RGMII_IO_MACRO_CONFIG fields */ 26 #define RGMII_CONFIG_FUNC_CLK_EN BIT(30) 27 #define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) 28 #define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20) 29 #define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17) 30 #define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8) 31 #define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6) 32 #define RGMII_CONFIG_INTF_SEL GENMASK(5, 4) 33 #define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) 34 #define RGMII_CONFIG_LOOPBACK_EN BIT(2) 35 #define RGMII_CONFIG_PROG_SWAP BIT(1) 36 #define RGMII_CONFIG_DDR_MODE BIT(0) 37 38 /* SDCC_HC_REG_DLL_CONFIG fields */ 39 #define SDCC_DLL_CONFIG_DLL_RST BIT(30) 40 #define SDCC_DLL_CONFIG_PDN BIT(29) 41 #define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24) 42 #define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20) 43 #define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) 44 #define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) 45 #define SDCC_DLL_CONFIG_CDR_EN BIT(17) 46 #define SDCC_DLL_CONFIG_DLL_EN BIT(16) 47 #define SDCC_DLL_MCLK_GATING_EN BIT(5) 48 #define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2) 49 50 /* SDCC_HC_REG_DDR_CONFIG fields */ 51 #define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) 52 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21) 53 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27) 54 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) 55 #define SDCC_DDR_CONFIG_TCXO_CYCLES_CNT GENMASK(11, 9) 56 #define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0) 57 58 /* SDCC_HC_REG_DLL_CONFIG2 fields */ 59 #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) 60 #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10) 61 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2) 62 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) 63 #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) 64 65 /* SDC4_STATUS bits */ 66 #define SDC4_STATUS_DLL_LOCK BIT(7) 67 68 /* RGMII_IO_MACRO_CONFIG2 fields */ 69 #define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17) 70 #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) 71 #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) 72 #define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) 73 #define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) 74 #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) 75 #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) 76 77 /* MAC_CTRL_REG bits */ 78 #define ETHQOS_MAC_CTRL_SPEED_MODE BIT(14) 79 #define ETHQOS_MAC_CTRL_PORT_SEL BIT(15) 80 81 struct ethqos_emac_por { 82 unsigned int offset; 83 unsigned int value; 84 }; 85 86 struct ethqos_emac_driver_data { 87 const struct ethqos_emac_por *por; 88 unsigned int num_por; 89 bool rgmii_config_loopback_en; 90 bool has_emac_ge_3; 91 const char *link_clk_name; 92 bool has_integrated_pcs; 93 struct dwmac4_addrs dwmac4_addrs; 94 }; 95 96 struct qcom_ethqos { 97 struct platform_device *pdev; 98 void __iomem *rgmii_base; 99 void __iomem *mac_base; 100 int (*configure_func)(struct qcom_ethqos *ethqos); 101 102 unsigned int link_clk_rate; 103 struct clk *link_clk; 104 struct phy *serdes_phy; 105 unsigned int speed; 106 phy_interface_t phy_mode; 107 108 const struct ethqos_emac_por *por; 109 unsigned int num_por; 110 bool rgmii_config_loopback_en; 111 bool has_emac_ge_3; 112 }; 113 114 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) 115 { 116 return readl(ethqos->rgmii_base + offset); 117 } 118 119 static void rgmii_writel(struct qcom_ethqos *ethqos, 120 int value, unsigned int offset) 121 { 122 writel(value, ethqos->rgmii_base + offset); 123 } 124 125 static void rgmii_updatel(struct qcom_ethqos *ethqos, 126 int mask, int val, unsigned int offset) 127 { 128 unsigned int temp; 129 130 temp = rgmii_readl(ethqos, offset); 131 temp = (temp & ~(mask)) | val; 132 rgmii_writel(ethqos, temp, offset); 133 } 134 135 static void rgmii_dump(void *priv) 136 { 137 struct qcom_ethqos *ethqos = priv; 138 struct device *dev = ðqos->pdev->dev; 139 140 dev_dbg(dev, "Rgmii register dump\n"); 141 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %x\n", 142 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG)); 143 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %x\n", 144 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG)); 145 dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %x\n", 146 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG)); 147 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n", 148 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2)); 149 dev_dbg(dev, "SDC4_STATUS: %x\n", 150 rgmii_readl(ethqos, SDC4_STATUS)); 151 dev_dbg(dev, "SDCC_USR_CTL: %x\n", 152 rgmii_readl(ethqos, SDCC_USR_CTL)); 153 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %x\n", 154 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2)); 155 dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %x\n", 156 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1)); 157 dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n", 158 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG)); 159 } 160 161 /* Clock rates */ 162 #define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL) 163 #define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL) 164 #define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL) 165 166 static void 167 ethqos_update_link_clk(struct qcom_ethqos *ethqos, unsigned int speed) 168 { 169 switch (speed) { 170 case SPEED_1000: 171 ethqos->link_clk_rate = RGMII_1000_NOM_CLK_FREQ; 172 break; 173 174 case SPEED_100: 175 ethqos->link_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ; 176 break; 177 178 case SPEED_10: 179 ethqos->link_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ; 180 break; 181 } 182 183 clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate); 184 } 185 186 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) 187 { 188 rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN, 189 RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); 190 } 191 192 static const struct ethqos_emac_por emac_v2_3_0_por[] = { 193 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, 194 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 195 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 196 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 197 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 198 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 199 }; 200 201 static const struct ethqos_emac_driver_data emac_v2_3_0_data = { 202 .por = emac_v2_3_0_por, 203 .num_por = ARRAY_SIZE(emac_v2_3_0_por), 204 .rgmii_config_loopback_en = true, 205 .has_emac_ge_3 = false, 206 }; 207 208 static const struct ethqos_emac_por emac_v2_1_0_por[] = { 209 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 }, 210 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 211 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 212 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 213 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 214 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 215 }; 216 217 static const struct ethqos_emac_driver_data emac_v2_1_0_data = { 218 .por = emac_v2_1_0_por, 219 .num_por = ARRAY_SIZE(emac_v2_1_0_por), 220 .rgmii_config_loopback_en = false, 221 .has_emac_ge_3 = false, 222 }; 223 224 static const struct ethqos_emac_por emac_v3_0_0_por[] = { 225 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 }, 226 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c }, 227 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 }, 228 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 229 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 230 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 231 }; 232 233 static const struct ethqos_emac_driver_data emac_v3_0_0_data = { 234 .por = emac_v3_0_0_por, 235 .num_por = ARRAY_SIZE(emac_v3_0_0_por), 236 .rgmii_config_loopback_en = false, 237 .has_emac_ge_3 = true, 238 .dwmac4_addrs = { 239 .dma_chan = 0x00008100, 240 .dma_chan_offset = 0x1000, 241 .mtl_chan = 0x00008000, 242 .mtl_chan_offset = 0x1000, 243 .mtl_ets_ctrl = 0x00008010, 244 .mtl_ets_ctrl_offset = 0x1000, 245 .mtl_txq_weight = 0x00008018, 246 .mtl_txq_weight_offset = 0x1000, 247 .mtl_send_slp_cred = 0x0000801c, 248 .mtl_send_slp_cred_offset = 0x1000, 249 .mtl_high_cred = 0x00008020, 250 .mtl_high_cred_offset = 0x1000, 251 .mtl_low_cred = 0x00008024, 252 .mtl_low_cred_offset = 0x1000, 253 }, 254 }; 255 256 static const struct ethqos_emac_por emac_v4_0_0_por[] = { 257 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 }, 258 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c }, 259 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 }, 260 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 261 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 262 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 263 }; 264 265 static const struct ethqos_emac_driver_data emac_v4_0_0_data = { 266 .por = emac_v4_0_0_por, 267 .num_por = ARRAY_SIZE(emac_v3_0_0_por), 268 .rgmii_config_loopback_en = false, 269 .has_emac_ge_3 = true, 270 .link_clk_name = "phyaux", 271 .has_integrated_pcs = true, 272 .dwmac4_addrs = { 273 .dma_chan = 0x00008100, 274 .dma_chan_offset = 0x1000, 275 .mtl_chan = 0x00008000, 276 .mtl_chan_offset = 0x1000, 277 .mtl_ets_ctrl = 0x00008010, 278 .mtl_ets_ctrl_offset = 0x1000, 279 .mtl_txq_weight = 0x00008018, 280 .mtl_txq_weight_offset = 0x1000, 281 .mtl_send_slp_cred = 0x0000801c, 282 .mtl_send_slp_cred_offset = 0x1000, 283 .mtl_high_cred = 0x00008020, 284 .mtl_high_cred_offset = 0x1000, 285 .mtl_low_cred = 0x00008024, 286 .mtl_low_cred_offset = 0x1000, 287 }, 288 }; 289 290 static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 291 { 292 struct device *dev = ðqos->pdev->dev; 293 unsigned int val; 294 int retry = 1000; 295 296 /* Set CDR_EN */ 297 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN, 298 SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG); 299 300 /* Set CDR_EXT_EN */ 301 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN, 302 SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG); 303 304 /* Clear CK_OUT_EN */ 305 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 306 0, SDCC_HC_REG_DLL_CONFIG); 307 308 /* Set DLL_EN */ 309 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 310 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 311 312 if (!ethqos->has_emac_ge_3) { 313 rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN, 314 0, SDCC_HC_REG_DLL_CONFIG); 315 316 rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE, 317 0, SDCC_HC_REG_DLL_CONFIG); 318 } 319 320 /* Wait for CK_OUT_EN clear */ 321 do { 322 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 323 val &= SDCC_DLL_CONFIG_CK_OUT_EN; 324 if (!val) 325 break; 326 mdelay(1); 327 retry--; 328 } while (retry > 0); 329 if (!retry) 330 dev_err(dev, "Clear CK_OUT_EN timedout\n"); 331 332 /* Set CK_OUT_EN */ 333 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 334 SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG); 335 336 /* Wait for CK_OUT_EN set */ 337 retry = 1000; 338 do { 339 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 340 val &= SDCC_DLL_CONFIG_CK_OUT_EN; 341 if (val) 342 break; 343 mdelay(1); 344 retry--; 345 } while (retry > 0); 346 if (!retry) 347 dev_err(dev, "Set CK_OUT_EN timedout\n"); 348 349 /* Set DDR_CAL_EN */ 350 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN, 351 SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2); 352 353 if (!ethqos->has_emac_ge_3) { 354 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS, 355 0, SDCC_HC_REG_DLL_CONFIG2); 356 357 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, 358 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2); 359 360 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, 361 BIT(2), SDCC_HC_REG_DLL_CONFIG2); 362 363 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 364 SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 365 SDCC_HC_REG_DLL_CONFIG2); 366 } 367 368 return 0; 369 } 370 371 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 372 { 373 struct device *dev = ðqos->pdev->dev; 374 int phase_shift; 375 int loopback; 376 377 /* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */ 378 if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID || 379 ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID) 380 phase_shift = 0; 381 else 382 phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN; 383 384 /* Disable loopback mode */ 385 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN, 386 0, RGMII_IO_MACRO_CONFIG2); 387 388 /* Determine if this platform wants loopback enabled after programming */ 389 if (ethqos->rgmii_config_loopback_en) 390 loopback = RGMII_CONFIG_LOOPBACK_EN; 391 else 392 loopback = 0; 393 394 /* Select RGMII, write 0 to interface select */ 395 rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL, 396 0, RGMII_IO_MACRO_CONFIG); 397 398 switch (ethqos->speed) { 399 case SPEED_1000: 400 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 401 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 402 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 403 0, RGMII_IO_MACRO_CONFIG); 404 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 405 RGMII_CONFIG_POS_NEG_DATA_SEL, 406 RGMII_IO_MACRO_CONFIG); 407 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 408 RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG); 409 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 410 0, RGMII_IO_MACRO_CONFIG2); 411 412 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 413 phase_shift, RGMII_IO_MACRO_CONFIG2); 414 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 415 0, RGMII_IO_MACRO_CONFIG2); 416 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 417 RGMII_CONFIG2_RX_PROG_SWAP, 418 RGMII_IO_MACRO_CONFIG2); 419 420 /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns, 421 * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns 422 */ 423 if (ethqos->has_emac_ge_3) { 424 /* 0.9 ns */ 425 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 426 115, SDCC_HC_REG_DDR_CONFIG); 427 } else { 428 /* 1.8 ns */ 429 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 430 57, SDCC_HC_REG_DDR_CONFIG); 431 } 432 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN, 433 SDCC_DDR_CONFIG_PRG_DLY_EN, 434 SDCC_HC_REG_DDR_CONFIG); 435 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 436 loopback, RGMII_IO_MACRO_CONFIG); 437 break; 438 439 case SPEED_100: 440 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 441 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 442 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 443 RGMII_CONFIG_BYPASS_TX_ID_EN, 444 RGMII_IO_MACRO_CONFIG); 445 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 446 0, RGMII_IO_MACRO_CONFIG); 447 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 448 0, RGMII_IO_MACRO_CONFIG); 449 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 450 0, RGMII_IO_MACRO_CONFIG2); 451 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 452 phase_shift, RGMII_IO_MACRO_CONFIG2); 453 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2, 454 BIT(6), RGMII_IO_MACRO_CONFIG); 455 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 456 0, RGMII_IO_MACRO_CONFIG2); 457 458 if (ethqos->has_emac_ge_3) 459 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 460 RGMII_CONFIG2_RX_PROG_SWAP, 461 RGMII_IO_MACRO_CONFIG2); 462 else 463 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 464 0, RGMII_IO_MACRO_CONFIG2); 465 466 /* Write 0x5 to PRG_RCLK_DLY_CODE */ 467 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 468 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 469 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 470 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 471 SDCC_HC_REG_DDR_CONFIG); 472 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 473 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 474 SDCC_HC_REG_DDR_CONFIG); 475 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 476 loopback, RGMII_IO_MACRO_CONFIG); 477 break; 478 479 case SPEED_10: 480 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 481 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 482 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 483 RGMII_CONFIG_BYPASS_TX_ID_EN, 484 RGMII_IO_MACRO_CONFIG); 485 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 486 0, RGMII_IO_MACRO_CONFIG); 487 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 488 0, RGMII_IO_MACRO_CONFIG); 489 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 490 0, RGMII_IO_MACRO_CONFIG2); 491 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 492 phase_shift, RGMII_IO_MACRO_CONFIG2); 493 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9, 494 BIT(12) | GENMASK(9, 8), 495 RGMII_IO_MACRO_CONFIG); 496 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 497 0, RGMII_IO_MACRO_CONFIG2); 498 if (ethqos->has_emac_ge_3) 499 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 500 RGMII_CONFIG2_RX_PROG_SWAP, 501 RGMII_IO_MACRO_CONFIG2); 502 else 503 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 504 0, RGMII_IO_MACRO_CONFIG2); 505 /* Write 0x5 to PRG_RCLK_DLY_CODE */ 506 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 507 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 508 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 509 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 510 SDCC_HC_REG_DDR_CONFIG); 511 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 512 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 513 SDCC_HC_REG_DDR_CONFIG); 514 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 515 loopback, RGMII_IO_MACRO_CONFIG); 516 break; 517 default: 518 dev_err(dev, "Invalid speed %d\n", ethqos->speed); 519 return -EINVAL; 520 } 521 522 return 0; 523 } 524 525 static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos) 526 { 527 struct device *dev = ðqos->pdev->dev; 528 volatile unsigned int dll_lock; 529 unsigned int i, retry = 1000; 530 531 /* Reset to POR values and enable clk */ 532 for (i = 0; i < ethqos->num_por; i++) 533 rgmii_writel(ethqos, ethqos->por[i].value, 534 ethqos->por[i].offset); 535 ethqos_set_func_clk_en(ethqos); 536 537 /* Initialize the DLL first */ 538 539 /* Set DLL_RST */ 540 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 541 SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG); 542 543 /* Set PDN */ 544 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 545 SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG); 546 547 if (ethqos->has_emac_ge_3) { 548 if (ethqos->speed == SPEED_1000) { 549 rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL); 550 rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL); 551 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 552 } else { 553 rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL); 554 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 555 } 556 } 557 558 /* Clear DLL_RST */ 559 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0, 560 SDCC_HC_REG_DLL_CONFIG); 561 562 /* Clear PDN */ 563 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0, 564 SDCC_HC_REG_DLL_CONFIG); 565 566 if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) { 567 /* Set DLL_EN */ 568 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 569 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 570 571 /* Set CK_OUT_EN */ 572 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 573 SDCC_DLL_CONFIG_CK_OUT_EN, 574 SDCC_HC_REG_DLL_CONFIG); 575 576 /* Set USR_CTL bit 26 with mask of 3 bits */ 577 if (!ethqos->has_emac_ge_3) 578 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), 579 SDCC_USR_CTL); 580 581 /* wait for DLL LOCK */ 582 do { 583 mdelay(1); 584 dll_lock = rgmii_readl(ethqos, SDC4_STATUS); 585 if (dll_lock & SDC4_STATUS_DLL_LOCK) 586 break; 587 retry--; 588 } while (retry > 0); 589 if (!retry) 590 dev_err(dev, "Timeout while waiting for DLL lock\n"); 591 } 592 593 if (ethqos->speed == SPEED_1000) 594 ethqos_dll_configure(ethqos); 595 596 ethqos_rgmii_macro_init(ethqos); 597 598 return 0; 599 } 600 601 static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos) 602 { 603 int val; 604 605 val = readl(ethqos->mac_base + MAC_CTRL_REG); 606 607 switch (ethqos->speed) { 608 case SPEED_1000: 609 val &= ~ETHQOS_MAC_CTRL_PORT_SEL; 610 rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG, 611 RGMII_CONFIG2_RGMII_CLK_SEL_CFG, 612 RGMII_IO_MACRO_CONFIG2); 613 break; 614 case SPEED_100: 615 val |= ETHQOS_MAC_CTRL_PORT_SEL | ETHQOS_MAC_CTRL_SPEED_MODE; 616 break; 617 case SPEED_10: 618 val |= ETHQOS_MAC_CTRL_PORT_SEL; 619 val &= ~ETHQOS_MAC_CTRL_SPEED_MODE; 620 break; 621 } 622 623 writel(val, ethqos->mac_base + MAC_CTRL_REG); 624 625 return val; 626 } 627 628 static int ethqos_configure(struct qcom_ethqos *ethqos) 629 { 630 return ethqos->configure_func(ethqos); 631 } 632 633 static void ethqos_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode) 634 { 635 struct qcom_ethqos *ethqos = priv; 636 637 ethqos->speed = speed; 638 ethqos_update_link_clk(ethqos, speed); 639 ethqos_configure(ethqos); 640 } 641 642 static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv) 643 { 644 struct qcom_ethqos *ethqos = priv; 645 int ret; 646 647 ret = phy_init(ethqos->serdes_phy); 648 if (ret) 649 return ret; 650 651 ret = phy_power_on(ethqos->serdes_phy); 652 if (ret) 653 return ret; 654 655 return phy_set_speed(ethqos->serdes_phy, ethqos->speed); 656 } 657 658 static void qcom_ethqos_serdes_powerdown(struct net_device *ndev, void *priv) 659 { 660 struct qcom_ethqos *ethqos = priv; 661 662 phy_power_off(ethqos->serdes_phy); 663 phy_exit(ethqos->serdes_phy); 664 } 665 666 static int ethqos_clks_config(void *priv, bool enabled) 667 { 668 struct qcom_ethqos *ethqos = priv; 669 int ret = 0; 670 671 if (enabled) { 672 ret = clk_prepare_enable(ethqos->link_clk); 673 if (ret) { 674 dev_err(ðqos->pdev->dev, "link_clk enable failed\n"); 675 return ret; 676 } 677 678 /* Enable functional clock to prevent DMA reset to timeout due 679 * to lacking PHY clock after the hardware block has been power 680 * cycled. The actual configuration will be adjusted once 681 * ethqos_fix_mac_speed() is invoked. 682 */ 683 ethqos_set_func_clk_en(ethqos); 684 } else { 685 clk_disable_unprepare(ethqos->link_clk); 686 } 687 688 return ret; 689 } 690 691 static void ethqos_clks_disable(void *data) 692 { 693 ethqos_clks_config(data, false); 694 } 695 696 static void ethqos_ptp_clk_freq_config(struct stmmac_priv *priv) 697 { 698 struct plat_stmmacenet_data *plat_dat = priv->plat; 699 int err; 700 701 if (!plat_dat->clk_ptp_ref) 702 return; 703 704 /* Max the PTP ref clock out to get the best resolution possible */ 705 err = clk_set_rate(plat_dat->clk_ptp_ref, ULONG_MAX); 706 if (err) 707 netdev_err(priv->dev, "Failed to max out clk_ptp_ref: %d\n", err); 708 plat_dat->clk_ptp_rate = clk_get_rate(plat_dat->clk_ptp_ref); 709 710 netdev_dbg(priv->dev, "PTP rate %d\n", plat_dat->clk_ptp_rate); 711 } 712 713 static int qcom_ethqos_probe(struct platform_device *pdev) 714 { 715 struct device_node *np = pdev->dev.of_node; 716 const struct ethqos_emac_driver_data *data; 717 struct plat_stmmacenet_data *plat_dat; 718 struct stmmac_resources stmmac_res; 719 struct device *dev = &pdev->dev; 720 struct qcom_ethqos *ethqos; 721 int ret; 722 723 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 724 if (ret) 725 return dev_err_probe(dev, ret, 726 "Failed to get platform resources\n"); 727 728 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 729 if (IS_ERR(plat_dat)) { 730 return dev_err_probe(dev, PTR_ERR(plat_dat), 731 "dt configuration failed\n"); 732 } 733 734 plat_dat->clks_config = ethqos_clks_config; 735 736 ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL); 737 if (!ethqos) 738 return -ENOMEM; 739 740 ret = of_get_phy_mode(np, ðqos->phy_mode); 741 if (ret) 742 return dev_err_probe(dev, ret, "Failed to get phy mode\n"); 743 switch (ethqos->phy_mode) { 744 case PHY_INTERFACE_MODE_RGMII: 745 case PHY_INTERFACE_MODE_RGMII_ID: 746 case PHY_INTERFACE_MODE_RGMII_RXID: 747 case PHY_INTERFACE_MODE_RGMII_TXID: 748 ethqos->configure_func = ethqos_configure_rgmii; 749 break; 750 case PHY_INTERFACE_MODE_SGMII: 751 ethqos->configure_func = ethqos_configure_sgmii; 752 break; 753 default: 754 dev_err(dev, "Unsupported phy mode %s\n", 755 phy_modes(ethqos->phy_mode)); 756 return -EINVAL; 757 } 758 759 ethqos->pdev = pdev; 760 ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); 761 if (IS_ERR(ethqos->rgmii_base)) 762 return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base), 763 "Failed to map rgmii resource\n"); 764 765 ethqos->mac_base = stmmac_res.addr; 766 767 data = of_device_get_match_data(dev); 768 ethqos->por = data->por; 769 ethqos->num_por = data->num_por; 770 ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en; 771 ethqos->has_emac_ge_3 = data->has_emac_ge_3; 772 773 ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii"); 774 if (IS_ERR(ethqos->link_clk)) 775 return dev_err_probe(dev, PTR_ERR(ethqos->link_clk), 776 "Failed to get link_clk\n"); 777 778 ret = ethqos_clks_config(ethqos, true); 779 if (ret) 780 return ret; 781 782 ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); 783 if (ret) 784 return ret; 785 786 ethqos->serdes_phy = devm_phy_optional_get(dev, "serdes"); 787 if (IS_ERR(ethqos->serdes_phy)) 788 return dev_err_probe(dev, PTR_ERR(ethqos->serdes_phy), 789 "Failed to get serdes phy\n"); 790 791 ethqos->speed = SPEED_1000; 792 ethqos_update_link_clk(ethqos, SPEED_1000); 793 ethqos_set_func_clk_en(ethqos); 794 795 plat_dat->bsp_priv = ethqos; 796 plat_dat->fix_mac_speed = ethqos_fix_mac_speed; 797 plat_dat->dump_debug_regs = rgmii_dump; 798 plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config; 799 plat_dat->has_gmac4 = 1; 800 if (ethqos->has_emac_ge_3) 801 plat_dat->dwmac4_addrs = &data->dwmac4_addrs; 802 plat_dat->pmt = 1; 803 if (of_property_read_bool(np, "snps,tso")) 804 plat_dat->flags |= STMMAC_FLAG_TSO_EN; 805 if (of_device_is_compatible(np, "qcom,qcs404-ethqos")) 806 plat_dat->flags |= STMMAC_FLAG_RX_CLK_RUNS_IN_LPI; 807 if (data->has_integrated_pcs) 808 plat_dat->flags |= STMMAC_FLAG_HAS_INTEGRATED_PCS; 809 810 if (ethqos->serdes_phy) { 811 plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup; 812 plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown; 813 } 814 815 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); 816 } 817 818 static const struct of_device_id qcom_ethqos_match[] = { 819 { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, 820 { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data}, 821 { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data}, 822 { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data}, 823 { } 824 }; 825 MODULE_DEVICE_TABLE(of, qcom_ethqos_match); 826 827 static struct platform_driver qcom_ethqos_driver = { 828 .probe = qcom_ethqos_probe, 829 .driver = { 830 .name = "qcom-ethqos", 831 .pm = &stmmac_pltfr_pm_ops, 832 .of_match_table = qcom_ethqos_match, 833 }, 834 }; 835 module_platform_driver(qcom_ethqos_driver); 836 837 MODULE_DESCRIPTION("Qualcomm ETHQOS driver"); 838 MODULE_LICENSE("GPL v2"); 839