1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2020, Loongson Corporation 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/pci.h> 7 #include <linux/dmi.h> 8 #include <linux/device.h> 9 #include <linux/of_irq.h> 10 #include "stmmac.h" 11 #include "dwmac_dma.h" 12 #include "dwmac1000.h" 13 14 #define DRIVER_NAME "dwmac-loongson-pci" 15 16 /* Normal Loongson Tx Summary */ 17 #define DMA_INTR_ENA_NIE_TX_LOONGSON 0x00040000 18 /* Normal Loongson Rx Summary */ 19 #define DMA_INTR_ENA_NIE_RX_LOONGSON 0x00020000 20 21 #define DMA_INTR_NORMAL_LOONGSON (DMA_INTR_ENA_NIE_TX_LOONGSON | \ 22 DMA_INTR_ENA_NIE_RX_LOONGSON | \ 23 DMA_INTR_ENA_RIE | DMA_INTR_ENA_TIE) 24 25 /* Abnormal Loongson Tx Summary */ 26 #define DMA_INTR_ENA_AIE_TX_LOONGSON 0x00010000 27 /* Abnormal Loongson Rx Summary */ 28 #define DMA_INTR_ENA_AIE_RX_LOONGSON 0x00008000 29 30 #define DMA_INTR_ABNORMAL_LOONGSON (DMA_INTR_ENA_AIE_TX_LOONGSON | \ 31 DMA_INTR_ENA_AIE_RX_LOONGSON | \ 32 DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE) 33 34 #define DMA_INTR_DEFAULT_MASK_LOONGSON (DMA_INTR_NORMAL_LOONGSON | \ 35 DMA_INTR_ABNORMAL_LOONGSON) 36 37 /* Normal Loongson Tx Interrupt Summary */ 38 #define DMA_STATUS_NIS_TX_LOONGSON 0x00040000 39 /* Normal Loongson Rx Interrupt Summary */ 40 #define DMA_STATUS_NIS_RX_LOONGSON 0x00020000 41 42 /* Abnormal Loongson Tx Interrupt Summary */ 43 #define DMA_STATUS_AIS_TX_LOONGSON 0x00010000 44 /* Abnormal Loongson Rx Interrupt Summary */ 45 #define DMA_STATUS_AIS_RX_LOONGSON 0x00008000 46 47 /* Fatal Loongson Tx Bus Error Interrupt */ 48 #define DMA_STATUS_FBI_TX_LOONGSON 0x00002000 49 /* Fatal Loongson Rx Bus Error Interrupt */ 50 #define DMA_STATUS_FBI_RX_LOONGSON 0x00001000 51 52 #define DMA_STATUS_MSK_COMMON_LOONGSON (DMA_STATUS_NIS_TX_LOONGSON | \ 53 DMA_STATUS_NIS_RX_LOONGSON | \ 54 DMA_STATUS_AIS_TX_LOONGSON | \ 55 DMA_STATUS_AIS_RX_LOONGSON | \ 56 DMA_STATUS_FBI_TX_LOONGSON | \ 57 DMA_STATUS_FBI_RX_LOONGSON) 58 59 #define DMA_STATUS_MSK_RX_LOONGSON (DMA_STATUS_ERI | DMA_STATUS_RWT | \ 60 DMA_STATUS_RPS | DMA_STATUS_RU | \ 61 DMA_STATUS_RI | DMA_STATUS_OVF | \ 62 DMA_STATUS_MSK_COMMON_LOONGSON) 63 64 #define DMA_STATUS_MSK_TX_LOONGSON (DMA_STATUS_ETI | DMA_STATUS_UNF | \ 65 DMA_STATUS_TJT | DMA_STATUS_TU | \ 66 DMA_STATUS_TPS | DMA_STATUS_TI | \ 67 DMA_STATUS_MSK_COMMON_LOONGSON) 68 69 #define PCI_DEVICE_ID_LOONGSON_GMAC1 0x7a03 70 #define PCI_DEVICE_ID_LOONGSON_GMAC2 0x7a23 71 #define PCI_DEVICE_ID_LOONGSON_GNET 0x7a13 72 #define DWMAC_CORE_MULTICHAN_V1 0x10 /* Loongson custom ID 0x10 */ 73 #define DWMAC_CORE_MULTICHAN_V2 0x12 /* Loongson custom ID 0x12 */ 74 75 struct loongson_data { 76 u32 multichan; 77 u32 loongson_id; 78 struct device *dev; 79 }; 80 81 struct stmmac_pci_info { 82 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); 83 }; 84 85 static void loongson_default_data(struct pci_dev *pdev, 86 struct plat_stmmacenet_data *plat) 87 { 88 struct loongson_data *ld = plat->bsp_priv; 89 90 /* Get bus_id, this can be overwritten later */ 91 plat->bus_id = pci_dev_id(pdev); 92 93 /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 94 plat->clk_csr = STMMAC_CSR_20_35M; 95 plat->has_gmac = 1; 96 plat->force_sf_dma_mode = 1; 97 98 /* Set default value for multicast hash bins */ 99 plat->multicast_filter_bins = 256; 100 101 plat->mac_interface = PHY_INTERFACE_MODE_NA; 102 103 /* Set default value for unicast filter entries */ 104 plat->unicast_filter_entries = 1; 105 106 /* Set the maxmtu to a default of JUMBO_LEN */ 107 plat->maxmtu = JUMBO_LEN; 108 109 /* Disable Priority config by default */ 110 plat->tx_queues_cfg[0].use_prio = false; 111 plat->rx_queues_cfg[0].use_prio = false; 112 113 /* Disable RX queues routing by default */ 114 plat->rx_queues_cfg[0].pkt_route = 0x0; 115 116 plat->clk_ref_rate = 125000000; 117 plat->clk_ptp_rate = 125000000; 118 119 /* Default to phy auto-detection */ 120 plat->phy_addr = -1; 121 122 plat->dma_cfg->pbl = 32; 123 plat->dma_cfg->pblx8 = true; 124 125 switch (ld->loongson_id) { 126 case DWMAC_CORE_MULTICHAN_V1: 127 ld->multichan = 1; 128 plat->rx_queues_to_use = 8; 129 plat->tx_queues_to_use = 8; 130 131 /* Only channel 0 supports checksum, 132 * so turn off checksum to enable multiple channels. 133 */ 134 for (int i = 1; i < 8; i++) 135 plat->tx_queues_cfg[i].coe_unsupported = 1; 136 137 break; 138 case DWMAC_CORE_MULTICHAN_V2: 139 ld->multichan = 1; 140 plat->rx_queues_to_use = 4; 141 plat->tx_queues_to_use = 4; 142 break; 143 default: 144 ld->multichan = 0; 145 plat->tx_queues_to_use = 1; 146 plat->rx_queues_to_use = 1; 147 break; 148 } 149 } 150 151 static int loongson_gmac_data(struct pci_dev *pdev, 152 struct plat_stmmacenet_data *plat) 153 { 154 loongson_default_data(pdev, plat); 155 156 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 157 158 return 0; 159 } 160 161 static struct stmmac_pci_info loongson_gmac_pci_info = { 162 .setup = loongson_gmac_data, 163 }; 164 165 static void loongson_gnet_fix_speed(void *priv, int speed, unsigned int mode) 166 { 167 struct loongson_data *ld = (struct loongson_data *)priv; 168 struct net_device *ndev = dev_get_drvdata(ld->dev); 169 struct stmmac_priv *ptr = netdev_priv(ndev); 170 171 /* The integrated PHY has a weird problem with switching from the low 172 * speeds to 1000Mbps mode. The speedup procedure requires the PHY-link 173 * re-negotiation. 174 */ 175 if (speed == SPEED_1000) { 176 if (readl(ptr->ioaddr + MAC_CTRL_REG) & 177 GMAC_CONTROL_PS) 178 /* Word around hardware bug, restart autoneg */ 179 phy_restart_aneg(ndev->phydev); 180 } 181 } 182 183 static int loongson_gnet_data(struct pci_dev *pdev, 184 struct plat_stmmacenet_data *plat) 185 { 186 loongson_default_data(pdev, plat); 187 188 plat->phy_interface = PHY_INTERFACE_MODE_GMII; 189 plat->mdio_bus_data->phy_mask = ~(u32)BIT(2); 190 plat->fix_mac_speed = loongson_gnet_fix_speed; 191 192 return 0; 193 } 194 195 static struct stmmac_pci_info loongson_gnet_pci_info = { 196 .setup = loongson_gnet_data, 197 }; 198 199 static void loongson_dwmac_dma_init_channel(struct stmmac_priv *priv, 200 void __iomem *ioaddr, 201 struct stmmac_dma_cfg *dma_cfg, 202 u32 chan) 203 { 204 int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 205 int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 206 u32 value; 207 208 value = readl(ioaddr + DMA_CHAN_BUS_MODE(chan)); 209 210 if (dma_cfg->pblx8) 211 value |= DMA_BUS_MODE_MAXPBL; 212 213 value |= DMA_BUS_MODE_USP; 214 value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK); 215 value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT); 216 value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 217 218 /* Set the Fixed burst mode */ 219 if (dma_cfg->fixed_burst) 220 value |= DMA_BUS_MODE_FB; 221 222 /* Mixed Burst has no effect when fb is set */ 223 if (dma_cfg->mixed_burst) 224 value |= DMA_BUS_MODE_MB; 225 226 if (dma_cfg->atds) 227 value |= DMA_BUS_MODE_ATDS; 228 229 if (dma_cfg->aal) 230 value |= DMA_BUS_MODE_AAL; 231 232 writel(value, ioaddr + DMA_CHAN_BUS_MODE(chan)); 233 234 /* Mask interrupts by writing to CSR7 */ 235 writel(DMA_INTR_DEFAULT_MASK_LOONGSON, ioaddr + 236 DMA_CHAN_INTR_ENA(chan)); 237 } 238 239 static int loongson_dwmac_dma_interrupt(struct stmmac_priv *priv, 240 void __iomem *ioaddr, 241 struct stmmac_extra_stats *x, 242 u32 chan, u32 dir) 243 { 244 struct stmmac_pcpu_stats *stats = this_cpu_ptr(priv->xstats.pcpu_stats); 245 u32 abnor_intr_status; 246 u32 nor_intr_status; 247 u32 fb_intr_status; 248 u32 intr_status; 249 int ret = 0; 250 251 /* read the status register (CSR5) */ 252 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan)); 253 254 if (dir == DMA_DIR_RX) 255 intr_status &= DMA_STATUS_MSK_RX_LOONGSON; 256 else if (dir == DMA_DIR_TX) 257 intr_status &= DMA_STATUS_MSK_TX_LOONGSON; 258 259 nor_intr_status = intr_status & (DMA_STATUS_NIS_TX_LOONGSON | 260 DMA_STATUS_NIS_RX_LOONGSON); 261 abnor_intr_status = intr_status & (DMA_STATUS_AIS_TX_LOONGSON | 262 DMA_STATUS_AIS_RX_LOONGSON); 263 fb_intr_status = intr_status & (DMA_STATUS_FBI_TX_LOONGSON | 264 DMA_STATUS_FBI_RX_LOONGSON); 265 266 /* ABNORMAL interrupts */ 267 if (unlikely(abnor_intr_status)) { 268 if (unlikely(intr_status & DMA_STATUS_UNF)) { 269 ret = tx_hard_error_bump_tc; 270 x->tx_undeflow_irq++; 271 } 272 if (unlikely(intr_status & DMA_STATUS_TJT)) 273 x->tx_jabber_irq++; 274 if (unlikely(intr_status & DMA_STATUS_OVF)) 275 x->rx_overflow_irq++; 276 if (unlikely(intr_status & DMA_STATUS_RU)) 277 x->rx_buf_unav_irq++; 278 if (unlikely(intr_status & DMA_STATUS_RPS)) 279 x->rx_process_stopped_irq++; 280 if (unlikely(intr_status & DMA_STATUS_RWT)) 281 x->rx_watchdog_irq++; 282 if (unlikely(intr_status & DMA_STATUS_ETI)) 283 x->tx_early_irq++; 284 if (unlikely(intr_status & DMA_STATUS_TPS)) { 285 x->tx_process_stopped_irq++; 286 ret = tx_hard_error; 287 } 288 if (unlikely(fb_intr_status)) { 289 x->fatal_bus_error_irq++; 290 ret = tx_hard_error; 291 } 292 } 293 /* TX/RX NORMAL interrupts */ 294 if (likely(nor_intr_status)) { 295 if (likely(intr_status & DMA_STATUS_RI)) { 296 u32 value = readl(ioaddr + DMA_INTR_ENA); 297 /* to schedule NAPI on real RIE event. */ 298 if (likely(value & DMA_INTR_ENA_RIE)) { 299 u64_stats_update_begin(&stats->syncp); 300 u64_stats_inc(&stats->rx_normal_irq_n[chan]); 301 u64_stats_update_end(&stats->syncp); 302 ret |= handle_rx; 303 } 304 } 305 if (likely(intr_status & DMA_STATUS_TI)) { 306 u64_stats_update_begin(&stats->syncp); 307 u64_stats_inc(&stats->tx_normal_irq_n[chan]); 308 u64_stats_update_end(&stats->syncp); 309 ret |= handle_tx; 310 } 311 if (unlikely(intr_status & DMA_STATUS_ERI)) 312 x->rx_early_irq++; 313 } 314 /* Optional hardware blocks, interrupts should be disabled */ 315 if (unlikely(intr_status & 316 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI))) 317 pr_warn("%s: unexpected status %08x\n", __func__, intr_status); 318 319 /* Clear the interrupt by writing a logic 1 to the CSR5[19-0] */ 320 writel((intr_status & 0x7ffff), ioaddr + DMA_CHAN_STATUS(chan)); 321 322 return ret; 323 } 324 325 static struct mac_device_info *loongson_dwmac_setup(void *apriv) 326 { 327 struct stmmac_priv *priv = apriv; 328 struct mac_device_info *mac; 329 struct stmmac_dma_ops *dma; 330 struct loongson_data *ld; 331 struct pci_dev *pdev; 332 333 ld = priv->plat->bsp_priv; 334 pdev = to_pci_dev(priv->device); 335 336 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 337 if (!mac) 338 return NULL; 339 340 dma = devm_kzalloc(priv->device, sizeof(*dma), GFP_KERNEL); 341 if (!dma) 342 return NULL; 343 344 /* The Loongson GMAC and GNET devices are based on the DW GMAC 345 * v3.50a and v3.73a IP-cores. But the HW designers have changed 346 * the GMAC_VERSION.SNPSVER field to the custom 0x10/0x12 value 347 * on the network controllers with the multi-channels feature 348 * available to emphasize the differences: multiple DMA-channels, 349 * AV feature and GMAC_INT_STATUS CSR flags layout. Get back the 350 * original value so the correct HW-interface would be selected. 351 */ 352 if (ld->multichan) { 353 priv->synopsys_id = DWMAC_CORE_3_70; 354 *dma = dwmac1000_dma_ops; 355 dma->init_chan = loongson_dwmac_dma_init_channel; 356 dma->dma_interrupt = loongson_dwmac_dma_interrupt; 357 mac->dma = dma; 358 } 359 360 priv->dev->priv_flags |= IFF_UNICAST_FLT; 361 362 /* Pre-initialize the respective "mac" fields as it's done in 363 * dwmac1000_setup() 364 */ 365 mac->pcsr = priv->ioaddr; 366 mac->multicast_filter_bins = priv->plat->multicast_filter_bins; 367 mac->unicast_filter_entries = priv->plat->unicast_filter_entries; 368 mac->mcast_bits_log2 = 0; 369 370 if (mac->multicast_filter_bins) 371 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins); 372 373 /* Loongson GMAC doesn't support the flow control. Loongson GNET 374 * without multi-channel doesn't support the half-duplex link mode. 375 */ 376 if (pdev->device != PCI_DEVICE_ID_LOONGSON_GNET) { 377 mac->link.caps = MAC_10 | MAC_100 | MAC_1000; 378 } else { 379 if (ld->multichan) 380 mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 381 MAC_10 | MAC_100 | MAC_1000; 382 else 383 mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 384 MAC_10FD | MAC_100FD | MAC_1000FD; 385 } 386 387 mac->link.duplex = GMAC_CONTROL_DM; 388 mac->link.speed10 = GMAC_CONTROL_PS; 389 mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES; 390 mac->link.speed1000 = 0; 391 mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES; 392 mac->mii.addr = GMAC_MII_ADDR; 393 mac->mii.data = GMAC_MII_DATA; 394 mac->mii.addr_shift = 11; 395 mac->mii.addr_mask = 0x0000F800; 396 mac->mii.reg_shift = 6; 397 mac->mii.reg_mask = 0x000007C0; 398 mac->mii.clk_csr_shift = 2; 399 mac->mii.clk_csr_mask = GENMASK(5, 2); 400 401 return mac; 402 } 403 404 static int loongson_dwmac_msi_config(struct pci_dev *pdev, 405 struct plat_stmmacenet_data *plat, 406 struct stmmac_resources *res) 407 { 408 int i, ch_num, ret, vecs; 409 410 ch_num = min(plat->tx_queues_to_use, plat->rx_queues_to_use); 411 412 vecs = roundup_pow_of_two(ch_num * 2 + 1); 413 ret = pci_alloc_irq_vectors(pdev, vecs, vecs, PCI_IRQ_MSI); 414 if (ret < 0) { 415 dev_warn(&pdev->dev, "Failed to allocate MSI IRQs\n"); 416 return ret; 417 } 418 419 res->irq = pci_irq_vector(pdev, 0); 420 421 for (i = 0; i < ch_num; i++) { 422 res->rx_irq[ch_num - 1 - i] = pci_irq_vector(pdev, 1 + i * 2); 423 } 424 425 for (i = 0; i < ch_num; i++) { 426 res->tx_irq[ch_num - 1 - i] = pci_irq_vector(pdev, 2 + i * 2); 427 } 428 429 plat->flags |= STMMAC_FLAG_MULTI_MSI_EN; 430 431 return 0; 432 } 433 434 static void loongson_dwmac_msi_clear(struct pci_dev *pdev) 435 { 436 pci_free_irq_vectors(pdev); 437 } 438 439 static int loongson_dwmac_dt_config(struct pci_dev *pdev, 440 struct plat_stmmacenet_data *plat, 441 struct stmmac_resources *res) 442 { 443 struct device_node *np = dev_of_node(&pdev->dev); 444 int ret; 445 446 plat->mdio_node = of_get_child_by_name(np, "mdio"); 447 if (plat->mdio_node) { 448 dev_info(&pdev->dev, "Found MDIO subnode\n"); 449 plat->mdio_bus_data->needs_reset = true; 450 } 451 452 ret = of_alias_get_id(np, "ethernet"); 453 if (ret >= 0) 454 plat->bus_id = ret; 455 456 res->irq = of_irq_get_byname(np, "macirq"); 457 if (res->irq < 0) { 458 dev_err(&pdev->dev, "IRQ macirq not found\n"); 459 ret = -ENODEV; 460 goto err_put_node; 461 } 462 463 res->wol_irq = of_irq_get_byname(np, "eth_wake_irq"); 464 if (res->wol_irq < 0) { 465 dev_info(&pdev->dev, 466 "IRQ eth_wake_irq not found, using macirq\n"); 467 res->wol_irq = res->irq; 468 } 469 470 res->lpi_irq = of_irq_get_byname(np, "eth_lpi"); 471 if (res->lpi_irq < 0) { 472 dev_err(&pdev->dev, "IRQ eth_lpi not found\n"); 473 ret = -ENODEV; 474 goto err_put_node; 475 } 476 477 ret = device_get_phy_mode(&pdev->dev); 478 if (ret < 0) { 479 dev_err(&pdev->dev, "phy_mode not found\n"); 480 ret = -ENODEV; 481 goto err_put_node; 482 } 483 484 plat->phy_interface = ret; 485 486 return 0; 487 488 err_put_node: 489 of_node_put(plat->mdio_node); 490 491 return ret; 492 } 493 494 static void loongson_dwmac_dt_clear(struct pci_dev *pdev, 495 struct plat_stmmacenet_data *plat) 496 { 497 of_node_put(plat->mdio_node); 498 } 499 500 static int loongson_dwmac_acpi_config(struct pci_dev *pdev, 501 struct plat_stmmacenet_data *plat, 502 struct stmmac_resources *res) 503 { 504 if (!pdev->irq) 505 return -EINVAL; 506 507 res->irq = pdev->irq; 508 509 return 0; 510 } 511 512 /* Loongson's DWMAC device may take nearly two seconds to complete DMA reset */ 513 static int loongson_dwmac_fix_reset(struct stmmac_priv *priv, void __iomem *ioaddr) 514 { 515 u32 value = readl(ioaddr + DMA_BUS_MODE); 516 517 if (value & DMA_BUS_MODE_SFT_RESET) { 518 netdev_err(priv->dev, "the PHY clock is missing\n"); 519 return -EINVAL; 520 } 521 522 value |= DMA_BUS_MODE_SFT_RESET; 523 writel(value, ioaddr + DMA_BUS_MODE); 524 525 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, 526 !(value & DMA_BUS_MODE_SFT_RESET), 527 10000, 2000000); 528 } 529 530 static int loongson_dwmac_suspend(struct device *dev, void *bsp_priv) 531 { 532 struct pci_dev *pdev = to_pci_dev(dev); 533 int ret; 534 535 ret = pci_save_state(pdev); 536 if (ret) 537 return ret; 538 539 pci_disable_device(pdev); 540 pci_wake_from_d3(pdev, true); 541 return 0; 542 } 543 544 static int loongson_dwmac_resume(struct device *dev, void *bsp_priv) 545 { 546 struct pci_dev *pdev = to_pci_dev(dev); 547 int ret; 548 549 pci_restore_state(pdev); 550 pci_set_power_state(pdev, PCI_D0); 551 552 ret = pci_enable_device(pdev); 553 if (ret) 554 return ret; 555 556 pci_set_master(pdev); 557 558 return 0; 559 } 560 561 static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id *id) 562 { 563 struct plat_stmmacenet_data *plat; 564 struct stmmac_resources res = {}; 565 struct stmmac_pci_info *info; 566 struct loongson_data *ld; 567 int ret; 568 569 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 570 if (!plat) 571 return -ENOMEM; 572 573 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, 574 sizeof(*plat->mdio_bus_data), 575 GFP_KERNEL); 576 if (!plat->mdio_bus_data) 577 return -ENOMEM; 578 579 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), GFP_KERNEL); 580 if (!plat->dma_cfg) 581 return -ENOMEM; 582 583 ld = devm_kzalloc(&pdev->dev, sizeof(*ld), GFP_KERNEL); 584 if (!ld) 585 return -ENOMEM; 586 587 /* Enable pci device */ 588 ret = pci_enable_device(pdev); 589 if (ret) { 590 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", __func__); 591 return ret; 592 } 593 594 pci_set_master(pdev); 595 596 /* Get the base address of device */ 597 res.addr = pcim_iomap_region(pdev, 0, DRIVER_NAME); 598 ret = PTR_ERR_OR_ZERO(res.addr); 599 if (ret) 600 goto err_disable_device; 601 602 plat->bsp_priv = ld; 603 plat->setup = loongson_dwmac_setup; 604 plat->fix_soc_reset = loongson_dwmac_fix_reset; 605 plat->suspend = loongson_dwmac_suspend; 606 plat->resume = loongson_dwmac_resume; 607 ld->dev = &pdev->dev; 608 ld->loongson_id = readl(res.addr + GMAC_VERSION) & 0xff; 609 610 info = (struct stmmac_pci_info *)id->driver_data; 611 ret = info->setup(pdev, plat); 612 if (ret) 613 goto err_disable_device; 614 615 plat->tx_fifo_size = SZ_16K * plat->tx_queues_to_use; 616 plat->rx_fifo_size = SZ_16K * plat->rx_queues_to_use; 617 618 if (dev_of_node(&pdev->dev)) 619 ret = loongson_dwmac_dt_config(pdev, plat, &res); 620 else 621 ret = loongson_dwmac_acpi_config(pdev, plat, &res); 622 if (ret) 623 goto err_disable_device; 624 625 /* Use the common MAC IRQ if per-channel MSIs allocation failed */ 626 if (ld->multichan) 627 loongson_dwmac_msi_config(pdev, plat, &res); 628 629 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); 630 if (ret) 631 goto err_plat_clear; 632 633 return 0; 634 635 err_plat_clear: 636 if (dev_of_node(&pdev->dev)) 637 loongson_dwmac_dt_clear(pdev, plat); 638 if (ld->multichan) 639 loongson_dwmac_msi_clear(pdev); 640 err_disable_device: 641 pci_disable_device(pdev); 642 return ret; 643 } 644 645 static void loongson_dwmac_remove(struct pci_dev *pdev) 646 { 647 struct net_device *ndev = dev_get_drvdata(&pdev->dev); 648 struct stmmac_priv *priv = netdev_priv(ndev); 649 struct loongson_data *ld; 650 651 ld = priv->plat->bsp_priv; 652 stmmac_dvr_remove(&pdev->dev); 653 654 if (dev_of_node(&pdev->dev)) 655 loongson_dwmac_dt_clear(pdev, priv->plat); 656 657 if (ld->multichan) 658 loongson_dwmac_msi_clear(pdev); 659 660 pci_disable_device(pdev); 661 } 662 663 static const struct pci_device_id loongson_dwmac_id_table[] = { 664 { PCI_DEVICE_DATA(LOONGSON, GMAC1, &loongson_gmac_pci_info) }, 665 { PCI_DEVICE_DATA(LOONGSON, GMAC2, &loongson_gmac_pci_info) }, 666 { PCI_DEVICE_DATA(LOONGSON, GNET, &loongson_gnet_pci_info) }, 667 {} 668 }; 669 MODULE_DEVICE_TABLE(pci, loongson_dwmac_id_table); 670 671 static struct pci_driver loongson_dwmac_driver = { 672 .name = DRIVER_NAME, 673 .id_table = loongson_dwmac_id_table, 674 .probe = loongson_dwmac_probe, 675 .remove = loongson_dwmac_remove, 676 .driver = { 677 .pm = &stmmac_simple_pm_ops, 678 }, 679 }; 680 681 module_pci_driver(loongson_dwmac_driver); 682 683 MODULE_DESCRIPTION("Loongson DWMAC PCI driver"); 684 MODULE_AUTHOR("Qing Zhang <zhangqing@loongson.cn>"); 685 MODULE_AUTHOR("Yanteng Si <siyanteng@loongson.cn>"); 686 MODULE_LICENSE("GPL v2"); 687