1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2020, Loongson Corporation 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/pci.h> 7 #include <linux/dmi.h> 8 #include <linux/device.h> 9 #include <linux/of_irq.h> 10 #include "stmmac.h" 11 #include "dwmac_dma.h" 12 #include "dwmac1000.h" 13 14 #define DRIVER_NAME "dwmac-loongson-pci" 15 16 /* Normal Loongson Tx Summary */ 17 #define DMA_INTR_ENA_NIE_TX_LOONGSON 0x00040000 18 /* Normal Loongson Rx Summary */ 19 #define DMA_INTR_ENA_NIE_RX_LOONGSON 0x00020000 20 21 #define DMA_INTR_NORMAL_LOONGSON (DMA_INTR_ENA_NIE_TX_LOONGSON | \ 22 DMA_INTR_ENA_NIE_RX_LOONGSON | \ 23 DMA_INTR_ENA_RIE | DMA_INTR_ENA_TIE) 24 25 /* Abnormal Loongson Tx Summary */ 26 #define DMA_INTR_ENA_AIE_TX_LOONGSON 0x00010000 27 /* Abnormal Loongson Rx Summary */ 28 #define DMA_INTR_ENA_AIE_RX_LOONGSON 0x00008000 29 30 #define DMA_INTR_ABNORMAL_LOONGSON (DMA_INTR_ENA_AIE_TX_LOONGSON | \ 31 DMA_INTR_ENA_AIE_RX_LOONGSON | \ 32 DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE) 33 34 #define DMA_INTR_DEFAULT_MASK_LOONGSON (DMA_INTR_NORMAL_LOONGSON | \ 35 DMA_INTR_ABNORMAL_LOONGSON) 36 37 /* Normal Loongson Tx Interrupt Summary */ 38 #define DMA_STATUS_NIS_TX_LOONGSON 0x00040000 39 /* Normal Loongson Rx Interrupt Summary */ 40 #define DMA_STATUS_NIS_RX_LOONGSON 0x00020000 41 42 /* Abnormal Loongson Tx Interrupt Summary */ 43 #define DMA_STATUS_AIS_TX_LOONGSON 0x00010000 44 /* Abnormal Loongson Rx Interrupt Summary */ 45 #define DMA_STATUS_AIS_RX_LOONGSON 0x00008000 46 47 /* Fatal Loongson Tx Bus Error Interrupt */ 48 #define DMA_STATUS_FBI_TX_LOONGSON 0x00002000 49 /* Fatal Loongson Rx Bus Error Interrupt */ 50 #define DMA_STATUS_FBI_RX_LOONGSON 0x00001000 51 52 #define DMA_STATUS_MSK_COMMON_LOONGSON (DMA_STATUS_NIS_TX_LOONGSON | \ 53 DMA_STATUS_NIS_RX_LOONGSON | \ 54 DMA_STATUS_AIS_TX_LOONGSON | \ 55 DMA_STATUS_AIS_RX_LOONGSON | \ 56 DMA_STATUS_FBI_TX_LOONGSON | \ 57 DMA_STATUS_FBI_RX_LOONGSON) 58 59 #define DMA_STATUS_MSK_RX_LOONGSON (DMA_STATUS_ERI | DMA_STATUS_RWT | \ 60 DMA_STATUS_RPS | DMA_STATUS_RU | \ 61 DMA_STATUS_RI | DMA_STATUS_OVF | \ 62 DMA_STATUS_MSK_COMMON_LOONGSON) 63 64 #define DMA_STATUS_MSK_TX_LOONGSON (DMA_STATUS_ETI | DMA_STATUS_UNF | \ 65 DMA_STATUS_TJT | DMA_STATUS_TU | \ 66 DMA_STATUS_TPS | DMA_STATUS_TI | \ 67 DMA_STATUS_MSK_COMMON_LOONGSON) 68 69 #define PCI_DEVICE_ID_LOONGSON_GMAC1 0x7a03 70 #define PCI_DEVICE_ID_LOONGSON_GMAC2 0x7a23 71 #define PCI_DEVICE_ID_LOONGSON_GNET 0x7a13 72 #define DWMAC_CORE_MULTICHAN_V1 0x10 /* Loongson custom ID 0x10 */ 73 #define DWMAC_CORE_MULTICHAN_V2 0x12 /* Loongson custom ID 0x12 */ 74 75 struct loongson_data { 76 u32 multichan; 77 u32 loongson_id; 78 struct device *dev; 79 }; 80 81 struct stmmac_pci_info { 82 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); 83 }; 84 85 static void loongson_default_data(struct pci_dev *pdev, 86 struct plat_stmmacenet_data *plat) 87 { 88 struct loongson_data *ld = plat->bsp_priv; 89 90 /* Get bus_id, this can be overwritten later */ 91 plat->bus_id = pci_dev_id(pdev); 92 93 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 94 plat->has_gmac = 1; 95 plat->force_sf_dma_mode = 1; 96 97 /* Set default value for multicast hash bins */ 98 plat->multicast_filter_bins = 256; 99 100 plat->mac_interface = PHY_INTERFACE_MODE_NA; 101 102 /* Set default value for unicast filter entries */ 103 plat->unicast_filter_entries = 1; 104 105 /* Set the maxmtu to a default of JUMBO_LEN */ 106 plat->maxmtu = JUMBO_LEN; 107 108 /* Disable Priority config by default */ 109 plat->tx_queues_cfg[0].use_prio = false; 110 plat->rx_queues_cfg[0].use_prio = false; 111 112 /* Disable RX queues routing by default */ 113 plat->rx_queues_cfg[0].pkt_route = 0x0; 114 115 plat->clk_ref_rate = 125000000; 116 plat->clk_ptp_rate = 125000000; 117 118 /* Default to phy auto-detection */ 119 plat->phy_addr = -1; 120 121 plat->dma_cfg->pbl = 32; 122 plat->dma_cfg->pblx8 = true; 123 124 switch (ld->loongson_id) { 125 case DWMAC_CORE_MULTICHAN_V1: 126 ld->multichan = 1; 127 plat->rx_queues_to_use = 8; 128 plat->tx_queues_to_use = 8; 129 130 /* Only channel 0 supports checksum, 131 * so turn off checksum to enable multiple channels. 132 */ 133 for (int i = 1; i < 8; i++) 134 plat->tx_queues_cfg[i].coe_unsupported = 1; 135 136 break; 137 case DWMAC_CORE_MULTICHAN_V2: 138 ld->multichan = 1; 139 plat->rx_queues_to_use = 4; 140 plat->tx_queues_to_use = 4; 141 break; 142 default: 143 ld->multichan = 0; 144 plat->tx_queues_to_use = 1; 145 plat->rx_queues_to_use = 1; 146 break; 147 } 148 } 149 150 static int loongson_gmac_data(struct pci_dev *pdev, 151 struct plat_stmmacenet_data *plat) 152 { 153 loongson_default_data(pdev, plat); 154 155 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 156 157 return 0; 158 } 159 160 static struct stmmac_pci_info loongson_gmac_pci_info = { 161 .setup = loongson_gmac_data, 162 }; 163 164 static void loongson_gnet_fix_speed(void *priv, int speed, unsigned int mode) 165 { 166 struct loongson_data *ld = (struct loongson_data *)priv; 167 struct net_device *ndev = dev_get_drvdata(ld->dev); 168 struct stmmac_priv *ptr = netdev_priv(ndev); 169 170 /* The integrated PHY has a weird problem with switching from the low 171 * speeds to 1000Mbps mode. The speedup procedure requires the PHY-link 172 * re-negotiation. 173 */ 174 if (speed == SPEED_1000) { 175 if (readl(ptr->ioaddr + MAC_CTRL_REG) & 176 GMAC_CONTROL_PS) 177 /* Word around hardware bug, restart autoneg */ 178 phy_restart_aneg(ndev->phydev); 179 } 180 } 181 182 static int loongson_gnet_data(struct pci_dev *pdev, 183 struct plat_stmmacenet_data *plat) 184 { 185 loongson_default_data(pdev, plat); 186 187 plat->phy_interface = PHY_INTERFACE_MODE_GMII; 188 plat->mdio_bus_data->phy_mask = ~(u32)BIT(2); 189 plat->fix_mac_speed = loongson_gnet_fix_speed; 190 191 return 0; 192 } 193 194 static struct stmmac_pci_info loongson_gnet_pci_info = { 195 .setup = loongson_gnet_data, 196 }; 197 198 static void loongson_dwmac_dma_init_channel(struct stmmac_priv *priv, 199 void __iomem *ioaddr, 200 struct stmmac_dma_cfg *dma_cfg, 201 u32 chan) 202 { 203 int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 204 int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 205 u32 value; 206 207 value = readl(ioaddr + DMA_CHAN_BUS_MODE(chan)); 208 209 if (dma_cfg->pblx8) 210 value |= DMA_BUS_MODE_MAXPBL; 211 212 value |= DMA_BUS_MODE_USP; 213 value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK); 214 value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT); 215 value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 216 217 /* Set the Fixed burst mode */ 218 if (dma_cfg->fixed_burst) 219 value |= DMA_BUS_MODE_FB; 220 221 /* Mixed Burst has no effect when fb is set */ 222 if (dma_cfg->mixed_burst) 223 value |= DMA_BUS_MODE_MB; 224 225 if (dma_cfg->atds) 226 value |= DMA_BUS_MODE_ATDS; 227 228 if (dma_cfg->aal) 229 value |= DMA_BUS_MODE_AAL; 230 231 writel(value, ioaddr + DMA_CHAN_BUS_MODE(chan)); 232 233 /* Mask interrupts by writing to CSR7 */ 234 writel(DMA_INTR_DEFAULT_MASK_LOONGSON, ioaddr + 235 DMA_CHAN_INTR_ENA(chan)); 236 } 237 238 static int loongson_dwmac_dma_interrupt(struct stmmac_priv *priv, 239 void __iomem *ioaddr, 240 struct stmmac_extra_stats *x, 241 u32 chan, u32 dir) 242 { 243 struct stmmac_pcpu_stats *stats = this_cpu_ptr(priv->xstats.pcpu_stats); 244 u32 abnor_intr_status; 245 u32 nor_intr_status; 246 u32 fb_intr_status; 247 u32 intr_status; 248 int ret = 0; 249 250 /* read the status register (CSR5) */ 251 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan)); 252 253 if (dir == DMA_DIR_RX) 254 intr_status &= DMA_STATUS_MSK_RX_LOONGSON; 255 else if (dir == DMA_DIR_TX) 256 intr_status &= DMA_STATUS_MSK_TX_LOONGSON; 257 258 nor_intr_status = intr_status & (DMA_STATUS_NIS_TX_LOONGSON | 259 DMA_STATUS_NIS_RX_LOONGSON); 260 abnor_intr_status = intr_status & (DMA_STATUS_AIS_TX_LOONGSON | 261 DMA_STATUS_AIS_RX_LOONGSON); 262 fb_intr_status = intr_status & (DMA_STATUS_FBI_TX_LOONGSON | 263 DMA_STATUS_FBI_RX_LOONGSON); 264 265 /* ABNORMAL interrupts */ 266 if (unlikely(abnor_intr_status)) { 267 if (unlikely(intr_status & DMA_STATUS_UNF)) { 268 ret = tx_hard_error_bump_tc; 269 x->tx_undeflow_irq++; 270 } 271 if (unlikely(intr_status & DMA_STATUS_TJT)) 272 x->tx_jabber_irq++; 273 if (unlikely(intr_status & DMA_STATUS_OVF)) 274 x->rx_overflow_irq++; 275 if (unlikely(intr_status & DMA_STATUS_RU)) 276 x->rx_buf_unav_irq++; 277 if (unlikely(intr_status & DMA_STATUS_RPS)) 278 x->rx_process_stopped_irq++; 279 if (unlikely(intr_status & DMA_STATUS_RWT)) 280 x->rx_watchdog_irq++; 281 if (unlikely(intr_status & DMA_STATUS_ETI)) 282 x->tx_early_irq++; 283 if (unlikely(intr_status & DMA_STATUS_TPS)) { 284 x->tx_process_stopped_irq++; 285 ret = tx_hard_error; 286 } 287 if (unlikely(fb_intr_status)) { 288 x->fatal_bus_error_irq++; 289 ret = tx_hard_error; 290 } 291 } 292 /* TX/RX NORMAL interrupts */ 293 if (likely(nor_intr_status)) { 294 if (likely(intr_status & DMA_STATUS_RI)) { 295 u32 value = readl(ioaddr + DMA_INTR_ENA); 296 /* to schedule NAPI on real RIE event. */ 297 if (likely(value & DMA_INTR_ENA_RIE)) { 298 u64_stats_update_begin(&stats->syncp); 299 u64_stats_inc(&stats->rx_normal_irq_n[chan]); 300 u64_stats_update_end(&stats->syncp); 301 ret |= handle_rx; 302 } 303 } 304 if (likely(intr_status & DMA_STATUS_TI)) { 305 u64_stats_update_begin(&stats->syncp); 306 u64_stats_inc(&stats->tx_normal_irq_n[chan]); 307 u64_stats_update_end(&stats->syncp); 308 ret |= handle_tx; 309 } 310 if (unlikely(intr_status & DMA_STATUS_ERI)) 311 x->rx_early_irq++; 312 } 313 /* Optional hardware blocks, interrupts should be disabled */ 314 if (unlikely(intr_status & 315 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI))) 316 pr_warn("%s: unexpected status %08x\n", __func__, intr_status); 317 318 /* Clear the interrupt by writing a logic 1 to the CSR5[19-0] */ 319 writel((intr_status & 0x7ffff), ioaddr + DMA_CHAN_STATUS(chan)); 320 321 return ret; 322 } 323 324 static struct mac_device_info *loongson_dwmac_setup(void *apriv) 325 { 326 struct stmmac_priv *priv = apriv; 327 struct mac_device_info *mac; 328 struct stmmac_dma_ops *dma; 329 struct loongson_data *ld; 330 struct pci_dev *pdev; 331 332 ld = priv->plat->bsp_priv; 333 pdev = to_pci_dev(priv->device); 334 335 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 336 if (!mac) 337 return NULL; 338 339 dma = devm_kzalloc(priv->device, sizeof(*dma), GFP_KERNEL); 340 if (!dma) 341 return NULL; 342 343 /* The Loongson GMAC and GNET devices are based on the DW GMAC 344 * v3.50a and v3.73a IP-cores. But the HW designers have changed 345 * the GMAC_VERSION.SNPSVER field to the custom 0x10/0x12 value 346 * on the network controllers with the multi-channels feature 347 * available to emphasize the differences: multiple DMA-channels, 348 * AV feature and GMAC_INT_STATUS CSR flags layout. Get back the 349 * original value so the correct HW-interface would be selected. 350 */ 351 if (ld->multichan) { 352 priv->synopsys_id = DWMAC_CORE_3_70; 353 *dma = dwmac1000_dma_ops; 354 dma->init_chan = loongson_dwmac_dma_init_channel; 355 dma->dma_interrupt = loongson_dwmac_dma_interrupt; 356 mac->dma = dma; 357 } 358 359 priv->dev->priv_flags |= IFF_UNICAST_FLT; 360 361 /* Pre-initialize the respective "mac" fields as it's done in 362 * dwmac1000_setup() 363 */ 364 mac->pcsr = priv->ioaddr; 365 mac->multicast_filter_bins = priv->plat->multicast_filter_bins; 366 mac->unicast_filter_entries = priv->plat->unicast_filter_entries; 367 mac->mcast_bits_log2 = 0; 368 369 if (mac->multicast_filter_bins) 370 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins); 371 372 /* Loongson GMAC doesn't support the flow control. Loongson GNET 373 * without multi-channel doesn't support the half-duplex link mode. 374 */ 375 if (pdev->device != PCI_DEVICE_ID_LOONGSON_GNET) { 376 mac->link.caps = MAC_10 | MAC_100 | MAC_1000; 377 } else { 378 if (ld->multichan) 379 mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 380 MAC_10 | MAC_100 | MAC_1000; 381 else 382 mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 383 MAC_10FD | MAC_100FD | MAC_1000FD; 384 } 385 386 mac->link.duplex = GMAC_CONTROL_DM; 387 mac->link.speed10 = GMAC_CONTROL_PS; 388 mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES; 389 mac->link.speed1000 = 0; 390 mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES; 391 mac->mii.addr = GMAC_MII_ADDR; 392 mac->mii.data = GMAC_MII_DATA; 393 mac->mii.addr_shift = 11; 394 mac->mii.addr_mask = 0x0000F800; 395 mac->mii.reg_shift = 6; 396 mac->mii.reg_mask = 0x000007C0; 397 mac->mii.clk_csr_shift = 2; 398 mac->mii.clk_csr_mask = GENMASK(5, 2); 399 400 return mac; 401 } 402 403 static int loongson_dwmac_msi_config(struct pci_dev *pdev, 404 struct plat_stmmacenet_data *plat, 405 struct stmmac_resources *res) 406 { 407 int i, ch_num, ret, vecs; 408 409 ch_num = min(plat->tx_queues_to_use, plat->rx_queues_to_use); 410 411 vecs = roundup_pow_of_two(ch_num * 2 + 1); 412 ret = pci_alloc_irq_vectors(pdev, vecs, vecs, PCI_IRQ_MSI); 413 if (ret < 0) { 414 dev_warn(&pdev->dev, "Failed to allocate MSI IRQs\n"); 415 return ret; 416 } 417 418 res->irq = pci_irq_vector(pdev, 0); 419 420 for (i = 0; i < ch_num; i++) { 421 res->rx_irq[ch_num - 1 - i] = pci_irq_vector(pdev, 1 + i * 2); 422 } 423 424 for (i = 0; i < ch_num; i++) { 425 res->tx_irq[ch_num - 1 - i] = pci_irq_vector(pdev, 2 + i * 2); 426 } 427 428 plat->flags |= STMMAC_FLAG_MULTI_MSI_EN; 429 430 return 0; 431 } 432 433 static void loongson_dwmac_msi_clear(struct pci_dev *pdev) 434 { 435 pci_free_irq_vectors(pdev); 436 } 437 438 static int loongson_dwmac_dt_config(struct pci_dev *pdev, 439 struct plat_stmmacenet_data *plat, 440 struct stmmac_resources *res) 441 { 442 struct device_node *np = dev_of_node(&pdev->dev); 443 int ret; 444 445 plat->mdio_node = of_get_child_by_name(np, "mdio"); 446 if (plat->mdio_node) { 447 dev_info(&pdev->dev, "Found MDIO subnode\n"); 448 plat->mdio_bus_data->needs_reset = true; 449 } 450 451 ret = of_alias_get_id(np, "ethernet"); 452 if (ret >= 0) 453 plat->bus_id = ret; 454 455 res->irq = of_irq_get_byname(np, "macirq"); 456 if (res->irq < 0) { 457 dev_err(&pdev->dev, "IRQ macirq not found\n"); 458 ret = -ENODEV; 459 goto err_put_node; 460 } 461 462 res->wol_irq = of_irq_get_byname(np, "eth_wake_irq"); 463 if (res->wol_irq < 0) { 464 dev_info(&pdev->dev, 465 "IRQ eth_wake_irq not found, using macirq\n"); 466 res->wol_irq = res->irq; 467 } 468 469 res->lpi_irq = of_irq_get_byname(np, "eth_lpi"); 470 if (res->lpi_irq < 0) { 471 dev_err(&pdev->dev, "IRQ eth_lpi not found\n"); 472 ret = -ENODEV; 473 goto err_put_node; 474 } 475 476 ret = device_get_phy_mode(&pdev->dev); 477 if (ret < 0) { 478 dev_err(&pdev->dev, "phy_mode not found\n"); 479 ret = -ENODEV; 480 goto err_put_node; 481 } 482 483 plat->phy_interface = ret; 484 485 return 0; 486 487 err_put_node: 488 of_node_put(plat->mdio_node); 489 490 return ret; 491 } 492 493 static void loongson_dwmac_dt_clear(struct pci_dev *pdev, 494 struct plat_stmmacenet_data *plat) 495 { 496 of_node_put(plat->mdio_node); 497 } 498 499 static int loongson_dwmac_acpi_config(struct pci_dev *pdev, 500 struct plat_stmmacenet_data *plat, 501 struct stmmac_resources *res) 502 { 503 if (!pdev->irq) 504 return -EINVAL; 505 506 res->irq = pdev->irq; 507 508 return 0; 509 } 510 511 /* Loongson's DWMAC device may take nearly two seconds to complete DMA reset */ 512 static int loongson_dwmac_fix_reset(void *priv, void __iomem *ioaddr) 513 { 514 u32 value = readl(ioaddr + DMA_BUS_MODE); 515 516 value |= DMA_BUS_MODE_SFT_RESET; 517 writel(value, ioaddr + DMA_BUS_MODE); 518 519 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, 520 !(value & DMA_BUS_MODE_SFT_RESET), 521 10000, 2000000); 522 } 523 524 static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id *id) 525 { 526 struct plat_stmmacenet_data *plat; 527 struct stmmac_resources res = {}; 528 struct stmmac_pci_info *info; 529 struct loongson_data *ld; 530 int ret; 531 532 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 533 if (!plat) 534 return -ENOMEM; 535 536 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, 537 sizeof(*plat->mdio_bus_data), 538 GFP_KERNEL); 539 if (!plat->mdio_bus_data) 540 return -ENOMEM; 541 542 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), GFP_KERNEL); 543 if (!plat->dma_cfg) 544 return -ENOMEM; 545 546 ld = devm_kzalloc(&pdev->dev, sizeof(*ld), GFP_KERNEL); 547 if (!ld) 548 return -ENOMEM; 549 550 /* Enable pci device */ 551 ret = pci_enable_device(pdev); 552 if (ret) { 553 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", __func__); 554 return ret; 555 } 556 557 pci_set_master(pdev); 558 559 /* Get the base address of device */ 560 res.addr = pcim_iomap_region(pdev, 0, DRIVER_NAME); 561 ret = PTR_ERR_OR_ZERO(res.addr); 562 if (ret) 563 goto err_disable_device; 564 565 plat->bsp_priv = ld; 566 plat->setup = loongson_dwmac_setup; 567 plat->fix_soc_reset = loongson_dwmac_fix_reset; 568 ld->dev = &pdev->dev; 569 ld->loongson_id = readl(res.addr + GMAC_VERSION) & 0xff; 570 571 info = (struct stmmac_pci_info *)id->driver_data; 572 ret = info->setup(pdev, plat); 573 if (ret) 574 goto err_disable_device; 575 576 plat->tx_fifo_size = SZ_16K * plat->tx_queues_to_use; 577 plat->rx_fifo_size = SZ_16K * plat->rx_queues_to_use; 578 579 if (dev_of_node(&pdev->dev)) 580 ret = loongson_dwmac_dt_config(pdev, plat, &res); 581 else 582 ret = loongson_dwmac_acpi_config(pdev, plat, &res); 583 if (ret) 584 goto err_disable_device; 585 586 /* Use the common MAC IRQ if per-channel MSIs allocation failed */ 587 if (ld->multichan) 588 loongson_dwmac_msi_config(pdev, plat, &res); 589 590 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); 591 if (ret) 592 goto err_plat_clear; 593 594 return 0; 595 596 err_plat_clear: 597 if (dev_of_node(&pdev->dev)) 598 loongson_dwmac_dt_clear(pdev, plat); 599 if (ld->multichan) 600 loongson_dwmac_msi_clear(pdev); 601 err_disable_device: 602 pci_disable_device(pdev); 603 return ret; 604 } 605 606 static void loongson_dwmac_remove(struct pci_dev *pdev) 607 { 608 struct net_device *ndev = dev_get_drvdata(&pdev->dev); 609 struct stmmac_priv *priv = netdev_priv(ndev); 610 struct loongson_data *ld; 611 612 ld = priv->plat->bsp_priv; 613 stmmac_dvr_remove(&pdev->dev); 614 615 if (dev_of_node(&pdev->dev)) 616 loongson_dwmac_dt_clear(pdev, priv->plat); 617 618 if (ld->multichan) 619 loongson_dwmac_msi_clear(pdev); 620 621 pci_disable_device(pdev); 622 } 623 624 static int __maybe_unused loongson_dwmac_suspend(struct device *dev) 625 { 626 struct pci_dev *pdev = to_pci_dev(dev); 627 int ret; 628 629 ret = stmmac_suspend(dev); 630 if (ret) 631 return ret; 632 633 ret = pci_save_state(pdev); 634 if (ret) 635 return ret; 636 637 pci_disable_device(pdev); 638 pci_wake_from_d3(pdev, true); 639 return 0; 640 } 641 642 static int __maybe_unused loongson_dwmac_resume(struct device *dev) 643 { 644 struct pci_dev *pdev = to_pci_dev(dev); 645 int ret; 646 647 pci_restore_state(pdev); 648 pci_set_power_state(pdev, PCI_D0); 649 650 ret = pci_enable_device(pdev); 651 if (ret) 652 return ret; 653 654 pci_set_master(pdev); 655 656 return stmmac_resume(dev); 657 } 658 659 static SIMPLE_DEV_PM_OPS(loongson_dwmac_pm_ops, loongson_dwmac_suspend, 660 loongson_dwmac_resume); 661 662 static const struct pci_device_id loongson_dwmac_id_table[] = { 663 { PCI_DEVICE_DATA(LOONGSON, GMAC1, &loongson_gmac_pci_info) }, 664 { PCI_DEVICE_DATA(LOONGSON, GMAC2, &loongson_gmac_pci_info) }, 665 { PCI_DEVICE_DATA(LOONGSON, GNET, &loongson_gnet_pci_info) }, 666 {} 667 }; 668 MODULE_DEVICE_TABLE(pci, loongson_dwmac_id_table); 669 670 static struct pci_driver loongson_dwmac_driver = { 671 .name = DRIVER_NAME, 672 .id_table = loongson_dwmac_id_table, 673 .probe = loongson_dwmac_probe, 674 .remove = loongson_dwmac_remove, 675 .driver = { 676 .pm = &loongson_dwmac_pm_ops, 677 }, 678 }; 679 680 module_pci_driver(loongson_dwmac_driver); 681 682 MODULE_DESCRIPTION("Loongson DWMAC PCI driver"); 683 MODULE_AUTHOR("Qing Zhang <zhangqing@loongson.cn>"); 684 MODULE_AUTHOR("Yanteng Si <siyanteng@loongson.cn>"); 685 MODULE_LICENSE("GPL v2"); 686