1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2020, Loongson Corporation 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/pci.h> 7 #include <linux/dmi.h> 8 #include <linux/device.h> 9 #include <linux/of_irq.h> 10 #include "stmmac.h" 11 #include "dwmac_dma.h" 12 #include "dwmac1000.h" 13 14 #define DRIVER_NAME "dwmac-loongson-pci" 15 16 /* Normal Loongson Tx Summary */ 17 #define DMA_INTR_ENA_NIE_TX_LOONGSON 0x00040000 18 /* Normal Loongson Rx Summary */ 19 #define DMA_INTR_ENA_NIE_RX_LOONGSON 0x00020000 20 21 #define DMA_INTR_NORMAL_LOONGSON (DMA_INTR_ENA_NIE_TX_LOONGSON | \ 22 DMA_INTR_ENA_NIE_RX_LOONGSON | \ 23 DMA_INTR_ENA_RIE | DMA_INTR_ENA_TIE) 24 25 /* Abnormal Loongson Tx Summary */ 26 #define DMA_INTR_ENA_AIE_TX_LOONGSON 0x00010000 27 /* Abnormal Loongson Rx Summary */ 28 #define DMA_INTR_ENA_AIE_RX_LOONGSON 0x00008000 29 30 #define DMA_INTR_ABNORMAL_LOONGSON (DMA_INTR_ENA_AIE_TX_LOONGSON | \ 31 DMA_INTR_ENA_AIE_RX_LOONGSON | \ 32 DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE) 33 34 #define DMA_INTR_DEFAULT_MASK_LOONGSON (DMA_INTR_NORMAL_LOONGSON | \ 35 DMA_INTR_ABNORMAL_LOONGSON) 36 37 /* Normal Loongson Tx Interrupt Summary */ 38 #define DMA_STATUS_NIS_TX_LOONGSON 0x00040000 39 /* Normal Loongson Rx Interrupt Summary */ 40 #define DMA_STATUS_NIS_RX_LOONGSON 0x00020000 41 42 /* Abnormal Loongson Tx Interrupt Summary */ 43 #define DMA_STATUS_AIS_TX_LOONGSON 0x00010000 44 /* Abnormal Loongson Rx Interrupt Summary */ 45 #define DMA_STATUS_AIS_RX_LOONGSON 0x00008000 46 47 /* Fatal Loongson Tx Bus Error Interrupt */ 48 #define DMA_STATUS_FBI_TX_LOONGSON 0x00002000 49 /* Fatal Loongson Rx Bus Error Interrupt */ 50 #define DMA_STATUS_FBI_RX_LOONGSON 0x00001000 51 52 #define DMA_STATUS_MSK_COMMON_LOONGSON (DMA_STATUS_NIS_TX_LOONGSON | \ 53 DMA_STATUS_NIS_RX_LOONGSON | \ 54 DMA_STATUS_AIS_TX_LOONGSON | \ 55 DMA_STATUS_AIS_RX_LOONGSON | \ 56 DMA_STATUS_FBI_TX_LOONGSON | \ 57 DMA_STATUS_FBI_RX_LOONGSON) 58 59 #define DMA_STATUS_MSK_RX_LOONGSON (DMA_STATUS_ERI | DMA_STATUS_RWT | \ 60 DMA_STATUS_RPS | DMA_STATUS_RU | \ 61 DMA_STATUS_RI | DMA_STATUS_OVF | \ 62 DMA_STATUS_MSK_COMMON_LOONGSON) 63 64 #define DMA_STATUS_MSK_TX_LOONGSON (DMA_STATUS_ETI | DMA_STATUS_UNF | \ 65 DMA_STATUS_TJT | DMA_STATUS_TU | \ 66 DMA_STATUS_TPS | DMA_STATUS_TI | \ 67 DMA_STATUS_MSK_COMMON_LOONGSON) 68 69 #define PCI_DEVICE_ID_LOONGSON_GMAC1 0x7a03 70 #define PCI_DEVICE_ID_LOONGSON_GMAC2 0x7a23 71 #define PCI_DEVICE_ID_LOONGSON_GNET 0x7a13 72 #define DWMAC_CORE_MULTICHAN_V1 0x10 /* Loongson custom ID 0x10 */ 73 #define DWMAC_CORE_MULTICHAN_V2 0x12 /* Loongson custom ID 0x12 */ 74 75 struct loongson_data { 76 u32 multichan; 77 u32 loongson_id; 78 struct device *dev; 79 }; 80 81 struct stmmac_pci_info { 82 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); 83 }; 84 85 static void loongson_default_data(struct pci_dev *pdev, 86 struct plat_stmmacenet_data *plat) 87 { 88 struct loongson_data *ld = plat->bsp_priv; 89 90 /* Get bus_id, this can be overwritten later */ 91 plat->bus_id = pci_dev_id(pdev); 92 93 /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 94 plat->clk_csr = STMMAC_CSR_20_35M; 95 plat->has_gmac = 1; 96 plat->force_sf_dma_mode = 1; 97 98 /* Set default value for multicast hash bins */ 99 plat->multicast_filter_bins = 256; 100 101 /* Set default value for unicast filter entries */ 102 plat->unicast_filter_entries = 1; 103 104 /* Set the maxmtu to a default of JUMBO_LEN */ 105 plat->maxmtu = JUMBO_LEN; 106 107 /* Disable Priority config by default */ 108 plat->tx_queues_cfg[0].use_prio = false; 109 plat->rx_queues_cfg[0].use_prio = false; 110 111 /* Disable RX queues routing by default */ 112 plat->rx_queues_cfg[0].pkt_route = 0x0; 113 114 plat->clk_ref_rate = 125000000; 115 plat->clk_ptp_rate = 125000000; 116 117 /* Default to phy auto-detection */ 118 plat->phy_addr = -1; 119 120 plat->dma_cfg->pbl = 32; 121 plat->dma_cfg->pblx8 = true; 122 123 switch (ld->loongson_id) { 124 case DWMAC_CORE_MULTICHAN_V1: 125 ld->multichan = 1; 126 plat->rx_queues_to_use = 8; 127 plat->tx_queues_to_use = 8; 128 129 /* Only channel 0 supports checksum, 130 * so turn off checksum to enable multiple channels. 131 */ 132 for (int i = 1; i < 8; i++) 133 plat->tx_queues_cfg[i].coe_unsupported = 1; 134 135 break; 136 case DWMAC_CORE_MULTICHAN_V2: 137 ld->multichan = 1; 138 plat->rx_queues_to_use = 4; 139 plat->tx_queues_to_use = 4; 140 break; 141 default: 142 ld->multichan = 0; 143 plat->tx_queues_to_use = 1; 144 plat->rx_queues_to_use = 1; 145 break; 146 } 147 } 148 149 static int loongson_gmac_data(struct pci_dev *pdev, 150 struct plat_stmmacenet_data *plat) 151 { 152 loongson_default_data(pdev, plat); 153 154 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 155 156 return 0; 157 } 158 159 static struct stmmac_pci_info loongson_gmac_pci_info = { 160 .setup = loongson_gmac_data, 161 }; 162 163 static void loongson_gnet_fix_speed(void *priv, int speed, unsigned int mode) 164 { 165 struct loongson_data *ld = (struct loongson_data *)priv; 166 struct net_device *ndev = dev_get_drvdata(ld->dev); 167 struct stmmac_priv *ptr = netdev_priv(ndev); 168 169 /* The integrated PHY has a weird problem with switching from the low 170 * speeds to 1000Mbps mode. The speedup procedure requires the PHY-link 171 * re-negotiation. 172 */ 173 if (speed == SPEED_1000) { 174 if (readl(ptr->ioaddr + MAC_CTRL_REG) & 175 GMAC_CONTROL_PS) 176 /* Word around hardware bug, restart autoneg */ 177 phy_restart_aneg(ndev->phydev); 178 } 179 } 180 181 static int loongson_gnet_data(struct pci_dev *pdev, 182 struct plat_stmmacenet_data *plat) 183 { 184 loongson_default_data(pdev, plat); 185 186 plat->phy_interface = PHY_INTERFACE_MODE_GMII; 187 plat->mdio_bus_data->phy_mask = ~(u32)BIT(2); 188 plat->fix_mac_speed = loongson_gnet_fix_speed; 189 190 return 0; 191 } 192 193 static struct stmmac_pci_info loongson_gnet_pci_info = { 194 .setup = loongson_gnet_data, 195 }; 196 197 static void loongson_dwmac_dma_init_channel(struct stmmac_priv *priv, 198 void __iomem *ioaddr, 199 struct stmmac_dma_cfg *dma_cfg, 200 u32 chan) 201 { 202 int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 203 int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 204 u32 value; 205 206 value = readl(ioaddr + DMA_CHAN_BUS_MODE(chan)); 207 208 if (dma_cfg->pblx8) 209 value |= DMA_BUS_MODE_MAXPBL; 210 211 value |= DMA_BUS_MODE_USP; 212 value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK); 213 value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT); 214 value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 215 216 /* Set the Fixed burst mode */ 217 if (dma_cfg->fixed_burst) 218 value |= DMA_BUS_MODE_FB; 219 220 /* Mixed Burst has no effect when fb is set */ 221 if (dma_cfg->mixed_burst) 222 value |= DMA_BUS_MODE_MB; 223 224 if (dma_cfg->atds) 225 value |= DMA_BUS_MODE_ATDS; 226 227 if (dma_cfg->aal) 228 value |= DMA_BUS_MODE_AAL; 229 230 writel(value, ioaddr + DMA_CHAN_BUS_MODE(chan)); 231 232 /* Mask interrupts by writing to CSR7 */ 233 writel(DMA_INTR_DEFAULT_MASK_LOONGSON, ioaddr + 234 DMA_CHAN_INTR_ENA(chan)); 235 } 236 237 static int loongson_dwmac_dma_interrupt(struct stmmac_priv *priv, 238 void __iomem *ioaddr, 239 struct stmmac_extra_stats *x, 240 u32 chan, u32 dir) 241 { 242 struct stmmac_pcpu_stats *stats = this_cpu_ptr(priv->xstats.pcpu_stats); 243 u32 abnor_intr_status; 244 u32 nor_intr_status; 245 u32 fb_intr_status; 246 u32 intr_status; 247 int ret = 0; 248 249 /* read the status register (CSR5) */ 250 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan)); 251 252 if (dir == DMA_DIR_RX) 253 intr_status &= DMA_STATUS_MSK_RX_LOONGSON; 254 else if (dir == DMA_DIR_TX) 255 intr_status &= DMA_STATUS_MSK_TX_LOONGSON; 256 257 nor_intr_status = intr_status & (DMA_STATUS_NIS_TX_LOONGSON | 258 DMA_STATUS_NIS_RX_LOONGSON); 259 abnor_intr_status = intr_status & (DMA_STATUS_AIS_TX_LOONGSON | 260 DMA_STATUS_AIS_RX_LOONGSON); 261 fb_intr_status = intr_status & (DMA_STATUS_FBI_TX_LOONGSON | 262 DMA_STATUS_FBI_RX_LOONGSON); 263 264 /* ABNORMAL interrupts */ 265 if (unlikely(abnor_intr_status)) { 266 if (unlikely(intr_status & DMA_STATUS_UNF)) { 267 ret = tx_hard_error_bump_tc; 268 x->tx_undeflow_irq++; 269 } 270 if (unlikely(intr_status & DMA_STATUS_TJT)) 271 x->tx_jabber_irq++; 272 if (unlikely(intr_status & DMA_STATUS_OVF)) 273 x->rx_overflow_irq++; 274 if (unlikely(intr_status & DMA_STATUS_RU)) 275 x->rx_buf_unav_irq++; 276 if (unlikely(intr_status & DMA_STATUS_RPS)) 277 x->rx_process_stopped_irq++; 278 if (unlikely(intr_status & DMA_STATUS_RWT)) 279 x->rx_watchdog_irq++; 280 if (unlikely(intr_status & DMA_STATUS_ETI)) 281 x->tx_early_irq++; 282 if (unlikely(intr_status & DMA_STATUS_TPS)) { 283 x->tx_process_stopped_irq++; 284 ret = tx_hard_error; 285 } 286 if (unlikely(fb_intr_status)) { 287 x->fatal_bus_error_irq++; 288 ret = tx_hard_error; 289 } 290 } 291 /* TX/RX NORMAL interrupts */ 292 if (likely(nor_intr_status)) { 293 if (likely(intr_status & DMA_STATUS_RI)) { 294 u32 value = readl(ioaddr + DMA_INTR_ENA); 295 /* to schedule NAPI on real RIE event. */ 296 if (likely(value & DMA_INTR_ENA_RIE)) { 297 u64_stats_update_begin(&stats->syncp); 298 u64_stats_inc(&stats->rx_normal_irq_n[chan]); 299 u64_stats_update_end(&stats->syncp); 300 ret |= handle_rx; 301 } 302 } 303 if (likely(intr_status & DMA_STATUS_TI)) { 304 u64_stats_update_begin(&stats->syncp); 305 u64_stats_inc(&stats->tx_normal_irq_n[chan]); 306 u64_stats_update_end(&stats->syncp); 307 ret |= handle_tx; 308 } 309 if (unlikely(intr_status & DMA_STATUS_ERI)) 310 x->rx_early_irq++; 311 } 312 /* Optional hardware blocks, interrupts should be disabled */ 313 if (unlikely(intr_status & 314 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI))) 315 pr_warn("%s: unexpected status %08x\n", __func__, intr_status); 316 317 /* Clear the interrupt by writing a logic 1 to the CSR5[19-0] */ 318 writel((intr_status & 0x7ffff), ioaddr + DMA_CHAN_STATUS(chan)); 319 320 return ret; 321 } 322 323 static struct mac_device_info *loongson_dwmac_setup(void *apriv) 324 { 325 struct stmmac_priv *priv = apriv; 326 struct mac_device_info *mac; 327 struct stmmac_dma_ops *dma; 328 struct loongson_data *ld; 329 struct pci_dev *pdev; 330 331 ld = priv->plat->bsp_priv; 332 pdev = to_pci_dev(priv->device); 333 334 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 335 if (!mac) 336 return NULL; 337 338 dma = devm_kzalloc(priv->device, sizeof(*dma), GFP_KERNEL); 339 if (!dma) 340 return NULL; 341 342 /* The Loongson GMAC and GNET devices are based on the DW GMAC 343 * v3.50a and v3.73a IP-cores. But the HW designers have changed 344 * the GMAC_VERSION.SNPSVER field to the custom 0x10/0x12 value 345 * on the network controllers with the multi-channels feature 346 * available to emphasize the differences: multiple DMA-channels, 347 * AV feature and GMAC_INT_STATUS CSR flags layout. Get back the 348 * original value so the correct HW-interface would be selected. 349 */ 350 if (ld->multichan) { 351 priv->synopsys_id = DWMAC_CORE_3_70; 352 *dma = dwmac1000_dma_ops; 353 dma->init_chan = loongson_dwmac_dma_init_channel; 354 dma->dma_interrupt = loongson_dwmac_dma_interrupt; 355 mac->dma = dma; 356 } 357 358 priv->dev->priv_flags |= IFF_UNICAST_FLT; 359 360 /* Pre-initialize the respective "mac" fields as it's done in 361 * dwmac1000_setup() 362 */ 363 mac->pcsr = priv->ioaddr; 364 mac->multicast_filter_bins = priv->plat->multicast_filter_bins; 365 mac->unicast_filter_entries = priv->plat->unicast_filter_entries; 366 mac->mcast_bits_log2 = 0; 367 368 if (mac->multicast_filter_bins) 369 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins); 370 371 /* Loongson GMAC doesn't support the flow control. Loongson GNET 372 * without multi-channel doesn't support the half-duplex link mode. 373 */ 374 if (pdev->device != PCI_DEVICE_ID_LOONGSON_GNET) { 375 mac->link.caps = MAC_10 | MAC_100 | MAC_1000; 376 } else { 377 if (ld->multichan) 378 mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 379 MAC_10 | MAC_100 | MAC_1000; 380 else 381 mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 382 MAC_10FD | MAC_100FD | MAC_1000FD; 383 } 384 385 mac->link.duplex = GMAC_CONTROL_DM; 386 mac->link.speed10 = GMAC_CONTROL_PS; 387 mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES; 388 mac->link.speed1000 = 0; 389 mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES; 390 mac->mii.addr = GMAC_MII_ADDR; 391 mac->mii.data = GMAC_MII_DATA; 392 mac->mii.addr_shift = 11; 393 mac->mii.addr_mask = 0x0000F800; 394 mac->mii.reg_shift = 6; 395 mac->mii.reg_mask = 0x000007C0; 396 mac->mii.clk_csr_shift = 2; 397 mac->mii.clk_csr_mask = GENMASK(5, 2); 398 399 return mac; 400 } 401 402 static int loongson_dwmac_msi_config(struct pci_dev *pdev, 403 struct plat_stmmacenet_data *plat, 404 struct stmmac_resources *res) 405 { 406 int i, ch_num, ret, vecs; 407 408 ch_num = min(plat->tx_queues_to_use, plat->rx_queues_to_use); 409 410 vecs = roundup_pow_of_two(ch_num * 2 + 1); 411 ret = pci_alloc_irq_vectors(pdev, vecs, vecs, PCI_IRQ_MSI); 412 if (ret < 0) { 413 dev_warn(&pdev->dev, "Failed to allocate MSI IRQs\n"); 414 return ret; 415 } 416 417 res->irq = pci_irq_vector(pdev, 0); 418 419 for (i = 0; i < ch_num; i++) { 420 res->rx_irq[ch_num - 1 - i] = pci_irq_vector(pdev, 1 + i * 2); 421 } 422 423 for (i = 0; i < ch_num; i++) { 424 res->tx_irq[ch_num - 1 - i] = pci_irq_vector(pdev, 2 + i * 2); 425 } 426 427 plat->flags |= STMMAC_FLAG_MULTI_MSI_EN; 428 429 return 0; 430 } 431 432 static void loongson_dwmac_msi_clear(struct pci_dev *pdev) 433 { 434 pci_free_irq_vectors(pdev); 435 } 436 437 static int loongson_dwmac_dt_config(struct pci_dev *pdev, 438 struct plat_stmmacenet_data *plat, 439 struct stmmac_resources *res) 440 { 441 struct device_node *np = dev_of_node(&pdev->dev); 442 int ret; 443 444 plat->mdio_node = of_get_child_by_name(np, "mdio"); 445 if (plat->mdio_node) { 446 dev_info(&pdev->dev, "Found MDIO subnode\n"); 447 plat->mdio_bus_data->needs_reset = true; 448 } 449 450 ret = of_alias_get_id(np, "ethernet"); 451 if (ret >= 0) 452 plat->bus_id = ret; 453 454 res->irq = of_irq_get_byname(np, "macirq"); 455 if (res->irq < 0) { 456 dev_err(&pdev->dev, "IRQ macirq not found\n"); 457 ret = -ENODEV; 458 goto err_put_node; 459 } 460 461 res->wol_irq = of_irq_get_byname(np, "eth_wake_irq"); 462 if (res->wol_irq < 0) { 463 dev_info(&pdev->dev, 464 "IRQ eth_wake_irq not found, using macirq\n"); 465 res->wol_irq = res->irq; 466 } 467 468 res->lpi_irq = of_irq_get_byname(np, "eth_lpi"); 469 if (res->lpi_irq < 0) { 470 dev_err(&pdev->dev, "IRQ eth_lpi not found\n"); 471 ret = -ENODEV; 472 goto err_put_node; 473 } 474 475 ret = device_get_phy_mode(&pdev->dev); 476 if (ret < 0) { 477 dev_err(&pdev->dev, "phy_mode not found\n"); 478 ret = -ENODEV; 479 goto err_put_node; 480 } 481 482 plat->phy_interface = ret; 483 484 return 0; 485 486 err_put_node: 487 of_node_put(plat->mdio_node); 488 489 return ret; 490 } 491 492 static void loongson_dwmac_dt_clear(struct pci_dev *pdev, 493 struct plat_stmmacenet_data *plat) 494 { 495 of_node_put(plat->mdio_node); 496 } 497 498 static int loongson_dwmac_acpi_config(struct pci_dev *pdev, 499 struct plat_stmmacenet_data *plat, 500 struct stmmac_resources *res) 501 { 502 if (!pdev->irq) 503 return -EINVAL; 504 505 res->irq = pdev->irq; 506 507 return 0; 508 } 509 510 /* Loongson's DWMAC device may take nearly two seconds to complete DMA reset */ 511 static int loongson_dwmac_fix_reset(struct stmmac_priv *priv, void __iomem *ioaddr) 512 { 513 u32 value = readl(ioaddr + DMA_BUS_MODE); 514 515 if (value & DMA_BUS_MODE_SFT_RESET) { 516 netdev_err(priv->dev, "the PHY clock is missing\n"); 517 return -EINVAL; 518 } 519 520 value |= DMA_BUS_MODE_SFT_RESET; 521 writel(value, ioaddr + DMA_BUS_MODE); 522 523 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, 524 !(value & DMA_BUS_MODE_SFT_RESET), 525 10000, 2000000); 526 } 527 528 static int loongson_dwmac_suspend(struct device *dev, void *bsp_priv) 529 { 530 struct pci_dev *pdev = to_pci_dev(dev); 531 int ret; 532 533 ret = pci_save_state(pdev); 534 if (ret) 535 return ret; 536 537 pci_disable_device(pdev); 538 pci_wake_from_d3(pdev, true); 539 return 0; 540 } 541 542 static int loongson_dwmac_resume(struct device *dev, void *bsp_priv) 543 { 544 struct pci_dev *pdev = to_pci_dev(dev); 545 int ret; 546 547 pci_restore_state(pdev); 548 pci_set_power_state(pdev, PCI_D0); 549 550 ret = pci_enable_device(pdev); 551 if (ret) 552 return ret; 553 554 pci_set_master(pdev); 555 556 return 0; 557 } 558 559 static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id *id) 560 { 561 struct plat_stmmacenet_data *plat; 562 struct stmmac_resources res = {}; 563 struct stmmac_pci_info *info; 564 struct loongson_data *ld; 565 int ret; 566 567 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 568 if (!plat) 569 return -ENOMEM; 570 571 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, 572 sizeof(*plat->mdio_bus_data), 573 GFP_KERNEL); 574 if (!plat->mdio_bus_data) 575 return -ENOMEM; 576 577 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), GFP_KERNEL); 578 if (!plat->dma_cfg) 579 return -ENOMEM; 580 581 ld = devm_kzalloc(&pdev->dev, sizeof(*ld), GFP_KERNEL); 582 if (!ld) 583 return -ENOMEM; 584 585 /* Enable pci device */ 586 ret = pci_enable_device(pdev); 587 if (ret) { 588 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", __func__); 589 return ret; 590 } 591 592 pci_set_master(pdev); 593 594 /* Get the base address of device */ 595 res.addr = pcim_iomap_region(pdev, 0, DRIVER_NAME); 596 ret = PTR_ERR_OR_ZERO(res.addr); 597 if (ret) 598 goto err_disable_device; 599 600 plat->bsp_priv = ld; 601 plat->setup = loongson_dwmac_setup; 602 plat->fix_soc_reset = loongson_dwmac_fix_reset; 603 plat->suspend = loongson_dwmac_suspend; 604 plat->resume = loongson_dwmac_resume; 605 ld->dev = &pdev->dev; 606 ld->loongson_id = readl(res.addr + GMAC_VERSION) & 0xff; 607 608 info = (struct stmmac_pci_info *)id->driver_data; 609 ret = info->setup(pdev, plat); 610 if (ret) 611 goto err_disable_device; 612 613 plat->tx_fifo_size = SZ_16K * plat->tx_queues_to_use; 614 plat->rx_fifo_size = SZ_16K * plat->rx_queues_to_use; 615 616 if (dev_of_node(&pdev->dev)) 617 ret = loongson_dwmac_dt_config(pdev, plat, &res); 618 else 619 ret = loongson_dwmac_acpi_config(pdev, plat, &res); 620 if (ret) 621 goto err_disable_device; 622 623 /* Use the common MAC IRQ if per-channel MSIs allocation failed */ 624 if (ld->multichan) 625 loongson_dwmac_msi_config(pdev, plat, &res); 626 627 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); 628 if (ret) 629 goto err_plat_clear; 630 631 return 0; 632 633 err_plat_clear: 634 if (dev_of_node(&pdev->dev)) 635 loongson_dwmac_dt_clear(pdev, plat); 636 if (ld->multichan) 637 loongson_dwmac_msi_clear(pdev); 638 err_disable_device: 639 pci_disable_device(pdev); 640 return ret; 641 } 642 643 static void loongson_dwmac_remove(struct pci_dev *pdev) 644 { 645 struct net_device *ndev = dev_get_drvdata(&pdev->dev); 646 struct stmmac_priv *priv = netdev_priv(ndev); 647 struct loongson_data *ld; 648 649 ld = priv->plat->bsp_priv; 650 stmmac_dvr_remove(&pdev->dev); 651 652 if (dev_of_node(&pdev->dev)) 653 loongson_dwmac_dt_clear(pdev, priv->plat); 654 655 if (ld->multichan) 656 loongson_dwmac_msi_clear(pdev); 657 658 pci_disable_device(pdev); 659 } 660 661 static const struct pci_device_id loongson_dwmac_id_table[] = { 662 { PCI_DEVICE_DATA(LOONGSON, GMAC1, &loongson_gmac_pci_info) }, 663 { PCI_DEVICE_DATA(LOONGSON, GMAC2, &loongson_gmac_pci_info) }, 664 { PCI_DEVICE_DATA(LOONGSON, GNET, &loongson_gnet_pci_info) }, 665 {} 666 }; 667 MODULE_DEVICE_TABLE(pci, loongson_dwmac_id_table); 668 669 static struct pci_driver loongson_dwmac_driver = { 670 .name = DRIVER_NAME, 671 .id_table = loongson_dwmac_id_table, 672 .probe = loongson_dwmac_probe, 673 .remove = loongson_dwmac_remove, 674 .driver = { 675 .pm = &stmmac_simple_pm_ops, 676 }, 677 }; 678 679 module_pci_driver(loongson_dwmac_driver); 680 681 MODULE_DESCRIPTION("Loongson DWMAC PCI driver"); 682 MODULE_AUTHOR("Qing Zhang <zhangqing@loongson.cn>"); 683 MODULE_AUTHOR("Yanteng Si <siyanteng@loongson.cn>"); 684 MODULE_LICENSE("GPL v2"); 685