1 /* 2 * Qualcomm Atheros IPQ806x GMAC glue layer 3 * 4 * Copyright (C) 2015 The Linux Foundation 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <linux/device.h> 20 #include <linux/platform_device.h> 21 #include <linux/phy.h> 22 #include <linux/regmap.h> 23 #include <linux/clk.h> 24 #include <linux/reset.h> 25 #include <linux/of_net.h> 26 #include <linux/mfd/syscon.h> 27 #include <linux/stmmac.h> 28 #include <linux/of_mdio.h> 29 #include <linux/module.h> 30 #include <linux/sys_soc.h> 31 #include <linux/bitfield.h> 32 33 #include "stmmac_platform.h" 34 35 #define NSS_COMMON_CLK_GATE 0x8 36 #define NSS_COMMON_CLK_GATE_PTP_EN(x) BIT(0x10 + x) 37 #define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x) BIT(0x9 + (x * 2)) 38 #define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x) BIT(0x8 + (x * 2)) 39 #define NSS_COMMON_CLK_GATE_GMII_RX_EN(x) BIT(0x4 + x) 40 #define NSS_COMMON_CLK_GATE_GMII_TX_EN(x) BIT(0x0 + x) 41 42 #define NSS_COMMON_CLK_DIV0 0xC 43 #define NSS_COMMON_CLK_DIV_OFFSET(x) (x * 8) 44 #define NSS_COMMON_CLK_DIV_MASK 0x7f 45 46 #define NSS_COMMON_CLK_SRC_CTRL 0x14 47 #define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (x) 48 /* Mode is coded on 1 bit but is different depending on the MAC ID: 49 * MAC0: QSGMII=0 RGMII=1 50 * MAC1: QSGMII=0 SGMII=0 RGMII=1 51 * MAC2 & MAC3: QSGMII=0 SGMII=1 52 */ 53 #define NSS_COMMON_CLK_SRC_CTRL_RGMII(x) 1 54 #define NSS_COMMON_CLK_SRC_CTRL_SGMII(x) ((x >= 2) ? 1 : 0) 55 56 #define NSS_COMMON_GMAC_CTL(x) (0x30 + (x * 4)) 57 #define NSS_COMMON_GMAC_CTL_CSYS_REQ BIT(19) 58 #define NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL BIT(16) 59 #define NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET 8 60 #define NSS_COMMON_GMAC_CTL_IFG_OFFSET 0 61 62 #define NSS_COMMON_CLK_DIV_RGMII_1000 1 63 #define NSS_COMMON_CLK_DIV_RGMII_100 9 64 #define NSS_COMMON_CLK_DIV_RGMII_10 99 65 #define NSS_COMMON_CLK_DIV_SGMII_1000 0 66 #define NSS_COMMON_CLK_DIV_SGMII_100 4 67 #define NSS_COMMON_CLK_DIV_SGMII_10 49 68 69 #define QSGMII_PCS_ALL_CH_CTL 0x80 70 #define QSGMII_PCS_CH_SPEED_FORCE BIT(1) 71 #define QSGMII_PCS_CH_SPEED_10 0x0 72 #define QSGMII_PCS_CH_SPEED_100 BIT(2) 73 #define QSGMII_PCS_CH_SPEED_1000 BIT(3) 74 #define QSGMII_PCS_CH_SPEED_MASK (QSGMII_PCS_CH_SPEED_FORCE | \ 75 QSGMII_PCS_CH_SPEED_10 | \ 76 QSGMII_PCS_CH_SPEED_100 | \ 77 QSGMII_PCS_CH_SPEED_1000) 78 #define QSGMII_PCS_CH_SPEED_SHIFT(x) ((x) * 4) 79 80 #define QSGMII_PCS_CAL_LCKDT_CTL 0x120 81 #define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19) 82 83 /* Only GMAC1/2/3 support SGMII and their CTL register are not contiguous */ 84 #define QSGMII_PHY_SGMII_CTL(x) ((x == 1) ? 0x134 : \ 85 (0x13c + (4 * (x - 2)))) 86 #define QSGMII_PHY_CDR_EN BIT(0) 87 #define QSGMII_PHY_RX_FRONT_EN BIT(1) 88 #define QSGMII_PHY_RX_SIGNAL_DETECT_EN BIT(2) 89 #define QSGMII_PHY_TX_DRIVER_EN BIT(3) 90 #define QSGMII_PHY_QSGMII_EN BIT(7) 91 #define QSGMII_PHY_DEEMPHASIS_LVL_MASK GENMASK(11, 10) 92 #define QSGMII_PHY_DEEMPHASIS_LVL(x) FIELD_PREP(QSGMII_PHY_DEEMPHASIS_LVL_MASK, (x)) 93 #define QSGMII_PHY_PHASE_LOOP_GAIN_MASK GENMASK(14, 12) 94 #define QSGMII_PHY_PHASE_LOOP_GAIN(x) FIELD_PREP(QSGMII_PHY_PHASE_LOOP_GAIN_MASK, (x)) 95 #define QSGMII_PHY_RX_DC_BIAS_MASK GENMASK(19, 18) 96 #define QSGMII_PHY_RX_DC_BIAS(x) FIELD_PREP(QSGMII_PHY_RX_DC_BIAS_MASK, (x)) 97 #define QSGMII_PHY_RX_INPUT_EQU_MASK GENMASK(21, 20) 98 #define QSGMII_PHY_RX_INPUT_EQU(x) FIELD_PREP(QSGMII_PHY_RX_INPUT_EQU_MASK, (x)) 99 #define QSGMII_PHY_CDR_PI_SLEW_MASK GENMASK(23, 22) 100 #define QSGMII_PHY_CDR_PI_SLEW(x) FIELD_PREP(QSGMII_PHY_CDR_PI_SLEW_MASK, (x)) 101 #define QSGMII_PHY_TX_SLEW_MASK GENMASK(27, 26) 102 #define QSGMII_PHY_TX_SLEW(x) FIELD_PREP(QSGMII_PHY_TX_SLEW_MASK, (x)) 103 #define QSGMII_PHY_TX_DRV_AMP_MASK GENMASK(31, 28) 104 #define QSGMII_PHY_TX_DRV_AMP(x) FIELD_PREP(QSGMII_PHY_TX_DRV_AMP_MASK, (x)) 105 106 struct ipq806x_gmac { 107 struct platform_device *pdev; 108 struct regmap *nss_common; 109 struct regmap *qsgmii_csr; 110 uint32_t id; 111 struct clk *core_clk; 112 phy_interface_t phy_mode; 113 }; 114 115 static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, int speed) 116 { 117 struct device *dev = &gmac->pdev->dev; 118 int div; 119 120 switch (speed) { 121 case SPEED_1000: 122 div = NSS_COMMON_CLK_DIV_SGMII_1000; 123 break; 124 125 case SPEED_100: 126 div = NSS_COMMON_CLK_DIV_SGMII_100; 127 break; 128 129 case SPEED_10: 130 div = NSS_COMMON_CLK_DIV_SGMII_10; 131 break; 132 133 default: 134 dev_err(dev, "Speed %dMbps not supported in SGMII\n", speed); 135 return -EINVAL; 136 } 137 138 return div; 139 } 140 141 static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, int speed) 142 { 143 struct device *dev = &gmac->pdev->dev; 144 int div; 145 146 switch (speed) { 147 case SPEED_1000: 148 div = NSS_COMMON_CLK_DIV_RGMII_1000; 149 break; 150 151 case SPEED_100: 152 div = NSS_COMMON_CLK_DIV_RGMII_100; 153 break; 154 155 case SPEED_10: 156 div = NSS_COMMON_CLK_DIV_RGMII_10; 157 break; 158 159 default: 160 dev_err(dev, "Speed %dMbps not supported in RGMII\n", speed); 161 return -EINVAL; 162 } 163 164 return div; 165 } 166 167 static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, int speed) 168 { 169 uint32_t clk_bits, val; 170 int div; 171 172 switch (gmac->phy_mode) { 173 case PHY_INTERFACE_MODE_RGMII: 174 case PHY_INTERFACE_MODE_RGMII_ID: 175 case PHY_INTERFACE_MODE_RGMII_RXID: 176 case PHY_INTERFACE_MODE_RGMII_TXID: 177 div = get_clk_div_rgmii(gmac, speed); 178 clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) | 179 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id); 180 break; 181 182 case PHY_INTERFACE_MODE_SGMII: 183 div = get_clk_div_sgmii(gmac, speed); 184 clk_bits = NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) | 185 NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id); 186 break; 187 188 default: 189 dev_err(&gmac->pdev->dev, "Unsupported PHY mode: \"%s\"\n", 190 phy_modes(gmac->phy_mode)); 191 return -EINVAL; 192 } 193 194 /* Disable the clocks */ 195 regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val); 196 val &= ~clk_bits; 197 regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); 198 199 /* Set the divider */ 200 regmap_read(gmac->nss_common, NSS_COMMON_CLK_DIV0, &val); 201 val &= ~(NSS_COMMON_CLK_DIV_MASK 202 << NSS_COMMON_CLK_DIV_OFFSET(gmac->id)); 203 val |= div << NSS_COMMON_CLK_DIV_OFFSET(gmac->id); 204 regmap_write(gmac->nss_common, NSS_COMMON_CLK_DIV0, val); 205 206 /* Enable the clock back */ 207 regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val); 208 val |= clk_bits; 209 regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); 210 211 return 0; 212 } 213 214 static int ipq806x_gmac_of_parse(struct ipq806x_gmac *gmac) 215 { 216 struct device *dev = &gmac->pdev->dev; 217 int ret; 218 219 ret = of_get_phy_mode(dev->of_node, &gmac->phy_mode); 220 if (ret) { 221 dev_err(dev, "missing phy mode property\n"); 222 return -EINVAL; 223 } 224 225 if (of_property_read_u32(dev->of_node, "qcom,id", &gmac->id) < 0) { 226 dev_err(dev, "missing qcom id property\n"); 227 return -EINVAL; 228 } 229 230 /* The GMACs are called 1 to 4 in the documentation, but to simplify the 231 * code and keep it consistent with the Linux convention, we'll number 232 * them from 0 to 3 here. 233 */ 234 if (gmac->id > 3) { 235 dev_err(dev, "invalid gmac id\n"); 236 return -EINVAL; 237 } 238 239 gmac->core_clk = devm_clk_get(dev, "stmmaceth"); 240 if (IS_ERR(gmac->core_clk)) { 241 dev_err(dev, "missing stmmaceth clk property\n"); 242 return PTR_ERR(gmac->core_clk); 243 } 244 clk_set_rate(gmac->core_clk, 266000000); 245 246 /* Setup the register map for the nss common registers */ 247 gmac->nss_common = syscon_regmap_lookup_by_phandle(dev->of_node, 248 "qcom,nss-common"); 249 if (IS_ERR(gmac->nss_common)) { 250 dev_err(dev, "missing nss-common node\n"); 251 return PTR_ERR(gmac->nss_common); 252 } 253 254 /* Setup the register map for the qsgmii csr registers */ 255 gmac->qsgmii_csr = syscon_regmap_lookup_by_phandle(dev->of_node, 256 "qcom,qsgmii-csr"); 257 if (IS_ERR(gmac->qsgmii_csr)) 258 dev_err(dev, "missing qsgmii-csr node\n"); 259 260 return PTR_ERR_OR_ZERO(gmac->qsgmii_csr); 261 } 262 263 static int ipq806x_gmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, 264 phy_interface_t interface, int speed) 265 { 266 struct ipq806x_gmac *gmac = bsp_priv; 267 268 return ipq806x_gmac_set_speed(gmac, speed); 269 } 270 271 static int 272 ipq806x_gmac_configure_qsgmii_pcs_speed(struct ipq806x_gmac *gmac) 273 { 274 struct platform_device *pdev = gmac->pdev; 275 struct device *dev = &pdev->dev; 276 struct device_node *dn; 277 int link_speed; 278 int val = 0; 279 int ret; 280 281 /* Some bootloader may apply wrong configuration and cause 282 * not functioning port. If fixed link is not set, 283 * reset the force speed bit. 284 */ 285 if (!of_phy_is_fixed_link(pdev->dev.of_node)) 286 goto write; 287 288 dn = of_get_child_by_name(pdev->dev.of_node, "fixed-link"); 289 ret = of_property_read_u32(dn, "speed", &link_speed); 290 of_node_put(dn); 291 if (ret) { 292 dev_err(dev, "found fixed-link node with no speed"); 293 return ret; 294 } 295 296 val = QSGMII_PCS_CH_SPEED_FORCE; 297 298 switch (link_speed) { 299 case SPEED_1000: 300 val |= QSGMII_PCS_CH_SPEED_1000; 301 break; 302 case SPEED_100: 303 val |= QSGMII_PCS_CH_SPEED_100; 304 break; 305 case SPEED_10: 306 val |= QSGMII_PCS_CH_SPEED_10; 307 break; 308 } 309 310 write: 311 regmap_update_bits(gmac->qsgmii_csr, QSGMII_PCS_ALL_CH_CTL, 312 QSGMII_PCS_CH_SPEED_MASK << 313 QSGMII_PCS_CH_SPEED_SHIFT(gmac->id), 314 val << 315 QSGMII_PCS_CH_SPEED_SHIFT(gmac->id)); 316 317 return 0; 318 } 319 320 static const struct soc_device_attribute ipq806x_gmac_soc_v1[] = { 321 { 322 .revision = "1.*", 323 }, 324 { 325 /* sentinel */ 326 } 327 }; 328 329 static int 330 ipq806x_gmac_configure_qsgmii_params(struct ipq806x_gmac *gmac) 331 { 332 struct platform_device *pdev = gmac->pdev; 333 const struct soc_device_attribute *soc; 334 struct device *dev = &pdev->dev; 335 u32 qsgmii_param; 336 337 switch (gmac->id) { 338 case 1: 339 soc = soc_device_match(ipq806x_gmac_soc_v1); 340 341 if (soc) 342 qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xc) | 343 QSGMII_PHY_TX_SLEW(0x2) | 344 QSGMII_PHY_DEEMPHASIS_LVL(0x2); 345 else 346 qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xd) | 347 QSGMII_PHY_TX_SLEW(0x0) | 348 QSGMII_PHY_DEEMPHASIS_LVL(0x0); 349 350 qsgmii_param |= QSGMII_PHY_RX_DC_BIAS(0x2); 351 break; 352 case 2: 353 case 3: 354 qsgmii_param = QSGMII_PHY_RX_DC_BIAS(0x3) | 355 QSGMII_PHY_TX_DRV_AMP(0xc); 356 break; 357 default: /* gmac 0 can't be set in SGMII mode */ 358 dev_err(dev, "gmac id %d can't be in SGMII mode", gmac->id); 359 return -EINVAL; 360 } 361 362 /* Common params across all gmac id */ 363 qsgmii_param |= QSGMII_PHY_CDR_EN | 364 QSGMII_PHY_RX_FRONT_EN | 365 QSGMII_PHY_RX_SIGNAL_DETECT_EN | 366 QSGMII_PHY_TX_DRIVER_EN | 367 QSGMII_PHY_QSGMII_EN | 368 QSGMII_PHY_PHASE_LOOP_GAIN(0x4) | 369 QSGMII_PHY_RX_INPUT_EQU(0x1) | 370 QSGMII_PHY_CDR_PI_SLEW(0x2); 371 372 regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id), 373 qsgmii_param); 374 375 return 0; 376 } 377 378 static int ipq806x_gmac_probe(struct platform_device *pdev) 379 { 380 struct plat_stmmacenet_data *plat_dat; 381 struct stmmac_resources stmmac_res; 382 struct device *dev = &pdev->dev; 383 struct ipq806x_gmac *gmac; 384 int val; 385 int err; 386 387 val = stmmac_get_platform_resources(pdev, &stmmac_res); 388 if (val) 389 return val; 390 391 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 392 if (IS_ERR(plat_dat)) 393 return PTR_ERR(plat_dat); 394 395 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); 396 if (!gmac) 397 return -ENOMEM; 398 399 gmac->pdev = pdev; 400 401 err = ipq806x_gmac_of_parse(gmac); 402 if (err) { 403 dev_err(dev, "device tree parsing error\n"); 404 return err; 405 } 406 407 regmap_write(gmac->qsgmii_csr, QSGMII_PCS_CAL_LCKDT_CTL, 408 QSGMII_PCS_CAL_LCKDT_CTL_RST); 409 410 /* Inter frame gap is set to 12 */ 411 val = 12 << NSS_COMMON_GMAC_CTL_IFG_OFFSET | 412 12 << NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET; 413 /* We also initiate an AXI low power exit request */ 414 val |= NSS_COMMON_GMAC_CTL_CSYS_REQ; 415 switch (gmac->phy_mode) { 416 case PHY_INTERFACE_MODE_RGMII: 417 case PHY_INTERFACE_MODE_RGMII_ID: 418 case PHY_INTERFACE_MODE_RGMII_RXID: 419 case PHY_INTERFACE_MODE_RGMII_TXID: 420 val |= NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL; 421 break; 422 case PHY_INTERFACE_MODE_SGMII: 423 val &= ~NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL; 424 break; 425 default: 426 goto err_unsupported_phy; 427 } 428 regmap_write(gmac->nss_common, NSS_COMMON_GMAC_CTL(gmac->id), val); 429 430 /* Configure the clock src according to the mode */ 431 regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val); 432 val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id)); 433 switch (gmac->phy_mode) { 434 case PHY_INTERFACE_MODE_RGMII: 435 case PHY_INTERFACE_MODE_RGMII_ID: 436 case PHY_INTERFACE_MODE_RGMII_RXID: 437 case PHY_INTERFACE_MODE_RGMII_TXID: 438 val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) << 439 NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id); 440 break; 441 case PHY_INTERFACE_MODE_SGMII: 442 val |= NSS_COMMON_CLK_SRC_CTRL_SGMII(gmac->id) << 443 NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id); 444 break; 445 default: 446 goto err_unsupported_phy; 447 } 448 regmap_write(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val); 449 450 /* Enable PTP clock */ 451 regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val); 452 val |= NSS_COMMON_CLK_GATE_PTP_EN(gmac->id); 453 switch (gmac->phy_mode) { 454 case PHY_INTERFACE_MODE_RGMII: 455 case PHY_INTERFACE_MODE_RGMII_ID: 456 case PHY_INTERFACE_MODE_RGMII_RXID: 457 case PHY_INTERFACE_MODE_RGMII_TXID: 458 val |= NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) | 459 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id); 460 break; 461 case PHY_INTERFACE_MODE_SGMII: 462 val |= NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) | 463 NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id); 464 break; 465 default: 466 goto err_unsupported_phy; 467 } 468 regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); 469 470 if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) { 471 err = ipq806x_gmac_configure_qsgmii_params(gmac); 472 if (err) 473 return err; 474 475 err = ipq806x_gmac_configure_qsgmii_pcs_speed(gmac); 476 if (err) 477 return err; 478 } 479 480 plat_dat->has_gmac = true; 481 plat_dat->bsp_priv = gmac; 482 plat_dat->set_clk_tx_rate = ipq806x_gmac_set_clk_tx_rate; 483 plat_dat->multicast_filter_bins = 0; 484 plat_dat->tx_fifo_size = 8192; 485 plat_dat->rx_fifo_size = 8192; 486 487 return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 488 489 err_unsupported_phy: 490 dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n", 491 phy_modes(gmac->phy_mode)); 492 return -EINVAL; 493 } 494 495 static const struct of_device_id ipq806x_gmac_dwmac_match[] = { 496 { .compatible = "qcom,ipq806x-gmac" }, 497 { } 498 }; 499 MODULE_DEVICE_TABLE(of, ipq806x_gmac_dwmac_match); 500 501 static struct platform_driver ipq806x_gmac_dwmac_driver = { 502 .probe = ipq806x_gmac_probe, 503 .remove = stmmac_pltfr_remove, 504 .driver = { 505 .name = "ipq806x-gmac-dwmac", 506 .pm = &stmmac_pltfr_pm_ops, 507 .of_match_table = ipq806x_gmac_dwmac_match, 508 }, 509 }; 510 module_platform_driver(ipq806x_gmac_dwmac_driver); 511 512 MODULE_AUTHOR("Mathieu Olivari <mathieu@codeaurora.org>"); 513 MODULE_DESCRIPTION("Qualcomm Atheros IPQ806x DWMAC specific glue layer"); 514 MODULE_LICENSE("Dual BSD/GPL"); 515