1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2020, Intel Corporation 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/pci.h> 7 #include <linux/dmi.h> 8 #include "dwmac-intel.h" 9 #include "dwmac4.h" 10 #include "stmmac.h" 11 #include "stmmac_ptp.h" 12 13 struct intel_priv_data { 14 int mdio_adhoc_addr; /* mdio address for serdes & etc */ 15 unsigned long crossts_adj; 16 bool is_pse; 17 }; 18 19 /* This struct is used to associate PCI Function of MAC controller on a board, 20 * discovered via DMI, with the address of PHY connected to the MAC. The 21 * negative value of the address means that MAC controller is not connected 22 * with PHY. 23 */ 24 struct stmmac_pci_func_data { 25 unsigned int func; 26 int phy_addr; 27 }; 28 29 struct stmmac_pci_dmi_data { 30 const struct stmmac_pci_func_data *func; 31 size_t nfuncs; 32 }; 33 34 struct stmmac_pci_info { 35 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); 36 }; 37 38 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, 39 const struct dmi_system_id *dmi_list) 40 { 41 const struct stmmac_pci_func_data *func_data; 42 const struct stmmac_pci_dmi_data *dmi_data; 43 const struct dmi_system_id *dmi_id; 44 int func = PCI_FUNC(pdev->devfn); 45 size_t n; 46 47 dmi_id = dmi_first_match(dmi_list); 48 if (!dmi_id) 49 return -ENODEV; 50 51 dmi_data = dmi_id->driver_data; 52 func_data = dmi_data->func; 53 54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) 55 if (func_data->func == func) 56 return func_data->phy_addr; 57 58 return -ENODEV; 59 } 60 61 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr, 62 int phyreg, u32 mask, u32 val) 63 { 64 unsigned int retries = 10; 65 int val_rd; 66 67 do { 68 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg); 69 if ((val_rd & mask) == (val & mask)) 70 return 0; 71 udelay(POLL_DELAY_US); 72 } while (--retries); 73 74 return -ETIMEDOUT; 75 } 76 77 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) 78 { 79 struct intel_priv_data *intel_priv = priv_data; 80 struct stmmac_priv *priv = netdev_priv(ndev); 81 int serdes_phy_addr = 0; 82 u32 data = 0; 83 84 if (!intel_priv->mdio_adhoc_addr) 85 return 0; 86 87 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 88 89 /* Set the serdes rate and the PCLK rate */ 90 data = mdiobus_read(priv->mii, serdes_phy_addr, 91 SERDES_GCR0); 92 93 data &= ~SERDES_RATE_MASK; 94 data &= ~SERDES_PCLK_MASK; 95 96 if (priv->plat->max_speed == 2500) 97 data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT | 98 SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT; 99 else 100 data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT | 101 SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT; 102 103 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 104 105 /* assert clk_req */ 106 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 107 data |= SERDES_PLL_CLK; 108 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 109 110 /* check for clk_ack assertion */ 111 data = serdes_status_poll(priv, serdes_phy_addr, 112 SERDES_GSR0, 113 SERDES_PLL_CLK, 114 SERDES_PLL_CLK); 115 116 if (data) { 117 dev_err(priv->device, "Serdes PLL clk request timeout\n"); 118 return data; 119 } 120 121 /* assert lane reset */ 122 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 123 data |= SERDES_RST; 124 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 125 126 /* check for assert lane reset reflection */ 127 data = serdes_status_poll(priv, serdes_phy_addr, 128 SERDES_GSR0, 129 SERDES_RST, 130 SERDES_RST); 131 132 if (data) { 133 dev_err(priv->device, "Serdes assert lane reset timeout\n"); 134 return data; 135 } 136 137 /* move power state to P0 */ 138 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 139 140 data &= ~SERDES_PWR_ST_MASK; 141 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT; 142 143 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 144 145 /* Check for P0 state */ 146 data = serdes_status_poll(priv, serdes_phy_addr, 147 SERDES_GSR0, 148 SERDES_PWR_ST_MASK, 149 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT); 150 151 if (data) { 152 dev_err(priv->device, "Serdes power state P0 timeout.\n"); 153 return data; 154 } 155 156 /* PSE only - ungate SGMII PHY Rx Clock */ 157 if (intel_priv->is_pse) 158 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, 159 0, SERDES_PHY_RX_CLK); 160 161 return 0; 162 } 163 164 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) 165 { 166 struct intel_priv_data *intel_priv = intel_data; 167 struct stmmac_priv *priv = netdev_priv(ndev); 168 int serdes_phy_addr = 0; 169 u32 data = 0; 170 171 if (!intel_priv->mdio_adhoc_addr) 172 return; 173 174 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 175 176 /* PSE only - gate SGMII PHY Rx Clock */ 177 if (intel_priv->is_pse) 178 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, 179 SERDES_PHY_RX_CLK, 0); 180 181 /* move power state to P3 */ 182 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 183 184 data &= ~SERDES_PWR_ST_MASK; 185 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT; 186 187 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 188 189 /* Check for P3 state */ 190 data = serdes_status_poll(priv, serdes_phy_addr, 191 SERDES_GSR0, 192 SERDES_PWR_ST_MASK, 193 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT); 194 195 if (data) { 196 dev_err(priv->device, "Serdes power state P3 timeout\n"); 197 return; 198 } 199 200 /* de-assert clk_req */ 201 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 202 data &= ~SERDES_PLL_CLK; 203 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 204 205 /* check for clk_ack de-assert */ 206 data = serdes_status_poll(priv, serdes_phy_addr, 207 SERDES_GSR0, 208 SERDES_PLL_CLK, 209 (u32)~SERDES_PLL_CLK); 210 211 if (data) { 212 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n"); 213 return; 214 } 215 216 /* de-assert lane reset */ 217 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 218 data &= ~SERDES_RST; 219 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 220 221 /* check for de-assert lane reset reflection */ 222 data = serdes_status_poll(priv, serdes_phy_addr, 223 SERDES_GSR0, 224 SERDES_RST, 225 (u32)~SERDES_RST); 226 227 if (data) { 228 dev_err(priv->device, "Serdes de-assert lane reset timeout\n"); 229 return; 230 } 231 } 232 233 static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data) 234 { 235 struct intel_priv_data *intel_priv = intel_data; 236 struct stmmac_priv *priv = netdev_priv(ndev); 237 int serdes_phy_addr = 0; 238 u32 data = 0; 239 240 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 241 242 /* Determine the link speed mode: 2.5Gbps/1Gbps */ 243 data = mdiobus_read(priv->mii, serdes_phy_addr, 244 SERDES_GCR); 245 246 if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) == 247 SERDES_LINK_MODE_2G5) { 248 dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n"); 249 priv->plat->max_speed = 2500; 250 priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX; 251 priv->plat->mdio_bus_data->default_an_inband = false; 252 } else { 253 priv->plat->max_speed = 1000; 254 } 255 } 256 257 /* Program PTP Clock Frequency for different variant of 258 * Intel mGBE that has slightly different GPO mapping 259 */ 260 static void intel_mgbe_ptp_clk_freq_config(struct stmmac_priv *priv) 261 { 262 struct intel_priv_data *intel_priv; 263 u32 gpio_value; 264 265 intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv; 266 267 gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS); 268 269 if (intel_priv->is_pse) { 270 /* For PSE GbE, use 200MHz */ 271 gpio_value &= ~PSE_PTP_CLK_FREQ_MASK; 272 gpio_value |= PSE_PTP_CLK_FREQ_200MHZ; 273 } else { 274 /* For PCH GbE, use 200MHz */ 275 gpio_value &= ~PCH_PTP_CLK_FREQ_MASK; 276 gpio_value |= PCH_PTP_CLK_FREQ_200MHZ; 277 } 278 279 writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS); 280 } 281 282 static void get_arttime(struct mii_bus *mii, int intel_adhoc_addr, 283 u64 *art_time) 284 { 285 u64 ns; 286 287 ns = mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE3); 288 ns <<= GMAC4_ART_TIME_SHIFT; 289 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE2); 290 ns <<= GMAC4_ART_TIME_SHIFT; 291 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE1); 292 ns <<= GMAC4_ART_TIME_SHIFT; 293 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE0); 294 295 *art_time = ns; 296 } 297 298 static int stmmac_cross_ts_isr(struct stmmac_priv *priv) 299 { 300 return (readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE); 301 } 302 303 static int intel_crosststamp(ktime_t *device, 304 struct system_counterval_t *system, 305 void *ctx) 306 { 307 struct intel_priv_data *intel_priv; 308 309 struct stmmac_priv *priv = (struct stmmac_priv *)ctx; 310 void __iomem *ptpaddr = priv->ptpaddr; 311 void __iomem *ioaddr = priv->hw->pcsr; 312 unsigned long flags; 313 u64 art_time = 0; 314 u64 ptp_time = 0; 315 u32 num_snapshot; 316 u32 gpio_value; 317 u32 acr_value; 318 int i; 319 320 if (!boot_cpu_has(X86_FEATURE_ART)) 321 return -EOPNOTSUPP; 322 323 intel_priv = priv->plat->bsp_priv; 324 325 /* Both internal crosstimestamping and external triggered event 326 * timestamping cannot be run concurrently. 327 */ 328 if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN) 329 return -EBUSY; 330 331 priv->plat->flags |= STMMAC_FLAG_INT_SNAPSHOT_EN; 332 333 mutex_lock(&priv->aux_ts_lock); 334 /* Enable Internal snapshot trigger */ 335 acr_value = readl(ptpaddr + PTP_ACR); 336 acr_value &= ~PTP_ACR_MASK; 337 switch (priv->plat->int_snapshot_num) { 338 case AUX_SNAPSHOT0: 339 acr_value |= PTP_ACR_ATSEN0; 340 break; 341 case AUX_SNAPSHOT1: 342 acr_value |= PTP_ACR_ATSEN1; 343 break; 344 case AUX_SNAPSHOT2: 345 acr_value |= PTP_ACR_ATSEN2; 346 break; 347 case AUX_SNAPSHOT3: 348 acr_value |= PTP_ACR_ATSEN3; 349 break; 350 default: 351 mutex_unlock(&priv->aux_ts_lock); 352 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; 353 return -EINVAL; 354 } 355 writel(acr_value, ptpaddr + PTP_ACR); 356 357 /* Clear FIFO */ 358 acr_value = readl(ptpaddr + PTP_ACR); 359 acr_value |= PTP_ACR_ATSFC; 360 writel(acr_value, ptpaddr + PTP_ACR); 361 /* Release the mutex */ 362 mutex_unlock(&priv->aux_ts_lock); 363 364 /* Trigger Internal snapshot signal 365 * Create a rising edge by just toggle the GPO1 to low 366 * and back to high. 367 */ 368 gpio_value = readl(ioaddr + GMAC_GPIO_STATUS); 369 gpio_value &= ~GMAC_GPO1; 370 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS); 371 gpio_value |= GMAC_GPO1; 372 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS); 373 374 /* Time sync done Indication - Interrupt method */ 375 if (!wait_event_interruptible_timeout(priv->tstamp_busy_wait, 376 stmmac_cross_ts_isr(priv), 377 HZ / 100)) { 378 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; 379 return -ETIMEDOUT; 380 } 381 382 num_snapshot = (readl(ioaddr + GMAC_TIMESTAMP_STATUS) & 383 GMAC_TIMESTAMP_ATSNS_MASK) >> 384 GMAC_TIMESTAMP_ATSNS_SHIFT; 385 386 /* Repeat until the timestamps are from the FIFO last segment */ 387 for (i = 0; i < num_snapshot; i++) { 388 read_lock_irqsave(&priv->ptp_lock, flags); 389 stmmac_get_ptptime(priv, ptpaddr, &ptp_time); 390 *device = ns_to_ktime(ptp_time); 391 read_unlock_irqrestore(&priv->ptp_lock, flags); 392 get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time); 393 *system = convert_art_to_tsc(art_time); 394 } 395 396 system->cycles *= intel_priv->crossts_adj; 397 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; 398 399 return 0; 400 } 401 402 static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv, 403 int base) 404 { 405 if (boot_cpu_has(X86_FEATURE_ART)) { 406 unsigned int art_freq; 407 408 /* On systems that support ART, ART frequency can be obtained 409 * from ECX register of CPUID leaf (0x15). 410 */ 411 art_freq = cpuid_ecx(ART_CPUID_LEAF); 412 do_div(art_freq, base); 413 intel_priv->crossts_adj = art_freq; 414 } 415 } 416 417 static void common_default_data(struct plat_stmmacenet_data *plat) 418 { 419 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 420 plat->has_gmac = 1; 421 plat->force_sf_dma_mode = 1; 422 423 plat->mdio_bus_data->needs_reset = true; 424 425 /* Set default value for multicast hash bins */ 426 plat->multicast_filter_bins = HASH_TABLE_SIZE; 427 428 /* Set default value for unicast filter entries */ 429 plat->unicast_filter_entries = 1; 430 431 /* Set the maxmtu to a default of JUMBO_LEN */ 432 plat->maxmtu = JUMBO_LEN; 433 434 /* Set default number of RX and TX queues to use */ 435 plat->tx_queues_to_use = 1; 436 plat->rx_queues_to_use = 1; 437 438 /* Disable Priority config by default */ 439 plat->tx_queues_cfg[0].use_prio = false; 440 plat->rx_queues_cfg[0].use_prio = false; 441 442 /* Disable RX queues routing by default */ 443 plat->rx_queues_cfg[0].pkt_route = 0x0; 444 } 445 446 static int intel_mgbe_common_data(struct pci_dev *pdev, 447 struct plat_stmmacenet_data *plat) 448 { 449 struct fwnode_handle *fwnode; 450 char clk_name[20]; 451 int ret; 452 int i; 453 454 plat->pdev = pdev; 455 plat->phy_addr = -1; 456 plat->clk_csr = 5; 457 plat->has_gmac = 0; 458 plat->has_gmac4 = 1; 459 plat->force_sf_dma_mode = 0; 460 plat->flags |= (STMMAC_FLAG_TSO_EN | STMMAC_FLAG_SPH_DISABLE); 461 462 /* Multiplying factor to the clk_eee_i clock time 463 * period to make it closer to 100 ns. This value 464 * should be programmed such that the clk_eee_time_period * 465 * (MULT_FACT_100NS + 1) should be within 80 ns to 120 ns 466 * clk_eee frequency is 19.2Mhz 467 * clk_eee_time_period is 52ns 468 * 52ns * (1 + 1) = 104ns 469 * MULT_FACT_100NS = 1 470 */ 471 plat->mult_fact_100ns = 1; 472 473 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; 474 475 for (i = 0; i < plat->rx_queues_to_use; i++) { 476 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 477 plat->rx_queues_cfg[i].chan = i; 478 479 /* Disable Priority config by default */ 480 plat->rx_queues_cfg[i].use_prio = false; 481 482 /* Disable RX queues routing by default */ 483 plat->rx_queues_cfg[i].pkt_route = 0x0; 484 } 485 486 for (i = 0; i < plat->tx_queues_to_use; i++) { 487 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 488 489 /* Disable Priority config by default */ 490 plat->tx_queues_cfg[i].use_prio = false; 491 /* Default TX Q0 to use TSO and rest TXQ for TBS */ 492 if (i > 0) 493 plat->tx_queues_cfg[i].tbs_en = 1; 494 } 495 496 /* FIFO size is 4096 bytes for 1 tx/rx queue */ 497 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; 498 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; 499 500 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; 501 plat->tx_queues_cfg[0].weight = 0x09; 502 plat->tx_queues_cfg[1].weight = 0x0A; 503 plat->tx_queues_cfg[2].weight = 0x0B; 504 plat->tx_queues_cfg[3].weight = 0x0C; 505 plat->tx_queues_cfg[4].weight = 0x0D; 506 plat->tx_queues_cfg[5].weight = 0x0E; 507 plat->tx_queues_cfg[6].weight = 0x0F; 508 plat->tx_queues_cfg[7].weight = 0x10; 509 510 plat->dma_cfg->pbl = 32; 511 plat->dma_cfg->pblx8 = true; 512 plat->dma_cfg->fixed_burst = 0; 513 plat->dma_cfg->mixed_burst = 0; 514 plat->dma_cfg->aal = 0; 515 plat->dma_cfg->dche = true; 516 517 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), 518 GFP_KERNEL); 519 if (!plat->axi) 520 return -ENOMEM; 521 522 plat->axi->axi_lpi_en = 0; 523 plat->axi->axi_xit_frm = 0; 524 plat->axi->axi_wr_osr_lmt = 1; 525 plat->axi->axi_rd_osr_lmt = 1; 526 plat->axi->axi_blen[0] = 4; 527 plat->axi->axi_blen[1] = 8; 528 plat->axi->axi_blen[2] = 16; 529 530 plat->ptp_max_adj = plat->clk_ptp_rate; 531 plat->eee_usecs_rate = plat->clk_ptp_rate; 532 533 /* Set system clock */ 534 sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev)); 535 536 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, 537 clk_name, NULL, 0, 538 plat->clk_ptp_rate); 539 540 if (IS_ERR(plat->stmmac_clk)) { 541 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); 542 plat->stmmac_clk = NULL; 543 } 544 545 ret = clk_prepare_enable(plat->stmmac_clk); 546 if (ret) { 547 clk_unregister_fixed_rate(plat->stmmac_clk); 548 return ret; 549 } 550 551 plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config; 552 553 /* Set default value for multicast hash bins */ 554 plat->multicast_filter_bins = HASH_TABLE_SIZE; 555 556 /* Set default value for unicast filter entries */ 557 plat->unicast_filter_entries = 1; 558 559 /* Set the maxmtu to a default of JUMBO_LEN */ 560 plat->maxmtu = JUMBO_LEN; 561 562 plat->flags |= STMMAC_FLAG_VLAN_FAIL_Q_EN; 563 564 /* Use the last Rx queue */ 565 plat->vlan_fail_q = plat->rx_queues_to_use - 1; 566 567 /* For fixed-link setup, we allow phy-mode setting */ 568 fwnode = dev_fwnode(&pdev->dev); 569 if (fwnode) { 570 int phy_mode; 571 572 /* "phy-mode" setting is optional. If it is set, 573 * we allow either sgmii or 1000base-x for now. 574 */ 575 phy_mode = fwnode_get_phy_mode(fwnode); 576 if (phy_mode >= 0) { 577 if (phy_mode == PHY_INTERFACE_MODE_SGMII || 578 phy_mode == PHY_INTERFACE_MODE_1000BASEX) 579 plat->phy_interface = phy_mode; 580 else 581 dev_warn(&pdev->dev, "Invalid phy-mode\n"); 582 } 583 } 584 585 /* Intel mgbe SGMII interface uses pcs-xcps */ 586 if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII || 587 plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { 588 plat->mdio_bus_data->has_xpcs = true; 589 plat->mdio_bus_data->default_an_inband = true; 590 } 591 592 /* Ensure mdio bus scan skips intel serdes and pcs-xpcs */ 593 plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR; 594 plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR; 595 596 plat->int_snapshot_num = AUX_SNAPSHOT1; 597 598 plat->crosststamp = intel_crosststamp; 599 plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; 600 601 /* Setup MSI vector offset specific to Intel mGbE controller */ 602 plat->msi_mac_vec = 29; 603 plat->msi_lpi_vec = 28; 604 plat->msi_sfty_ce_vec = 27; 605 plat->msi_sfty_ue_vec = 26; 606 plat->msi_rx_base_vec = 0; 607 plat->msi_tx_base_vec = 1; 608 609 return 0; 610 } 611 612 static int ehl_common_data(struct pci_dev *pdev, 613 struct plat_stmmacenet_data *plat) 614 { 615 plat->rx_queues_to_use = 8; 616 plat->tx_queues_to_use = 8; 617 plat->flags |= STMMAC_FLAG_USE_PHY_WOL; 618 plat->flags |= STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY; 619 620 plat->safety_feat_cfg->tsoee = 1; 621 plat->safety_feat_cfg->mrxpee = 1; 622 plat->safety_feat_cfg->mestee = 1; 623 plat->safety_feat_cfg->mrxee = 1; 624 plat->safety_feat_cfg->mtxee = 1; 625 plat->safety_feat_cfg->epsi = 0; 626 plat->safety_feat_cfg->edpp = 0; 627 plat->safety_feat_cfg->prtyen = 0; 628 plat->safety_feat_cfg->tmouten = 0; 629 630 return intel_mgbe_common_data(pdev, plat); 631 } 632 633 static int ehl_sgmii_data(struct pci_dev *pdev, 634 struct plat_stmmacenet_data *plat) 635 { 636 plat->bus_id = 1; 637 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 638 plat->speed_mode_2500 = intel_speed_mode_2500; 639 plat->serdes_powerup = intel_serdes_powerup; 640 plat->serdes_powerdown = intel_serdes_powerdown; 641 642 plat->clk_ptp_rate = 204800000; 643 644 return ehl_common_data(pdev, plat); 645 } 646 647 static struct stmmac_pci_info ehl_sgmii1g_info = { 648 .setup = ehl_sgmii_data, 649 }; 650 651 static int ehl_rgmii_data(struct pci_dev *pdev, 652 struct plat_stmmacenet_data *plat) 653 { 654 plat->bus_id = 1; 655 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; 656 657 plat->clk_ptp_rate = 204800000; 658 659 return ehl_common_data(pdev, plat); 660 } 661 662 static struct stmmac_pci_info ehl_rgmii1g_info = { 663 .setup = ehl_rgmii_data, 664 }; 665 666 static int ehl_pse0_common_data(struct pci_dev *pdev, 667 struct plat_stmmacenet_data *plat) 668 { 669 struct intel_priv_data *intel_priv = plat->bsp_priv; 670 671 intel_priv->is_pse = true; 672 plat->bus_id = 2; 673 plat->host_dma_width = 32; 674 675 plat->clk_ptp_rate = 200000000; 676 677 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ); 678 679 return ehl_common_data(pdev, plat); 680 } 681 682 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev, 683 struct plat_stmmacenet_data *plat) 684 { 685 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 686 return ehl_pse0_common_data(pdev, plat); 687 } 688 689 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = { 690 .setup = ehl_pse0_rgmii1g_data, 691 }; 692 693 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, 694 struct plat_stmmacenet_data *plat) 695 { 696 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 697 plat->speed_mode_2500 = intel_speed_mode_2500; 698 plat->serdes_powerup = intel_serdes_powerup; 699 plat->serdes_powerdown = intel_serdes_powerdown; 700 return ehl_pse0_common_data(pdev, plat); 701 } 702 703 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = { 704 .setup = ehl_pse0_sgmii1g_data, 705 }; 706 707 static int ehl_pse1_common_data(struct pci_dev *pdev, 708 struct plat_stmmacenet_data *plat) 709 { 710 struct intel_priv_data *intel_priv = plat->bsp_priv; 711 712 intel_priv->is_pse = true; 713 plat->bus_id = 3; 714 plat->host_dma_width = 32; 715 716 plat->clk_ptp_rate = 200000000; 717 718 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ); 719 720 return ehl_common_data(pdev, plat); 721 } 722 723 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev, 724 struct plat_stmmacenet_data *plat) 725 { 726 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 727 return ehl_pse1_common_data(pdev, plat); 728 } 729 730 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = { 731 .setup = ehl_pse1_rgmii1g_data, 732 }; 733 734 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, 735 struct plat_stmmacenet_data *plat) 736 { 737 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 738 plat->speed_mode_2500 = intel_speed_mode_2500; 739 plat->serdes_powerup = intel_serdes_powerup; 740 plat->serdes_powerdown = intel_serdes_powerdown; 741 return ehl_pse1_common_data(pdev, plat); 742 } 743 744 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = { 745 .setup = ehl_pse1_sgmii1g_data, 746 }; 747 748 static int tgl_common_data(struct pci_dev *pdev, 749 struct plat_stmmacenet_data *plat) 750 { 751 plat->rx_queues_to_use = 6; 752 plat->tx_queues_to_use = 4; 753 plat->clk_ptp_rate = 204800000; 754 plat->speed_mode_2500 = intel_speed_mode_2500; 755 756 plat->safety_feat_cfg->tsoee = 1; 757 plat->safety_feat_cfg->mrxpee = 0; 758 plat->safety_feat_cfg->mestee = 1; 759 plat->safety_feat_cfg->mrxee = 1; 760 plat->safety_feat_cfg->mtxee = 1; 761 plat->safety_feat_cfg->epsi = 0; 762 plat->safety_feat_cfg->edpp = 0; 763 plat->safety_feat_cfg->prtyen = 0; 764 plat->safety_feat_cfg->tmouten = 0; 765 766 return intel_mgbe_common_data(pdev, plat); 767 } 768 769 static int tgl_sgmii_phy0_data(struct pci_dev *pdev, 770 struct plat_stmmacenet_data *plat) 771 { 772 plat->bus_id = 1; 773 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 774 plat->serdes_powerup = intel_serdes_powerup; 775 plat->serdes_powerdown = intel_serdes_powerdown; 776 return tgl_common_data(pdev, plat); 777 } 778 779 static struct stmmac_pci_info tgl_sgmii1g_phy0_info = { 780 .setup = tgl_sgmii_phy0_data, 781 }; 782 783 static int tgl_sgmii_phy1_data(struct pci_dev *pdev, 784 struct plat_stmmacenet_data *plat) 785 { 786 plat->bus_id = 2; 787 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 788 plat->serdes_powerup = intel_serdes_powerup; 789 plat->serdes_powerdown = intel_serdes_powerdown; 790 return tgl_common_data(pdev, plat); 791 } 792 793 static struct stmmac_pci_info tgl_sgmii1g_phy1_info = { 794 .setup = tgl_sgmii_phy1_data, 795 }; 796 797 static int adls_sgmii_phy0_data(struct pci_dev *pdev, 798 struct plat_stmmacenet_data *plat) 799 { 800 plat->bus_id = 1; 801 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 802 803 /* SerDes power up and power down are done in BIOS for ADL */ 804 805 return tgl_common_data(pdev, plat); 806 } 807 808 static struct stmmac_pci_info adls_sgmii1g_phy0_info = { 809 .setup = adls_sgmii_phy0_data, 810 }; 811 812 static int adls_sgmii_phy1_data(struct pci_dev *pdev, 813 struct plat_stmmacenet_data *plat) 814 { 815 plat->bus_id = 2; 816 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 817 818 /* SerDes power up and power down are done in BIOS for ADL */ 819 820 return tgl_common_data(pdev, plat); 821 } 822 823 static struct stmmac_pci_info adls_sgmii1g_phy1_info = { 824 .setup = adls_sgmii_phy1_data, 825 }; 826 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { 827 { 828 .func = 6, 829 .phy_addr = 1, 830 }, 831 }; 832 833 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = { 834 .func = galileo_stmmac_func_data, 835 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data), 836 }; 837 838 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = { 839 { 840 .func = 6, 841 .phy_addr = 1, 842 }, 843 { 844 .func = 7, 845 .phy_addr = 1, 846 }, 847 }; 848 849 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = { 850 .func = iot2040_stmmac_func_data, 851 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data), 852 }; 853 854 static const struct dmi_system_id quark_pci_dmi[] = { 855 { 856 .matches = { 857 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 858 }, 859 .driver_data = (void *)&galileo_stmmac_dmi_data, 860 }, 861 { 862 .matches = { 863 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 864 }, 865 .driver_data = (void *)&galileo_stmmac_dmi_data, 866 }, 867 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040. 868 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which 869 * has only one pci network device while other asset tags are 870 * for IOT2040 which has two. 871 */ 872 { 873 .matches = { 874 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 875 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, 876 "6ES7647-0AA00-0YA2"), 877 }, 878 .driver_data = (void *)&galileo_stmmac_dmi_data, 879 }, 880 { 881 .matches = { 882 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 883 }, 884 .driver_data = (void *)&iot2040_stmmac_dmi_data, 885 }, 886 {} 887 }; 888 889 static int quark_default_data(struct pci_dev *pdev, 890 struct plat_stmmacenet_data *plat) 891 { 892 int ret; 893 894 /* Set common default data first */ 895 common_default_data(plat); 896 897 /* Refuse to load the driver and register net device if MAC controller 898 * does not connect to any PHY interface. 899 */ 900 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi); 901 if (ret < 0) { 902 /* Return error to the caller on DMI enabled boards. */ 903 if (dmi_get_system_info(DMI_BOARD_NAME)) 904 return ret; 905 906 /* Galileo boards with old firmware don't support DMI. We always 907 * use 1 here as PHY address, so at least the first found MAC 908 * controller would be probed. 909 */ 910 ret = 1; 911 } 912 913 plat->bus_id = pci_dev_id(pdev); 914 plat->phy_addr = ret; 915 plat->phy_interface = PHY_INTERFACE_MODE_RMII; 916 917 plat->dma_cfg->pbl = 16; 918 plat->dma_cfg->pblx8 = true; 919 plat->dma_cfg->fixed_burst = 1; 920 /* AXI (TODO) */ 921 922 return 0; 923 } 924 925 static const struct stmmac_pci_info quark_info = { 926 .setup = quark_default_data, 927 }; 928 929 static int stmmac_config_single_msi(struct pci_dev *pdev, 930 struct plat_stmmacenet_data *plat, 931 struct stmmac_resources *res) 932 { 933 int ret; 934 935 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 936 if (ret < 0) { 937 dev_info(&pdev->dev, "%s: Single IRQ enablement failed\n", 938 __func__); 939 return ret; 940 } 941 942 res->irq = pci_irq_vector(pdev, 0); 943 res->wol_irq = res->irq; 944 plat->flags &= ~STMMAC_FLAG_MULTI_MSI_EN; 945 dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n", 946 __func__); 947 948 return 0; 949 } 950 951 static int stmmac_config_multi_msi(struct pci_dev *pdev, 952 struct plat_stmmacenet_data *plat, 953 struct stmmac_resources *res) 954 { 955 int ret; 956 int i; 957 958 if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX || 959 plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) { 960 dev_info(&pdev->dev, "%s: Invalid RX & TX vector defined\n", 961 __func__); 962 return -1; 963 } 964 965 ret = pci_alloc_irq_vectors(pdev, 2, STMMAC_MSI_VEC_MAX, 966 PCI_IRQ_MSI | PCI_IRQ_MSIX); 967 if (ret < 0) { 968 dev_info(&pdev->dev, "%s: multi MSI enablement failed\n", 969 __func__); 970 return ret; 971 } 972 973 /* For RX MSI */ 974 for (i = 0; i < plat->rx_queues_to_use; i++) { 975 res->rx_irq[i] = pci_irq_vector(pdev, 976 plat->msi_rx_base_vec + i * 2); 977 } 978 979 /* For TX MSI */ 980 for (i = 0; i < plat->tx_queues_to_use; i++) { 981 res->tx_irq[i] = pci_irq_vector(pdev, 982 plat->msi_tx_base_vec + i * 2); 983 } 984 985 if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX) 986 res->irq = pci_irq_vector(pdev, plat->msi_mac_vec); 987 if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX) 988 res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec); 989 if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX) 990 res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec); 991 if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX) 992 res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec); 993 if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX) 994 res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec); 995 996 plat->flags |= STMMAC_FLAG_MULTI_MSI_EN; 997 dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__); 998 999 return 0; 1000 } 1001 1002 /** 1003 * intel_eth_pci_probe 1004 * 1005 * @pdev: pci device pointer 1006 * @id: pointer to table of device id/id's. 1007 * 1008 * Description: This probing function gets called for all PCI devices which 1009 * match the ID table and are not "owned" by other driver yet. This function 1010 * gets passed a "struct pci_dev *" for each device whose entry in the ID table 1011 * matches the device. The probe functions returns zero when the driver choose 1012 * to take "ownership" of the device or an error code(-ve no) otherwise. 1013 */ 1014 static int intel_eth_pci_probe(struct pci_dev *pdev, 1015 const struct pci_device_id *id) 1016 { 1017 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; 1018 struct intel_priv_data *intel_priv; 1019 struct plat_stmmacenet_data *plat; 1020 struct stmmac_resources res; 1021 int ret; 1022 1023 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL); 1024 if (!intel_priv) 1025 return -ENOMEM; 1026 1027 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 1028 if (!plat) 1029 return -ENOMEM; 1030 1031 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, 1032 sizeof(*plat->mdio_bus_data), 1033 GFP_KERNEL); 1034 if (!plat->mdio_bus_data) 1035 return -ENOMEM; 1036 1037 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), 1038 GFP_KERNEL); 1039 if (!plat->dma_cfg) 1040 return -ENOMEM; 1041 1042 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev, 1043 sizeof(*plat->safety_feat_cfg), 1044 GFP_KERNEL); 1045 if (!plat->safety_feat_cfg) 1046 return -ENOMEM; 1047 1048 /* Enable pci device */ 1049 ret = pcim_enable_device(pdev); 1050 if (ret) { 1051 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", 1052 __func__); 1053 return ret; 1054 } 1055 1056 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 1057 if (ret) 1058 return ret; 1059 1060 pci_set_master(pdev); 1061 1062 plat->bsp_priv = intel_priv; 1063 intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR; 1064 intel_priv->crossts_adj = 1; 1065 1066 /* Initialize all MSI vectors to invalid so that it can be set 1067 * according to platform data settings below. 1068 * Note: MSI vector takes value from 0 upto 31 (STMMAC_MSI_VEC_MAX) 1069 */ 1070 plat->msi_mac_vec = STMMAC_MSI_VEC_MAX; 1071 plat->msi_wol_vec = STMMAC_MSI_VEC_MAX; 1072 plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX; 1073 plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX; 1074 plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX; 1075 plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX; 1076 plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX; 1077 1078 ret = info->setup(pdev, plat); 1079 if (ret) 1080 return ret; 1081 1082 memset(&res, 0, sizeof(res)); 1083 res.addr = pcim_iomap_table(pdev)[0]; 1084 1085 if (plat->eee_usecs_rate > 0) { 1086 u32 tx_lpi_usec; 1087 1088 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1; 1089 writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER); 1090 } 1091 1092 ret = stmmac_config_multi_msi(pdev, plat, &res); 1093 if (ret) { 1094 ret = stmmac_config_single_msi(pdev, plat, &res); 1095 if (ret) { 1096 dev_err(&pdev->dev, "%s: ERROR: failed to enable IRQ\n", 1097 __func__); 1098 goto err_alloc_irq; 1099 } 1100 } 1101 1102 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); 1103 if (ret) { 1104 goto err_alloc_irq; 1105 } 1106 1107 return 0; 1108 1109 err_alloc_irq: 1110 clk_disable_unprepare(plat->stmmac_clk); 1111 clk_unregister_fixed_rate(plat->stmmac_clk); 1112 return ret; 1113 } 1114 1115 /** 1116 * intel_eth_pci_remove 1117 * 1118 * @pdev: pci device pointer 1119 * Description: this function calls the main to free the net resources 1120 * and releases the PCI resources. 1121 */ 1122 static void intel_eth_pci_remove(struct pci_dev *pdev) 1123 { 1124 struct net_device *ndev = dev_get_drvdata(&pdev->dev); 1125 struct stmmac_priv *priv = netdev_priv(ndev); 1126 1127 stmmac_dvr_remove(&pdev->dev); 1128 1129 clk_disable_unprepare(priv->plat->stmmac_clk); 1130 clk_unregister_fixed_rate(priv->plat->stmmac_clk); 1131 } 1132 1133 static int __maybe_unused intel_eth_pci_suspend(struct device *dev) 1134 { 1135 struct pci_dev *pdev = to_pci_dev(dev); 1136 int ret; 1137 1138 ret = stmmac_suspend(dev); 1139 if (ret) 1140 return ret; 1141 1142 ret = pci_save_state(pdev); 1143 if (ret) 1144 return ret; 1145 1146 pci_wake_from_d3(pdev, true); 1147 pci_set_power_state(pdev, PCI_D3hot); 1148 return 0; 1149 } 1150 1151 static int __maybe_unused intel_eth_pci_resume(struct device *dev) 1152 { 1153 struct pci_dev *pdev = to_pci_dev(dev); 1154 int ret; 1155 1156 pci_restore_state(pdev); 1157 pci_set_power_state(pdev, PCI_D0); 1158 1159 ret = pcim_enable_device(pdev); 1160 if (ret) 1161 return ret; 1162 1163 pci_set_master(pdev); 1164 1165 return stmmac_resume(dev); 1166 } 1167 1168 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, 1169 intel_eth_pci_resume); 1170 1171 #define PCI_DEVICE_ID_INTEL_QUARK 0x0937 1172 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30 1173 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G 0x4b31 1174 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32 1175 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC 1176 * which are named PSE0 and PSE1 1177 */ 1178 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0 1179 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1 1180 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2 1181 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0 1182 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1 1183 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2 1184 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0 0x43ac 1185 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1 0x43a2 1186 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G 0xa0ac 1187 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0 0x7aac 1188 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1 0x7aad 1189 #define PCI_DEVICE_ID_INTEL_ADLN_SGMII1G 0x54ac 1190 #define PCI_DEVICE_ID_INTEL_RPLP_SGMII1G 0x51ac 1191 1192 static const struct pci_device_id intel_eth_pci_id_table[] = { 1193 { PCI_DEVICE_DATA(INTEL, QUARK, &quark_info) }, 1194 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, &ehl_rgmii1g_info) }, 1195 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, &ehl_sgmii1g_info) }, 1196 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, &ehl_sgmii1g_info) }, 1197 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, &ehl_pse0_rgmii1g_info) }, 1198 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, &ehl_pse0_sgmii1g_info) }, 1199 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, &ehl_pse0_sgmii1g_info) }, 1200 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, &ehl_pse1_rgmii1g_info) }, 1201 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, &ehl_pse1_sgmii1g_info) }, 1202 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, &ehl_pse1_sgmii1g_info) }, 1203 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, &tgl_sgmii1g_phy0_info) }, 1204 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, &tgl_sgmii1g_phy0_info) }, 1205 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) }, 1206 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) }, 1207 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) }, 1208 { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &tgl_sgmii1g_phy0_info) }, 1209 { PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &tgl_sgmii1g_phy0_info) }, 1210 {} 1211 }; 1212 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table); 1213 1214 static struct pci_driver intel_eth_pci_driver = { 1215 .name = "intel-eth-pci", 1216 .id_table = intel_eth_pci_id_table, 1217 .probe = intel_eth_pci_probe, 1218 .remove = intel_eth_pci_remove, 1219 .driver = { 1220 .pm = &intel_eth_pm_ops, 1221 }, 1222 }; 1223 1224 module_pci_driver(intel_eth_pci_driver); 1225 1226 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver"); 1227 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>"); 1228 MODULE_LICENSE("GPL v2"); 1229