1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2020, Intel Corporation 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/pci.h> 7 #include <linux/dmi.h> 8 #include "dwmac-intel.h" 9 #include "dwmac4.h" 10 #include "stmmac.h" 11 #include "stmmac_ptp.h" 12 13 struct intel_priv_data { 14 int mdio_adhoc_addr; /* mdio address for serdes & etc */ 15 unsigned long crossts_adj; 16 bool is_pse; 17 }; 18 19 /* This struct is used to associate PCI Function of MAC controller on a board, 20 * discovered via DMI, with the address of PHY connected to the MAC. The 21 * negative value of the address means that MAC controller is not connected 22 * with PHY. 23 */ 24 struct stmmac_pci_func_data { 25 unsigned int func; 26 int phy_addr; 27 }; 28 29 struct stmmac_pci_dmi_data { 30 const struct stmmac_pci_func_data *func; 31 size_t nfuncs; 32 }; 33 34 struct stmmac_pci_info { 35 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); 36 }; 37 38 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, 39 const struct dmi_system_id *dmi_list) 40 { 41 const struct stmmac_pci_func_data *func_data; 42 const struct stmmac_pci_dmi_data *dmi_data; 43 const struct dmi_system_id *dmi_id; 44 int func = PCI_FUNC(pdev->devfn); 45 size_t n; 46 47 dmi_id = dmi_first_match(dmi_list); 48 if (!dmi_id) 49 return -ENODEV; 50 51 dmi_data = dmi_id->driver_data; 52 func_data = dmi_data->func; 53 54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) 55 if (func_data->func == func) 56 return func_data->phy_addr; 57 58 return -ENODEV; 59 } 60 61 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr, 62 int phyreg, u32 mask, u32 val) 63 { 64 unsigned int retries = 10; 65 int val_rd; 66 67 do { 68 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg); 69 if ((val_rd & mask) == (val & mask)) 70 return 0; 71 udelay(POLL_DELAY_US); 72 } while (--retries); 73 74 return -ETIMEDOUT; 75 } 76 77 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) 78 { 79 struct intel_priv_data *intel_priv = priv_data; 80 struct stmmac_priv *priv = netdev_priv(ndev); 81 int serdes_phy_addr = 0; 82 u32 data = 0; 83 84 if (!intel_priv->mdio_adhoc_addr) 85 return 0; 86 87 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 88 89 /* Set the serdes rate and the PCLK rate */ 90 data = mdiobus_read(priv->mii, serdes_phy_addr, 91 SERDES_GCR0); 92 93 data &= ~SERDES_RATE_MASK; 94 data &= ~SERDES_PCLK_MASK; 95 96 if (priv->plat->max_speed == 2500) 97 data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT | 98 SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT; 99 else 100 data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT | 101 SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT; 102 103 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 104 105 /* assert clk_req */ 106 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 107 data |= SERDES_PLL_CLK; 108 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 109 110 /* check for clk_ack assertion */ 111 data = serdes_status_poll(priv, serdes_phy_addr, 112 SERDES_GSR0, 113 SERDES_PLL_CLK, 114 SERDES_PLL_CLK); 115 116 if (data) { 117 dev_err(priv->device, "Serdes PLL clk request timeout\n"); 118 return data; 119 } 120 121 /* assert lane reset */ 122 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 123 data |= SERDES_RST; 124 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 125 126 /* check for assert lane reset reflection */ 127 data = serdes_status_poll(priv, serdes_phy_addr, 128 SERDES_GSR0, 129 SERDES_RST, 130 SERDES_RST); 131 132 if (data) { 133 dev_err(priv->device, "Serdes assert lane reset timeout\n"); 134 return data; 135 } 136 137 /* move power state to P0 */ 138 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 139 140 data &= ~SERDES_PWR_ST_MASK; 141 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT; 142 143 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 144 145 /* Check for P0 state */ 146 data = serdes_status_poll(priv, serdes_phy_addr, 147 SERDES_GSR0, 148 SERDES_PWR_ST_MASK, 149 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT); 150 151 if (data) { 152 dev_err(priv->device, "Serdes power state P0 timeout.\n"); 153 return data; 154 } 155 156 /* PSE only - ungate SGMII PHY Rx Clock */ 157 if (intel_priv->is_pse) 158 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, 159 0, SERDES_PHY_RX_CLK); 160 161 return 0; 162 } 163 164 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) 165 { 166 struct intel_priv_data *intel_priv = intel_data; 167 struct stmmac_priv *priv = netdev_priv(ndev); 168 int serdes_phy_addr = 0; 169 u32 data = 0; 170 171 if (!intel_priv->mdio_adhoc_addr) 172 return; 173 174 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 175 176 /* PSE only - gate SGMII PHY Rx Clock */ 177 if (intel_priv->is_pse) 178 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, 179 SERDES_PHY_RX_CLK, 0); 180 181 /* move power state to P3 */ 182 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 183 184 data &= ~SERDES_PWR_ST_MASK; 185 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT; 186 187 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 188 189 /* Check for P3 state */ 190 data = serdes_status_poll(priv, serdes_phy_addr, 191 SERDES_GSR0, 192 SERDES_PWR_ST_MASK, 193 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT); 194 195 if (data) { 196 dev_err(priv->device, "Serdes power state P3 timeout\n"); 197 return; 198 } 199 200 /* de-assert clk_req */ 201 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 202 data &= ~SERDES_PLL_CLK; 203 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 204 205 /* check for clk_ack de-assert */ 206 data = serdes_status_poll(priv, serdes_phy_addr, 207 SERDES_GSR0, 208 SERDES_PLL_CLK, 209 (u32)~SERDES_PLL_CLK); 210 211 if (data) { 212 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n"); 213 return; 214 } 215 216 /* de-assert lane reset */ 217 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 218 data &= ~SERDES_RST; 219 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 220 221 /* check for de-assert lane reset reflection */ 222 data = serdes_status_poll(priv, serdes_phy_addr, 223 SERDES_GSR0, 224 SERDES_RST, 225 (u32)~SERDES_RST); 226 227 if (data) { 228 dev_err(priv->device, "Serdes de-assert lane reset timeout\n"); 229 return; 230 } 231 } 232 233 static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data) 234 { 235 struct intel_priv_data *intel_priv = intel_data; 236 struct stmmac_priv *priv = netdev_priv(ndev); 237 int serdes_phy_addr = 0; 238 u32 data = 0; 239 240 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 241 242 /* Determine the link speed mode: 2.5Gbps/1Gbps */ 243 data = mdiobus_read(priv->mii, serdes_phy_addr, 244 SERDES_GCR); 245 246 if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) == 247 SERDES_LINK_MODE_2G5) { 248 dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n"); 249 priv->plat->max_speed = 2500; 250 priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX; 251 priv->plat->mdio_bus_data->xpcs_an_inband = false; 252 } else { 253 priv->plat->max_speed = 1000; 254 priv->plat->mdio_bus_data->xpcs_an_inband = true; 255 } 256 } 257 258 /* Program PTP Clock Frequency for different variant of 259 * Intel mGBE that has slightly different GPO mapping 260 */ 261 static void intel_mgbe_ptp_clk_freq_config(void *npriv) 262 { 263 struct stmmac_priv *priv = (struct stmmac_priv *)npriv; 264 struct intel_priv_data *intel_priv; 265 u32 gpio_value; 266 267 intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv; 268 269 gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS); 270 271 if (intel_priv->is_pse) { 272 /* For PSE GbE, use 200MHz */ 273 gpio_value &= ~PSE_PTP_CLK_FREQ_MASK; 274 gpio_value |= PSE_PTP_CLK_FREQ_200MHZ; 275 } else { 276 /* For PCH GbE, use 200MHz */ 277 gpio_value &= ~PCH_PTP_CLK_FREQ_MASK; 278 gpio_value |= PCH_PTP_CLK_FREQ_200MHZ; 279 } 280 281 writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS); 282 } 283 284 static void get_arttime(struct mii_bus *mii, int intel_adhoc_addr, 285 u64 *art_time) 286 { 287 u64 ns; 288 289 ns = mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE3); 290 ns <<= GMAC4_ART_TIME_SHIFT; 291 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE2); 292 ns <<= GMAC4_ART_TIME_SHIFT; 293 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE1); 294 ns <<= GMAC4_ART_TIME_SHIFT; 295 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE0); 296 297 *art_time = ns; 298 } 299 300 static int intel_crosststamp(ktime_t *device, 301 struct system_counterval_t *system, 302 void *ctx) 303 { 304 struct intel_priv_data *intel_priv; 305 306 struct stmmac_priv *priv = (struct stmmac_priv *)ctx; 307 void __iomem *ptpaddr = priv->ptpaddr; 308 void __iomem *ioaddr = priv->hw->pcsr; 309 unsigned long flags; 310 u64 art_time = 0; 311 u64 ptp_time = 0; 312 u32 num_snapshot; 313 u32 gpio_value; 314 u32 acr_value; 315 int ret; 316 u32 v; 317 int i; 318 319 if (!boot_cpu_has(X86_FEATURE_ART)) 320 return -EOPNOTSUPP; 321 322 intel_priv = priv->plat->bsp_priv; 323 324 /* Both internal crosstimestamping and external triggered event 325 * timestamping cannot be run concurrently. 326 */ 327 if (priv->plat->ext_snapshot_en) 328 return -EBUSY; 329 330 mutex_lock(&priv->aux_ts_lock); 331 /* Enable Internal snapshot trigger */ 332 acr_value = readl(ptpaddr + PTP_ACR); 333 acr_value &= ~PTP_ACR_MASK; 334 switch (priv->plat->int_snapshot_num) { 335 case AUX_SNAPSHOT0: 336 acr_value |= PTP_ACR_ATSEN0; 337 break; 338 case AUX_SNAPSHOT1: 339 acr_value |= PTP_ACR_ATSEN1; 340 break; 341 case AUX_SNAPSHOT2: 342 acr_value |= PTP_ACR_ATSEN2; 343 break; 344 case AUX_SNAPSHOT3: 345 acr_value |= PTP_ACR_ATSEN3; 346 break; 347 default: 348 mutex_unlock(&priv->aux_ts_lock); 349 return -EINVAL; 350 } 351 writel(acr_value, ptpaddr + PTP_ACR); 352 353 /* Clear FIFO */ 354 acr_value = readl(ptpaddr + PTP_ACR); 355 acr_value |= PTP_ACR_ATSFC; 356 writel(acr_value, ptpaddr + PTP_ACR); 357 /* Release the mutex */ 358 mutex_unlock(&priv->aux_ts_lock); 359 360 /* Trigger Internal snapshot signal 361 * Create a rising edge by just toggle the GPO1 to low 362 * and back to high. 363 */ 364 gpio_value = readl(ioaddr + GMAC_GPIO_STATUS); 365 gpio_value &= ~GMAC_GPO1; 366 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS); 367 gpio_value |= GMAC_GPO1; 368 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS); 369 370 /* Poll for time sync operation done */ 371 ret = readl_poll_timeout(priv->ioaddr + GMAC_INT_STATUS, v, 372 (v & GMAC_INT_TSIE), 100, 10000); 373 374 if (ret == -ETIMEDOUT) { 375 pr_err("%s: Wait for time sync operation timeout\n", __func__); 376 return ret; 377 } 378 379 num_snapshot = (readl(ioaddr + GMAC_TIMESTAMP_STATUS) & 380 GMAC_TIMESTAMP_ATSNS_MASK) >> 381 GMAC_TIMESTAMP_ATSNS_SHIFT; 382 383 /* Repeat until the timestamps are from the FIFO last segment */ 384 for (i = 0; i < num_snapshot; i++) { 385 read_lock_irqsave(&priv->ptp_lock, flags); 386 stmmac_get_ptptime(priv, ptpaddr, &ptp_time); 387 *device = ns_to_ktime(ptp_time); 388 read_unlock_irqrestore(&priv->ptp_lock, flags); 389 get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time); 390 *system = convert_art_to_tsc(art_time); 391 } 392 393 system->cycles *= intel_priv->crossts_adj; 394 395 return 0; 396 } 397 398 static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv, 399 int base) 400 { 401 if (boot_cpu_has(X86_FEATURE_ART)) { 402 unsigned int art_freq; 403 404 /* On systems that support ART, ART frequency can be obtained 405 * from ECX register of CPUID leaf (0x15). 406 */ 407 art_freq = cpuid_ecx(ART_CPUID_LEAF); 408 do_div(art_freq, base); 409 intel_priv->crossts_adj = art_freq; 410 } 411 } 412 413 static void common_default_data(struct plat_stmmacenet_data *plat) 414 { 415 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 416 plat->has_gmac = 1; 417 plat->force_sf_dma_mode = 1; 418 419 plat->mdio_bus_data->needs_reset = true; 420 421 /* Set default value for multicast hash bins */ 422 plat->multicast_filter_bins = HASH_TABLE_SIZE; 423 424 /* Set default value for unicast filter entries */ 425 plat->unicast_filter_entries = 1; 426 427 /* Set the maxmtu to a default of JUMBO_LEN */ 428 plat->maxmtu = JUMBO_LEN; 429 430 /* Set default number of RX and TX queues to use */ 431 plat->tx_queues_to_use = 1; 432 plat->rx_queues_to_use = 1; 433 434 /* Disable Priority config by default */ 435 plat->tx_queues_cfg[0].use_prio = false; 436 plat->rx_queues_cfg[0].use_prio = false; 437 438 /* Disable RX queues routing by default */ 439 plat->rx_queues_cfg[0].pkt_route = 0x0; 440 } 441 442 static int intel_mgbe_common_data(struct pci_dev *pdev, 443 struct plat_stmmacenet_data *plat) 444 { 445 struct fwnode_handle *fwnode; 446 char clk_name[20]; 447 int ret; 448 int i; 449 450 plat->pdev = pdev; 451 plat->phy_addr = -1; 452 plat->clk_csr = 5; 453 plat->has_gmac = 0; 454 plat->has_gmac4 = 1; 455 plat->force_sf_dma_mode = 0; 456 plat->tso_en = 1; 457 plat->sph_disable = 1; 458 459 /* Multiplying factor to the clk_eee_i clock time 460 * period to make it closer to 100 ns. This value 461 * should be programmed such that the clk_eee_time_period * 462 * (MULT_FACT_100NS + 1) should be within 80 ns to 120 ns 463 * clk_eee frequency is 19.2Mhz 464 * clk_eee_time_period is 52ns 465 * 52ns * (1 + 1) = 104ns 466 * MULT_FACT_100NS = 1 467 */ 468 plat->mult_fact_100ns = 1; 469 470 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; 471 472 for (i = 0; i < plat->rx_queues_to_use; i++) { 473 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 474 plat->rx_queues_cfg[i].chan = i; 475 476 /* Disable Priority config by default */ 477 plat->rx_queues_cfg[i].use_prio = false; 478 479 /* Disable RX queues routing by default */ 480 plat->rx_queues_cfg[i].pkt_route = 0x0; 481 } 482 483 for (i = 0; i < plat->tx_queues_to_use; i++) { 484 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 485 486 /* Disable Priority config by default */ 487 plat->tx_queues_cfg[i].use_prio = false; 488 /* Default TX Q0 to use TSO and rest TXQ for TBS */ 489 if (i > 0) 490 plat->tx_queues_cfg[i].tbs_en = 1; 491 } 492 493 /* FIFO size is 4096 bytes for 1 tx/rx queue */ 494 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; 495 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; 496 497 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; 498 plat->tx_queues_cfg[0].weight = 0x09; 499 plat->tx_queues_cfg[1].weight = 0x0A; 500 plat->tx_queues_cfg[2].weight = 0x0B; 501 plat->tx_queues_cfg[3].weight = 0x0C; 502 plat->tx_queues_cfg[4].weight = 0x0D; 503 plat->tx_queues_cfg[5].weight = 0x0E; 504 plat->tx_queues_cfg[6].weight = 0x0F; 505 plat->tx_queues_cfg[7].weight = 0x10; 506 507 plat->dma_cfg->pbl = 32; 508 plat->dma_cfg->pblx8 = true; 509 plat->dma_cfg->fixed_burst = 0; 510 plat->dma_cfg->mixed_burst = 0; 511 plat->dma_cfg->aal = 0; 512 plat->dma_cfg->dche = true; 513 514 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), 515 GFP_KERNEL); 516 if (!plat->axi) 517 return -ENOMEM; 518 519 plat->axi->axi_lpi_en = 0; 520 plat->axi->axi_xit_frm = 0; 521 plat->axi->axi_wr_osr_lmt = 1; 522 plat->axi->axi_rd_osr_lmt = 1; 523 plat->axi->axi_blen[0] = 4; 524 plat->axi->axi_blen[1] = 8; 525 plat->axi->axi_blen[2] = 16; 526 527 plat->ptp_max_adj = plat->clk_ptp_rate; 528 plat->eee_usecs_rate = plat->clk_ptp_rate; 529 530 /* Set system clock */ 531 sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev)); 532 533 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, 534 clk_name, NULL, 0, 535 plat->clk_ptp_rate); 536 537 if (IS_ERR(plat->stmmac_clk)) { 538 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); 539 plat->stmmac_clk = NULL; 540 } 541 542 ret = clk_prepare_enable(plat->stmmac_clk); 543 if (ret) { 544 clk_unregister_fixed_rate(plat->stmmac_clk); 545 return ret; 546 } 547 548 plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config; 549 550 /* Set default value for multicast hash bins */ 551 plat->multicast_filter_bins = HASH_TABLE_SIZE; 552 553 /* Set default value for unicast filter entries */ 554 plat->unicast_filter_entries = 1; 555 556 /* Set the maxmtu to a default of JUMBO_LEN */ 557 plat->maxmtu = JUMBO_LEN; 558 559 plat->vlan_fail_q_en = true; 560 561 /* Use the last Rx queue */ 562 plat->vlan_fail_q = plat->rx_queues_to_use - 1; 563 564 /* For fixed-link setup, we allow phy-mode setting */ 565 fwnode = dev_fwnode(&pdev->dev); 566 if (fwnode) { 567 int phy_mode; 568 569 /* "phy-mode" setting is optional. If it is set, 570 * we allow either sgmii or 1000base-x for now. 571 */ 572 phy_mode = fwnode_get_phy_mode(fwnode); 573 if (phy_mode >= 0) { 574 if (phy_mode == PHY_INTERFACE_MODE_SGMII || 575 phy_mode == PHY_INTERFACE_MODE_1000BASEX) 576 plat->phy_interface = phy_mode; 577 else 578 dev_warn(&pdev->dev, "Invalid phy-mode\n"); 579 } 580 } 581 582 /* Intel mgbe SGMII interface uses pcs-xcps */ 583 if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII || 584 plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { 585 plat->mdio_bus_data->has_xpcs = true; 586 plat->mdio_bus_data->xpcs_an_inband = true; 587 } 588 589 /* For fixed-link setup, we clear xpcs_an_inband */ 590 if (fwnode) { 591 struct fwnode_handle *fixed_node; 592 593 fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link"); 594 if (fixed_node) 595 plat->mdio_bus_data->xpcs_an_inband = false; 596 597 fwnode_handle_put(fixed_node); 598 } 599 600 /* Ensure mdio bus scan skips intel serdes and pcs-xpcs */ 601 plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR; 602 plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR; 603 604 plat->int_snapshot_num = AUX_SNAPSHOT1; 605 plat->ext_snapshot_num = AUX_SNAPSHOT0; 606 607 plat->has_crossts = true; 608 plat->crosststamp = intel_crosststamp; 609 610 /* Setup MSI vector offset specific to Intel mGbE controller */ 611 plat->msi_mac_vec = 29; 612 plat->msi_lpi_vec = 28; 613 plat->msi_sfty_ce_vec = 27; 614 plat->msi_sfty_ue_vec = 26; 615 plat->msi_rx_base_vec = 0; 616 plat->msi_tx_base_vec = 1; 617 618 return 0; 619 } 620 621 static int ehl_common_data(struct pci_dev *pdev, 622 struct plat_stmmacenet_data *plat) 623 { 624 plat->rx_queues_to_use = 8; 625 plat->tx_queues_to_use = 8; 626 plat->clk_ptp_rate = 200000000; 627 plat->use_phy_wol = 1; 628 629 plat->safety_feat_cfg->tsoee = 1; 630 plat->safety_feat_cfg->mrxpee = 1; 631 plat->safety_feat_cfg->mestee = 1; 632 plat->safety_feat_cfg->mrxee = 1; 633 plat->safety_feat_cfg->mtxee = 1; 634 plat->safety_feat_cfg->epsi = 0; 635 plat->safety_feat_cfg->edpp = 0; 636 plat->safety_feat_cfg->prtyen = 0; 637 plat->safety_feat_cfg->tmouten = 0; 638 639 return intel_mgbe_common_data(pdev, plat); 640 } 641 642 static int ehl_sgmii_data(struct pci_dev *pdev, 643 struct plat_stmmacenet_data *plat) 644 { 645 plat->bus_id = 1; 646 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 647 plat->speed_mode_2500 = intel_speed_mode_2500; 648 plat->serdes_powerup = intel_serdes_powerup; 649 plat->serdes_powerdown = intel_serdes_powerdown; 650 651 return ehl_common_data(pdev, plat); 652 } 653 654 static struct stmmac_pci_info ehl_sgmii1g_info = { 655 .setup = ehl_sgmii_data, 656 }; 657 658 static int ehl_rgmii_data(struct pci_dev *pdev, 659 struct plat_stmmacenet_data *plat) 660 { 661 plat->bus_id = 1; 662 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; 663 664 return ehl_common_data(pdev, plat); 665 } 666 667 static struct stmmac_pci_info ehl_rgmii1g_info = { 668 .setup = ehl_rgmii_data, 669 }; 670 671 static int ehl_pse0_common_data(struct pci_dev *pdev, 672 struct plat_stmmacenet_data *plat) 673 { 674 struct intel_priv_data *intel_priv = plat->bsp_priv; 675 676 intel_priv->is_pse = true; 677 plat->bus_id = 2; 678 plat->addr64 = 32; 679 680 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ); 681 682 return ehl_common_data(pdev, plat); 683 } 684 685 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev, 686 struct plat_stmmacenet_data *plat) 687 { 688 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 689 return ehl_pse0_common_data(pdev, plat); 690 } 691 692 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = { 693 .setup = ehl_pse0_rgmii1g_data, 694 }; 695 696 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, 697 struct plat_stmmacenet_data *plat) 698 { 699 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 700 plat->speed_mode_2500 = intel_speed_mode_2500; 701 plat->serdes_powerup = intel_serdes_powerup; 702 plat->serdes_powerdown = intel_serdes_powerdown; 703 return ehl_pse0_common_data(pdev, plat); 704 } 705 706 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = { 707 .setup = ehl_pse0_sgmii1g_data, 708 }; 709 710 static int ehl_pse1_common_data(struct pci_dev *pdev, 711 struct plat_stmmacenet_data *plat) 712 { 713 struct intel_priv_data *intel_priv = plat->bsp_priv; 714 715 intel_priv->is_pse = true; 716 plat->bus_id = 3; 717 plat->addr64 = 32; 718 719 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ); 720 721 return ehl_common_data(pdev, plat); 722 } 723 724 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev, 725 struct plat_stmmacenet_data *plat) 726 { 727 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 728 return ehl_pse1_common_data(pdev, plat); 729 } 730 731 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = { 732 .setup = ehl_pse1_rgmii1g_data, 733 }; 734 735 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, 736 struct plat_stmmacenet_data *plat) 737 { 738 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 739 plat->speed_mode_2500 = intel_speed_mode_2500; 740 plat->serdes_powerup = intel_serdes_powerup; 741 plat->serdes_powerdown = intel_serdes_powerdown; 742 return ehl_pse1_common_data(pdev, plat); 743 } 744 745 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = { 746 .setup = ehl_pse1_sgmii1g_data, 747 }; 748 749 static int tgl_common_data(struct pci_dev *pdev, 750 struct plat_stmmacenet_data *plat) 751 { 752 plat->rx_queues_to_use = 6; 753 plat->tx_queues_to_use = 4; 754 plat->clk_ptp_rate = 200000000; 755 plat->speed_mode_2500 = intel_speed_mode_2500; 756 757 plat->safety_feat_cfg->tsoee = 1; 758 plat->safety_feat_cfg->mrxpee = 0; 759 plat->safety_feat_cfg->mestee = 1; 760 plat->safety_feat_cfg->mrxee = 1; 761 plat->safety_feat_cfg->mtxee = 1; 762 plat->safety_feat_cfg->epsi = 0; 763 plat->safety_feat_cfg->edpp = 0; 764 plat->safety_feat_cfg->prtyen = 0; 765 plat->safety_feat_cfg->tmouten = 0; 766 767 return intel_mgbe_common_data(pdev, plat); 768 } 769 770 static int tgl_sgmii_phy0_data(struct pci_dev *pdev, 771 struct plat_stmmacenet_data *plat) 772 { 773 plat->bus_id = 1; 774 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 775 plat->serdes_powerup = intel_serdes_powerup; 776 plat->serdes_powerdown = intel_serdes_powerdown; 777 return tgl_common_data(pdev, plat); 778 } 779 780 static struct stmmac_pci_info tgl_sgmii1g_phy0_info = { 781 .setup = tgl_sgmii_phy0_data, 782 }; 783 784 static int tgl_sgmii_phy1_data(struct pci_dev *pdev, 785 struct plat_stmmacenet_data *plat) 786 { 787 plat->bus_id = 2; 788 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 789 plat->serdes_powerup = intel_serdes_powerup; 790 plat->serdes_powerdown = intel_serdes_powerdown; 791 return tgl_common_data(pdev, plat); 792 } 793 794 static struct stmmac_pci_info tgl_sgmii1g_phy1_info = { 795 .setup = tgl_sgmii_phy1_data, 796 }; 797 798 static int adls_sgmii_phy0_data(struct pci_dev *pdev, 799 struct plat_stmmacenet_data *plat) 800 { 801 plat->bus_id = 1; 802 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 803 804 /* SerDes power up and power down are done in BIOS for ADL */ 805 806 return tgl_common_data(pdev, plat); 807 } 808 809 static struct stmmac_pci_info adls_sgmii1g_phy0_info = { 810 .setup = adls_sgmii_phy0_data, 811 }; 812 813 static int adls_sgmii_phy1_data(struct pci_dev *pdev, 814 struct plat_stmmacenet_data *plat) 815 { 816 plat->bus_id = 2; 817 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 818 819 /* SerDes power up and power down are done in BIOS for ADL */ 820 821 return tgl_common_data(pdev, plat); 822 } 823 824 static struct stmmac_pci_info adls_sgmii1g_phy1_info = { 825 .setup = adls_sgmii_phy1_data, 826 }; 827 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { 828 { 829 .func = 6, 830 .phy_addr = 1, 831 }, 832 }; 833 834 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = { 835 .func = galileo_stmmac_func_data, 836 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data), 837 }; 838 839 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = { 840 { 841 .func = 6, 842 .phy_addr = 1, 843 }, 844 { 845 .func = 7, 846 .phy_addr = 1, 847 }, 848 }; 849 850 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = { 851 .func = iot2040_stmmac_func_data, 852 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data), 853 }; 854 855 static const struct dmi_system_id quark_pci_dmi[] = { 856 { 857 .matches = { 858 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 859 }, 860 .driver_data = (void *)&galileo_stmmac_dmi_data, 861 }, 862 { 863 .matches = { 864 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 865 }, 866 .driver_data = (void *)&galileo_stmmac_dmi_data, 867 }, 868 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040. 869 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which 870 * has only one pci network device while other asset tags are 871 * for IOT2040 which has two. 872 */ 873 { 874 .matches = { 875 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 876 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, 877 "6ES7647-0AA00-0YA2"), 878 }, 879 .driver_data = (void *)&galileo_stmmac_dmi_data, 880 }, 881 { 882 .matches = { 883 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 884 }, 885 .driver_data = (void *)&iot2040_stmmac_dmi_data, 886 }, 887 {} 888 }; 889 890 static int quark_default_data(struct pci_dev *pdev, 891 struct plat_stmmacenet_data *plat) 892 { 893 int ret; 894 895 /* Set common default data first */ 896 common_default_data(plat); 897 898 /* Refuse to load the driver and register net device if MAC controller 899 * does not connect to any PHY interface. 900 */ 901 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi); 902 if (ret < 0) { 903 /* Return error to the caller on DMI enabled boards. */ 904 if (dmi_get_system_info(DMI_BOARD_NAME)) 905 return ret; 906 907 /* Galileo boards with old firmware don't support DMI. We always 908 * use 1 here as PHY address, so at least the first found MAC 909 * controller would be probed. 910 */ 911 ret = 1; 912 } 913 914 plat->bus_id = pci_dev_id(pdev); 915 plat->phy_addr = ret; 916 plat->phy_interface = PHY_INTERFACE_MODE_RMII; 917 918 plat->dma_cfg->pbl = 16; 919 plat->dma_cfg->pblx8 = true; 920 plat->dma_cfg->fixed_burst = 1; 921 /* AXI (TODO) */ 922 923 return 0; 924 } 925 926 static const struct stmmac_pci_info quark_info = { 927 .setup = quark_default_data, 928 }; 929 930 static int stmmac_config_single_msi(struct pci_dev *pdev, 931 struct plat_stmmacenet_data *plat, 932 struct stmmac_resources *res) 933 { 934 int ret; 935 936 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 937 if (ret < 0) { 938 dev_info(&pdev->dev, "%s: Single IRQ enablement failed\n", 939 __func__); 940 return ret; 941 } 942 943 res->irq = pci_irq_vector(pdev, 0); 944 res->wol_irq = res->irq; 945 plat->multi_msi_en = 0; 946 dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n", 947 __func__); 948 949 return 0; 950 } 951 952 static int stmmac_config_multi_msi(struct pci_dev *pdev, 953 struct plat_stmmacenet_data *plat, 954 struct stmmac_resources *res) 955 { 956 int ret; 957 int i; 958 959 if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX || 960 plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) { 961 dev_info(&pdev->dev, "%s: Invalid RX & TX vector defined\n", 962 __func__); 963 return -1; 964 } 965 966 ret = pci_alloc_irq_vectors(pdev, 2, STMMAC_MSI_VEC_MAX, 967 PCI_IRQ_MSI | PCI_IRQ_MSIX); 968 if (ret < 0) { 969 dev_info(&pdev->dev, "%s: multi MSI enablement failed\n", 970 __func__); 971 return ret; 972 } 973 974 /* For RX MSI */ 975 for (i = 0; i < plat->rx_queues_to_use; i++) { 976 res->rx_irq[i] = pci_irq_vector(pdev, 977 plat->msi_rx_base_vec + i * 2); 978 } 979 980 /* For TX MSI */ 981 for (i = 0; i < plat->tx_queues_to_use; i++) { 982 res->tx_irq[i] = pci_irq_vector(pdev, 983 plat->msi_tx_base_vec + i * 2); 984 } 985 986 if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX) 987 res->irq = pci_irq_vector(pdev, plat->msi_mac_vec); 988 if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX) 989 res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec); 990 if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX) 991 res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec); 992 if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX) 993 res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec); 994 if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX) 995 res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec); 996 997 plat->multi_msi_en = 1; 998 dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__); 999 1000 return 0; 1001 } 1002 1003 /** 1004 * intel_eth_pci_probe 1005 * 1006 * @pdev: pci device pointer 1007 * @id: pointer to table of device id/id's. 1008 * 1009 * Description: This probing function gets called for all PCI devices which 1010 * match the ID table and are not "owned" by other driver yet. This function 1011 * gets passed a "struct pci_dev *" for each device whose entry in the ID table 1012 * matches the device. The probe functions returns zero when the driver choose 1013 * to take "ownership" of the device or an error code(-ve no) otherwise. 1014 */ 1015 static int intel_eth_pci_probe(struct pci_dev *pdev, 1016 const struct pci_device_id *id) 1017 { 1018 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; 1019 struct intel_priv_data *intel_priv; 1020 struct plat_stmmacenet_data *plat; 1021 struct stmmac_resources res; 1022 int ret; 1023 1024 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL); 1025 if (!intel_priv) 1026 return -ENOMEM; 1027 1028 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 1029 if (!plat) 1030 return -ENOMEM; 1031 1032 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, 1033 sizeof(*plat->mdio_bus_data), 1034 GFP_KERNEL); 1035 if (!plat->mdio_bus_data) 1036 return -ENOMEM; 1037 1038 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), 1039 GFP_KERNEL); 1040 if (!plat->dma_cfg) 1041 return -ENOMEM; 1042 1043 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev, 1044 sizeof(*plat->safety_feat_cfg), 1045 GFP_KERNEL); 1046 if (!plat->safety_feat_cfg) 1047 return -ENOMEM; 1048 1049 /* Enable pci device */ 1050 ret = pcim_enable_device(pdev); 1051 if (ret) { 1052 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", 1053 __func__); 1054 return ret; 1055 } 1056 1057 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 1058 if (ret) 1059 return ret; 1060 1061 pci_set_master(pdev); 1062 1063 plat->bsp_priv = intel_priv; 1064 intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR; 1065 intel_priv->crossts_adj = 1; 1066 1067 /* Initialize all MSI vectors to invalid so that it can be set 1068 * according to platform data settings below. 1069 * Note: MSI vector takes value from 0 upto 31 (STMMAC_MSI_VEC_MAX) 1070 */ 1071 plat->msi_mac_vec = STMMAC_MSI_VEC_MAX; 1072 plat->msi_wol_vec = STMMAC_MSI_VEC_MAX; 1073 plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX; 1074 plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX; 1075 plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX; 1076 plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX; 1077 plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX; 1078 1079 ret = info->setup(pdev, plat); 1080 if (ret) 1081 return ret; 1082 1083 memset(&res, 0, sizeof(res)); 1084 res.addr = pcim_iomap_table(pdev)[0]; 1085 1086 if (plat->eee_usecs_rate > 0) { 1087 u32 tx_lpi_usec; 1088 1089 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1; 1090 writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER); 1091 } 1092 1093 ret = stmmac_config_multi_msi(pdev, plat, &res); 1094 if (ret) { 1095 ret = stmmac_config_single_msi(pdev, plat, &res); 1096 if (ret) { 1097 dev_err(&pdev->dev, "%s: ERROR: failed to enable IRQ\n", 1098 __func__); 1099 goto err_alloc_irq; 1100 } 1101 } 1102 1103 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); 1104 if (ret) { 1105 goto err_alloc_irq; 1106 } 1107 1108 return 0; 1109 1110 err_alloc_irq: 1111 clk_disable_unprepare(plat->stmmac_clk); 1112 clk_unregister_fixed_rate(plat->stmmac_clk); 1113 return ret; 1114 } 1115 1116 /** 1117 * intel_eth_pci_remove 1118 * 1119 * @pdev: pci device pointer 1120 * Description: this function calls the main to free the net resources 1121 * and releases the PCI resources. 1122 */ 1123 static void intel_eth_pci_remove(struct pci_dev *pdev) 1124 { 1125 struct net_device *ndev = dev_get_drvdata(&pdev->dev); 1126 struct stmmac_priv *priv = netdev_priv(ndev); 1127 1128 stmmac_dvr_remove(&pdev->dev); 1129 1130 clk_unregister_fixed_rate(priv->plat->stmmac_clk); 1131 1132 pcim_iounmap_regions(pdev, BIT(0)); 1133 } 1134 1135 static int __maybe_unused intel_eth_pci_suspend(struct device *dev) 1136 { 1137 struct pci_dev *pdev = to_pci_dev(dev); 1138 int ret; 1139 1140 ret = stmmac_suspend(dev); 1141 if (ret) 1142 return ret; 1143 1144 ret = pci_save_state(pdev); 1145 if (ret) 1146 return ret; 1147 1148 pci_wake_from_d3(pdev, true); 1149 pci_set_power_state(pdev, PCI_D3hot); 1150 return 0; 1151 } 1152 1153 static int __maybe_unused intel_eth_pci_resume(struct device *dev) 1154 { 1155 struct pci_dev *pdev = to_pci_dev(dev); 1156 int ret; 1157 1158 pci_restore_state(pdev); 1159 pci_set_power_state(pdev, PCI_D0); 1160 1161 ret = pcim_enable_device(pdev); 1162 if (ret) 1163 return ret; 1164 1165 pci_set_master(pdev); 1166 1167 return stmmac_resume(dev); 1168 } 1169 1170 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, 1171 intel_eth_pci_resume); 1172 1173 #define PCI_DEVICE_ID_INTEL_QUARK 0x0937 1174 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30 1175 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G 0x4b31 1176 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32 1177 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC 1178 * which are named PSE0 and PSE1 1179 */ 1180 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0 1181 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1 1182 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2 1183 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0 1184 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1 1185 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2 1186 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0 0x43ac 1187 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1 0x43a2 1188 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G 0xa0ac 1189 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0 0x7aac 1190 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1 0x7aad 1191 #define PCI_DEVICE_ID_INTEL_ADLN_SGMII1G 0x54ac 1192 #define PCI_DEVICE_ID_INTEL_RPLP_SGMII1G 0x51ac 1193 1194 static const struct pci_device_id intel_eth_pci_id_table[] = { 1195 { PCI_DEVICE_DATA(INTEL, QUARK, &quark_info) }, 1196 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, &ehl_rgmii1g_info) }, 1197 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, &ehl_sgmii1g_info) }, 1198 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, &ehl_sgmii1g_info) }, 1199 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, &ehl_pse0_rgmii1g_info) }, 1200 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, &ehl_pse0_sgmii1g_info) }, 1201 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, &ehl_pse0_sgmii1g_info) }, 1202 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, &ehl_pse1_rgmii1g_info) }, 1203 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, &ehl_pse1_sgmii1g_info) }, 1204 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, &ehl_pse1_sgmii1g_info) }, 1205 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, &tgl_sgmii1g_phy0_info) }, 1206 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, &tgl_sgmii1g_phy0_info) }, 1207 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) }, 1208 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) }, 1209 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) }, 1210 { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &tgl_sgmii1g_phy0_info) }, 1211 { PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &tgl_sgmii1g_phy0_info) }, 1212 {} 1213 }; 1214 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table); 1215 1216 static struct pci_driver intel_eth_pci_driver = { 1217 .name = "intel-eth-pci", 1218 .id_table = intel_eth_pci_id_table, 1219 .probe = intel_eth_pci_probe, 1220 .remove = intel_eth_pci_remove, 1221 .driver = { 1222 .pm = &intel_eth_pm_ops, 1223 }, 1224 }; 1225 1226 module_pci_driver(intel_eth_pci_driver); 1227 1228 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver"); 1229 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>"); 1230 MODULE_LICENSE("GPL v2"); 1231