1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Synopsys DWC Ethernet Quality-of-Service v4.10a linux driver 4 * 5 * Copyright (C) 2016 Joao Pinto <jpinto@synopsys.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/device.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/ethtool.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/ioport.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_net.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/platform_device.h> 21 #include <linux/reset.h> 22 #include <linux/stmmac.h> 23 24 #include "stmmac_platform.h" 25 #include "dwmac4.h" 26 27 struct tegra_eqos { 28 struct device *dev; 29 void __iomem *regs; 30 31 struct reset_control *rst; 32 struct clk *clk_master; 33 struct clk *clk_slave; 34 struct clk *clk_tx; 35 struct clk *clk_rx; 36 37 struct gpio_desc *reset; 38 }; 39 40 static int dwc_eth_dwmac_config_dt(struct platform_device *pdev, 41 struct plat_stmmacenet_data *plat_dat) 42 { 43 struct device *dev = &pdev->dev; 44 u32 burst_map = 0; 45 u32 bit_index = 0; 46 u32 a_index = 0; 47 48 if (!plat_dat->axi) { 49 plat_dat->axi = kzalloc(sizeof(struct stmmac_axi), GFP_KERNEL); 50 51 if (!plat_dat->axi) 52 return -ENOMEM; 53 } 54 55 plat_dat->axi->axi_lpi_en = device_property_read_bool(dev, 56 "snps,en-lpi"); 57 if (device_property_read_u32(dev, "snps,write-requests", 58 &plat_dat->axi->axi_wr_osr_lmt)) { 59 /** 60 * Since the register has a reset value of 1, if property 61 * is missing, default to 1. 62 */ 63 plat_dat->axi->axi_wr_osr_lmt = 1; 64 } else { 65 /** 66 * If property exists, to keep the behavior from dwc_eth_qos, 67 * subtract one after parsing. 68 */ 69 plat_dat->axi->axi_wr_osr_lmt--; 70 } 71 72 if (device_property_read_u32(dev, "snps,read-requests", 73 &plat_dat->axi->axi_rd_osr_lmt)) { 74 /** 75 * Since the register has a reset value of 1, if property 76 * is missing, default to 1. 77 */ 78 plat_dat->axi->axi_rd_osr_lmt = 1; 79 } else { 80 /** 81 * If property exists, to keep the behavior from dwc_eth_qos, 82 * subtract one after parsing. 83 */ 84 plat_dat->axi->axi_rd_osr_lmt--; 85 } 86 device_property_read_u32(dev, "snps,burst-map", &burst_map); 87 88 /* converts burst-map bitmask to burst array */ 89 for (bit_index = 0; bit_index < 7; bit_index++) { 90 if (burst_map & (1 << bit_index)) { 91 switch (bit_index) { 92 case 0: 93 plat_dat->axi->axi_blen[a_index] = 4; break; 94 case 1: 95 plat_dat->axi->axi_blen[a_index] = 8; break; 96 case 2: 97 plat_dat->axi->axi_blen[a_index] = 16; break; 98 case 3: 99 plat_dat->axi->axi_blen[a_index] = 32; break; 100 case 4: 101 plat_dat->axi->axi_blen[a_index] = 64; break; 102 case 5: 103 plat_dat->axi->axi_blen[a_index] = 128; break; 104 case 6: 105 plat_dat->axi->axi_blen[a_index] = 256; break; 106 default: 107 break; 108 } 109 a_index++; 110 } 111 } 112 113 /* dwc-qos needs GMAC4, AAL, TSO and PMT */ 114 plat_dat->has_gmac4 = 1; 115 plat_dat->dma_cfg->aal = 1; 116 plat_dat->flags |= STMMAC_FLAG_TSO_EN; 117 plat_dat->pmt = 1; 118 119 return 0; 120 } 121 122 static int dwc_qos_probe(struct platform_device *pdev, 123 struct plat_stmmacenet_data *plat_dat, 124 struct stmmac_resources *stmmac_res) 125 { 126 int err; 127 128 plat_dat->stmmac_clk = devm_clk_get(&pdev->dev, "apb_pclk"); 129 if (IS_ERR(plat_dat->stmmac_clk)) { 130 dev_err(&pdev->dev, "apb_pclk clock not found.\n"); 131 return PTR_ERR(plat_dat->stmmac_clk); 132 } 133 134 err = clk_prepare_enable(plat_dat->stmmac_clk); 135 if (err < 0) { 136 dev_err(&pdev->dev, "failed to enable apb_pclk clock: %d\n", 137 err); 138 return err; 139 } 140 141 plat_dat->pclk = devm_clk_get(&pdev->dev, "phy_ref_clk"); 142 if (IS_ERR(plat_dat->pclk)) { 143 dev_err(&pdev->dev, "phy_ref_clk clock not found.\n"); 144 err = PTR_ERR(plat_dat->pclk); 145 goto disable; 146 } 147 148 err = clk_prepare_enable(plat_dat->pclk); 149 if (err < 0) { 150 dev_err(&pdev->dev, "failed to enable phy_ref clock: %d\n", 151 err); 152 goto disable; 153 } 154 155 return 0; 156 157 disable: 158 clk_disable_unprepare(plat_dat->stmmac_clk); 159 return err; 160 } 161 162 static void dwc_qos_remove(struct platform_device *pdev) 163 { 164 struct net_device *ndev = platform_get_drvdata(pdev); 165 struct stmmac_priv *priv = netdev_priv(ndev); 166 167 clk_disable_unprepare(priv->plat->pclk); 168 clk_disable_unprepare(priv->plat->stmmac_clk); 169 } 170 171 #define SDMEMCOMPPADCTRL 0x8800 172 #define SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31) 173 174 #define AUTO_CAL_CONFIG 0x8804 175 #define AUTO_CAL_CONFIG_START BIT(31) 176 #define AUTO_CAL_CONFIG_ENABLE BIT(29) 177 178 #define AUTO_CAL_STATUS 0x880c 179 #define AUTO_CAL_STATUS_ACTIVE BIT(31) 180 181 static void tegra_eqos_fix_speed(void *priv, unsigned int speed, unsigned int mode) 182 { 183 struct tegra_eqos *eqos = priv; 184 bool needs_calibration = false; 185 long rate = 125000000; 186 u32 value; 187 int err; 188 189 switch (speed) { 190 case SPEED_1000: 191 case SPEED_100: 192 needs_calibration = true; 193 fallthrough; 194 195 case SPEED_10: 196 rate = rgmii_clock(speed); 197 break; 198 199 default: 200 dev_err(eqos->dev, "invalid speed %u\n", speed); 201 break; 202 } 203 204 if (needs_calibration) { 205 /* calibrate */ 206 value = readl(eqos->regs + SDMEMCOMPPADCTRL); 207 value |= SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD; 208 writel(value, eqos->regs + SDMEMCOMPPADCTRL); 209 210 udelay(1); 211 212 value = readl(eqos->regs + AUTO_CAL_CONFIG); 213 value |= AUTO_CAL_CONFIG_START | AUTO_CAL_CONFIG_ENABLE; 214 writel(value, eqos->regs + AUTO_CAL_CONFIG); 215 216 err = readl_poll_timeout_atomic(eqos->regs + AUTO_CAL_STATUS, 217 value, 218 value & AUTO_CAL_STATUS_ACTIVE, 219 1, 10); 220 if (err < 0) { 221 dev_err(eqos->dev, "calibration did not start\n"); 222 goto failed; 223 } 224 225 err = readl_poll_timeout_atomic(eqos->regs + AUTO_CAL_STATUS, 226 value, 227 (value & AUTO_CAL_STATUS_ACTIVE) == 0, 228 20, 200); 229 if (err < 0) { 230 dev_err(eqos->dev, "calibration didn't finish\n"); 231 goto failed; 232 } 233 234 failed: 235 value = readl(eqos->regs + SDMEMCOMPPADCTRL); 236 value &= ~SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD; 237 writel(value, eqos->regs + SDMEMCOMPPADCTRL); 238 } else { 239 value = readl(eqos->regs + AUTO_CAL_CONFIG); 240 value &= ~AUTO_CAL_CONFIG_ENABLE; 241 writel(value, eqos->regs + AUTO_CAL_CONFIG); 242 } 243 244 err = clk_set_rate(eqos->clk_tx, rate); 245 if (err < 0) 246 dev_err(eqos->dev, "failed to set TX rate: %d\n", err); 247 } 248 249 static int tegra_eqos_init(struct platform_device *pdev, void *priv) 250 { 251 struct tegra_eqos *eqos = priv; 252 unsigned long rate; 253 u32 value; 254 255 rate = clk_get_rate(eqos->clk_slave); 256 257 value = (rate / 1000000) - 1; 258 writel(value, eqos->regs + GMAC_1US_TIC_COUNTER); 259 260 return 0; 261 } 262 263 static int tegra_eqos_probe(struct platform_device *pdev, 264 struct plat_stmmacenet_data *data, 265 struct stmmac_resources *res) 266 { 267 struct device *dev = &pdev->dev; 268 struct tegra_eqos *eqos; 269 int err; 270 271 eqos = devm_kzalloc(&pdev->dev, sizeof(*eqos), GFP_KERNEL); 272 if (!eqos) 273 return -ENOMEM; 274 275 eqos->dev = &pdev->dev; 276 eqos->regs = res->addr; 277 278 if (!is_of_node(dev->fwnode)) 279 goto bypass_clk_reset_gpio; 280 281 eqos->clk_master = devm_clk_get(&pdev->dev, "master_bus"); 282 if (IS_ERR(eqos->clk_master)) { 283 err = PTR_ERR(eqos->clk_master); 284 goto error; 285 } 286 287 err = clk_prepare_enable(eqos->clk_master); 288 if (err < 0) 289 goto error; 290 291 eqos->clk_slave = devm_clk_get(&pdev->dev, "slave_bus"); 292 if (IS_ERR(eqos->clk_slave)) { 293 err = PTR_ERR(eqos->clk_slave); 294 goto disable_master; 295 } 296 297 data->stmmac_clk = eqos->clk_slave; 298 299 err = clk_prepare_enable(eqos->clk_slave); 300 if (err < 0) 301 goto disable_master; 302 303 eqos->clk_rx = devm_clk_get(&pdev->dev, "rx"); 304 if (IS_ERR(eqos->clk_rx)) { 305 err = PTR_ERR(eqos->clk_rx); 306 goto disable_slave; 307 } 308 309 err = clk_prepare_enable(eqos->clk_rx); 310 if (err < 0) 311 goto disable_slave; 312 313 eqos->clk_tx = devm_clk_get(&pdev->dev, "tx"); 314 if (IS_ERR(eqos->clk_tx)) { 315 err = PTR_ERR(eqos->clk_tx); 316 goto disable_rx; 317 } 318 319 err = clk_prepare_enable(eqos->clk_tx); 320 if (err < 0) 321 goto disable_rx; 322 323 eqos->reset = devm_gpiod_get(&pdev->dev, "phy-reset", GPIOD_OUT_HIGH); 324 if (IS_ERR(eqos->reset)) { 325 err = PTR_ERR(eqos->reset); 326 goto disable_tx; 327 } 328 329 usleep_range(2000, 4000); 330 gpiod_set_value(eqos->reset, 0); 331 332 /* MDIO bus was already reset just above */ 333 data->mdio_bus_data->needs_reset = false; 334 335 eqos->rst = devm_reset_control_get(&pdev->dev, "eqos"); 336 if (IS_ERR(eqos->rst)) { 337 err = PTR_ERR(eqos->rst); 338 goto reset_phy; 339 } 340 341 err = reset_control_assert(eqos->rst); 342 if (err < 0) 343 goto reset_phy; 344 345 usleep_range(2000, 4000); 346 347 err = reset_control_deassert(eqos->rst); 348 if (err < 0) 349 goto reset_phy; 350 351 usleep_range(2000, 4000); 352 353 bypass_clk_reset_gpio: 354 data->fix_mac_speed = tegra_eqos_fix_speed; 355 data->init = tegra_eqos_init; 356 data->bsp_priv = eqos; 357 data->flags |= STMMAC_FLAG_SPH_DISABLE; 358 359 err = tegra_eqos_init(pdev, eqos); 360 if (err < 0) 361 goto reset; 362 363 return 0; 364 reset: 365 reset_control_assert(eqos->rst); 366 reset_phy: 367 gpiod_set_value(eqos->reset, 1); 368 disable_tx: 369 clk_disable_unprepare(eqos->clk_tx); 370 disable_rx: 371 clk_disable_unprepare(eqos->clk_rx); 372 disable_slave: 373 clk_disable_unprepare(eqos->clk_slave); 374 disable_master: 375 clk_disable_unprepare(eqos->clk_master); 376 error: 377 return err; 378 } 379 380 static void tegra_eqos_remove(struct platform_device *pdev) 381 { 382 struct tegra_eqos *eqos = get_stmmac_bsp_priv(&pdev->dev); 383 384 reset_control_assert(eqos->rst); 385 gpiod_set_value(eqos->reset, 1); 386 clk_disable_unprepare(eqos->clk_tx); 387 clk_disable_unprepare(eqos->clk_rx); 388 clk_disable_unprepare(eqos->clk_slave); 389 clk_disable_unprepare(eqos->clk_master); 390 } 391 392 struct dwc_eth_dwmac_data { 393 int (*probe)(struct platform_device *pdev, 394 struct plat_stmmacenet_data *data, 395 struct stmmac_resources *res); 396 void (*remove)(struct platform_device *pdev); 397 }; 398 399 static const struct dwc_eth_dwmac_data dwc_qos_data = { 400 .probe = dwc_qos_probe, 401 .remove = dwc_qos_remove, 402 }; 403 404 static const struct dwc_eth_dwmac_data tegra_eqos_data = { 405 .probe = tegra_eqos_probe, 406 .remove = tegra_eqos_remove, 407 }; 408 409 static int dwc_eth_dwmac_probe(struct platform_device *pdev) 410 { 411 const struct dwc_eth_dwmac_data *data; 412 struct plat_stmmacenet_data *plat_dat; 413 struct stmmac_resources stmmac_res; 414 int ret; 415 416 data = device_get_match_data(&pdev->dev); 417 418 memset(&stmmac_res, 0, sizeof(struct stmmac_resources)); 419 420 /** 421 * Since stmmac_platform supports name IRQ only, basic platform 422 * resource initialization is done in the glue logic. 423 */ 424 stmmac_res.irq = platform_get_irq(pdev, 0); 425 if (stmmac_res.irq < 0) 426 return stmmac_res.irq; 427 stmmac_res.wol_irq = stmmac_res.irq; 428 429 stmmac_res.addr = devm_platform_ioremap_resource(pdev, 0); 430 if (IS_ERR(stmmac_res.addr)) 431 return PTR_ERR(stmmac_res.addr); 432 433 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 434 if (IS_ERR(plat_dat)) 435 return PTR_ERR(plat_dat); 436 437 ret = data->probe(pdev, plat_dat, &stmmac_res); 438 if (ret < 0) { 439 dev_err_probe(&pdev->dev, ret, "failed to probe subdriver\n"); 440 return ret; 441 } 442 443 ret = dwc_eth_dwmac_config_dt(pdev, plat_dat); 444 if (ret) 445 goto remove; 446 447 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 448 if (ret) 449 goto remove; 450 451 return ret; 452 453 remove: 454 data->remove(pdev); 455 456 return ret; 457 } 458 459 static void dwc_eth_dwmac_remove(struct platform_device *pdev) 460 { 461 const struct dwc_eth_dwmac_data *data = device_get_match_data(&pdev->dev); 462 463 stmmac_dvr_remove(&pdev->dev); 464 465 data->remove(pdev); 466 } 467 468 static const struct of_device_id dwc_eth_dwmac_match[] = { 469 { .compatible = "snps,dwc-qos-ethernet-4.10", .data = &dwc_qos_data }, 470 { .compatible = "nvidia,tegra186-eqos", .data = &tegra_eqos_data }, 471 { } 472 }; 473 MODULE_DEVICE_TABLE(of, dwc_eth_dwmac_match); 474 475 static struct platform_driver dwc_eth_dwmac_driver = { 476 .probe = dwc_eth_dwmac_probe, 477 .remove = dwc_eth_dwmac_remove, 478 .driver = { 479 .name = "dwc-eth-dwmac", 480 .pm = &stmmac_pltfr_pm_ops, 481 .of_match_table = dwc_eth_dwmac_match, 482 }, 483 }; 484 module_platform_driver(dwc_eth_dwmac_driver); 485 486 MODULE_AUTHOR("Joao Pinto <jpinto@synopsys.com>"); 487 MODULE_DESCRIPTION("Synopsys DWC Ethernet Quality-of-Service v4.10a driver"); 488 MODULE_LICENSE("GPL v2"); 489