1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 Header File to describe the DMA descriptors and related definitions. 4 This is for DWMAC100 and 1000 cores. 5 6 7 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 8 *******************************************************************************/ 9 10 #ifndef __DESCS_H__ 11 #define __DESCS_H__ 12 13 #include <linux/bitops.h> 14 15 /* Normal receive descriptor defines */ 16 17 /* RDES0 */ 18 #define RDES0_PAYLOAD_CSUM_ERR BIT(0) 19 #define RDES0_CRC_ERROR BIT(1) 20 #define RDES0_DRIBBLING BIT(2) 21 #define RDES0_MII_ERROR BIT(3) 22 #define RDES0_RECEIVE_WATCHDOG BIT(4) 23 #define RDES0_FRAME_TYPE BIT(5) 24 #define RDES0_COLLISION BIT(6) 25 #define RDES0_IPC_CSUM_ERROR BIT(7) 26 #define RDES0_LAST_DESCRIPTOR BIT(8) 27 #define RDES0_FIRST_DESCRIPTOR BIT(9) 28 #define RDES0_VLAN_TAG BIT(10) 29 #define RDES0_OVERFLOW_ERROR BIT(11) 30 #define RDES0_LENGTH_ERROR BIT(12) 31 #define RDES0_SA_FILTER_FAIL BIT(13) 32 #define RDES0_DESCRIPTOR_ERROR BIT(14) 33 #define RDES0_ERROR_SUMMARY BIT(15) 34 #define RDES0_FRAME_LEN_MASK GENMASK(29, 16) 35 #define RDES0_DA_FILTER_FAIL BIT(30) 36 #define RDES0_OWN BIT(31) 37 /* RDES1 */ 38 #define RDES1_BUFFER1_SIZE_MASK GENMASK(10, 0) 39 #define RDES1_BUFFER2_SIZE_MASK GENMASK(21, 11) 40 #define RDES1_SECOND_ADDRESS_CHAINED BIT(24) 41 #define RDES1_END_RING BIT(25) 42 #define RDES1_DISABLE_IC BIT(31) 43 44 /* Enhanced receive descriptor defines */ 45 46 /* RDES0 (similar to normal RDES) */ 47 #define ERDES0_RX_MAC_ADDR BIT(0) 48 49 /* RDES1: completely differ from normal desc definitions */ 50 #define ERDES1_BUFFER1_SIZE_MASK GENMASK(12, 0) 51 #define ERDES1_SECOND_ADDRESS_CHAINED BIT(14) 52 #define ERDES1_END_RING BIT(15) 53 #define ERDES1_BUFFER2_SIZE_MASK GENMASK(28, 16) 54 #define ERDES1_DISABLE_IC BIT(31) 55 56 /* Normal transmit descriptor defines */ 57 /* TDES0 */ 58 #define TDES0_DEFERRED BIT(0) 59 #define TDES0_UNDERFLOW_ERROR BIT(1) 60 #define TDES0_EXCESSIVE_DEFERRAL BIT(2) 61 #define TDES0_COLLISION_COUNT_MASK GENMASK(6, 3) 62 #define TDES0_VLAN_FRAME BIT(7) 63 #define TDES0_EXCESSIVE_COLLISIONS BIT(8) 64 #define TDES0_LATE_COLLISION BIT(9) 65 #define TDES0_NO_CARRIER BIT(10) 66 #define TDES0_LOSS_CARRIER BIT(11) 67 #define TDES0_PAYLOAD_ERROR BIT(12) 68 #define TDES0_FRAME_FLUSHED BIT(13) 69 #define TDES0_JABBER_TIMEOUT BIT(14) 70 #define TDES0_ERROR_SUMMARY BIT(15) 71 #define TDES0_IP_HEADER_ERROR BIT(16) 72 #define TDES0_TIME_STAMP_STATUS BIT(17) 73 #define TDES0_OWN ((u32)BIT(31)) /* silence sparse */ 74 /* TDES1 */ 75 #define TDES1_BUFFER1_SIZE_MASK GENMASK(10, 0) 76 #define TDES1_BUFFER2_SIZE_MASK GENMASK(21, 11) 77 #define TDES1_TIME_STAMP_ENABLE BIT(22) 78 #define TDES1_DISABLE_PADDING BIT(23) 79 #define TDES1_SECOND_ADDRESS_CHAINED BIT(24) 80 #define TDES1_END_RING BIT(25) 81 #define TDES1_CRC_DISABLE BIT(26) 82 #define TDES1_CHECKSUM_INSERTION_MASK GENMASK(28, 27) 83 #define TDES1_FIRST_SEGMENT BIT(29) 84 #define TDES1_LAST_SEGMENT BIT(30) 85 #define TDES1_INTERRUPT BIT(31) 86 87 /* Enhanced transmit descriptor defines */ 88 /* TDES0 */ 89 #define ETDES0_DEFERRED BIT(0) 90 #define ETDES0_UNDERFLOW_ERROR BIT(1) 91 #define ETDES0_EXCESSIVE_DEFERRAL BIT(2) 92 #define ETDES0_COLLISION_COUNT_MASK GENMASK(6, 3) 93 #define ETDES0_VLAN_FRAME BIT(7) 94 #define ETDES0_EXCESSIVE_COLLISIONS BIT(8) 95 #define ETDES0_LATE_COLLISION BIT(9) 96 #define ETDES0_NO_CARRIER BIT(10) 97 #define ETDES0_LOSS_CARRIER BIT(11) 98 #define ETDES0_PAYLOAD_ERROR BIT(12) 99 #define ETDES0_FRAME_FLUSHED BIT(13) 100 #define ETDES0_JABBER_TIMEOUT BIT(14) 101 #define ETDES0_ERROR_SUMMARY BIT(15) 102 #define ETDES0_IP_HEADER_ERROR BIT(16) 103 #define ETDES0_TIME_STAMP_STATUS BIT(17) 104 #define ETDES0_SECOND_ADDRESS_CHAINED BIT(20) 105 #define ETDES0_END_RING BIT(21) 106 #define ETDES0_CHECKSUM_INSERTION_MASK GENMASK(23, 22) 107 #define ETDES0_TIME_STAMP_ENABLE BIT(25) 108 #define ETDES0_DISABLE_PADDING BIT(26) 109 #define ETDES0_CRC_DISABLE BIT(27) 110 #define ETDES0_FIRST_SEGMENT BIT(28) 111 #define ETDES0_LAST_SEGMENT BIT(29) 112 #define ETDES0_INTERRUPT BIT(30) 113 #define ETDES0_OWN ((u32)BIT(31)) /* silence sparse */ 114 /* TDES1 */ 115 #define ETDES1_BUFFER1_SIZE_MASK GENMASK(12, 0) 116 #define ETDES1_BUFFER2_SIZE_MASK GENMASK(28, 16) 117 118 /* Extended Receive descriptor definitions */ 119 #define ERDES4_IP_PAYLOAD_TYPE_MASK GENMASK(6, 2) 120 #define ERDES4_IP_HDR_ERR BIT(3) 121 #define ERDES4_IP_PAYLOAD_ERR BIT(4) 122 #define ERDES4_IP_CSUM_BYPASSED BIT(5) 123 #define ERDES4_IPV4_PKT_RCVD BIT(6) 124 #define ERDES4_IPV6_PKT_RCVD BIT(7) 125 #define ERDES4_MSG_TYPE_MASK GENMASK(11, 8) 126 #define ERDES4_PTP_FRAME_TYPE BIT(12) 127 #define ERDES4_PTP_VER BIT(13) 128 #define ERDES4_TIMESTAMP_DROPPED BIT(14) 129 #define ERDES4_AV_PKT_RCVD BIT(16) 130 #define ERDES4_AV_TAGGED_PKT_RCVD BIT(17) 131 #define ERDES4_VLAN_TAG_PRI_VAL_MASK GENMASK(20, 18) 132 #define ERDES4_L3_FILTER_MATCH BIT(24) 133 #define ERDES4_L4_FILTER_MATCH BIT(25) 134 #define ERDES4_L3_L4_FILT_NO_MATCH_MASK GENMASK(27, 26) 135 136 /* Extended RDES4 message type definitions */ 137 #define RDES_EXT_NO_PTP 0x0 138 #define RDES_EXT_SYNC 0x1 139 #define RDES_EXT_FOLLOW_UP 0x2 140 #define RDES_EXT_DELAY_REQ 0x3 141 #define RDES_EXT_DELAY_RESP 0x4 142 #define RDES_EXT_PDELAY_REQ 0x5 143 #define RDES_EXT_PDELAY_RESP 0x6 144 #define RDES_EXT_PDELAY_FOLLOW_UP 0x7 145 #define RDES_PTP_ANNOUNCE 0x8 146 #define RDES_PTP_MANAGEMENT 0x9 147 #define RDES_PTP_SIGNALING 0xa 148 #define RDES_PTP_PKT_RESERVED_TYPE 0xf 149 150 /* Basic descriptor structure for normal and alternate descriptors */ 151 struct dma_desc { 152 __le32 des0; 153 __le32 des1; 154 __le32 des2; 155 __le32 des3; 156 }; 157 158 /* Extended descriptor structure (e.g. >= databook 3.50a) */ 159 struct dma_extended_desc { 160 struct dma_desc basic; /* Basic descriptors */ 161 __le32 des4; /* Extended Status */ 162 __le32 des5; /* Reserved */ 163 __le32 des6; /* Tx/Rx Timestamp Low */ 164 __le32 des7; /* Tx/Rx Timestamp High */ 165 }; 166 167 /* Enhanced descriptor for TBS */ 168 struct dma_edesc { 169 __le32 des4; 170 __le32 des5; 171 __le32 des6; 172 __le32 des7; 173 struct dma_desc basic; 174 }; 175 176 /* Transmit checksum insertion control */ 177 #define TX_CIC_FULL 3 /* Include IP header and pseudoheader */ 178 179 #endif /* __DESCS_H__ */ 180