1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 STMMAC Common Header File 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #ifndef __COMMON_H__ 12 #define __COMMON_H__ 13 14 #include <linux/etherdevice.h> 15 #include <linux/netdevice.h> 16 #include <linux/stmmac.h> 17 #include <linux/phy.h> 18 #include <linux/pcs/pcs-xpcs.h> 19 #include <linux/module.h> 20 #if IS_ENABLED(CONFIG_VLAN_8021Q) 21 #define STMMAC_VLAN_TAG_USED 22 #include <linux/if_vlan.h> 23 #endif 24 25 #include "descs.h" 26 #include "hwif.h" 27 #include "mmc.h" 28 29 #define DWMAC_SNPSVER GENMASK_U32(7, 0) 30 #define DWMAC_USERVER GENMASK_U32(15, 8) 31 32 /* Synopsys Core versions */ 33 #define DWMAC_CORE_3_40 0x34 34 #define DWMAC_CORE_3_50 0x35 35 #define DWMAC_CORE_3_70 0x37 36 #define DWMAC_CORE_4_00 0x40 37 #define DWMAC_CORE_4_10 0x41 38 #define DWMAC_CORE_5_00 0x50 39 #define DWMAC_CORE_5_10 0x51 40 #define DWMAC_CORE_5_20 0x52 41 #define DWXGMAC_CORE_2_10 0x21 42 #define DWXGMAC_CORE_2_20 0x22 43 #define DWXLGMAC_CORE_2_00 0x20 44 45 /* Device ID */ 46 #define DWXGMAC_ID 0x76 47 #define DWXLGMAC_ID 0x27 48 49 static inline bool dwmac_is_xmac(enum dwmac_core_type core_type) 50 { 51 return core_type == DWMAC_CORE_GMAC4 || core_type == DWMAC_CORE_XGMAC; 52 } 53 54 #define STMMAC_CHAN0 0 /* Always supported and default for all chips */ 55 56 /* TX and RX Descriptor Length, these need to be power of two. 57 * TX descriptor length less than 64 may cause transmit queue timed out error. 58 * RX descriptor length less than 64 may cause inconsistent Rx chain error. 59 */ 60 #define DMA_MIN_TX_SIZE 64 61 #define DMA_MAX_TX_SIZE 1024 62 #define DMA_DEFAULT_TX_SIZE 512 63 #define DMA_MIN_RX_SIZE 64 64 #define DMA_MAX_RX_SIZE 1024 65 #define DMA_DEFAULT_RX_SIZE 512 66 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1)) 67 68 #undef FRAME_FILTER_DEBUG 69 /* #define FRAME_FILTER_DEBUG */ 70 71 struct stmmac_q_tx_stats { 72 u64_stats_t tx_bytes; 73 u64_stats_t tx_set_ic_bit; 74 u64_stats_t tx_tso_frames; 75 u64_stats_t tx_tso_nfrags; 76 }; 77 78 struct stmmac_napi_tx_stats { 79 u64_stats_t tx_packets; 80 u64_stats_t tx_pkt_n; 81 u64_stats_t poll; 82 u64_stats_t tx_clean; 83 u64_stats_t tx_set_ic_bit; 84 }; 85 86 struct stmmac_txq_stats { 87 /* Updates protected by tx queue lock. */ 88 struct u64_stats_sync q_syncp; 89 struct stmmac_q_tx_stats q; 90 91 /* Updates protected by NAPI poll logic. */ 92 struct u64_stats_sync napi_syncp; 93 struct stmmac_napi_tx_stats napi; 94 } ____cacheline_aligned_in_smp; 95 96 struct stmmac_napi_rx_stats { 97 u64_stats_t rx_bytes; 98 u64_stats_t rx_packets; 99 u64_stats_t rx_pkt_n; 100 u64_stats_t poll; 101 }; 102 103 struct stmmac_rxq_stats { 104 /* Updates protected by NAPI poll logic. */ 105 struct u64_stats_sync napi_syncp; 106 struct stmmac_napi_rx_stats napi; 107 } ____cacheline_aligned_in_smp; 108 109 /* Updates on each CPU protected by not allowing nested irqs. */ 110 struct stmmac_pcpu_stats { 111 struct u64_stats_sync syncp; 112 u64_stats_t rx_normal_irq_n[MTL_MAX_RX_QUEUES]; 113 u64_stats_t tx_normal_irq_n[MTL_MAX_TX_QUEUES]; 114 }; 115 116 /* Extra statistic and debug information exposed by ethtool */ 117 struct stmmac_extra_stats { 118 /* Transmit errors */ 119 unsigned long tx_underflow ____cacheline_aligned; 120 unsigned long tx_carrier; 121 unsigned long tx_losscarrier; 122 unsigned long vlan_tag; 123 unsigned long tx_deferred; 124 unsigned long tx_vlan; 125 unsigned long tx_jabber; 126 unsigned long tx_frame_flushed; 127 unsigned long tx_payload_error; 128 unsigned long tx_ip_header_error; 129 unsigned long tx_collision; 130 /* Receive errors */ 131 unsigned long rx_desc; 132 unsigned long sa_filter_fail; 133 unsigned long overflow_error; 134 unsigned long ipc_csum_error; 135 unsigned long rx_collision; 136 unsigned long rx_crc_errors; 137 unsigned long dribbling_bit; 138 unsigned long rx_length; 139 unsigned long rx_mii; 140 unsigned long rx_multicast; 141 unsigned long rx_gmac_overflow; 142 unsigned long rx_watchdog; 143 unsigned long da_rx_filter_fail; 144 unsigned long sa_rx_filter_fail; 145 unsigned long rx_missed_cntr; 146 unsigned long rx_overflow_cntr; 147 unsigned long rx_vlan; 148 unsigned long rx_split_hdr_pkt_n; 149 /* Tx/Rx IRQ error info */ 150 unsigned long tx_undeflow_irq; 151 unsigned long tx_process_stopped_irq; 152 unsigned long tx_jabber_irq; 153 unsigned long rx_overflow_irq; 154 unsigned long rx_buf_unav_irq; 155 unsigned long rx_process_stopped_irq; 156 unsigned long rx_watchdog_irq; 157 unsigned long tx_early_irq; 158 unsigned long fatal_bus_error_irq; 159 /* Tx/Rx IRQ Events */ 160 unsigned long rx_early_irq; 161 unsigned long threshold; 162 unsigned long irq_receive_pmt_irq_n; 163 /* MMC info */ 164 unsigned long mmc_tx_irq_n; 165 unsigned long mmc_rx_irq_n; 166 unsigned long mmc_rx_csum_offload_irq_n; 167 /* EEE */ 168 unsigned long irq_tx_path_in_lpi_mode_n; 169 unsigned long irq_tx_path_exit_lpi_mode_n; 170 unsigned long irq_rx_path_in_lpi_mode_n; 171 unsigned long irq_rx_path_exit_lpi_mode_n; 172 unsigned long phy_eee_wakeup_error_n; 173 /* Extended RDES status */ 174 unsigned long ip_hdr_err; 175 unsigned long ip_payload_err; 176 unsigned long ip_csum_bypassed; 177 unsigned long ipv4_pkt_rcvd; 178 unsigned long ipv6_pkt_rcvd; 179 unsigned long no_ptp_rx_msg_type_ext; 180 unsigned long ptp_rx_msg_type_sync; 181 unsigned long ptp_rx_msg_type_follow_up; 182 unsigned long ptp_rx_msg_type_delay_req; 183 unsigned long ptp_rx_msg_type_delay_resp; 184 unsigned long ptp_rx_msg_type_pdelay_req; 185 unsigned long ptp_rx_msg_type_pdelay_resp; 186 unsigned long ptp_rx_msg_type_pdelay_follow_up; 187 unsigned long ptp_rx_msg_type_announce; 188 unsigned long ptp_rx_msg_type_management; 189 unsigned long ptp_rx_msg_pkt_reserved_type; 190 unsigned long ptp_frame_type; 191 unsigned long ptp_ver; 192 unsigned long timestamp_dropped; 193 unsigned long av_pkt_rcvd; 194 unsigned long av_tagged_pkt_rcvd; 195 unsigned long vlan_tag_priority_val; 196 unsigned long l3_filter_match; 197 unsigned long l4_filter_match; 198 unsigned long l3_l4_filter_no_match; 199 /* PCS */ 200 unsigned long irq_pcs_ane_n; 201 unsigned long irq_pcs_link_n; 202 unsigned long irq_rgmii_n; 203 /* debug register */ 204 unsigned long mtl_tx_status_fifo_full; 205 unsigned long mtl_tx_fifo_not_empty; 206 unsigned long mmtl_fifo_ctrl; 207 unsigned long mtl_tx_fifo_read_ctrl_write; 208 unsigned long mtl_tx_fifo_read_ctrl_wait; 209 unsigned long mtl_tx_fifo_read_ctrl_read; 210 unsigned long mtl_tx_fifo_read_ctrl_idle; 211 unsigned long mac_tx_in_pause; 212 unsigned long mac_tx_frame_ctrl_xfer; 213 unsigned long mac_tx_frame_ctrl_idle; 214 unsigned long mac_tx_frame_ctrl_wait; 215 unsigned long mac_tx_frame_ctrl_pause; 216 unsigned long mac_gmii_tx_proto_engine; 217 unsigned long mtl_rx_fifo_fill_level_full; 218 unsigned long mtl_rx_fifo_fill_above_thresh; 219 unsigned long mtl_rx_fifo_fill_below_thresh; 220 unsigned long mtl_rx_fifo_fill_level_empty; 221 unsigned long mtl_rx_fifo_read_ctrl_flush; 222 unsigned long mtl_rx_fifo_read_ctrl_read_data; 223 unsigned long mtl_rx_fifo_read_ctrl_status; 224 unsigned long mtl_rx_fifo_read_ctrl_idle; 225 unsigned long mtl_rx_fifo_ctrl_active; 226 unsigned long mac_rx_frame_ctrl_fifo; 227 unsigned long mac_gmii_rx_proto_engine; 228 /* EST */ 229 unsigned long mtl_est_cgce; 230 unsigned long mtl_est_hlbs; 231 unsigned long mtl_est_hlbf; 232 unsigned long mtl_est_btre; 233 unsigned long mtl_est_btrlm; 234 unsigned long max_sdu_txq_drop[MTL_MAX_TX_QUEUES]; 235 unsigned long mtl_est_txq_hlbf[MTL_MAX_TX_QUEUES]; 236 unsigned long mtl_est_txq_hlbs[MTL_MAX_TX_QUEUES]; 237 /* per queue statistics */ 238 struct stmmac_txq_stats txq_stats[MTL_MAX_TX_QUEUES]; 239 struct stmmac_rxq_stats rxq_stats[MTL_MAX_RX_QUEUES]; 240 struct stmmac_pcpu_stats __percpu *pcpu_stats; 241 unsigned long rx_dropped; 242 unsigned long rx_errors; 243 unsigned long tx_dropped; 244 unsigned long tx_errors; 245 }; 246 247 /* Safety Feature statistics exposed by ethtool */ 248 struct stmmac_safety_stats { 249 unsigned long mac_errors[32]; 250 unsigned long mtl_errors[32]; 251 unsigned long dma_errors[32]; 252 unsigned long dma_dpp_errors[32]; 253 }; 254 255 /* Number of fields in Safety Stats */ 256 #define STMMAC_SAFETY_FEAT_SIZE \ 257 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long)) 258 259 /* CSR Frequency Access Defines*/ 260 #define CSR_F_35M 35000000 261 #define CSR_F_60M 60000000 262 #define CSR_F_100M 100000000 263 #define CSR_F_150M 150000000 264 #define CSR_F_250M 250000000 265 #define CSR_F_300M 300000000 266 #define CSR_F_500M 500000000 267 #define CSR_F_800M 800000000 268 269 #define MAC_CSR_H_FRQ_MASK 0x20 270 271 #define HASH_TABLE_SIZE 64 272 #define PAUSE_TIME 0xffff 273 274 /* Flow Control defines */ 275 #define FLOW_OFF 0 276 #define FLOW_RX 1 277 #define FLOW_TX 2 278 #define FLOW_AUTO (FLOW_TX | FLOW_RX) 279 280 /* PCS defines */ 281 #define STMMAC_PCS_SGMII (1 << 1) 282 283 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ 284 285 /* DMA HW feature register fields */ 286 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */ 287 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */ 288 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */ 289 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */ 290 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */ 291 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */ 292 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */ 293 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */ 294 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */ 295 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */ 296 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */ 297 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */ 298 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */ 299 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */ 300 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */ 301 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */ 302 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */ 303 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */ 304 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */ 305 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */ 306 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */ 307 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */ 308 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */ 309 /* Timestamping with Internal System Time */ 310 #define DMA_HW_FEAT_INTTSEN 0x02000000 311 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */ 312 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */ 313 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */ 314 #define DEFAULT_DMA_PBL 8 315 316 /* phy_intf_sel_i and ACTPHYIF encodings */ 317 #define PHY_INTF_SEL_GMII_MII 0 318 #define PHY_INTF_SEL_RGMII 1 319 #define PHY_INTF_SEL_SGMII 2 320 #define PHY_INTF_SEL_TBI 3 321 #define PHY_INTF_SEL_RMII 4 322 #define PHY_INTF_SEL_RTBI 5 323 #define PHY_INTF_SEL_SMII 6 324 #define PHY_INTF_SEL_REVMII 7 325 326 /* MSI defines */ 327 #define STMMAC_MSI_VEC_MAX 32 328 329 /* PCS status and mask defines */ 330 #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */ 331 #define PCS_LINK_IRQ BIT(1) /* PCS Link */ 332 #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */ 333 334 /* Max/Min RI Watchdog Timer count value */ 335 #define MAX_DMA_RIWT 0xff 336 #define MIN_DMA_RIWT 0x10 337 #define DEF_DMA_RIWT 0xa0 338 /* Tx coalesce parameters */ 339 #define STMMAC_COAL_TX_TIMER 5000 340 #define STMMAC_MAX_COAL_TX_TICK 100000 341 #define STMMAC_TX_MAX_FRAMES 256 342 #define STMMAC_TX_FRAMES 25 343 #define STMMAC_RX_FRAMES 0 344 345 /* Packets types */ 346 enum packets_types { 347 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */ 348 PACKET_PTPQ = 0x2, /* PTP Packets */ 349 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */ 350 PACKET_UPQ = 0x4, /* Untagged Packets */ 351 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */ 352 }; 353 354 /* Rx IPC status */ 355 enum rx_frame_status { 356 good_frame = 0x0, 357 discard_frame = 0x1, 358 csum_none = 0x2, 359 llc_snap = 0x4, 360 dma_own = 0x8, 361 rx_not_ls = 0x10, 362 }; 363 364 /* Tx status */ 365 enum tx_frame_status { 366 tx_done = 0x0, 367 tx_not_ls = 0x1, 368 tx_err = 0x2, 369 tx_dma_own = 0x4, 370 tx_err_bump_tc = 0x8, 371 }; 372 373 enum dma_irq_status { 374 tx_hard_error = 0x1, 375 tx_hard_error_bump_tc = 0x2, 376 handle_rx = 0x4, 377 handle_tx = 0x8, 378 }; 379 380 enum dma_irq_dir { 381 DMA_DIR_RX = 0x1, 382 DMA_DIR_TX = 0x2, 383 DMA_DIR_RXTX = 0x3, 384 }; 385 386 enum request_irq_err { 387 REQ_IRQ_ERR_ALL, 388 REQ_IRQ_ERR_TX, 389 REQ_IRQ_ERR_RX, 390 REQ_IRQ_ERR_SFTY, 391 REQ_IRQ_ERR_SFTY_UE, 392 REQ_IRQ_ERR_SFTY_CE, 393 REQ_IRQ_ERR_LPI, 394 REQ_IRQ_ERR_WOL, 395 REQ_IRQ_ERR_MAC, 396 REQ_IRQ_ERR_NO, 397 }; 398 399 /* EEE and LPI defines */ 400 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0) 401 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1) 402 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2) 403 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3) 404 405 /* FPE defines */ 406 #define FPE_EVENT_UNKNOWN 0 407 #define FPE_EVENT_TRSP BIT(0) 408 #define FPE_EVENT_TVER BIT(1) 409 #define FPE_EVENT_RRSP BIT(2) 410 #define FPE_EVENT_RVER BIT(3) 411 412 #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8) 413 414 /* DMA HW capabilities */ 415 struct dma_features { 416 unsigned int mbps_10_100; 417 unsigned int mbps_1000; 418 unsigned int half_duplex; 419 unsigned int hash_filter; 420 unsigned int multi_addr; 421 unsigned int pcs; 422 unsigned int sma_mdio; 423 unsigned int pmt_remote_wake_up; 424 unsigned int pmt_magic_frame; 425 unsigned int rmon; 426 /* IEEE 1588-2002 */ 427 unsigned int time_stamp; 428 /* IEEE 1588-2008 */ 429 unsigned int atime_stamp; 430 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 431 unsigned int eee; 432 unsigned int av; 433 unsigned int hash_tb_sz; 434 unsigned int tsoen; 435 /* TX and RX csum */ 436 unsigned int tx_coe; 437 unsigned int rx_coe; 438 unsigned int rx_coe_type1; 439 unsigned int rx_coe_type2; 440 unsigned int rxfifo_over_2048; 441 /* TX and RX number of channels */ 442 unsigned int number_rx_channel; 443 unsigned int number_tx_channel; 444 /* TX and RX number of queues */ 445 unsigned int number_rx_queues; 446 unsigned int number_tx_queues; 447 /* PPS output */ 448 unsigned int pps_out_num; 449 /* Number of Traffic Classes */ 450 unsigned int numtc; 451 /* DCB Feature Enable */ 452 unsigned int dcben; 453 /* IEEE 1588 High Word Register Enable */ 454 unsigned int advthword; 455 /* PTP Offload Enable */ 456 unsigned int ptoen; 457 /* One-Step Timestamping Enable */ 458 unsigned int osten; 459 /* Priority-Based Flow Control Enable */ 460 unsigned int pfcen; 461 /* Alternate (enhanced) DESC mode */ 462 unsigned int enh_desc; 463 /* TX and RX FIFO sizes */ 464 unsigned int tx_fifo_size; 465 unsigned int rx_fifo_size; 466 /* Automotive Safety Package */ 467 unsigned int asp; 468 /* RX Parser */ 469 unsigned int frpsel; 470 unsigned int frpbs; 471 unsigned int frpes; 472 unsigned int addr64; 473 unsigned int host_dma_width; 474 unsigned int rssen; 475 unsigned int vlhash; 476 unsigned int sphen; 477 unsigned int vlins; 478 unsigned int dvlan; 479 unsigned int l3l4fnum; 480 unsigned int arpoffsel; 481 /* One Step for PTP over UDP/IP Feature Enable */ 482 unsigned int pou_ost_en; 483 /* Tx Timestamp FIFO Depth */ 484 unsigned int ttsfd; 485 /* Queue/Channel-Based VLAN tag insertion on Tx */ 486 unsigned int cbtisel; 487 /* Supported Parallel Instruction Processor Engines */ 488 unsigned int frppipe_num; 489 /* Number of Extended VLAN Tag Filters */ 490 unsigned int nrvf_num; 491 /* TSN Features */ 492 unsigned int estwid; 493 unsigned int estdep; 494 unsigned int estsel; 495 unsigned int fpesel; 496 unsigned int tbssel; 497 /* Number of DMA channels enabled for TBS */ 498 unsigned int tbs_ch_num; 499 /* Per-Stream Filtering Enable */ 500 unsigned int sgfsel; 501 /* Numbers of Auxiliary Snapshot Inputs */ 502 unsigned int aux_snapshot_n; 503 /* Timestamp System Time Source */ 504 unsigned int tssrc; 505 /* Enhanced DMA Enable */ 506 unsigned int edma; 507 /* Different Descriptor Cache Enable */ 508 unsigned int ediffc; 509 /* VxLAN/NVGRE Enable */ 510 unsigned int vxn; 511 /* Debug Memory Interface Enable */ 512 unsigned int dbgmem; 513 /* Number of Policing Counters */ 514 unsigned int pcsel; 515 }; 516 517 /* RX Buffer size must be multiple of 4/8/16 bytes */ 518 #define BUF_SIZE_16KiB 16368 519 #define BUF_SIZE_8KiB 8188 520 #define BUF_SIZE_4KiB 4096 521 #define BUF_SIZE_2KiB 2048 522 523 /* Power Down and WOL */ 524 #define PMT_NOT_SUPPORTED 0 525 #define PMT_SUPPORTED 1 526 527 /* Common MAC defines */ 528 #define MAC_CTRL_REG 0x00000000 /* MAC Control */ 529 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ 530 #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */ 531 532 /* Default LPI timers */ 533 #define STMMAC_DEFAULT_LIT_LS 0x3E8 534 #define STMMAC_DEFAULT_TWT_LS 0x1E 535 #define STMMAC_ET_MAX 0xFFFFF 536 537 /* Common LPI register bits */ 538 #define LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable, gmac4, xgmac2 only */ 539 #define LPI_CTRL_STATUS_LPIATE BIT(20) /* LPI Timer Enable, gmac4 only */ 540 #define LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */ 541 #define LPI_CTRL_STATUS_PLSEN BIT(18) /* Enable PHY Link Status */ 542 #define LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */ 543 #define LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */ 544 #define LPI_CTRL_STATUS_RLPIST BIT(9) /* Receive LPI state, gmac1000 only? */ 545 #define LPI_CTRL_STATUS_TLPIST BIT(8) /* Transmit LPI state, gmac1000 only? */ 546 #define LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */ 547 #define LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */ 548 #define LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */ 549 #define LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */ 550 551 /* Common definitions for AXI Master Bus Mode */ 552 #define DMA_AXI_AAL BIT(12) 553 #define DMA_AXI_BLEN256 BIT(7) 554 #define DMA_AXI_BLEN128 BIT(6) 555 #define DMA_AXI_BLEN64 BIT(5) 556 #define DMA_AXI_BLEN32 BIT(4) 557 #define DMA_AXI_BLEN16 BIT(3) 558 #define DMA_AXI_BLEN8 BIT(2) 559 #define DMA_AXI_BLEN4 BIT(1) 560 #define DMA_AXI_BLEN_MASK GENMASK(7, 1) 561 562 void stmmac_axi_blen_to_mask(u32 *regval, const u32 *blen, size_t len); 563 564 #define STMMAC_CHAIN_MODE 0x1 565 #define STMMAC_RING_MODE 0x2 566 567 #define JUMBO_LEN 9000 568 569 /* Receive Side Scaling */ 570 #define STMMAC_RSS_HASH_KEY_SIZE 40 571 #define STMMAC_RSS_MAX_TABLE_SIZE 256 572 573 /* VLAN */ 574 #define STMMAC_VLAN_NONE 0x0 575 #define STMMAC_VLAN_REMOVE 0x1 576 #define STMMAC_VLAN_INSERT 0x2 577 #define STMMAC_VLAN_REPLACE 0x3 578 579 struct mac_device_info; 580 581 struct mac_link { 582 u32 caps; 583 u32 speed_mask; 584 u32 speed10; 585 u32 speed100; 586 u32 speed1000; 587 u32 speed2500; 588 u32 duplex; 589 struct { 590 u32 speed2500; 591 u32 speed5000; 592 u32 speed10000; 593 } xgmii; 594 struct { 595 u32 speed25000; 596 u32 speed40000; 597 u32 speed50000; 598 u32 speed100000; 599 } xlgmii; 600 }; 601 602 struct mii_regs { 603 unsigned int addr; /* MII Address */ 604 unsigned int data; /* MII Data */ 605 unsigned int addr_shift; /* MII address shift */ 606 unsigned int reg_shift; /* MII reg shift */ 607 unsigned int addr_mask; /* MII address mask */ 608 unsigned int reg_mask; /* MII reg mask */ 609 unsigned int clk_csr_shift; 610 unsigned int clk_csr_mask; 611 }; 612 613 struct mac_device_info { 614 const struct stmmac_ops *mac; 615 const struct stmmac_desc_ops *desc; 616 const struct stmmac_dma_ops *dma; 617 const struct stmmac_mode_ops *mode; 618 const struct stmmac_hwtimestamp *ptp; 619 const struct stmmac_tc_ops *tc; 620 const struct stmmac_mmc_ops *mmc; 621 const struct stmmac_est_ops *est; 622 const struct stmmac_vlan_ops *vlan; 623 struct dw_xpcs *xpcs; 624 struct phylink_pcs *phylink_pcs; 625 struct mii_regs mii; /* MII register Addresses */ 626 struct mac_link link; 627 void __iomem *pcsr; /* vpointer to device CSRs */ 628 unsigned int multicast_filter_bins; 629 unsigned int unicast_filter_entries; 630 unsigned int mcast_bits_log2; 631 unsigned int rx_csum; 632 unsigned int pcs; 633 unsigned int xlgmac; 634 unsigned int num_vlan; 635 u32 vlan_filter[32]; 636 bool vlan_fail_q_en; 637 u8 vlan_fail_q; 638 bool hw_vlan_en; 639 bool reverse_sgmii_enable; 640 641 /* This spinlock protects read-modify-write of the interrupt 642 * mask/enable registers. 643 */ 644 spinlock_t irq_ctrl_lock; 645 }; 646 647 struct stmmac_rx_routing { 648 u32 reg_mask; 649 u32 reg_shift; 650 }; 651 652 int dwmac100_setup(struct stmmac_priv *priv); 653 int dwmac1000_setup(struct stmmac_priv *priv); 654 int dwmac4_setup(struct stmmac_priv *priv); 655 int dwxgmac2_setup(struct stmmac_priv *priv); 656 int dwxlgmac2_setup(struct stmmac_priv *priv); 657 658 void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], 659 unsigned int high, unsigned int low); 660 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 661 unsigned int high, unsigned int low); 662 void stmmac_set_mac(void __iomem *ioaddr, bool enable); 663 664 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], 665 unsigned int high, unsigned int low); 666 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 667 unsigned int high, unsigned int low); 668 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable); 669 670 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); 671 672 #endif /* __COMMON_H__ */ 673