1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 STMMAC Common Header File 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #ifndef __COMMON_H__ 12 #define __COMMON_H__ 13 14 #include <linux/etherdevice.h> 15 #include <linux/netdevice.h> 16 #include <linux/stmmac.h> 17 #include <linux/phy.h> 18 #include <linux/mdio-xpcs.h> 19 #include <linux/module.h> 20 #if IS_ENABLED(CONFIG_VLAN_8021Q) 21 #define STMMAC_VLAN_TAG_USED 22 #include <linux/if_vlan.h> 23 #endif 24 25 #include "descs.h" 26 #include "hwif.h" 27 #include "mmc.h" 28 29 /* Synopsys Core versions */ 30 #define DWMAC_CORE_3_40 0x34 31 #define DWMAC_CORE_3_50 0x35 32 #define DWMAC_CORE_4_00 0x40 33 #define DWMAC_CORE_4_10 0x41 34 #define DWMAC_CORE_5_00 0x50 35 #define DWMAC_CORE_5_10 0x51 36 #define DWXGMAC_CORE_2_10 0x21 37 38 #define STMMAC_CHAN0 0 /* Always supported and default for all chips */ 39 40 /* These need to be power of two, and >= 4 */ 41 #define DMA_TX_SIZE 512 42 #define DMA_RX_SIZE 512 43 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1)) 44 45 #undef FRAME_FILTER_DEBUG 46 /* #define FRAME_FILTER_DEBUG */ 47 48 /* Extra statistic and debug information exposed by ethtool */ 49 struct stmmac_extra_stats { 50 /* Transmit errors */ 51 unsigned long tx_underflow ____cacheline_aligned; 52 unsigned long tx_carrier; 53 unsigned long tx_losscarrier; 54 unsigned long vlan_tag; 55 unsigned long tx_deferred; 56 unsigned long tx_vlan; 57 unsigned long tx_jabber; 58 unsigned long tx_frame_flushed; 59 unsigned long tx_payload_error; 60 unsigned long tx_ip_header_error; 61 /* Receive errors */ 62 unsigned long rx_desc; 63 unsigned long sa_filter_fail; 64 unsigned long overflow_error; 65 unsigned long ipc_csum_error; 66 unsigned long rx_collision; 67 unsigned long rx_crc_errors; 68 unsigned long dribbling_bit; 69 unsigned long rx_length; 70 unsigned long rx_mii; 71 unsigned long rx_multicast; 72 unsigned long rx_gmac_overflow; 73 unsigned long rx_watchdog; 74 unsigned long da_rx_filter_fail; 75 unsigned long sa_rx_filter_fail; 76 unsigned long rx_missed_cntr; 77 unsigned long rx_overflow_cntr; 78 unsigned long rx_vlan; 79 unsigned long rx_split_hdr_pkt_n; 80 /* Tx/Rx IRQ error info */ 81 unsigned long tx_undeflow_irq; 82 unsigned long tx_process_stopped_irq; 83 unsigned long tx_jabber_irq; 84 unsigned long rx_overflow_irq; 85 unsigned long rx_buf_unav_irq; 86 unsigned long rx_process_stopped_irq; 87 unsigned long rx_watchdog_irq; 88 unsigned long tx_early_irq; 89 unsigned long fatal_bus_error_irq; 90 /* Tx/Rx IRQ Events */ 91 unsigned long rx_early_irq; 92 unsigned long threshold; 93 unsigned long tx_pkt_n; 94 unsigned long rx_pkt_n; 95 unsigned long normal_irq_n; 96 unsigned long rx_normal_irq_n; 97 unsigned long napi_poll; 98 unsigned long tx_normal_irq_n; 99 unsigned long tx_clean; 100 unsigned long tx_set_ic_bit; 101 unsigned long irq_receive_pmt_irq_n; 102 /* MMC info */ 103 unsigned long mmc_tx_irq_n; 104 unsigned long mmc_rx_irq_n; 105 unsigned long mmc_rx_csum_offload_irq_n; 106 /* EEE */ 107 unsigned long irq_tx_path_in_lpi_mode_n; 108 unsigned long irq_tx_path_exit_lpi_mode_n; 109 unsigned long irq_rx_path_in_lpi_mode_n; 110 unsigned long irq_rx_path_exit_lpi_mode_n; 111 unsigned long phy_eee_wakeup_error_n; 112 /* Extended RDES status */ 113 unsigned long ip_hdr_err; 114 unsigned long ip_payload_err; 115 unsigned long ip_csum_bypassed; 116 unsigned long ipv4_pkt_rcvd; 117 unsigned long ipv6_pkt_rcvd; 118 unsigned long no_ptp_rx_msg_type_ext; 119 unsigned long ptp_rx_msg_type_sync; 120 unsigned long ptp_rx_msg_type_follow_up; 121 unsigned long ptp_rx_msg_type_delay_req; 122 unsigned long ptp_rx_msg_type_delay_resp; 123 unsigned long ptp_rx_msg_type_pdelay_req; 124 unsigned long ptp_rx_msg_type_pdelay_resp; 125 unsigned long ptp_rx_msg_type_pdelay_follow_up; 126 unsigned long ptp_rx_msg_type_announce; 127 unsigned long ptp_rx_msg_type_management; 128 unsigned long ptp_rx_msg_pkt_reserved_type; 129 unsigned long ptp_frame_type; 130 unsigned long ptp_ver; 131 unsigned long timestamp_dropped; 132 unsigned long av_pkt_rcvd; 133 unsigned long av_tagged_pkt_rcvd; 134 unsigned long vlan_tag_priority_val; 135 unsigned long l3_filter_match; 136 unsigned long l4_filter_match; 137 unsigned long l3_l4_filter_no_match; 138 /* PCS */ 139 unsigned long irq_pcs_ane_n; 140 unsigned long irq_pcs_link_n; 141 unsigned long irq_rgmii_n; 142 unsigned long pcs_link; 143 unsigned long pcs_duplex; 144 unsigned long pcs_speed; 145 /* debug register */ 146 unsigned long mtl_tx_status_fifo_full; 147 unsigned long mtl_tx_fifo_not_empty; 148 unsigned long mmtl_fifo_ctrl; 149 unsigned long mtl_tx_fifo_read_ctrl_write; 150 unsigned long mtl_tx_fifo_read_ctrl_wait; 151 unsigned long mtl_tx_fifo_read_ctrl_read; 152 unsigned long mtl_tx_fifo_read_ctrl_idle; 153 unsigned long mac_tx_in_pause; 154 unsigned long mac_tx_frame_ctrl_xfer; 155 unsigned long mac_tx_frame_ctrl_idle; 156 unsigned long mac_tx_frame_ctrl_wait; 157 unsigned long mac_tx_frame_ctrl_pause; 158 unsigned long mac_gmii_tx_proto_engine; 159 unsigned long mtl_rx_fifo_fill_level_full; 160 unsigned long mtl_rx_fifo_fill_above_thresh; 161 unsigned long mtl_rx_fifo_fill_below_thresh; 162 unsigned long mtl_rx_fifo_fill_level_empty; 163 unsigned long mtl_rx_fifo_read_ctrl_flush; 164 unsigned long mtl_rx_fifo_read_ctrl_read_data; 165 unsigned long mtl_rx_fifo_read_ctrl_status; 166 unsigned long mtl_rx_fifo_read_ctrl_idle; 167 unsigned long mtl_rx_fifo_ctrl_active; 168 unsigned long mac_rx_frame_ctrl_fifo; 169 unsigned long mac_gmii_rx_proto_engine; 170 /* TSO */ 171 unsigned long tx_tso_frames; 172 unsigned long tx_tso_nfrags; 173 }; 174 175 /* Safety Feature statistics exposed by ethtool */ 176 struct stmmac_safety_stats { 177 unsigned long mac_errors[32]; 178 unsigned long mtl_errors[32]; 179 unsigned long dma_errors[32]; 180 }; 181 182 /* Number of fields in Safety Stats */ 183 #define STMMAC_SAFETY_FEAT_SIZE \ 184 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long)) 185 186 /* CSR Frequency Access Defines*/ 187 #define CSR_F_35M 35000000 188 #define CSR_F_60M 60000000 189 #define CSR_F_100M 100000000 190 #define CSR_F_150M 150000000 191 #define CSR_F_250M 250000000 192 #define CSR_F_300M 300000000 193 194 #define MAC_CSR_H_FRQ_MASK 0x20 195 196 #define HASH_TABLE_SIZE 64 197 #define PAUSE_TIME 0xffff 198 199 /* Flow Control defines */ 200 #define FLOW_OFF 0 201 #define FLOW_RX 1 202 #define FLOW_TX 2 203 #define FLOW_AUTO (FLOW_TX | FLOW_RX) 204 205 /* PCS defines */ 206 #define STMMAC_PCS_RGMII (1 << 0) 207 #define STMMAC_PCS_SGMII (1 << 1) 208 #define STMMAC_PCS_TBI (1 << 2) 209 #define STMMAC_PCS_RTBI (1 << 3) 210 211 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ 212 213 /* DAM HW feature register fields */ 214 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */ 215 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */ 216 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */ 217 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */ 218 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */ 219 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */ 220 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */ 221 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */ 222 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */ 223 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */ 224 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */ 225 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */ 226 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */ 227 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */ 228 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */ 229 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */ 230 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */ 231 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */ 232 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */ 233 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */ 234 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */ 235 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */ 236 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */ 237 /* Timestamping with Internal System Time */ 238 #define DMA_HW_FEAT_INTTSEN 0x02000000 239 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */ 240 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */ 241 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */ 242 #define DEFAULT_DMA_PBL 8 243 244 /* PCS status and mask defines */ 245 #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */ 246 #define PCS_LINK_IRQ BIT(1) /* PCS Link */ 247 #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */ 248 249 /* Max/Min RI Watchdog Timer count value */ 250 #define MAX_DMA_RIWT 0xff 251 #define MIN_DMA_RIWT 0x10 252 #define DEF_DMA_RIWT 0xa0 253 /* Tx coalesce parameters */ 254 #define STMMAC_COAL_TX_TIMER 1000 255 #define STMMAC_MAX_COAL_TX_TICK 100000 256 #define STMMAC_TX_MAX_FRAMES 256 257 #define STMMAC_TX_FRAMES 25 258 #define STMMAC_RX_FRAMES 0 259 260 /* Packets types */ 261 enum packets_types { 262 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */ 263 PACKET_PTPQ = 0x2, /* PTP Packets */ 264 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */ 265 PACKET_UPQ = 0x4, /* Untagged Packets */ 266 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */ 267 }; 268 269 /* Rx IPC status */ 270 enum rx_frame_status { 271 good_frame = 0x0, 272 discard_frame = 0x1, 273 csum_none = 0x2, 274 llc_snap = 0x4, 275 dma_own = 0x8, 276 rx_not_ls = 0x10, 277 }; 278 279 /* Tx status */ 280 enum tx_frame_status { 281 tx_done = 0x0, 282 tx_not_ls = 0x1, 283 tx_err = 0x2, 284 tx_dma_own = 0x4, 285 }; 286 287 enum dma_irq_status { 288 tx_hard_error = 0x1, 289 tx_hard_error_bump_tc = 0x2, 290 handle_rx = 0x4, 291 handle_tx = 0x8, 292 }; 293 294 /* EEE and LPI defines */ 295 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0) 296 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1) 297 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2) 298 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3) 299 300 #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8) 301 302 /* Physical Coding Sublayer */ 303 struct rgmii_adv { 304 unsigned int pause; 305 unsigned int duplex; 306 unsigned int lp_pause; 307 unsigned int lp_duplex; 308 }; 309 310 #define STMMAC_PCS_PAUSE 1 311 #define STMMAC_PCS_ASYM_PAUSE 2 312 313 /* DMA HW capabilities */ 314 struct dma_features { 315 unsigned int mbps_10_100; 316 unsigned int mbps_1000; 317 unsigned int half_duplex; 318 unsigned int hash_filter; 319 unsigned int multi_addr; 320 unsigned int pcs; 321 unsigned int sma_mdio; 322 unsigned int pmt_remote_wake_up; 323 unsigned int pmt_magic_frame; 324 unsigned int rmon; 325 /* IEEE 1588-2002 */ 326 unsigned int time_stamp; 327 /* IEEE 1588-2008 */ 328 unsigned int atime_stamp; 329 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 330 unsigned int eee; 331 unsigned int av; 332 unsigned int hash_tb_sz; 333 unsigned int tsoen; 334 /* TX and RX csum */ 335 unsigned int tx_coe; 336 unsigned int rx_coe; 337 unsigned int rx_coe_type1; 338 unsigned int rx_coe_type2; 339 unsigned int rxfifo_over_2048; 340 /* TX and RX number of channels */ 341 unsigned int number_rx_channel; 342 unsigned int number_tx_channel; 343 /* TX and RX number of queues */ 344 unsigned int number_rx_queues; 345 unsigned int number_tx_queues; 346 /* PPS output */ 347 unsigned int pps_out_num; 348 /* Alternate (enhanced) DESC mode */ 349 unsigned int enh_desc; 350 /* TX and RX FIFO sizes */ 351 unsigned int tx_fifo_size; 352 unsigned int rx_fifo_size; 353 /* Automotive Safety Package */ 354 unsigned int asp; 355 /* RX Parser */ 356 unsigned int frpsel; 357 unsigned int frpbs; 358 unsigned int frpes; 359 unsigned int addr64; 360 unsigned int rssen; 361 unsigned int vlhash; 362 unsigned int sphen; 363 unsigned int vlins; 364 unsigned int dvlan; 365 unsigned int l3l4fnum; 366 unsigned int arpoffsel; 367 /* TSN Features */ 368 unsigned int estwid; 369 unsigned int estdep; 370 unsigned int estsel; 371 unsigned int fpesel; 372 unsigned int tbssel; 373 }; 374 375 /* RX Buffer size must be multiple of 4/8/16 bytes */ 376 #define BUF_SIZE_16KiB 16368 377 #define BUF_SIZE_8KiB 8188 378 #define BUF_SIZE_4KiB 4096 379 #define BUF_SIZE_2KiB 2048 380 381 /* Power Down and WOL */ 382 #define PMT_NOT_SUPPORTED 0 383 #define PMT_SUPPORTED 1 384 385 /* Common MAC defines */ 386 #define MAC_CTRL_REG 0x00000000 /* MAC Control */ 387 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ 388 #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */ 389 390 /* Default LPI timers */ 391 #define STMMAC_DEFAULT_LIT_LS 0x3E8 392 #define STMMAC_DEFAULT_TWT_LS 0x1E 393 394 #define STMMAC_CHAIN_MODE 0x1 395 #define STMMAC_RING_MODE 0x2 396 397 #define JUMBO_LEN 9000 398 399 /* Receive Side Scaling */ 400 #define STMMAC_RSS_HASH_KEY_SIZE 40 401 #define STMMAC_RSS_MAX_TABLE_SIZE 256 402 403 /* VLAN */ 404 #define STMMAC_VLAN_NONE 0x0 405 #define STMMAC_VLAN_REMOVE 0x1 406 #define STMMAC_VLAN_INSERT 0x2 407 #define STMMAC_VLAN_REPLACE 0x3 408 409 extern const struct stmmac_desc_ops enh_desc_ops; 410 extern const struct stmmac_desc_ops ndesc_ops; 411 412 struct mac_device_info; 413 414 extern const struct stmmac_hwtimestamp stmmac_ptp; 415 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops; 416 417 struct mac_link { 418 u32 speed_mask; 419 u32 speed10; 420 u32 speed100; 421 u32 speed1000; 422 u32 speed2500; 423 u32 duplex; 424 struct { 425 u32 speed2500; 426 u32 speed5000; 427 u32 speed10000; 428 } xgmii; 429 }; 430 431 struct mii_regs { 432 unsigned int addr; /* MII Address */ 433 unsigned int data; /* MII Data */ 434 unsigned int addr_shift; /* MII address shift */ 435 unsigned int reg_shift; /* MII reg shift */ 436 unsigned int addr_mask; /* MII address mask */ 437 unsigned int reg_mask; /* MII reg mask */ 438 unsigned int clk_csr_shift; 439 unsigned int clk_csr_mask; 440 }; 441 442 struct mac_device_info { 443 const struct stmmac_ops *mac; 444 const struct stmmac_desc_ops *desc; 445 const struct stmmac_dma_ops *dma; 446 const struct stmmac_mode_ops *mode; 447 const struct stmmac_hwtimestamp *ptp; 448 const struct stmmac_tc_ops *tc; 449 const struct stmmac_mmc_ops *mmc; 450 const struct mdio_xpcs_ops *xpcs; 451 struct mdio_xpcs_args xpcs_args; 452 struct mii_regs mii; /* MII register Addresses */ 453 struct mac_link link; 454 void __iomem *pcsr; /* vpointer to device CSRs */ 455 unsigned int multicast_filter_bins; 456 unsigned int unicast_filter_entries; 457 unsigned int mcast_bits_log2; 458 unsigned int rx_csum; 459 unsigned int pcs; 460 unsigned int pmt; 461 unsigned int ps; 462 }; 463 464 struct stmmac_rx_routing { 465 u32 reg_mask; 466 u32 reg_shift; 467 }; 468 469 int dwmac100_setup(struct stmmac_priv *priv); 470 int dwmac1000_setup(struct stmmac_priv *priv); 471 int dwmac4_setup(struct stmmac_priv *priv); 472 int dwxgmac2_setup(struct stmmac_priv *priv); 473 474 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], 475 unsigned int high, unsigned int low); 476 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 477 unsigned int high, unsigned int low); 478 void stmmac_set_mac(void __iomem *ioaddr, bool enable); 479 480 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6], 481 unsigned int high, unsigned int low); 482 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 483 unsigned int high, unsigned int low); 484 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable); 485 486 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); 487 488 extern const struct stmmac_mode_ops ring_mode_ops; 489 extern const struct stmmac_mode_ops chain_mode_ops; 490 extern const struct stmmac_desc_ops dwmac4_desc_ops; 491 492 #endif /* __COMMON_H__ */ 493