1config STMMAC_ETH 2 tristate "STMicroelectronics 10/100/1000 Ethernet driver" 3 depends on HAS_IOMEM 4 select NET_CORE 5 select MII 6 select PHYLIB 7 select CRC32 8 ---help--- 9 This is the driver for the Ethernet IPs are built around a 10 Synopsys IP Core and only tested on the STMicroelectronics 11 platforms. 12 13if STMMAC_ETH 14 15config STMMAC_DEBUG_FS 16 bool "Enable monitoring via sysFS " 17 default n 18 depends on STMMAC_ETH && DEBUG_FS 19 -- help 20 The stmmac entry in /sys reports DMA TX/RX rings 21 or (if supported) the HW cap register. 22 23config STMMAC_DA 24 bool "STMMAC DMA arbitration scheme" 25 default n 26 ---help--- 27 Selecting this option, rx has priority over Tx (only for Giga 28 Ethernet device). 29 By default, the DMA arbitration scheme is based on Round-robin 30 (rx:tx priority is 1:1). 31 32config STMMAC_TIMER 33 bool "STMMAC Timer optimisation" 34 default n 35 depends on RTC_HCTOSYS_DEVICE 36 ---help--- 37 Use an external timer for mitigating the number of network 38 interrupts. Currently, for SH architectures, it is possible 39 to use the TMU channel 2 and the SH-RTC device. 40 41choice 42 prompt "Select Timer device" 43 depends on STMMAC_TIMER 44 45config STMMAC_TMU_TIMER 46 bool "TMU channel 2" 47 depends on CPU_SH4 48 ---help--- 49 50config STMMAC_RTC_TIMER 51 bool "Real time clock" 52 depends on RTC_CLASS 53 ---help--- 54 55endchoice 56 57choice 58 prompt "Select the DMA TX/RX descriptor operating modes" 59 depends on STMMAC_ETH 60 ---help--- 61 This driver supports DMA descriptor to operate both in dual buffer 62 (RING) and linked-list(CHAINED) mode. In RING mode each descriptor 63 points to two data buffer pointers whereas in CHAINED mode they 64 points to only one data buffer pointer. 65 66config STMMAC_RING 67 bool "Enable Descriptor Ring Mode" 68 69config STMMAC_CHAINED 70 bool "Enable Descriptor Chained Mode" 71 72endchoice 73 74 75endif 76