1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * SpacemiT K1 Ethernet hardware definitions 4 * 5 * Copyright (C) 2023-2025 SpacemiT (Hangzhou) Technology Co. Ltd 6 * Copyright (C) 2025 Vivian Wang <wangruikang@iscas.ac.cn> 7 */ 8 9 #ifndef _K1_EMAC_H_ 10 #define _K1_EMAC_H_ 11 12 #include <linux/stddef.h> 13 14 /* APMU syscon registers */ 15 16 #define APMU_EMAC_CTRL_REG 0x0 17 18 #define PHY_INTF_RGMII BIT(2) 19 20 /* 21 * Only valid for RMII mode 22 * 0: Ref clock from External PHY 23 * 1: Ref clock from SoC 24 */ 25 #define REF_CLK_SEL BIT(3) 26 27 /* 28 * Function clock select 29 * 0: 208 MHz 30 * 1: 312 MHz 31 */ 32 #define FUNC_CLK_SEL BIT(4) 33 34 /* Only valid for RMII, invert TX clk */ 35 #define RMII_TX_CLK_SEL BIT(6) 36 37 /* Only valid for RMII, invert RX clk */ 38 #define RMII_RX_CLK_SEL BIT(7) 39 40 /* 41 * Only valid for RGMII 42 * 0: TX clk from RX clk 43 * 1: TX clk from SoC 44 */ 45 #define RGMII_TX_CLK_SEL BIT(8) 46 47 #define PHY_IRQ_EN BIT(12) 48 #define AXI_SINGLE_ID BIT(13) 49 50 #define APMU_EMAC_DLINE_REG 0x4 51 52 #define EMAC_RX_DLINE_EN BIT(0) 53 #define EMAC_RX_DLINE_STEP_MASK GENMASK(5, 4) 54 #define EMAC_RX_DLINE_CODE_MASK GENMASK(15, 8) 55 56 #define EMAC_TX_DLINE_EN BIT(16) 57 #define EMAC_TX_DLINE_STEP_MASK GENMASK(21, 20) 58 #define EMAC_TX_DLINE_CODE_MASK GENMASK(31, 24) 59 60 #define EMAC_DLINE_STEP_15P6 0 /* 15.6 ps/step */ 61 #define EMAC_DLINE_STEP_24P4 1 /* 24.4 ps/step */ 62 #define EMAC_DLINE_STEP_29P7 2 /* 29.7 ps/step */ 63 #define EMAC_DLINE_STEP_35P1 3 /* 35.1 ps/step */ 64 65 /* DMA register set */ 66 #define DMA_CONFIGURATION 0x0000 67 #define DMA_CONTROL 0x0004 68 #define DMA_STATUS_IRQ 0x0008 69 #define DMA_INTERRUPT_ENABLE 0x000c 70 71 #define DMA_TRANSMIT_AUTO_POLL_COUNTER 0x0010 72 #define DMA_TRANSMIT_POLL_DEMAND 0x0014 73 #define DMA_RECEIVE_POLL_DEMAND 0x0018 74 75 #define DMA_TRANSMIT_BASE_ADDRESS 0x001c 76 #define DMA_RECEIVE_BASE_ADDRESS 0x0020 77 #define DMA_MISSED_FRAME_COUNTER 0x0024 78 #define DMA_STOP_FLUSH_COUNTER 0x0028 79 80 #define DMA_RECEIVE_IRQ_MITIGATION_CTRL 0x002c 81 82 #define DMA_CURRENT_TRANSMIT_DESCRIPTOR_POINTER 0x0030 83 #define DMA_CURRENT_TRANSMIT_BUFFER_POINTER 0x0034 84 #define DMA_CURRENT_RECEIVE_DESCRIPTOR_POINTER 0x0038 85 #define DMA_CURRENT_RECEIVE_BUFFER_POINTER 0x003c 86 87 /* MAC Register set */ 88 #define MAC_GLOBAL_CONTROL 0x0100 89 #define MAC_TRANSMIT_CONTROL 0x0104 90 #define MAC_RECEIVE_CONTROL 0x0108 91 #define MAC_MAXIMUM_FRAME_SIZE 0x010c 92 #define MAC_TRANSMIT_JABBER_SIZE 0x0110 93 #define MAC_RECEIVE_JABBER_SIZE 0x0114 94 #define MAC_ADDRESS_CONTROL 0x0118 95 #define MAC_MDIO_CLK_DIV 0x011c 96 #define MAC_ADDRESS1_HIGH 0x0120 97 #define MAC_ADDRESS1_MED 0x0124 98 #define MAC_ADDRESS1_LOW 0x0128 99 #define MAC_ADDRESS2_HIGH 0x012c 100 #define MAC_ADDRESS2_MED 0x0130 101 #define MAC_ADDRESS2_LOW 0x0134 102 #define MAC_ADDRESS3_HIGH 0x0138 103 #define MAC_ADDRESS3_MED 0x013c 104 #define MAC_ADDRESS3_LOW 0x0140 105 #define MAC_ADDRESS4_HIGH 0x0144 106 #define MAC_ADDRESS4_MED 0x0148 107 #define MAC_ADDRESS4_LOW 0x014c 108 #define MAC_MULTICAST_HASH_TABLE1 0x0150 109 #define MAC_MULTICAST_HASH_TABLE2 0x0154 110 #define MAC_MULTICAST_HASH_TABLE3 0x0158 111 #define MAC_MULTICAST_HASH_TABLE4 0x015c 112 #define MAC_FC_CONTROL 0x0160 113 #define MAC_FC_PAUSE_FRAME_GENERATE 0x0164 114 #define MAC_FC_SOURCE_ADDRESS_HIGH 0x0168 115 #define MAC_FC_SOURCE_ADDRESS_MED 0x016c 116 #define MAC_FC_SOURCE_ADDRESS_LOW 0x0170 117 #define MAC_FC_DESTINATION_ADDRESS_HIGH 0x0174 118 #define MAC_FC_DESTINATION_ADDRESS_MED 0x0178 119 #define MAC_FC_DESTINATION_ADDRESS_LOW 0x017c 120 #define MAC_FC_PAUSE_TIME_VALUE 0x0180 121 #define MAC_FC_HIGH_PAUSE_TIME 0x0184 122 #define MAC_FC_LOW_PAUSE_TIME 0x0188 123 #define MAC_FC_PAUSE_HIGH_THRESHOLD 0x018c 124 #define MAC_FC_PAUSE_LOW_THRESHOLD 0x0190 125 #define MAC_MDIO_CONTROL 0x01a0 126 #define MAC_MDIO_DATA 0x01a4 127 #define MAC_RX_STATCTR_CONTROL 0x01a8 128 #define MAC_RX_STATCTR_DATA_HIGH 0x01ac 129 #define MAC_RX_STATCTR_DATA_LOW 0x01b0 130 #define MAC_TX_STATCTR_CONTROL 0x01b4 131 #define MAC_TX_STATCTR_DATA_HIGH 0x01b8 132 #define MAC_TX_STATCTR_DATA_LOW 0x01bc 133 #define MAC_TRANSMIT_FIFO_ALMOST_FULL 0x01c0 134 #define MAC_TRANSMIT_PACKET_START_THRESHOLD 0x01c4 135 #define MAC_RECEIVE_PACKET_START_THRESHOLD 0x01c8 136 #define MAC_STATUS_IRQ 0x01e0 137 #define MAC_INTERRUPT_ENABLE 0x01e4 138 139 /* Used for register dump */ 140 #define EMAC_DMA_REG_CNT 16 141 #define EMAC_MAC_REG_CNT 124 142 143 /* DMA_CONFIGURATION (0x0000) */ 144 145 /* 146 * 0-DMA controller in normal operation mode, 147 * 1-DMA controller reset to default state, 148 * clearing all internal state information 149 */ 150 #define MREGBIT_SOFTWARE_RESET BIT(0) 151 152 #define MREGBIT_BURST_1WORD BIT(1) 153 #define MREGBIT_BURST_2WORD BIT(2) 154 #define MREGBIT_BURST_4WORD BIT(3) 155 #define MREGBIT_BURST_8WORD BIT(4) 156 #define MREGBIT_BURST_16WORD BIT(5) 157 #define MREGBIT_BURST_32WORD BIT(6) 158 #define MREGBIT_BURST_64WORD BIT(7) 159 #define MREGBIT_BURST_LENGTH GENMASK(7, 1) 160 #define MREGBIT_DESCRIPTOR_SKIP_LENGTH GENMASK(12, 8) 161 162 /* For Receive and Transmit DMA operate in Big-Endian mode for Descriptors. */ 163 #define MREGBIT_DESCRIPTOR_BYTE_ORDERING BIT(13) 164 165 #define MREGBIT_BIG_LITLE_ENDIAN BIT(14) 166 #define MREGBIT_TX_RX_ARBITRATION BIT(15) 167 #define MREGBIT_WAIT_FOR_DONE BIT(16) 168 #define MREGBIT_STRICT_BURST BIT(17) 169 #define MREGBIT_DMA_64BIT_MODE BIT(18) 170 171 /* DMA_CONTROL (0x0004) */ 172 #define MREGBIT_START_STOP_TRANSMIT_DMA BIT(0) 173 #define MREGBIT_START_STOP_RECEIVE_DMA BIT(1) 174 175 /* DMA_STATUS_IRQ (0x0008) */ 176 #define MREGBIT_TRANSMIT_TRANSFER_DONE_IRQ BIT(0) 177 #define MREGBIT_TRANSMIT_DES_UNAVAILABLE_IRQ BIT(1) 178 #define MREGBIT_TRANSMIT_DMA_STOPPED_IRQ BIT(2) 179 #define MREGBIT_RECEIVE_TRANSFER_DONE_IRQ BIT(4) 180 #define MREGBIT_RECEIVE_DES_UNAVAILABLE_IRQ BIT(5) 181 #define MREGBIT_RECEIVE_DMA_STOPPED_IRQ BIT(6) 182 #define MREGBIT_RECEIVE_MISSED_FRAME_IRQ BIT(7) 183 #define MREGBIT_MAC_IRQ BIT(8) 184 #define MREGBIT_TRANSMIT_DMA_STATE GENMASK(18, 16) 185 #define MREGBIT_RECEIVE_DMA_STATE GENMASK(23, 20) 186 187 /* DMA_INTERRUPT_ENABLE (0x000c) */ 188 #define MREGBIT_TRANSMIT_TRANSFER_DONE_INTR_ENABLE BIT(0) 189 #define MREGBIT_TRANSMIT_DES_UNAVAILABLE_INTR_ENABLE BIT(1) 190 #define MREGBIT_TRANSMIT_DMA_STOPPED_INTR_ENABLE BIT(2) 191 #define MREGBIT_RECEIVE_TRANSFER_DONE_INTR_ENABLE BIT(4) 192 #define MREGBIT_RECEIVE_DES_UNAVAILABLE_INTR_ENABLE BIT(5) 193 #define MREGBIT_RECEIVE_DMA_STOPPED_INTR_ENABLE BIT(6) 194 #define MREGBIT_RECEIVE_MISSED_FRAME_INTR_ENABLE BIT(7) 195 #define MREGBIT_MAC_INTR_ENABLE BIT(8) 196 197 /* DMA_RECEIVE_IRQ_MITIGATION_CTRL (0x002c) */ 198 #define MREGBIT_RECEIVE_IRQ_FRAME_COUNTER_MASK GENMASK(7, 0) 199 #define MREGBIT_RECEIVE_IRQ_TIMEOUT_COUNTER_MASK GENMASK(27, 8) 200 #define MREGBIT_RECEIVE_IRQ_FRAME_COUNTER_MODE BIT(30) 201 #define MREGBIT_RECEIVE_IRQ_MITIGATION_ENABLE BIT(31) 202 203 /* MAC_GLOBAL_CONTROL (0x0100) */ 204 #define MREGBIT_SPEED GENMASK(1, 0) 205 #define MREGBIT_SPEED_10M 0x0 206 #define MREGBIT_SPEED_100M BIT(0) 207 #define MREGBIT_SPEED_1000M BIT(1) 208 #define MREGBIT_FULL_DUPLEX_MODE BIT(2) 209 #define MREGBIT_RESET_RX_STAT_COUNTERS BIT(3) 210 #define MREGBIT_RESET_TX_STAT_COUNTERS BIT(4) 211 #define MREGBIT_UNICAST_WAKEUP_MODE BIT(8) 212 #define MREGBIT_MAGIC_PACKET_WAKEUP_MODE BIT(9) 213 214 /* MAC_TRANSMIT_CONTROL (0x0104) */ 215 #define MREGBIT_TRANSMIT_ENABLE BIT(0) 216 #define MREGBIT_INVERT_FCS BIT(1) 217 #define MREGBIT_DISABLE_FCS_INSERT BIT(2) 218 #define MREGBIT_TRANSMIT_AUTO_RETRY BIT(3) 219 #define MREGBIT_IFG_LEN GENMASK(6, 4) 220 #define MREGBIT_PREAMBLE_LENGTH GENMASK(9, 7) 221 222 /* MAC_RECEIVE_CONTROL (0x0108) */ 223 #define MREGBIT_RECEIVE_ENABLE BIT(0) 224 #define MREGBIT_DISABLE_FCS_CHECK BIT(1) 225 #define MREGBIT_STRIP_FCS BIT(2) 226 #define MREGBIT_STORE_FORWARD BIT(3) 227 #define MREGBIT_STATUS_FIRST BIT(4) 228 #define MREGBIT_PASS_BAD_FRAMES BIT(5) 229 #define MREGBIT_ACOOUNT_VLAN BIT(6) 230 231 /* MAC_MAXIMUM_FRAME_SIZE (0x010c) */ 232 #define MREGBIT_MAX_FRAME_SIZE GENMASK(13, 0) 233 234 /* MAC_TRANSMIT_JABBER_SIZE (0x0110) */ 235 #define MREGBIT_TRANSMIT_JABBER_SIZE GENMASK(15, 0) 236 237 /* MAC_RECEIVE_JABBER_SIZE (0x0114) */ 238 #define MREGBIT_RECEIVE_JABBER_SIZE GENMASK(15, 0) 239 240 /* MAC_ADDRESS_CONTROL (0x0118) */ 241 #define MREGBIT_MAC_ADDRESS1_ENABLE BIT(0) 242 #define MREGBIT_MAC_ADDRESS2_ENABLE BIT(1) 243 #define MREGBIT_MAC_ADDRESS3_ENABLE BIT(2) 244 #define MREGBIT_MAC_ADDRESS4_ENABLE BIT(3) 245 #define MREGBIT_INVERSE_MAC_ADDRESS1_ENABLE BIT(4) 246 #define MREGBIT_INVERSE_MAC_ADDRESS2_ENABLE BIT(5) 247 #define MREGBIT_INVERSE_MAC_ADDRESS3_ENABLE BIT(6) 248 #define MREGBIT_INVERSE_MAC_ADDRESS4_ENABLE BIT(7) 249 #define MREGBIT_PROMISCUOUS_MODE BIT(8) 250 251 /* MAC_FC_CONTROL (0x0160) */ 252 #define MREGBIT_FC_DECODE_ENABLE BIT(0) 253 #define MREGBIT_FC_GENERATION_ENABLE BIT(1) 254 #define MREGBIT_AUTO_FC_GENERATION_ENABLE BIT(2) 255 #define MREGBIT_MULTICAST_MODE BIT(3) 256 #define MREGBIT_BLOCK_PAUSE_FRAMES BIT(4) 257 258 /* MAC_FC_PAUSE_FRAME_GENERATE (0x0164) */ 259 #define MREGBIT_GENERATE_PAUSE_FRAME BIT(0) 260 261 /* MAC_FC_PAUSE_TIME_VALUE (0x0180) */ 262 #define MREGBIT_MAC_FC_PAUSE_TIME GENMASK(15, 0) 263 264 /* MAC_MDIO_CONTROL (0x01a0) */ 265 #define MREGBIT_PHY_ADDRESS GENMASK(4, 0) 266 #define MREGBIT_REGISTER_ADDRESS GENMASK(9, 5) 267 #define MREGBIT_MDIO_READ_WRITE BIT(10) 268 #define MREGBIT_START_MDIO_TRANS BIT(15) 269 270 /* MAC_MDIO_DATA (0x01a4) */ 271 #define MREGBIT_MDIO_DATA GENMASK(15, 0) 272 273 /* MAC_RX_STATCTR_CONTROL (0x01a8) */ 274 #define MREGBIT_RX_COUNTER_NUMBER GENMASK(4, 0) 275 #define MREGBIT_START_RX_COUNTER_READ BIT(15) 276 277 /* MAC_RX_STATCTR_DATA_HIGH (0x01ac) */ 278 #define MREGBIT_RX_STATCTR_DATA_HIGH GENMASK(15, 0) 279 /* MAC_RX_STATCTR_DATA_LOW (0x01b0) */ 280 #define MREGBIT_RX_STATCTR_DATA_LOW GENMASK(15, 0) 281 282 /* MAC_TX_STATCTR_CONTROL (0x01b4) */ 283 #define MREGBIT_TX_COUNTER_NUMBER GENMASK(4, 0) 284 #define MREGBIT_START_TX_COUNTER_READ BIT(15) 285 286 /* MAC_TX_STATCTR_DATA_HIGH (0x01b8) */ 287 #define MREGBIT_TX_STATCTR_DATA_HIGH GENMASK(15, 0) 288 /* MAC_TX_STATCTR_DATA_LOW (0x01bc) */ 289 #define MREGBIT_TX_STATCTR_DATA_LOW GENMASK(15, 0) 290 291 /* MAC_TRANSMIT_FIFO_ALMOST_FULL (0x01c0) */ 292 #define MREGBIT_TX_FIFO_AF GENMASK(13, 0) 293 294 /* MAC_TRANSMIT_PACKET_START_THRESHOLD (0x01c4) */ 295 #define MREGBIT_TX_PACKET_START_THRESHOLD GENMASK(13, 0) 296 297 /* MAC_RECEIVE_PACKET_START_THRESHOLD (0x01c8) */ 298 #define MREGBIT_RX_PACKET_START_THRESHOLD GENMASK(13, 0) 299 300 /* MAC_STATUS_IRQ (0x01e0) */ 301 #define MREGBIT_MAC_UNDERRUN_IRQ BIT(0) 302 #define MREGBIT_MAC_JABBER_IRQ BIT(1) 303 304 /* MAC_INTERRUPT_ENABLE (0x01e4) */ 305 #define MREGBIT_MAC_UNDERRUN_INTERRUPT_ENABLE BIT(0) 306 #define MREGBIT_JABBER_INTERRUPT_ENABLE BIT(1) 307 308 /* RX DMA descriptor */ 309 310 #define RX_DESC_0_FRAME_PACKET_LENGTH_MASK GENMASK(13, 0) 311 #define RX_DESC_0_FRAME_ALIGN_ERR BIT(14) 312 #define RX_DESC_0_FRAME_RUNT BIT(15) 313 #define RX_DESC_0_FRAME_ETHERNET_TYPE BIT(16) 314 #define RX_DESC_0_FRAME_VLAN BIT(17) 315 #define RX_DESC_0_FRAME_MULTICAST BIT(18) 316 #define RX_DESC_0_FRAME_BROADCAST BIT(19) 317 #define RX_DESC_0_FRAME_CRC_ERR BIT(20) 318 #define RX_DESC_0_FRAME_MAX_LEN_ERR BIT(21) 319 #define RX_DESC_0_FRAME_JABBER_ERR BIT(22) 320 #define RX_DESC_0_FRAME_LENGTH_ERR BIT(23) 321 #define RX_DESC_0_FRAME_MAC_ADDR1_MATCH BIT(24) 322 #define RX_DESC_0_FRAME_MAC_ADDR2_MATCH BIT(25) 323 #define RX_DESC_0_FRAME_MAC_ADDR3_MATCH BIT(26) 324 #define RX_DESC_0_FRAME_MAC_ADDR4_MATCH BIT(27) 325 #define RX_DESC_0_FRAME_PAUSE_CTRL BIT(28) 326 #define RX_DESC_0_LAST_DESCRIPTOR BIT(29) 327 #define RX_DESC_0_FIRST_DESCRIPTOR BIT(30) 328 #define RX_DESC_0_OWN BIT(31) 329 330 #define RX_DESC_1_BUFFER_SIZE_1_MASK GENMASK(11, 0) 331 #define RX_DESC_1_BUFFER_SIZE_2_MASK GENMASK(23, 12) 332 /* [24] reserved */ 333 #define RX_DESC_1_SECOND_ADDRESS_CHAINED BIT(25) 334 #define RX_DESC_1_END_RING BIT(26) 335 /* [29:27] reserved */ 336 #define RX_DESC_1_RX_TIMESTAMP BIT(30) 337 #define RX_DESC_1_PTP_PKT BIT(31) 338 339 /* TX DMA descriptor */ 340 341 /* [29:0] unused */ 342 #define TX_DESC_0_TX_TIMESTAMP BIT(30) 343 #define TX_DESC_0_OWN BIT(31) 344 345 #define TX_DESC_1_BUFFER_SIZE_1_MASK GENMASK(11, 0) 346 #define TX_DESC_1_BUFFER_SIZE_2_MASK GENMASK(23, 12) 347 #define TX_DESC_1_FORCE_EOP_ERROR BIT(24) 348 #define TX_DESC_1_SECOND_ADDRESS_CHAINED BIT(25) 349 #define TX_DESC_1_END_RING BIT(26) 350 #define TX_DESC_1_DISABLE_PADDING BIT(27) 351 #define TX_DESC_1_ADD_CRC_DISABLE BIT(28) 352 #define TX_DESC_1_FIRST_SEGMENT BIT(29) 353 #define TX_DESC_1_LAST_SEGMENT BIT(30) 354 #define TX_DESC_1_INTERRUPT_ON_COMPLETION BIT(31) 355 356 struct emac_desc { 357 u32 desc0; 358 u32 desc1; 359 u32 buffer_addr_1; 360 u32 buffer_addr_2; 361 }; 362 363 /* Keep stats in this order, index used for accessing hardware */ 364 365 union emac_hw_tx_stats { 366 struct { 367 u64 tx_ok_pkts; 368 u64 tx_total_pkts; 369 u64 tx_ok_bytes; 370 u64 tx_err_pkts; 371 u64 tx_singleclsn_pkts; 372 u64 tx_multiclsn_pkts; 373 u64 tx_lateclsn_pkts; 374 u64 tx_excessclsn_pkts; 375 u64 tx_unicast_pkts; 376 u64 tx_multicast_pkts; 377 u64 tx_broadcast_pkts; 378 u64 tx_pause_pkts; 379 } stats; 380 381 DECLARE_FLEX_ARRAY(u64, array); 382 }; 383 384 union emac_hw_rx_stats { 385 struct { 386 u64 rx_ok_pkts; 387 u64 rx_total_pkts; 388 u64 rx_crc_err_pkts; 389 u64 rx_align_err_pkts; 390 u64 rx_err_total_pkts; 391 u64 rx_ok_bytes; 392 u64 rx_total_bytes; 393 u64 rx_unicast_pkts; 394 u64 rx_multicast_pkts; 395 u64 rx_broadcast_pkts; 396 u64 rx_pause_pkts; 397 u64 rx_len_err_pkts; 398 u64 rx_len_undersize_pkts; 399 u64 rx_len_oversize_pkts; 400 u64 rx_len_fragment_pkts; 401 u64 rx_len_jabber_pkts; 402 u64 rx_64_pkts; 403 u64 rx_65_127_pkts; 404 u64 rx_128_255_pkts; 405 u64 rx_256_511_pkts; 406 u64 rx_512_1023_pkts; 407 u64 rx_1024_1518_pkts; 408 u64 rx_1519_plus_pkts; 409 u64 rx_drp_fifo_full_pkts; 410 u64 rx_truncate_fifo_full_pkts; 411 } stats; 412 413 DECLARE_FLEX_ARRAY(u64, array); 414 }; 415 416 #endif /* _K1_EMAC_H_ */ 417