1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sni_ave.c - Socionext UniPhier AVE ethernet driver 4 * Copyright 2014 Panasonic Corporation 5 * Copyright 2015-2017 Socionext Inc. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/etherdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/mii.h> 16 #include <linux/module.h> 17 #include <linux/netdevice.h> 18 #include <linux/of.h> 19 #include <linux/of_net.h> 20 #include <linux/of_mdio.h> 21 #include <linux/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/regmap.h> 24 #include <linux/reset.h> 25 #include <linux/types.h> 26 #include <linux/u64_stats_sync.h> 27 28 /* General Register Group */ 29 #define AVE_IDR 0x000 /* ID */ 30 #define AVE_VR 0x004 /* Version */ 31 #define AVE_GRR 0x008 /* Global Reset */ 32 #define AVE_CFGR 0x00c /* Configuration */ 33 34 /* Interrupt Register Group */ 35 #define AVE_GIMR 0x100 /* Global Interrupt Mask */ 36 #define AVE_GISR 0x104 /* Global Interrupt Status */ 37 38 /* MAC Register Group */ 39 #define AVE_TXCR 0x200 /* TX Setup */ 40 #define AVE_RXCR 0x204 /* RX Setup */ 41 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */ 42 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */ 43 #define AVE_MDIOCTR 0x214 /* MDIO Control */ 44 #define AVE_MDIOAR 0x218 /* MDIO Address */ 45 #define AVE_MDIOWDR 0x21c /* MDIO Data */ 46 #define AVE_MDIOSR 0x220 /* MDIO Status */ 47 #define AVE_MDIORDR 0x224 /* MDIO Rd Data */ 48 49 /* Descriptor Control Register Group */ 50 #define AVE_DESCC 0x300 /* Descriptor Control */ 51 #define AVE_TXDC 0x304 /* TX Descriptor Configuration */ 52 #define AVE_RXDC0 0x308 /* RX Descriptor Ring0 Configuration */ 53 #define AVE_IIRQC 0x34c /* Interval IRQ Control */ 54 55 /* Packet Filter Register Group */ 56 #define AVE_PKTF_BASE 0x800 /* PF Base Address */ 57 #define AVE_PFMBYTE_BASE 0xd00 /* PF Mask Byte Base Address */ 58 #define AVE_PFMBIT_BASE 0xe00 /* PF Mask Bit Base Address */ 59 #define AVE_PFSEL_BASE 0xf00 /* PF Selector Base Address */ 60 #define AVE_PFEN 0xffc /* Packet Filter Enable */ 61 #define AVE_PKTF(ent) (AVE_PKTF_BASE + (ent) * 0x40) 62 #define AVE_PFMBYTE(ent) (AVE_PFMBYTE_BASE + (ent) * 8) 63 #define AVE_PFMBIT(ent) (AVE_PFMBIT_BASE + (ent) * 4) 64 #define AVE_PFSEL(ent) (AVE_PFSEL_BASE + (ent) * 4) 65 66 /* 64bit descriptor memory */ 67 #define AVE_DESC_SIZE_64 12 /* Descriptor Size */ 68 69 #define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */ 70 #define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */ 71 72 #define AVE_TXDM_SIZE_64 0x0ba0 /* Tx Descriptor Memory Size 3KB */ 73 #define AVE_RXDM_SIZE_64 0x6000 /* Rx Descriptor Memory Size 24KB */ 74 75 /* 32bit descriptor memory */ 76 #define AVE_DESC_SIZE_32 8 /* Descriptor Size */ 77 78 #define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */ 79 #define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */ 80 81 #define AVE_TXDM_SIZE_32 0x07c0 /* Tx Descriptor Memory Size 2KB */ 82 #define AVE_RXDM_SIZE_32 0x4000 /* Rx Descriptor Memory Size 16KB */ 83 84 /* RMII Bridge Register Group */ 85 #define AVE_RSTCTRL 0x8028 /* Reset control */ 86 #define AVE_RSTCTRL_RMIIRST BIT(16) 87 #define AVE_LINKSEL 0x8034 /* Link speed setting */ 88 #define AVE_LINKSEL_100M BIT(0) 89 90 /* AVE_GRR */ 91 #define AVE_GRR_RXFFR BIT(5) /* Reset RxFIFO */ 92 #define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */ 93 #define AVE_GRR_GRST BIT(0) /* Reset all MAC */ 94 95 /* AVE_CFGR */ 96 #define AVE_CFGR_FLE BIT(31) /* Filter Function */ 97 #define AVE_CFGR_CHE BIT(30) /* Checksum Function */ 98 #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */ 99 #define AVE_CFGR_IPFCEN BIT(24) /* IP fragment sum Enable */ 100 101 /* AVE_GISR (common with GIMR) */ 102 #define AVE_GI_PHY BIT(24) /* PHY interrupt */ 103 #define AVE_GI_TX BIT(16) /* Tx complete */ 104 #define AVE_GI_RXERR BIT(8) /* Receive frame more than max size */ 105 #define AVE_GI_RXOVF BIT(7) /* Overflow at the RxFIFO */ 106 #define AVE_GI_RXDROP BIT(6) /* Drop packet */ 107 #define AVE_GI_RXIINT BIT(5) /* Interval interrupt */ 108 109 /* AVE_TXCR */ 110 #define AVE_TXCR_FLOCTR BIT(18) /* Flow control */ 111 #define AVE_TXCR_TXSPD_1G BIT(17) 112 #define AVE_TXCR_TXSPD_100 BIT(16) 113 114 /* AVE_RXCR */ 115 #define AVE_RXCR_RXEN BIT(30) /* Rx enable */ 116 #define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */ 117 #define AVE_RXCR_FLOCTR BIT(21) /* Flow control */ 118 #define AVE_RXCR_AFEN BIT(19) /* MAC address filter */ 119 #define AVE_RXCR_DRPEN BIT(18) /* Drop pause frame */ 120 #define AVE_RXCR_MPSIZ_MASK GENMASK(10, 0) 121 122 /* AVE_MDIOCTR */ 123 #define AVE_MDIOCTR_RREQ BIT(3) /* Read request */ 124 #define AVE_MDIOCTR_WREQ BIT(2) /* Write request */ 125 126 /* AVE_MDIOSR */ 127 #define AVE_MDIOSR_STS BIT(0) /* access status */ 128 129 /* AVE_DESCC */ 130 #define AVE_DESCC_STATUS_MASK GENMASK(31, 16) 131 #define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */ 132 #define AVE_DESCC_RDSTP BIT(4) /* Pause Rx descriptor */ 133 #define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */ 134 135 /* AVE_TXDC */ 136 #define AVE_TXDC_SIZE GENMASK(27, 16) /* Size of Tx descriptor */ 137 #define AVE_TXDC_ADDR GENMASK(11, 0) /* Start address */ 138 #define AVE_TXDC_ADDR_START 0 139 140 /* AVE_RXDC0 */ 141 #define AVE_RXDC0_SIZE GENMASK(30, 16) /* Size of Rx descriptor */ 142 #define AVE_RXDC0_ADDR GENMASK(14, 0) /* Start address */ 143 #define AVE_RXDC0_ADDR_START 0 144 145 /* AVE_IIRQC */ 146 #define AVE_IIRQC_EN0 BIT(27) /* Enable interval interrupt Ring0 */ 147 #define AVE_IIRQC_BSCK GENMASK(15, 0) /* Interval count unit */ 148 149 /* Command status for descriptor */ 150 #define AVE_STS_OWN BIT(31) /* Descriptor ownership */ 151 #define AVE_STS_INTR BIT(29) /* Request for interrupt */ 152 #define AVE_STS_OK BIT(27) /* Normal transmit */ 153 /* TX */ 154 #define AVE_STS_NOCSUM BIT(28) /* No use HW checksum */ 155 #define AVE_STS_1ST BIT(26) /* Head of buffer chain */ 156 #define AVE_STS_LAST BIT(25) /* Tail of buffer chain */ 157 #define AVE_STS_OWC BIT(21) /* Out of window,Late Collision */ 158 #define AVE_STS_EC BIT(20) /* Excess collision occurred */ 159 #define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0) 160 /* RX */ 161 #define AVE_STS_CSSV BIT(21) /* Checksum check performed */ 162 #define AVE_STS_CSER BIT(20) /* Checksum error detected */ 163 #define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0) 164 165 /* Packet filter */ 166 #define AVE_PFMBYTE_MASK0 (GENMASK(31, 8) | GENMASK(5, 0)) 167 #define AVE_PFMBYTE_MASK1 GENMASK(25, 0) 168 #define AVE_PFMBIT_MASK GENMASK(15, 0) 169 170 #define AVE_PF_SIZE 17 /* Number of all packet filter */ 171 #define AVE_PF_MULTICAST_SIZE 7 /* Number of multicast filter */ 172 173 #define AVE_PFNUM_FILTER 0 /* No.0 */ 174 #define AVE_PFNUM_UNICAST 1 /* No.1 */ 175 #define AVE_PFNUM_BROADCAST 2 /* No.2 */ 176 #define AVE_PFNUM_MULTICAST 11 /* No.11-17 */ 177 178 /* NETIF Message control */ 179 #define AVE_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 180 NETIF_MSG_PROBE | \ 181 NETIF_MSG_LINK | \ 182 NETIF_MSG_TIMER | \ 183 NETIF_MSG_IFDOWN | \ 184 NETIF_MSG_IFUP | \ 185 NETIF_MSG_RX_ERR | \ 186 NETIF_MSG_TX_ERR) 187 188 /* Parameter for descriptor */ 189 #define AVE_NR_TXDESC 64 /* Tx descriptor */ 190 #define AVE_NR_RXDESC 256 /* Rx descriptor */ 191 192 #define AVE_DESC_OFS_CMDSTS 0 193 #define AVE_DESC_OFS_ADDRL 4 194 #define AVE_DESC_OFS_ADDRU 8 195 196 /* Parameter for ethernet frame */ 197 #define AVE_MAX_ETHFRAME 1518 198 #define AVE_FRAME_HEADROOM 2 199 200 /* Parameter for interrupt */ 201 #define AVE_INTM_COUNT 20 202 #define AVE_FORCE_TXINTCNT 1 203 204 /* SG */ 205 #define SG_ETPINMODE 0x540 206 #define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */ 207 #define SG_ETPINMODE_RMII(ins) BIT(ins) 208 209 #define IS_DESC_64BIT(p) ((p)->data->is_desc_64bit) 210 211 #define AVE_MAX_CLKS 4 212 #define AVE_MAX_RSTS 2 213 214 enum desc_id { 215 AVE_DESCID_RX, 216 AVE_DESCID_TX, 217 }; 218 219 enum desc_state { 220 AVE_DESC_RX_PERMIT, 221 AVE_DESC_RX_SUSPEND, 222 AVE_DESC_START, 223 AVE_DESC_STOP, 224 }; 225 226 struct ave_desc { 227 struct sk_buff *skbs; 228 dma_addr_t skbs_dma; 229 size_t skbs_dmalen; 230 }; 231 232 struct ave_desc_info { 233 u32 ndesc; /* number of descriptor */ 234 u32 daddr; /* start address of descriptor */ 235 u32 proc_idx; /* index of processing packet */ 236 u32 done_idx; /* index of processed packet */ 237 struct ave_desc *desc; /* skb info related descriptor */ 238 }; 239 240 struct ave_stats { 241 struct u64_stats_sync syncp; 242 u64 packets; 243 u64 bytes; 244 u64 errors; 245 u64 dropped; 246 u64 collisions; 247 u64 fifo_errors; 248 }; 249 250 struct ave_private { 251 void __iomem *base; 252 int irq; 253 int phy_id; 254 unsigned int desc_size; 255 u32 msg_enable; 256 int nclks; 257 struct clk *clk[AVE_MAX_CLKS]; 258 int nrsts; 259 struct reset_control *rst[AVE_MAX_RSTS]; 260 phy_interface_t phy_mode; 261 struct phy_device *phydev; 262 struct mii_bus *mdio; 263 struct regmap *regmap; 264 unsigned int pinmode_mask; 265 unsigned int pinmode_val; 266 u32 wolopts; 267 268 /* stats */ 269 struct ave_stats stats_rx; 270 struct ave_stats stats_tx; 271 272 /* NAPI support */ 273 struct net_device *ndev; 274 struct napi_struct napi_rx; 275 struct napi_struct napi_tx; 276 277 /* descriptor */ 278 struct ave_desc_info rx; 279 struct ave_desc_info tx; 280 281 /* flow control */ 282 int pause_auto; 283 int pause_rx; 284 int pause_tx; 285 286 const struct ave_soc_data *data; 287 }; 288 289 struct ave_soc_data { 290 bool is_desc_64bit; 291 const char *clock_names[AVE_MAX_CLKS]; 292 const char *reset_names[AVE_MAX_RSTS]; 293 int (*get_pinmode)(struct ave_private *priv, 294 phy_interface_t phy_mode, u32 arg); 295 }; 296 297 static u32 ave_desc_read(struct net_device *ndev, enum desc_id id, int entry, 298 int offset) 299 { 300 struct ave_private *priv = netdev_priv(ndev); 301 u32 addr; 302 303 addr = ((id == AVE_DESCID_TX) ? priv->tx.daddr : priv->rx.daddr) 304 + entry * priv->desc_size + offset; 305 306 return readl(priv->base + addr); 307 } 308 309 static u32 ave_desc_read_cmdsts(struct net_device *ndev, enum desc_id id, 310 int entry) 311 { 312 return ave_desc_read(ndev, id, entry, AVE_DESC_OFS_CMDSTS); 313 } 314 315 static void ave_desc_write(struct net_device *ndev, enum desc_id id, 316 int entry, int offset, u32 val) 317 { 318 struct ave_private *priv = netdev_priv(ndev); 319 u32 addr; 320 321 addr = ((id == AVE_DESCID_TX) ? priv->tx.daddr : priv->rx.daddr) 322 + entry * priv->desc_size + offset; 323 324 writel(val, priv->base + addr); 325 } 326 327 static void ave_desc_write_cmdsts(struct net_device *ndev, enum desc_id id, 328 int entry, u32 val) 329 { 330 ave_desc_write(ndev, id, entry, AVE_DESC_OFS_CMDSTS, val); 331 } 332 333 static void ave_desc_write_addr(struct net_device *ndev, enum desc_id id, 334 int entry, dma_addr_t paddr) 335 { 336 struct ave_private *priv = netdev_priv(ndev); 337 338 ave_desc_write(ndev, id, entry, AVE_DESC_OFS_ADDRL, 339 lower_32_bits(paddr)); 340 if (IS_DESC_64BIT(priv)) 341 ave_desc_write(ndev, id, 342 entry, AVE_DESC_OFS_ADDRU, 343 upper_32_bits(paddr)); 344 } 345 346 static u32 ave_irq_disable_all(struct net_device *ndev) 347 { 348 struct ave_private *priv = netdev_priv(ndev); 349 u32 ret; 350 351 ret = readl(priv->base + AVE_GIMR); 352 writel(0, priv->base + AVE_GIMR); 353 354 return ret; 355 } 356 357 static void ave_irq_restore(struct net_device *ndev, u32 val) 358 { 359 struct ave_private *priv = netdev_priv(ndev); 360 361 writel(val, priv->base + AVE_GIMR); 362 } 363 364 static void ave_irq_enable(struct net_device *ndev, u32 bitflag) 365 { 366 struct ave_private *priv = netdev_priv(ndev); 367 368 writel(readl(priv->base + AVE_GIMR) | bitflag, priv->base + AVE_GIMR); 369 writel(bitflag, priv->base + AVE_GISR); 370 } 371 372 static void ave_hw_write_macaddr(struct net_device *ndev, 373 const unsigned char *mac_addr, 374 int reg1, int reg2) 375 { 376 struct ave_private *priv = netdev_priv(ndev); 377 378 writel(mac_addr[0] | mac_addr[1] << 8 | 379 mac_addr[2] << 16 | mac_addr[3] << 24, priv->base + reg1); 380 writel(mac_addr[4] | mac_addr[5] << 8, priv->base + reg2); 381 } 382 383 static void ave_hw_read_version(struct net_device *ndev, char *buf, int len) 384 { 385 struct ave_private *priv = netdev_priv(ndev); 386 u32 major, minor, vr; 387 388 vr = readl(priv->base + AVE_VR); 389 major = (vr & GENMASK(15, 8)) >> 8; 390 minor = (vr & GENMASK(7, 0)); 391 snprintf(buf, len, "v%u.%u", major, minor); 392 } 393 394 static void ave_ethtool_get_drvinfo(struct net_device *ndev, 395 struct ethtool_drvinfo *info) 396 { 397 struct device *dev = ndev->dev.parent; 398 399 strscpy(info->driver, dev->driver->name, sizeof(info->driver)); 400 strscpy(info->bus_info, dev_name(dev), sizeof(info->bus_info)); 401 ave_hw_read_version(ndev, info->fw_version, sizeof(info->fw_version)); 402 } 403 404 static u32 ave_ethtool_get_msglevel(struct net_device *ndev) 405 { 406 struct ave_private *priv = netdev_priv(ndev); 407 408 return priv->msg_enable; 409 } 410 411 static void ave_ethtool_set_msglevel(struct net_device *ndev, u32 val) 412 { 413 struct ave_private *priv = netdev_priv(ndev); 414 415 priv->msg_enable = val; 416 } 417 418 static void ave_ethtool_get_wol(struct net_device *ndev, 419 struct ethtool_wolinfo *wol) 420 { 421 wol->supported = 0; 422 wol->wolopts = 0; 423 424 if (ndev->phydev) 425 phy_ethtool_get_wol(ndev->phydev, wol); 426 } 427 428 static int __ave_ethtool_set_wol(struct net_device *ndev, 429 struct ethtool_wolinfo *wol) 430 { 431 if (!ndev->phydev || 432 (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))) 433 return -EOPNOTSUPP; 434 435 return phy_ethtool_set_wol(ndev->phydev, wol); 436 } 437 438 static int ave_ethtool_set_wol(struct net_device *ndev, 439 struct ethtool_wolinfo *wol) 440 { 441 int ret; 442 443 ret = __ave_ethtool_set_wol(ndev, wol); 444 if (!ret) 445 device_set_wakeup_enable(&ndev->dev, !!wol->wolopts); 446 447 return ret; 448 } 449 450 static void ave_ethtool_get_pauseparam(struct net_device *ndev, 451 struct ethtool_pauseparam *pause) 452 { 453 struct ave_private *priv = netdev_priv(ndev); 454 455 pause->autoneg = priv->pause_auto; 456 pause->rx_pause = priv->pause_rx; 457 pause->tx_pause = priv->pause_tx; 458 } 459 460 static int ave_ethtool_set_pauseparam(struct net_device *ndev, 461 struct ethtool_pauseparam *pause) 462 { 463 struct ave_private *priv = netdev_priv(ndev); 464 struct phy_device *phydev = ndev->phydev; 465 466 if (!phydev) 467 return -EINVAL; 468 469 priv->pause_auto = pause->autoneg; 470 priv->pause_rx = pause->rx_pause; 471 priv->pause_tx = pause->tx_pause; 472 473 phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause); 474 475 return 0; 476 } 477 478 static const struct ethtool_ops ave_ethtool_ops = { 479 .get_link_ksettings = phy_ethtool_get_link_ksettings, 480 .set_link_ksettings = phy_ethtool_set_link_ksettings, 481 .get_drvinfo = ave_ethtool_get_drvinfo, 482 .nway_reset = phy_ethtool_nway_reset, 483 .get_link = ethtool_op_get_link, 484 .get_msglevel = ave_ethtool_get_msglevel, 485 .set_msglevel = ave_ethtool_set_msglevel, 486 .get_wol = ave_ethtool_get_wol, 487 .set_wol = ave_ethtool_set_wol, 488 .get_pauseparam = ave_ethtool_get_pauseparam, 489 .set_pauseparam = ave_ethtool_set_pauseparam, 490 }; 491 492 static int ave_mdiobus_read(struct mii_bus *bus, int phyid, int regnum) 493 { 494 struct net_device *ndev = bus->priv; 495 struct ave_private *priv; 496 u32 mdioctl, mdiosr; 497 int ret; 498 499 priv = netdev_priv(ndev); 500 501 /* write address */ 502 writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR); 503 504 /* read request */ 505 mdioctl = readl(priv->base + AVE_MDIOCTR); 506 writel((mdioctl | AVE_MDIOCTR_RREQ) & ~AVE_MDIOCTR_WREQ, 507 priv->base + AVE_MDIOCTR); 508 509 ret = readl_poll_timeout(priv->base + AVE_MDIOSR, mdiosr, 510 !(mdiosr & AVE_MDIOSR_STS), 20, 2000); 511 if (ret) { 512 netdev_err(ndev, "failed to read (phy:%d reg:%x)\n", 513 phyid, regnum); 514 return ret; 515 } 516 517 return readl(priv->base + AVE_MDIORDR) & GENMASK(15, 0); 518 } 519 520 static int ave_mdiobus_write(struct mii_bus *bus, int phyid, int regnum, 521 u16 val) 522 { 523 struct net_device *ndev = bus->priv; 524 struct ave_private *priv; 525 u32 mdioctl, mdiosr; 526 int ret; 527 528 priv = netdev_priv(ndev); 529 530 /* write address */ 531 writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR); 532 533 /* write data */ 534 writel(val, priv->base + AVE_MDIOWDR); 535 536 /* write request */ 537 mdioctl = readl(priv->base + AVE_MDIOCTR); 538 writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ, 539 priv->base + AVE_MDIOCTR); 540 541 ret = readl_poll_timeout(priv->base + AVE_MDIOSR, mdiosr, 542 !(mdiosr & AVE_MDIOSR_STS), 20, 2000); 543 if (ret) 544 netdev_err(ndev, "failed to write (phy:%d reg:%x)\n", 545 phyid, regnum); 546 547 return ret; 548 } 549 550 static int ave_dma_map(struct net_device *ndev, struct ave_desc *desc, 551 void *ptr, size_t len, enum dma_data_direction dir, 552 dma_addr_t *paddr) 553 { 554 dma_addr_t map_addr; 555 556 map_addr = dma_map_single(ndev->dev.parent, ptr, len, dir); 557 if (unlikely(dma_mapping_error(ndev->dev.parent, map_addr))) 558 return -ENOMEM; 559 560 desc->skbs_dma = map_addr; 561 desc->skbs_dmalen = len; 562 *paddr = map_addr; 563 564 return 0; 565 } 566 567 static void ave_dma_unmap(struct net_device *ndev, struct ave_desc *desc, 568 enum dma_data_direction dir) 569 { 570 if (!desc->skbs_dma) 571 return; 572 573 dma_unmap_single(ndev->dev.parent, 574 desc->skbs_dma, desc->skbs_dmalen, dir); 575 desc->skbs_dma = 0; 576 } 577 578 /* Prepare Rx descriptor and memory */ 579 static int ave_rxdesc_prepare(struct net_device *ndev, int entry) 580 { 581 struct ave_private *priv = netdev_priv(ndev); 582 struct sk_buff *skb; 583 dma_addr_t paddr; 584 int ret; 585 586 skb = priv->rx.desc[entry].skbs; 587 if (!skb) { 588 skb = netdev_alloc_skb(ndev, AVE_MAX_ETHFRAME); 589 if (!skb) 590 return -ENOMEM; 591 skb->data += AVE_FRAME_HEADROOM; 592 skb->tail += AVE_FRAME_HEADROOM; 593 } 594 595 /* set disable to cmdsts */ 596 ave_desc_write_cmdsts(ndev, AVE_DESCID_RX, entry, 597 AVE_STS_INTR | AVE_STS_OWN); 598 599 /* map Rx buffer 600 * Rx buffer set to the Rx descriptor has two restrictions: 601 * - Rx buffer address is 4 byte aligned. 602 * - Rx buffer begins with 2 byte headroom, and data will be put from 603 * (buffer + 2). 604 * To satisfy this, specify the address to put back the buffer 605 * pointer advanced by AVE_FRAME_HEADROOM, and expand the map size 606 * by AVE_FRAME_HEADROOM. 607 */ 608 ret = ave_dma_map(ndev, &priv->rx.desc[entry], 609 skb->data - AVE_FRAME_HEADROOM, 610 AVE_MAX_ETHFRAME + AVE_FRAME_HEADROOM, 611 DMA_FROM_DEVICE, &paddr); 612 if (ret) { 613 netdev_err(ndev, "can't map skb for Rx\n"); 614 dev_kfree_skb_any(skb); 615 return ret; 616 } 617 priv->rx.desc[entry].skbs = skb; 618 619 /* set buffer pointer */ 620 ave_desc_write_addr(ndev, AVE_DESCID_RX, entry, paddr); 621 622 /* set enable to cmdsts */ 623 ave_desc_write_cmdsts(ndev, AVE_DESCID_RX, entry, 624 AVE_STS_INTR | AVE_MAX_ETHFRAME); 625 626 return ret; 627 } 628 629 /* Switch state of descriptor */ 630 static int ave_desc_switch(struct net_device *ndev, enum desc_state state) 631 { 632 struct ave_private *priv = netdev_priv(ndev); 633 int ret = 0; 634 u32 val; 635 636 switch (state) { 637 case AVE_DESC_START: 638 writel(AVE_DESCC_TD | AVE_DESCC_RD0, priv->base + AVE_DESCC); 639 break; 640 641 case AVE_DESC_STOP: 642 writel(0, priv->base + AVE_DESCC); 643 if (readl_poll_timeout(priv->base + AVE_DESCC, val, !val, 644 150, 15000)) { 645 netdev_err(ndev, "can't stop descriptor\n"); 646 ret = -EBUSY; 647 } 648 break; 649 650 case AVE_DESC_RX_SUSPEND: 651 val = readl(priv->base + AVE_DESCC); 652 val |= AVE_DESCC_RDSTP; 653 val &= ~AVE_DESCC_STATUS_MASK; 654 writel(val, priv->base + AVE_DESCC); 655 if (readl_poll_timeout(priv->base + AVE_DESCC, val, 656 val & (AVE_DESCC_RDSTP << 16), 657 150, 150000)) { 658 netdev_err(ndev, "can't suspend descriptor\n"); 659 ret = -EBUSY; 660 } 661 break; 662 663 case AVE_DESC_RX_PERMIT: 664 val = readl(priv->base + AVE_DESCC); 665 val &= ~AVE_DESCC_RDSTP; 666 val &= ~AVE_DESCC_STATUS_MASK; 667 writel(val, priv->base + AVE_DESCC); 668 break; 669 670 default: 671 ret = -EINVAL; 672 break; 673 } 674 675 return ret; 676 } 677 678 static int ave_tx_complete(struct net_device *ndev) 679 { 680 struct ave_private *priv = netdev_priv(ndev); 681 u32 proc_idx, done_idx, ndesc, cmdsts; 682 unsigned int nr_freebuf = 0; 683 unsigned int tx_packets = 0; 684 unsigned int tx_bytes = 0; 685 686 proc_idx = priv->tx.proc_idx; 687 done_idx = priv->tx.done_idx; 688 ndesc = priv->tx.ndesc; 689 690 /* free pre-stored skb from done_idx to proc_idx */ 691 while (proc_idx != done_idx) { 692 cmdsts = ave_desc_read_cmdsts(ndev, AVE_DESCID_TX, done_idx); 693 694 /* do nothing if owner is HW (==1 for Tx) */ 695 if (cmdsts & AVE_STS_OWN) 696 break; 697 698 /* check Tx status and updates statistics */ 699 if (cmdsts & AVE_STS_OK) { 700 tx_bytes += cmdsts & AVE_STS_PKTLEN_TX_MASK; 701 /* success */ 702 if (cmdsts & AVE_STS_LAST) 703 tx_packets++; 704 } else { 705 /* error */ 706 if (cmdsts & AVE_STS_LAST) { 707 priv->stats_tx.errors++; 708 if (cmdsts & (AVE_STS_OWC | AVE_STS_EC)) 709 priv->stats_tx.collisions++; 710 } 711 } 712 713 /* release skb */ 714 if (priv->tx.desc[done_idx].skbs) { 715 ave_dma_unmap(ndev, &priv->tx.desc[done_idx], 716 DMA_TO_DEVICE); 717 dev_consume_skb_any(priv->tx.desc[done_idx].skbs); 718 priv->tx.desc[done_idx].skbs = NULL; 719 nr_freebuf++; 720 } 721 done_idx = (done_idx + 1) % ndesc; 722 } 723 724 priv->tx.done_idx = done_idx; 725 726 /* update stats */ 727 u64_stats_update_begin(&priv->stats_tx.syncp); 728 priv->stats_tx.packets += tx_packets; 729 priv->stats_tx.bytes += tx_bytes; 730 u64_stats_update_end(&priv->stats_tx.syncp); 731 732 /* wake queue for freeing buffer */ 733 if (unlikely(netif_queue_stopped(ndev)) && nr_freebuf) 734 netif_wake_queue(ndev); 735 736 return nr_freebuf; 737 } 738 739 static int ave_rx_receive(struct net_device *ndev, int num) 740 { 741 struct ave_private *priv = netdev_priv(ndev); 742 unsigned int rx_packets = 0; 743 unsigned int rx_bytes = 0; 744 u32 proc_idx, done_idx; 745 struct sk_buff *skb; 746 unsigned int pktlen; 747 int restpkt, npkts; 748 u32 ndesc, cmdsts; 749 750 proc_idx = priv->rx.proc_idx; 751 done_idx = priv->rx.done_idx; 752 ndesc = priv->rx.ndesc; 753 restpkt = ((proc_idx + ndesc - 1) - done_idx) % ndesc; 754 755 for (npkts = 0; npkts < num; npkts++) { 756 /* we can't receive more packet, so fill desc quickly */ 757 if (--restpkt < 0) 758 break; 759 760 cmdsts = ave_desc_read_cmdsts(ndev, AVE_DESCID_RX, proc_idx); 761 762 /* do nothing if owner is HW (==0 for Rx) */ 763 if (!(cmdsts & AVE_STS_OWN)) 764 break; 765 766 if (!(cmdsts & AVE_STS_OK)) { 767 priv->stats_rx.errors++; 768 proc_idx = (proc_idx + 1) % ndesc; 769 continue; 770 } 771 772 pktlen = cmdsts & AVE_STS_PKTLEN_RX_MASK; 773 774 /* get skbuff for rx */ 775 skb = priv->rx.desc[proc_idx].skbs; 776 priv->rx.desc[proc_idx].skbs = NULL; 777 778 ave_dma_unmap(ndev, &priv->rx.desc[proc_idx], DMA_FROM_DEVICE); 779 780 skb->dev = ndev; 781 skb_put(skb, pktlen); 782 skb->protocol = eth_type_trans(skb, ndev); 783 784 if ((cmdsts & AVE_STS_CSSV) && (!(cmdsts & AVE_STS_CSER))) 785 skb->ip_summed = CHECKSUM_UNNECESSARY; 786 787 rx_packets++; 788 rx_bytes += pktlen; 789 790 netif_receive_skb(skb); 791 792 proc_idx = (proc_idx + 1) % ndesc; 793 } 794 795 priv->rx.proc_idx = proc_idx; 796 797 /* update stats */ 798 u64_stats_update_begin(&priv->stats_rx.syncp); 799 priv->stats_rx.packets += rx_packets; 800 priv->stats_rx.bytes += rx_bytes; 801 u64_stats_update_end(&priv->stats_rx.syncp); 802 803 /* refill the Rx buffers */ 804 while (proc_idx != done_idx) { 805 if (ave_rxdesc_prepare(ndev, done_idx)) 806 break; 807 done_idx = (done_idx + 1) % ndesc; 808 } 809 810 priv->rx.done_idx = done_idx; 811 812 return npkts; 813 } 814 815 static int ave_napi_poll_rx(struct napi_struct *napi, int budget) 816 { 817 struct ave_private *priv; 818 struct net_device *ndev; 819 int num; 820 821 priv = container_of(napi, struct ave_private, napi_rx); 822 ndev = priv->ndev; 823 824 num = ave_rx_receive(ndev, budget); 825 if (num < budget) { 826 napi_complete_done(napi, num); 827 828 /* enable Rx interrupt when NAPI finishes */ 829 ave_irq_enable(ndev, AVE_GI_RXIINT); 830 } 831 832 return num; 833 } 834 835 static int ave_napi_poll_tx(struct napi_struct *napi, int budget) 836 { 837 struct ave_private *priv; 838 struct net_device *ndev; 839 int num; 840 841 priv = container_of(napi, struct ave_private, napi_tx); 842 ndev = priv->ndev; 843 844 num = ave_tx_complete(ndev); 845 napi_complete(napi); 846 847 /* enable Tx interrupt when NAPI finishes */ 848 ave_irq_enable(ndev, AVE_GI_TX); 849 850 return num; 851 } 852 853 static void ave_global_reset(struct net_device *ndev) 854 { 855 struct ave_private *priv = netdev_priv(ndev); 856 u32 val; 857 858 /* set config register */ 859 val = AVE_CFGR_FLE | AVE_CFGR_IPFCEN | AVE_CFGR_CHE; 860 if (!phy_interface_mode_is_rgmii(priv->phy_mode)) 861 val |= AVE_CFGR_MII; 862 writel(val, priv->base + AVE_CFGR); 863 864 /* reset RMII register */ 865 val = readl(priv->base + AVE_RSTCTRL); 866 val &= ~AVE_RSTCTRL_RMIIRST; 867 writel(val, priv->base + AVE_RSTCTRL); 868 869 /* assert reset */ 870 writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->base + AVE_GRR); 871 msleep(20); 872 873 /* 1st, negate PHY reset only */ 874 writel(AVE_GRR_GRST, priv->base + AVE_GRR); 875 msleep(40); 876 877 /* negate reset */ 878 writel(0, priv->base + AVE_GRR); 879 msleep(40); 880 881 /* negate RMII register */ 882 val = readl(priv->base + AVE_RSTCTRL); 883 val |= AVE_RSTCTRL_RMIIRST; 884 writel(val, priv->base + AVE_RSTCTRL); 885 886 ave_irq_disable_all(ndev); 887 } 888 889 static void ave_rxfifo_reset(struct net_device *ndev) 890 { 891 struct ave_private *priv = netdev_priv(ndev); 892 u32 rxcr_org; 893 894 /* save and disable MAC receive op */ 895 rxcr_org = readl(priv->base + AVE_RXCR); 896 writel(rxcr_org & (~AVE_RXCR_RXEN), priv->base + AVE_RXCR); 897 898 /* suspend Rx descriptor */ 899 ave_desc_switch(ndev, AVE_DESC_RX_SUSPEND); 900 901 /* receive all packets before descriptor starts */ 902 ave_rx_receive(ndev, priv->rx.ndesc); 903 904 /* assert reset */ 905 writel(AVE_GRR_RXFFR, priv->base + AVE_GRR); 906 udelay(50); 907 908 /* negate reset */ 909 writel(0, priv->base + AVE_GRR); 910 udelay(20); 911 912 /* negate interrupt status */ 913 writel(AVE_GI_RXOVF, priv->base + AVE_GISR); 914 915 /* permit descriptor */ 916 ave_desc_switch(ndev, AVE_DESC_RX_PERMIT); 917 918 /* restore MAC reccieve op */ 919 writel(rxcr_org, priv->base + AVE_RXCR); 920 } 921 922 static irqreturn_t ave_irq_handler(int irq, void *netdev) 923 { 924 struct net_device *ndev = (struct net_device *)netdev; 925 struct ave_private *priv = netdev_priv(ndev); 926 u32 gimr_val, gisr_val; 927 928 gimr_val = ave_irq_disable_all(ndev); 929 930 /* get interrupt status */ 931 gisr_val = readl(priv->base + AVE_GISR); 932 933 /* PHY */ 934 if (gisr_val & AVE_GI_PHY) 935 writel(AVE_GI_PHY, priv->base + AVE_GISR); 936 937 /* check exceeding packet */ 938 if (gisr_val & AVE_GI_RXERR) { 939 writel(AVE_GI_RXERR, priv->base + AVE_GISR); 940 netdev_err(ndev, "receive a packet exceeding frame buffer\n"); 941 } 942 943 gisr_val &= gimr_val; 944 if (!gisr_val) 945 goto exit_isr; 946 947 /* RxFIFO overflow */ 948 if (gisr_val & AVE_GI_RXOVF) { 949 priv->stats_rx.fifo_errors++; 950 ave_rxfifo_reset(ndev); 951 goto exit_isr; 952 } 953 954 /* Rx drop */ 955 if (gisr_val & AVE_GI_RXDROP) { 956 priv->stats_rx.dropped++; 957 writel(AVE_GI_RXDROP, priv->base + AVE_GISR); 958 } 959 960 /* Rx interval */ 961 if (gisr_val & AVE_GI_RXIINT) { 962 napi_schedule(&priv->napi_rx); 963 /* still force to disable Rx interrupt until NAPI finishes */ 964 gimr_val &= ~AVE_GI_RXIINT; 965 } 966 967 /* Tx completed */ 968 if (gisr_val & AVE_GI_TX) { 969 napi_schedule(&priv->napi_tx); 970 /* still force to disable Tx interrupt until NAPI finishes */ 971 gimr_val &= ~AVE_GI_TX; 972 } 973 974 exit_isr: 975 ave_irq_restore(ndev, gimr_val); 976 977 return IRQ_HANDLED; 978 } 979 980 static int ave_pfsel_start(struct net_device *ndev, unsigned int entry) 981 { 982 struct ave_private *priv = netdev_priv(ndev); 983 u32 val; 984 985 if (WARN_ON(entry > AVE_PF_SIZE)) 986 return -EINVAL; 987 988 val = readl(priv->base + AVE_PFEN); 989 writel(val | BIT(entry), priv->base + AVE_PFEN); 990 991 return 0; 992 } 993 994 static int ave_pfsel_stop(struct net_device *ndev, unsigned int entry) 995 { 996 struct ave_private *priv = netdev_priv(ndev); 997 u32 val; 998 999 if (WARN_ON(entry > AVE_PF_SIZE)) 1000 return -EINVAL; 1001 1002 val = readl(priv->base + AVE_PFEN); 1003 writel(val & ~BIT(entry), priv->base + AVE_PFEN); 1004 1005 return 0; 1006 } 1007 1008 static int ave_pfsel_set_macaddr(struct net_device *ndev, 1009 unsigned int entry, 1010 const unsigned char *mac_addr, 1011 unsigned int set_size) 1012 { 1013 struct ave_private *priv = netdev_priv(ndev); 1014 1015 if (WARN_ON(entry > AVE_PF_SIZE)) 1016 return -EINVAL; 1017 if (WARN_ON(set_size > 6)) 1018 return -EINVAL; 1019 1020 ave_pfsel_stop(ndev, entry); 1021 1022 /* set MAC address for the filter */ 1023 ave_hw_write_macaddr(ndev, mac_addr, 1024 AVE_PKTF(entry), AVE_PKTF(entry) + 4); 1025 1026 /* set byte mask */ 1027 writel(GENMASK(31, set_size) & AVE_PFMBYTE_MASK0, 1028 priv->base + AVE_PFMBYTE(entry)); 1029 writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4); 1030 1031 /* set bit mask filter */ 1032 writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry)); 1033 1034 /* set selector to ring 0 */ 1035 writel(0, priv->base + AVE_PFSEL(entry)); 1036 1037 /* restart filter */ 1038 ave_pfsel_start(ndev, entry); 1039 1040 return 0; 1041 } 1042 1043 static void ave_pfsel_set_promisc(struct net_device *ndev, 1044 unsigned int entry, u32 rxring) 1045 { 1046 struct ave_private *priv = netdev_priv(ndev); 1047 1048 if (WARN_ON(entry > AVE_PF_SIZE)) 1049 return; 1050 1051 ave_pfsel_stop(ndev, entry); 1052 1053 /* set byte mask */ 1054 writel(AVE_PFMBYTE_MASK0, priv->base + AVE_PFMBYTE(entry)); 1055 writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4); 1056 1057 /* set bit mask filter */ 1058 writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry)); 1059 1060 /* set selector to rxring */ 1061 writel(rxring, priv->base + AVE_PFSEL(entry)); 1062 1063 ave_pfsel_start(ndev, entry); 1064 } 1065 1066 static void ave_pfsel_init(struct net_device *ndev) 1067 { 1068 unsigned char bcast_mac[ETH_ALEN]; 1069 int i; 1070 1071 eth_broadcast_addr(bcast_mac); 1072 1073 for (i = 0; i < AVE_PF_SIZE; i++) 1074 ave_pfsel_stop(ndev, i); 1075 1076 /* promiscious entry, select ring 0 */ 1077 ave_pfsel_set_promisc(ndev, AVE_PFNUM_FILTER, 0); 1078 1079 /* unicast entry */ 1080 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_UNICAST, ndev->dev_addr, 6); 1081 1082 /* broadcast entry */ 1083 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_BROADCAST, bcast_mac, 6); 1084 } 1085 1086 static void ave_phy_adjust_link(struct net_device *ndev) 1087 { 1088 struct ave_private *priv = netdev_priv(ndev); 1089 struct phy_device *phydev = ndev->phydev; 1090 u32 val, txcr, rxcr, rxcr_org; 1091 u16 rmt_adv = 0, lcl_adv = 0; 1092 u8 cap; 1093 1094 /* set RGMII speed */ 1095 val = readl(priv->base + AVE_TXCR); 1096 val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G); 1097 1098 if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000) 1099 val |= AVE_TXCR_TXSPD_1G; 1100 else if (phydev->speed == SPEED_100) 1101 val |= AVE_TXCR_TXSPD_100; 1102 1103 writel(val, priv->base + AVE_TXCR); 1104 1105 /* set RMII speed (100M/10M only) */ 1106 if (!phy_interface_is_rgmii(phydev)) { 1107 val = readl(priv->base + AVE_LINKSEL); 1108 if (phydev->speed == SPEED_10) 1109 val &= ~AVE_LINKSEL_100M; 1110 else 1111 val |= AVE_LINKSEL_100M; 1112 writel(val, priv->base + AVE_LINKSEL); 1113 } 1114 1115 /* check current RXCR/TXCR */ 1116 rxcr = readl(priv->base + AVE_RXCR); 1117 txcr = readl(priv->base + AVE_TXCR); 1118 rxcr_org = rxcr; 1119 1120 if (phydev->duplex) { 1121 rxcr |= AVE_RXCR_FDUPEN; 1122 1123 if (phydev->pause) 1124 rmt_adv |= LPA_PAUSE_CAP; 1125 if (phydev->asym_pause) 1126 rmt_adv |= LPA_PAUSE_ASYM; 1127 1128 lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising); 1129 cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 1130 if (cap & FLOW_CTRL_TX) 1131 txcr |= AVE_TXCR_FLOCTR; 1132 else 1133 txcr &= ~AVE_TXCR_FLOCTR; 1134 if (cap & FLOW_CTRL_RX) 1135 rxcr |= AVE_RXCR_FLOCTR; 1136 else 1137 rxcr &= ~AVE_RXCR_FLOCTR; 1138 } else { 1139 rxcr &= ~AVE_RXCR_FDUPEN; 1140 rxcr &= ~AVE_RXCR_FLOCTR; 1141 txcr &= ~AVE_TXCR_FLOCTR; 1142 } 1143 1144 if (rxcr_org != rxcr) { 1145 /* disable Rx mac */ 1146 writel(rxcr & ~AVE_RXCR_RXEN, priv->base + AVE_RXCR); 1147 /* change and enable TX/Rx mac */ 1148 writel(txcr, priv->base + AVE_TXCR); 1149 writel(rxcr, priv->base + AVE_RXCR); 1150 } 1151 1152 phy_print_status(phydev); 1153 } 1154 1155 static void ave_macaddr_init(struct net_device *ndev) 1156 { 1157 ave_hw_write_macaddr(ndev, ndev->dev_addr, AVE_RXMAC1R, AVE_RXMAC2R); 1158 1159 /* pfsel unicast entry */ 1160 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_UNICAST, ndev->dev_addr, 6); 1161 } 1162 1163 static int ave_init(struct net_device *ndev) 1164 { 1165 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1166 struct ave_private *priv = netdev_priv(ndev); 1167 struct device *dev = ndev->dev.parent; 1168 struct device_node *np = dev->of_node; 1169 struct device_node *mdio_np; 1170 struct phy_device *phydev; 1171 int nc, nr, ret; 1172 1173 /* enable clk because of hw access until ndo_open */ 1174 for (nc = 0; nc < priv->nclks; nc++) { 1175 ret = clk_prepare_enable(priv->clk[nc]); 1176 if (ret) { 1177 dev_err(dev, "can't enable clock\n"); 1178 goto out_clk_disable; 1179 } 1180 } 1181 1182 for (nr = 0; nr < priv->nrsts; nr++) { 1183 ret = reset_control_deassert(priv->rst[nr]); 1184 if (ret) { 1185 dev_err(dev, "can't deassert reset\n"); 1186 goto out_reset_assert; 1187 } 1188 } 1189 1190 ret = regmap_update_bits(priv->regmap, SG_ETPINMODE, 1191 priv->pinmode_mask, priv->pinmode_val); 1192 if (ret) 1193 goto out_reset_assert; 1194 1195 ave_global_reset(ndev); 1196 1197 mdio_np = of_get_child_by_name(np, "mdio"); 1198 if (!mdio_np) { 1199 dev_err(dev, "mdio node not found\n"); 1200 ret = -EINVAL; 1201 goto out_reset_assert; 1202 } 1203 ret = of_mdiobus_register(priv->mdio, mdio_np); 1204 of_node_put(mdio_np); 1205 if (ret) { 1206 dev_err(dev, "failed to register mdiobus\n"); 1207 goto out_reset_assert; 1208 } 1209 1210 phydev = of_phy_get_and_connect(ndev, np, ave_phy_adjust_link); 1211 if (!phydev) { 1212 dev_err(dev, "could not attach to PHY\n"); 1213 ret = -ENODEV; 1214 goto out_mdio_unregister; 1215 } 1216 1217 priv->phydev = phydev; 1218 1219 ave_ethtool_get_wol(ndev, &wol); 1220 device_set_wakeup_capable(&ndev->dev, !!wol.supported); 1221 1222 /* set wol initial state disabled */ 1223 wol.wolopts = 0; 1224 __ave_ethtool_set_wol(ndev, &wol); 1225 1226 if (!phy_interface_is_rgmii(phydev)) 1227 phy_set_max_speed(phydev, SPEED_100); 1228 1229 phy_support_asym_pause(phydev); 1230 1231 phydev->mac_managed_pm = true; 1232 1233 phy_attached_info(phydev); 1234 1235 return 0; 1236 1237 out_mdio_unregister: 1238 mdiobus_unregister(priv->mdio); 1239 out_reset_assert: 1240 while (--nr >= 0) 1241 reset_control_assert(priv->rst[nr]); 1242 out_clk_disable: 1243 while (--nc >= 0) 1244 clk_disable_unprepare(priv->clk[nc]); 1245 1246 return ret; 1247 } 1248 1249 static void ave_uninit(struct net_device *ndev) 1250 { 1251 struct ave_private *priv = netdev_priv(ndev); 1252 int i; 1253 1254 phy_disconnect(priv->phydev); 1255 mdiobus_unregister(priv->mdio); 1256 1257 /* disable clk because of hw access after ndo_stop */ 1258 for (i = 0; i < priv->nrsts; i++) 1259 reset_control_assert(priv->rst[i]); 1260 for (i = 0; i < priv->nclks; i++) 1261 clk_disable_unprepare(priv->clk[i]); 1262 } 1263 1264 static int ave_open(struct net_device *ndev) 1265 { 1266 struct ave_private *priv = netdev_priv(ndev); 1267 int entry; 1268 int ret; 1269 u32 val; 1270 1271 ret = request_irq(priv->irq, ave_irq_handler, IRQF_SHARED, ndev->name, 1272 ndev); 1273 if (ret) 1274 return ret; 1275 1276 priv->tx.desc = kcalloc(priv->tx.ndesc, sizeof(*priv->tx.desc), 1277 GFP_KERNEL); 1278 if (!priv->tx.desc) { 1279 ret = -ENOMEM; 1280 goto out_free_irq; 1281 } 1282 1283 priv->rx.desc = kcalloc(priv->rx.ndesc, sizeof(*priv->rx.desc), 1284 GFP_KERNEL); 1285 if (!priv->rx.desc) { 1286 kfree(priv->tx.desc); 1287 ret = -ENOMEM; 1288 goto out_free_irq; 1289 } 1290 1291 /* initialize Tx work and descriptor */ 1292 priv->tx.proc_idx = 0; 1293 priv->tx.done_idx = 0; 1294 for (entry = 0; entry < priv->tx.ndesc; entry++) { 1295 ave_desc_write_cmdsts(ndev, AVE_DESCID_TX, entry, 0); 1296 ave_desc_write_addr(ndev, AVE_DESCID_TX, entry, 0); 1297 } 1298 writel(AVE_TXDC_ADDR_START | 1299 (((priv->tx.ndesc * priv->desc_size) << 16) & AVE_TXDC_SIZE), 1300 priv->base + AVE_TXDC); 1301 1302 /* initialize Rx work and descriptor */ 1303 priv->rx.proc_idx = 0; 1304 priv->rx.done_idx = 0; 1305 for (entry = 0; entry < priv->rx.ndesc; entry++) { 1306 if (ave_rxdesc_prepare(ndev, entry)) 1307 break; 1308 } 1309 writel(AVE_RXDC0_ADDR_START | 1310 (((priv->rx.ndesc * priv->desc_size) << 16) & AVE_RXDC0_SIZE), 1311 priv->base + AVE_RXDC0); 1312 1313 ave_desc_switch(ndev, AVE_DESC_START); 1314 1315 ave_pfsel_init(ndev); 1316 ave_macaddr_init(ndev); 1317 1318 /* set Rx configuration */ 1319 /* full duplex, enable pause drop, enalbe flow control */ 1320 val = AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_DRPEN | 1321 AVE_RXCR_FLOCTR | (AVE_MAX_ETHFRAME & AVE_RXCR_MPSIZ_MASK); 1322 writel(val, priv->base + AVE_RXCR); 1323 1324 /* set Tx configuration */ 1325 /* enable flow control, disable loopback */ 1326 writel(AVE_TXCR_FLOCTR, priv->base + AVE_TXCR); 1327 1328 /* enable timer, clear EN,INTM, and mask interval unit(BSCK) */ 1329 val = readl(priv->base + AVE_IIRQC) & AVE_IIRQC_BSCK; 1330 val |= AVE_IIRQC_EN0 | (AVE_INTM_COUNT << 16); 1331 writel(val, priv->base + AVE_IIRQC); 1332 1333 val = AVE_GI_RXIINT | AVE_GI_RXOVF | AVE_GI_TX | AVE_GI_RXDROP; 1334 ave_irq_restore(ndev, val); 1335 1336 napi_enable(&priv->napi_rx); 1337 napi_enable(&priv->napi_tx); 1338 1339 phy_start(ndev->phydev); 1340 phy_start_aneg(ndev->phydev); 1341 netif_start_queue(ndev); 1342 1343 return 0; 1344 1345 out_free_irq: 1346 disable_irq(priv->irq); 1347 free_irq(priv->irq, ndev); 1348 1349 return ret; 1350 } 1351 1352 static int ave_stop(struct net_device *ndev) 1353 { 1354 struct ave_private *priv = netdev_priv(ndev); 1355 int entry; 1356 1357 ave_irq_disable_all(ndev); 1358 disable_irq(priv->irq); 1359 free_irq(priv->irq, ndev); 1360 1361 netif_tx_disable(ndev); 1362 phy_stop(ndev->phydev); 1363 napi_disable(&priv->napi_tx); 1364 napi_disable(&priv->napi_rx); 1365 1366 ave_desc_switch(ndev, AVE_DESC_STOP); 1367 1368 /* free Tx buffer */ 1369 for (entry = 0; entry < priv->tx.ndesc; entry++) { 1370 if (!priv->tx.desc[entry].skbs) 1371 continue; 1372 1373 ave_dma_unmap(ndev, &priv->tx.desc[entry], DMA_TO_DEVICE); 1374 dev_kfree_skb_any(priv->tx.desc[entry].skbs); 1375 priv->tx.desc[entry].skbs = NULL; 1376 } 1377 priv->tx.proc_idx = 0; 1378 priv->tx.done_idx = 0; 1379 1380 /* free Rx buffer */ 1381 for (entry = 0; entry < priv->rx.ndesc; entry++) { 1382 if (!priv->rx.desc[entry].skbs) 1383 continue; 1384 1385 ave_dma_unmap(ndev, &priv->rx.desc[entry], DMA_FROM_DEVICE); 1386 dev_kfree_skb_any(priv->rx.desc[entry].skbs); 1387 priv->rx.desc[entry].skbs = NULL; 1388 } 1389 priv->rx.proc_idx = 0; 1390 priv->rx.done_idx = 0; 1391 1392 kfree(priv->tx.desc); 1393 kfree(priv->rx.desc); 1394 1395 return 0; 1396 } 1397 1398 static netdev_tx_t ave_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1399 { 1400 struct ave_private *priv = netdev_priv(ndev); 1401 u32 proc_idx, done_idx, ndesc, cmdsts; 1402 int ret, freepkt; 1403 dma_addr_t paddr; 1404 1405 proc_idx = priv->tx.proc_idx; 1406 done_idx = priv->tx.done_idx; 1407 ndesc = priv->tx.ndesc; 1408 freepkt = ((done_idx + ndesc - 1) - proc_idx) % ndesc; 1409 1410 /* stop queue when not enough entry */ 1411 if (unlikely(freepkt < 1)) { 1412 netif_stop_queue(ndev); 1413 return NETDEV_TX_BUSY; 1414 } 1415 1416 /* add padding for short packet */ 1417 if (skb_put_padto(skb, ETH_ZLEN)) { 1418 priv->stats_tx.dropped++; 1419 return NETDEV_TX_OK; 1420 } 1421 1422 /* map Tx buffer 1423 * Tx buffer set to the Tx descriptor doesn't have any restriction. 1424 */ 1425 ret = ave_dma_map(ndev, &priv->tx.desc[proc_idx], 1426 skb->data, skb->len, DMA_TO_DEVICE, &paddr); 1427 if (ret) { 1428 dev_kfree_skb_any(skb); 1429 priv->stats_tx.dropped++; 1430 return NETDEV_TX_OK; 1431 } 1432 1433 priv->tx.desc[proc_idx].skbs = skb; 1434 1435 ave_desc_write_addr(ndev, AVE_DESCID_TX, proc_idx, paddr); 1436 1437 cmdsts = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST | 1438 (skb->len & AVE_STS_PKTLEN_TX_MASK); 1439 1440 /* set interrupt per AVE_FORCE_TXINTCNT or when queue is stopped */ 1441 if (!(proc_idx % AVE_FORCE_TXINTCNT) || netif_queue_stopped(ndev)) 1442 cmdsts |= AVE_STS_INTR; 1443 1444 /* disable checksum calculation when skb doesn't calurate checksum */ 1445 if (skb->ip_summed == CHECKSUM_NONE || 1446 skb->ip_summed == CHECKSUM_UNNECESSARY) 1447 cmdsts |= AVE_STS_NOCSUM; 1448 1449 ave_desc_write_cmdsts(ndev, AVE_DESCID_TX, proc_idx, cmdsts); 1450 1451 priv->tx.proc_idx = (proc_idx + 1) % ndesc; 1452 1453 return NETDEV_TX_OK; 1454 } 1455 1456 static int ave_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) 1457 { 1458 return phy_mii_ioctl(ndev->phydev, ifr, cmd); 1459 } 1460 1461 static const u8 v4multi_macadr[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 1462 static const u8 v6multi_macadr[] = { 0x33, 0x00, 0x00, 0x00, 0x00, 0x00 }; 1463 1464 static void ave_set_rx_mode(struct net_device *ndev) 1465 { 1466 struct ave_private *priv = netdev_priv(ndev); 1467 struct netdev_hw_addr *hw_adr; 1468 int count, mc_cnt; 1469 u32 val; 1470 1471 /* MAC addr filter enable for promiscious mode */ 1472 mc_cnt = netdev_mc_count(ndev); 1473 val = readl(priv->base + AVE_RXCR); 1474 if (ndev->flags & IFF_PROMISC || !mc_cnt) 1475 val &= ~AVE_RXCR_AFEN; 1476 else 1477 val |= AVE_RXCR_AFEN; 1478 writel(val, priv->base + AVE_RXCR); 1479 1480 /* set all multicast address */ 1481 if ((ndev->flags & IFF_ALLMULTI) || mc_cnt > AVE_PF_MULTICAST_SIZE) { 1482 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_MULTICAST, 1483 v4multi_macadr, 1); 1484 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_MULTICAST + 1, 1485 v6multi_macadr, 1); 1486 } else { 1487 /* stop all multicast filter */ 1488 for (count = 0; count < AVE_PF_MULTICAST_SIZE; count++) 1489 ave_pfsel_stop(ndev, AVE_PFNUM_MULTICAST + count); 1490 1491 /* set multicast addresses */ 1492 count = 0; 1493 netdev_for_each_mc_addr(hw_adr, ndev) { 1494 if (count == mc_cnt) 1495 break; 1496 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_MULTICAST + count, 1497 hw_adr->addr, 6); 1498 count++; 1499 } 1500 } 1501 } 1502 1503 static void ave_get_stats64(struct net_device *ndev, 1504 struct rtnl_link_stats64 *stats) 1505 { 1506 struct ave_private *priv = netdev_priv(ndev); 1507 unsigned int start; 1508 1509 do { 1510 start = u64_stats_fetch_begin(&priv->stats_rx.syncp); 1511 stats->rx_packets = priv->stats_rx.packets; 1512 stats->rx_bytes = priv->stats_rx.bytes; 1513 } while (u64_stats_fetch_retry(&priv->stats_rx.syncp, start)); 1514 1515 do { 1516 start = u64_stats_fetch_begin(&priv->stats_tx.syncp); 1517 stats->tx_packets = priv->stats_tx.packets; 1518 stats->tx_bytes = priv->stats_tx.bytes; 1519 } while (u64_stats_fetch_retry(&priv->stats_tx.syncp, start)); 1520 1521 stats->rx_errors = priv->stats_rx.errors; 1522 stats->tx_errors = priv->stats_tx.errors; 1523 stats->rx_dropped = priv->stats_rx.dropped; 1524 stats->tx_dropped = priv->stats_tx.dropped; 1525 stats->rx_fifo_errors = priv->stats_rx.fifo_errors; 1526 stats->collisions = priv->stats_tx.collisions; 1527 } 1528 1529 static int ave_set_mac_address(struct net_device *ndev, void *p) 1530 { 1531 int ret = eth_mac_addr(ndev, p); 1532 1533 if (ret) 1534 return ret; 1535 1536 ave_macaddr_init(ndev); 1537 1538 return 0; 1539 } 1540 1541 static const struct net_device_ops ave_netdev_ops = { 1542 .ndo_init = ave_init, 1543 .ndo_uninit = ave_uninit, 1544 .ndo_open = ave_open, 1545 .ndo_stop = ave_stop, 1546 .ndo_start_xmit = ave_start_xmit, 1547 .ndo_eth_ioctl = ave_ioctl, 1548 .ndo_set_rx_mode = ave_set_rx_mode, 1549 .ndo_get_stats64 = ave_get_stats64, 1550 .ndo_set_mac_address = ave_set_mac_address, 1551 }; 1552 1553 static int ave_probe(struct platform_device *pdev) 1554 { 1555 const struct ave_soc_data *data; 1556 struct device *dev = &pdev->dev; 1557 char buf[ETHTOOL_FWVERS_LEN]; 1558 struct of_phandle_args args; 1559 phy_interface_t phy_mode; 1560 struct ave_private *priv; 1561 struct net_device *ndev; 1562 struct device_node *np; 1563 void __iomem *base; 1564 const char *name; 1565 int i, irq, ret; 1566 u64 dma_mask; 1567 u32 ave_id; 1568 1569 data = of_device_get_match_data(dev); 1570 if (WARN_ON(!data)) 1571 return -EINVAL; 1572 1573 np = dev->of_node; 1574 ret = of_get_phy_mode(np, &phy_mode); 1575 if (ret) { 1576 dev_err(dev, "phy-mode not found\n"); 1577 return ret; 1578 } 1579 1580 irq = platform_get_irq(pdev, 0); 1581 if (irq < 0) 1582 return irq; 1583 1584 base = devm_platform_ioremap_resource(pdev, 0); 1585 if (IS_ERR(base)) 1586 return PTR_ERR(base); 1587 1588 ndev = devm_alloc_etherdev(dev, sizeof(struct ave_private)); 1589 if (!ndev) { 1590 dev_err(dev, "can't allocate ethernet device\n"); 1591 return -ENOMEM; 1592 } 1593 1594 ndev->netdev_ops = &ave_netdev_ops; 1595 ndev->ethtool_ops = &ave_ethtool_ops; 1596 SET_NETDEV_DEV(ndev, dev); 1597 1598 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_RXCSUM); 1599 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_RXCSUM); 1600 1601 ndev->max_mtu = AVE_MAX_ETHFRAME - (ETH_HLEN + ETH_FCS_LEN); 1602 1603 ret = of_get_ethdev_address(np, ndev); 1604 if (ret) { 1605 /* if the mac address is invalid, use random mac address */ 1606 eth_hw_addr_random(ndev); 1607 dev_warn(dev, "Using random MAC address: %pM\n", 1608 ndev->dev_addr); 1609 } 1610 1611 priv = netdev_priv(ndev); 1612 priv->base = base; 1613 priv->irq = irq; 1614 priv->ndev = ndev; 1615 priv->msg_enable = netif_msg_init(-1, AVE_DEFAULT_MSG_ENABLE); 1616 priv->phy_mode = phy_mode; 1617 priv->data = data; 1618 1619 if (IS_DESC_64BIT(priv)) { 1620 priv->desc_size = AVE_DESC_SIZE_64; 1621 priv->tx.daddr = AVE_TXDM_64; 1622 priv->rx.daddr = AVE_RXDM_64; 1623 dma_mask = DMA_BIT_MASK(64); 1624 } else { 1625 priv->desc_size = AVE_DESC_SIZE_32; 1626 priv->tx.daddr = AVE_TXDM_32; 1627 priv->rx.daddr = AVE_RXDM_32; 1628 dma_mask = DMA_BIT_MASK(32); 1629 } 1630 ret = dma_set_mask(dev, dma_mask); 1631 if (ret) 1632 return ret; 1633 1634 priv->tx.ndesc = AVE_NR_TXDESC; 1635 priv->rx.ndesc = AVE_NR_RXDESC; 1636 1637 u64_stats_init(&priv->stats_tx.syncp); 1638 u64_stats_init(&priv->stats_rx.syncp); 1639 1640 for (i = 0; i < AVE_MAX_CLKS; i++) { 1641 name = priv->data->clock_names[i]; 1642 if (!name) 1643 break; 1644 priv->clk[i] = devm_clk_get(dev, name); 1645 if (IS_ERR(priv->clk[i])) 1646 return PTR_ERR(priv->clk[i]); 1647 priv->nclks++; 1648 } 1649 1650 for (i = 0; i < AVE_MAX_RSTS; i++) { 1651 name = priv->data->reset_names[i]; 1652 if (!name) 1653 break; 1654 priv->rst[i] = devm_reset_control_get_shared(dev, name); 1655 if (IS_ERR(priv->rst[i])) 1656 return PTR_ERR(priv->rst[i]); 1657 priv->nrsts++; 1658 } 1659 1660 ret = of_parse_phandle_with_fixed_args(np, 1661 "socionext,syscon-phy-mode", 1662 1, 0, &args); 1663 if (ret) { 1664 dev_err(dev, "can't get syscon-phy-mode property\n"); 1665 return ret; 1666 } 1667 priv->regmap = syscon_node_to_regmap(args.np); 1668 of_node_put(args.np); 1669 if (IS_ERR(priv->regmap)) { 1670 dev_err(dev, "can't map syscon-phy-mode\n"); 1671 return PTR_ERR(priv->regmap); 1672 } 1673 ret = priv->data->get_pinmode(priv, phy_mode, args.args[0]); 1674 if (ret) { 1675 dev_err(dev, "invalid phy-mode setting\n"); 1676 return ret; 1677 } 1678 1679 priv->mdio = devm_mdiobus_alloc(dev); 1680 if (!priv->mdio) 1681 return -ENOMEM; 1682 priv->mdio->priv = ndev; 1683 priv->mdio->parent = dev; 1684 priv->mdio->read = ave_mdiobus_read; 1685 priv->mdio->write = ave_mdiobus_write; 1686 priv->mdio->name = "uniphier-mdio"; 1687 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%x", 1688 pdev->name, pdev->id); 1689 1690 /* Register as a NAPI supported driver */ 1691 netif_napi_add(ndev, &priv->napi_rx, ave_napi_poll_rx); 1692 netif_napi_add_tx(ndev, &priv->napi_tx, ave_napi_poll_tx); 1693 1694 platform_set_drvdata(pdev, ndev); 1695 1696 ret = register_netdev(ndev); 1697 if (ret) { 1698 dev_err(dev, "failed to register netdevice\n"); 1699 goto out_del_napi; 1700 } 1701 1702 /* get ID and version */ 1703 ave_id = readl(priv->base + AVE_IDR); 1704 ave_hw_read_version(ndev, buf, sizeof(buf)); 1705 1706 dev_info(dev, "Socionext %c%c%c%c Ethernet IP %s (irq=%d, phy=%s)\n", 1707 (ave_id >> 24) & 0xff, (ave_id >> 16) & 0xff, 1708 (ave_id >> 8) & 0xff, (ave_id >> 0) & 0xff, 1709 buf, priv->irq, phy_modes(phy_mode)); 1710 1711 return 0; 1712 1713 out_del_napi: 1714 netif_napi_del(&priv->napi_rx); 1715 netif_napi_del(&priv->napi_tx); 1716 1717 return ret; 1718 } 1719 1720 static void ave_remove(struct platform_device *pdev) 1721 { 1722 struct net_device *ndev = platform_get_drvdata(pdev); 1723 struct ave_private *priv = netdev_priv(ndev); 1724 1725 unregister_netdev(ndev); 1726 netif_napi_del(&priv->napi_rx); 1727 netif_napi_del(&priv->napi_tx); 1728 } 1729 1730 #ifdef CONFIG_PM_SLEEP 1731 static int ave_suspend(struct device *dev) 1732 { 1733 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1734 struct net_device *ndev = dev_get_drvdata(dev); 1735 struct ave_private *priv = netdev_priv(ndev); 1736 int ret = 0; 1737 1738 if (netif_running(ndev)) { 1739 ret = ave_stop(ndev); 1740 netif_device_detach(ndev); 1741 } 1742 1743 ave_ethtool_get_wol(ndev, &wol); 1744 priv->wolopts = wol.wolopts; 1745 1746 return ret; 1747 } 1748 1749 static int ave_resume(struct device *dev) 1750 { 1751 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1752 struct net_device *ndev = dev_get_drvdata(dev); 1753 struct ave_private *priv = netdev_priv(ndev); 1754 int ret = 0; 1755 1756 ave_global_reset(ndev); 1757 1758 ret = phy_init_hw(ndev->phydev); 1759 if (ret) 1760 return ret; 1761 1762 ave_ethtool_get_wol(ndev, &wol); 1763 wol.wolopts = priv->wolopts; 1764 __ave_ethtool_set_wol(ndev, &wol); 1765 1766 if (netif_running(ndev)) { 1767 ret = ave_open(ndev); 1768 netif_device_attach(ndev); 1769 } 1770 1771 return ret; 1772 } 1773 1774 static SIMPLE_DEV_PM_OPS(ave_pm_ops, ave_suspend, ave_resume); 1775 #define AVE_PM_OPS (&ave_pm_ops) 1776 #else 1777 #define AVE_PM_OPS NULL 1778 #endif 1779 1780 static int ave_pro4_get_pinmode(struct ave_private *priv, 1781 phy_interface_t phy_mode, u32 arg) 1782 { 1783 if (arg > 0) 1784 return -EINVAL; 1785 1786 priv->pinmode_mask = SG_ETPINMODE_RMII(0); 1787 1788 switch (phy_mode) { 1789 case PHY_INTERFACE_MODE_RMII: 1790 priv->pinmode_val = SG_ETPINMODE_RMII(0); 1791 break; 1792 case PHY_INTERFACE_MODE_MII: 1793 case PHY_INTERFACE_MODE_RGMII: 1794 case PHY_INTERFACE_MODE_RGMII_ID: 1795 case PHY_INTERFACE_MODE_RGMII_RXID: 1796 case PHY_INTERFACE_MODE_RGMII_TXID: 1797 priv->pinmode_val = 0; 1798 break; 1799 default: 1800 return -EINVAL; 1801 } 1802 1803 return 0; 1804 } 1805 1806 static int ave_ld11_get_pinmode(struct ave_private *priv, 1807 phy_interface_t phy_mode, u32 arg) 1808 { 1809 if (arg > 0) 1810 return -EINVAL; 1811 1812 priv->pinmode_mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); 1813 1814 switch (phy_mode) { 1815 case PHY_INTERFACE_MODE_INTERNAL: 1816 priv->pinmode_val = 0; 1817 break; 1818 case PHY_INTERFACE_MODE_RMII: 1819 priv->pinmode_val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); 1820 break; 1821 default: 1822 return -EINVAL; 1823 } 1824 1825 return 0; 1826 } 1827 1828 static int ave_ld20_get_pinmode(struct ave_private *priv, 1829 phy_interface_t phy_mode, u32 arg) 1830 { 1831 if (arg > 0) 1832 return -EINVAL; 1833 1834 priv->pinmode_mask = SG_ETPINMODE_RMII(0); 1835 1836 switch (phy_mode) { 1837 case PHY_INTERFACE_MODE_RMII: 1838 priv->pinmode_val = SG_ETPINMODE_RMII(0); 1839 break; 1840 case PHY_INTERFACE_MODE_RGMII: 1841 case PHY_INTERFACE_MODE_RGMII_ID: 1842 case PHY_INTERFACE_MODE_RGMII_RXID: 1843 case PHY_INTERFACE_MODE_RGMII_TXID: 1844 priv->pinmode_val = 0; 1845 break; 1846 default: 1847 return -EINVAL; 1848 } 1849 1850 return 0; 1851 } 1852 1853 static int ave_pxs3_get_pinmode(struct ave_private *priv, 1854 phy_interface_t phy_mode, u32 arg) 1855 { 1856 if (arg > 1) 1857 return -EINVAL; 1858 1859 priv->pinmode_mask = SG_ETPINMODE_RMII(arg); 1860 1861 switch (phy_mode) { 1862 case PHY_INTERFACE_MODE_RMII: 1863 priv->pinmode_val = SG_ETPINMODE_RMII(arg); 1864 break; 1865 case PHY_INTERFACE_MODE_RGMII: 1866 case PHY_INTERFACE_MODE_RGMII_ID: 1867 case PHY_INTERFACE_MODE_RGMII_RXID: 1868 case PHY_INTERFACE_MODE_RGMII_TXID: 1869 priv->pinmode_val = 0; 1870 break; 1871 default: 1872 return -EINVAL; 1873 } 1874 1875 return 0; 1876 } 1877 1878 static const struct ave_soc_data ave_pro4_data = { 1879 .is_desc_64bit = false, 1880 .clock_names = { 1881 "gio", "ether", "ether-gb", "ether-phy", 1882 }, 1883 .reset_names = { 1884 "gio", "ether", 1885 }, 1886 .get_pinmode = ave_pro4_get_pinmode, 1887 }; 1888 1889 static const struct ave_soc_data ave_pxs2_data = { 1890 .is_desc_64bit = false, 1891 .clock_names = { 1892 "ether", 1893 }, 1894 .reset_names = { 1895 "ether", 1896 }, 1897 .get_pinmode = ave_pro4_get_pinmode, 1898 }; 1899 1900 static const struct ave_soc_data ave_ld11_data = { 1901 .is_desc_64bit = false, 1902 .clock_names = { 1903 "ether", 1904 }, 1905 .reset_names = { 1906 "ether", 1907 }, 1908 .get_pinmode = ave_ld11_get_pinmode, 1909 }; 1910 1911 static const struct ave_soc_data ave_ld20_data = { 1912 .is_desc_64bit = true, 1913 .clock_names = { 1914 "ether", 1915 }, 1916 .reset_names = { 1917 "ether", 1918 }, 1919 .get_pinmode = ave_ld20_get_pinmode, 1920 }; 1921 1922 static const struct ave_soc_data ave_pxs3_data = { 1923 .is_desc_64bit = false, 1924 .clock_names = { 1925 "ether", 1926 }, 1927 .reset_names = { 1928 "ether", 1929 }, 1930 .get_pinmode = ave_pxs3_get_pinmode, 1931 }; 1932 1933 static const struct ave_soc_data ave_nx1_data = { 1934 .is_desc_64bit = true, 1935 .clock_names = { 1936 "ether", 1937 }, 1938 .reset_names = { 1939 "ether", 1940 }, 1941 .get_pinmode = ave_pxs3_get_pinmode, 1942 }; 1943 1944 static const struct of_device_id of_ave_match[] = { 1945 { 1946 .compatible = "socionext,uniphier-pro4-ave4", 1947 .data = &ave_pro4_data, 1948 }, 1949 { 1950 .compatible = "socionext,uniphier-pxs2-ave4", 1951 .data = &ave_pxs2_data, 1952 }, 1953 { 1954 .compatible = "socionext,uniphier-ld11-ave4", 1955 .data = &ave_ld11_data, 1956 }, 1957 { 1958 .compatible = "socionext,uniphier-ld20-ave4", 1959 .data = &ave_ld20_data, 1960 }, 1961 { 1962 .compatible = "socionext,uniphier-pxs3-ave4", 1963 .data = &ave_pxs3_data, 1964 }, 1965 { 1966 .compatible = "socionext,uniphier-nx1-ave4", 1967 .data = &ave_nx1_data, 1968 }, 1969 { /* Sentinel */ } 1970 }; 1971 MODULE_DEVICE_TABLE(of, of_ave_match); 1972 1973 static struct platform_driver ave_driver = { 1974 .probe = ave_probe, 1975 .remove = ave_remove, 1976 .driver = { 1977 .name = "ave", 1978 .pm = AVE_PM_OPS, 1979 .of_match_table = of_ave_match, 1980 }, 1981 }; 1982 module_platform_driver(ave_driver); 1983 1984 MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>"); 1985 MODULE_DESCRIPTION("Socionext UniPhier AVE ethernet driver"); 1986 MODULE_LICENSE("GPL v2"); 1987