1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * sni_ave.c - Socionext UniPhier AVE ethernet driver 4 * Copyright 2014 Panasonic Corporation 5 * Copyright 2015-2017 Socionext Inc. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/etherdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/mii.h> 16 #include <linux/module.h> 17 #include <linux/netdevice.h> 18 #include <linux/of_net.h> 19 #include <linux/of_mdio.h> 20 #include <linux/of_platform.h> 21 #include <linux/phy.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 #include <linux/types.h> 25 #include <linux/u64_stats_sync.h> 26 27 /* General Register Group */ 28 #define AVE_IDR 0x000 /* ID */ 29 #define AVE_VR 0x004 /* Version */ 30 #define AVE_GRR 0x008 /* Global Reset */ 31 #define AVE_CFGR 0x00c /* Configuration */ 32 33 /* Interrupt Register Group */ 34 #define AVE_GIMR 0x100 /* Global Interrupt Mask */ 35 #define AVE_GISR 0x104 /* Global Interrupt Status */ 36 37 /* MAC Register Group */ 38 #define AVE_TXCR 0x200 /* TX Setup */ 39 #define AVE_RXCR 0x204 /* RX Setup */ 40 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */ 41 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */ 42 #define AVE_MDIOCTR 0x214 /* MDIO Control */ 43 #define AVE_MDIOAR 0x218 /* MDIO Address */ 44 #define AVE_MDIOWDR 0x21c /* MDIO Data */ 45 #define AVE_MDIOSR 0x220 /* MDIO Status */ 46 #define AVE_MDIORDR 0x224 /* MDIO Rd Data */ 47 48 /* Descriptor Control Register Group */ 49 #define AVE_DESCC 0x300 /* Descriptor Control */ 50 #define AVE_TXDC 0x304 /* TX Descriptor Configuration */ 51 #define AVE_RXDC0 0x308 /* RX Descriptor Ring0 Configuration */ 52 #define AVE_IIRQC 0x34c /* Interval IRQ Control */ 53 54 /* Packet Filter Register Group */ 55 #define AVE_PKTF_BASE 0x800 /* PF Base Address */ 56 #define AVE_PFMBYTE_BASE 0xd00 /* PF Mask Byte Base Address */ 57 #define AVE_PFMBIT_BASE 0xe00 /* PF Mask Bit Base Address */ 58 #define AVE_PFSEL_BASE 0xf00 /* PF Selector Base Address */ 59 #define AVE_PFEN 0xffc /* Packet Filter Enable */ 60 #define AVE_PKTF(ent) (AVE_PKTF_BASE + (ent) * 0x40) 61 #define AVE_PFMBYTE(ent) (AVE_PFMBYTE_BASE + (ent) * 8) 62 #define AVE_PFMBIT(ent) (AVE_PFMBIT_BASE + (ent) * 4) 63 #define AVE_PFSEL(ent) (AVE_PFSEL_BASE + (ent) * 4) 64 65 /* 64bit descriptor memory */ 66 #define AVE_DESC_SIZE_64 12 /* Descriptor Size */ 67 68 #define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */ 69 #define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */ 70 71 #define AVE_TXDM_SIZE_64 0x0ba0 /* Tx Descriptor Memory Size 3KB */ 72 #define AVE_RXDM_SIZE_64 0x6000 /* Rx Descriptor Memory Size 24KB */ 73 74 /* 32bit descriptor memory */ 75 #define AVE_DESC_SIZE_32 8 /* Descriptor Size */ 76 77 #define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */ 78 #define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */ 79 80 #define AVE_TXDM_SIZE_32 0x07c0 /* Tx Descriptor Memory Size 2KB */ 81 #define AVE_RXDM_SIZE_32 0x4000 /* Rx Descriptor Memory Size 16KB */ 82 83 /* RMII Bridge Register Group */ 84 #define AVE_RSTCTRL 0x8028 /* Reset control */ 85 #define AVE_RSTCTRL_RMIIRST BIT(16) 86 #define AVE_LINKSEL 0x8034 /* Link speed setting */ 87 #define AVE_LINKSEL_100M BIT(0) 88 89 /* AVE_GRR */ 90 #define AVE_GRR_RXFFR BIT(5) /* Reset RxFIFO */ 91 #define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */ 92 #define AVE_GRR_GRST BIT(0) /* Reset all MAC */ 93 94 /* AVE_CFGR */ 95 #define AVE_CFGR_FLE BIT(31) /* Filter Function */ 96 #define AVE_CFGR_CHE BIT(30) /* Checksum Function */ 97 #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */ 98 #define AVE_CFGR_IPFCEN BIT(24) /* IP fragment sum Enable */ 99 100 /* AVE_GISR (common with GIMR) */ 101 #define AVE_GI_PHY BIT(24) /* PHY interrupt */ 102 #define AVE_GI_TX BIT(16) /* Tx complete */ 103 #define AVE_GI_RXERR BIT(8) /* Receive frame more than max size */ 104 #define AVE_GI_RXOVF BIT(7) /* Overflow at the RxFIFO */ 105 #define AVE_GI_RXDROP BIT(6) /* Drop packet */ 106 #define AVE_GI_RXIINT BIT(5) /* Interval interrupt */ 107 108 /* AVE_TXCR */ 109 #define AVE_TXCR_FLOCTR BIT(18) /* Flow control */ 110 #define AVE_TXCR_TXSPD_1G BIT(17) 111 #define AVE_TXCR_TXSPD_100 BIT(16) 112 113 /* AVE_RXCR */ 114 #define AVE_RXCR_RXEN BIT(30) /* Rx enable */ 115 #define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */ 116 #define AVE_RXCR_FLOCTR BIT(21) /* Flow control */ 117 #define AVE_RXCR_AFEN BIT(19) /* MAC address filter */ 118 #define AVE_RXCR_DRPEN BIT(18) /* Drop pause frame */ 119 #define AVE_RXCR_MPSIZ_MASK GENMASK(10, 0) 120 121 /* AVE_MDIOCTR */ 122 #define AVE_MDIOCTR_RREQ BIT(3) /* Read request */ 123 #define AVE_MDIOCTR_WREQ BIT(2) /* Write request */ 124 125 /* AVE_MDIOSR */ 126 #define AVE_MDIOSR_STS BIT(0) /* access status */ 127 128 /* AVE_DESCC */ 129 #define AVE_DESCC_STATUS_MASK GENMASK(31, 16) 130 #define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */ 131 #define AVE_DESCC_RDSTP BIT(4) /* Pause Rx descriptor */ 132 #define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */ 133 134 /* AVE_TXDC */ 135 #define AVE_TXDC_SIZE GENMASK(27, 16) /* Size of Tx descriptor */ 136 #define AVE_TXDC_ADDR GENMASK(11, 0) /* Start address */ 137 #define AVE_TXDC_ADDR_START 0 138 139 /* AVE_RXDC0 */ 140 #define AVE_RXDC0_SIZE GENMASK(30, 16) /* Size of Rx descriptor */ 141 #define AVE_RXDC0_ADDR GENMASK(14, 0) /* Start address */ 142 #define AVE_RXDC0_ADDR_START 0 143 144 /* AVE_IIRQC */ 145 #define AVE_IIRQC_EN0 BIT(27) /* Enable interval interrupt Ring0 */ 146 #define AVE_IIRQC_BSCK GENMASK(15, 0) /* Interval count unit */ 147 148 /* Command status for descriptor */ 149 #define AVE_STS_OWN BIT(31) /* Descriptor ownership */ 150 #define AVE_STS_INTR BIT(29) /* Request for interrupt */ 151 #define AVE_STS_OK BIT(27) /* Normal transmit */ 152 /* TX */ 153 #define AVE_STS_NOCSUM BIT(28) /* No use HW checksum */ 154 #define AVE_STS_1ST BIT(26) /* Head of buffer chain */ 155 #define AVE_STS_LAST BIT(25) /* Tail of buffer chain */ 156 #define AVE_STS_OWC BIT(21) /* Out of window,Late Collision */ 157 #define AVE_STS_EC BIT(20) /* Excess collision occurred */ 158 #define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0) 159 /* RX */ 160 #define AVE_STS_CSSV BIT(21) /* Checksum check performed */ 161 #define AVE_STS_CSER BIT(20) /* Checksum error detected */ 162 #define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0) 163 164 /* Packet filter */ 165 #define AVE_PFMBYTE_MASK0 (GENMASK(31, 8) | GENMASK(5, 0)) 166 #define AVE_PFMBYTE_MASK1 GENMASK(25, 0) 167 #define AVE_PFMBIT_MASK GENMASK(15, 0) 168 169 #define AVE_PF_SIZE 17 /* Number of all packet filter */ 170 #define AVE_PF_MULTICAST_SIZE 7 /* Number of multicast filter */ 171 172 #define AVE_PFNUM_FILTER 0 /* No.0 */ 173 #define AVE_PFNUM_UNICAST 1 /* No.1 */ 174 #define AVE_PFNUM_BROADCAST 2 /* No.2 */ 175 #define AVE_PFNUM_MULTICAST 11 /* No.11-17 */ 176 177 /* NETIF Message control */ 178 #define AVE_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 179 NETIF_MSG_PROBE | \ 180 NETIF_MSG_LINK | \ 181 NETIF_MSG_TIMER | \ 182 NETIF_MSG_IFDOWN | \ 183 NETIF_MSG_IFUP | \ 184 NETIF_MSG_RX_ERR | \ 185 NETIF_MSG_TX_ERR) 186 187 /* Parameter for descriptor */ 188 #define AVE_NR_TXDESC 64 /* Tx descriptor */ 189 #define AVE_NR_RXDESC 256 /* Rx descriptor */ 190 191 #define AVE_DESC_OFS_CMDSTS 0 192 #define AVE_DESC_OFS_ADDRL 4 193 #define AVE_DESC_OFS_ADDRU 8 194 195 /* Parameter for ethernet frame */ 196 #define AVE_MAX_ETHFRAME 1518 197 #define AVE_FRAME_HEADROOM 2 198 199 /* Parameter for interrupt */ 200 #define AVE_INTM_COUNT 20 201 #define AVE_FORCE_TXINTCNT 1 202 203 /* SG */ 204 #define SG_ETPINMODE 0x540 205 #define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */ 206 #define SG_ETPINMODE_RMII(ins) BIT(ins) 207 208 #define IS_DESC_64BIT(p) ((p)->data->is_desc_64bit) 209 210 #define AVE_MAX_CLKS 4 211 #define AVE_MAX_RSTS 2 212 213 enum desc_id { 214 AVE_DESCID_RX, 215 AVE_DESCID_TX, 216 }; 217 218 enum desc_state { 219 AVE_DESC_RX_PERMIT, 220 AVE_DESC_RX_SUSPEND, 221 AVE_DESC_START, 222 AVE_DESC_STOP, 223 }; 224 225 struct ave_desc { 226 struct sk_buff *skbs; 227 dma_addr_t skbs_dma; 228 size_t skbs_dmalen; 229 }; 230 231 struct ave_desc_info { 232 u32 ndesc; /* number of descriptor */ 233 u32 daddr; /* start address of descriptor */ 234 u32 proc_idx; /* index of processing packet */ 235 u32 done_idx; /* index of processed packet */ 236 struct ave_desc *desc; /* skb info related descriptor */ 237 }; 238 239 struct ave_stats { 240 struct u64_stats_sync syncp; 241 u64 packets; 242 u64 bytes; 243 u64 errors; 244 u64 dropped; 245 u64 collisions; 246 u64 fifo_errors; 247 }; 248 249 struct ave_private { 250 void __iomem *base; 251 int irq; 252 int phy_id; 253 unsigned int desc_size; 254 u32 msg_enable; 255 int nclks; 256 struct clk *clk[AVE_MAX_CLKS]; 257 int nrsts; 258 struct reset_control *rst[AVE_MAX_RSTS]; 259 phy_interface_t phy_mode; 260 struct phy_device *phydev; 261 struct mii_bus *mdio; 262 struct regmap *regmap; 263 unsigned int pinmode_mask; 264 unsigned int pinmode_val; 265 u32 wolopts; 266 267 /* stats */ 268 struct ave_stats stats_rx; 269 struct ave_stats stats_tx; 270 271 /* NAPI support */ 272 struct net_device *ndev; 273 struct napi_struct napi_rx; 274 struct napi_struct napi_tx; 275 276 /* descriptor */ 277 struct ave_desc_info rx; 278 struct ave_desc_info tx; 279 280 /* flow control */ 281 int pause_auto; 282 int pause_rx; 283 int pause_tx; 284 285 const struct ave_soc_data *data; 286 }; 287 288 struct ave_soc_data { 289 bool is_desc_64bit; 290 const char *clock_names[AVE_MAX_CLKS]; 291 const char *reset_names[AVE_MAX_RSTS]; 292 int (*get_pinmode)(struct ave_private *priv, 293 phy_interface_t phy_mode, u32 arg); 294 }; 295 296 static u32 ave_desc_read(struct net_device *ndev, enum desc_id id, int entry, 297 int offset) 298 { 299 struct ave_private *priv = netdev_priv(ndev); 300 u32 addr; 301 302 addr = ((id == AVE_DESCID_TX) ? priv->tx.daddr : priv->rx.daddr) 303 + entry * priv->desc_size + offset; 304 305 return readl(priv->base + addr); 306 } 307 308 static u32 ave_desc_read_cmdsts(struct net_device *ndev, enum desc_id id, 309 int entry) 310 { 311 return ave_desc_read(ndev, id, entry, AVE_DESC_OFS_CMDSTS); 312 } 313 314 static void ave_desc_write(struct net_device *ndev, enum desc_id id, 315 int entry, int offset, u32 val) 316 { 317 struct ave_private *priv = netdev_priv(ndev); 318 u32 addr; 319 320 addr = ((id == AVE_DESCID_TX) ? priv->tx.daddr : priv->rx.daddr) 321 + entry * priv->desc_size + offset; 322 323 writel(val, priv->base + addr); 324 } 325 326 static void ave_desc_write_cmdsts(struct net_device *ndev, enum desc_id id, 327 int entry, u32 val) 328 { 329 ave_desc_write(ndev, id, entry, AVE_DESC_OFS_CMDSTS, val); 330 } 331 332 static void ave_desc_write_addr(struct net_device *ndev, enum desc_id id, 333 int entry, dma_addr_t paddr) 334 { 335 struct ave_private *priv = netdev_priv(ndev); 336 337 ave_desc_write(ndev, id, entry, AVE_DESC_OFS_ADDRL, 338 lower_32_bits(paddr)); 339 if (IS_DESC_64BIT(priv)) 340 ave_desc_write(ndev, id, 341 entry, AVE_DESC_OFS_ADDRU, 342 upper_32_bits(paddr)); 343 } 344 345 static u32 ave_irq_disable_all(struct net_device *ndev) 346 { 347 struct ave_private *priv = netdev_priv(ndev); 348 u32 ret; 349 350 ret = readl(priv->base + AVE_GIMR); 351 writel(0, priv->base + AVE_GIMR); 352 353 return ret; 354 } 355 356 static void ave_irq_restore(struct net_device *ndev, u32 val) 357 { 358 struct ave_private *priv = netdev_priv(ndev); 359 360 writel(val, priv->base + AVE_GIMR); 361 } 362 363 static void ave_irq_enable(struct net_device *ndev, u32 bitflag) 364 { 365 struct ave_private *priv = netdev_priv(ndev); 366 367 writel(readl(priv->base + AVE_GIMR) | bitflag, priv->base + AVE_GIMR); 368 writel(bitflag, priv->base + AVE_GISR); 369 } 370 371 static void ave_hw_write_macaddr(struct net_device *ndev, 372 const unsigned char *mac_addr, 373 int reg1, int reg2) 374 { 375 struct ave_private *priv = netdev_priv(ndev); 376 377 writel(mac_addr[0] | mac_addr[1] << 8 | 378 mac_addr[2] << 16 | mac_addr[3] << 24, priv->base + reg1); 379 writel(mac_addr[4] | mac_addr[5] << 8, priv->base + reg2); 380 } 381 382 static void ave_hw_read_version(struct net_device *ndev, char *buf, int len) 383 { 384 struct ave_private *priv = netdev_priv(ndev); 385 u32 major, minor, vr; 386 387 vr = readl(priv->base + AVE_VR); 388 major = (vr & GENMASK(15, 8)) >> 8; 389 minor = (vr & GENMASK(7, 0)); 390 snprintf(buf, len, "v%u.%u", major, minor); 391 } 392 393 static void ave_ethtool_get_drvinfo(struct net_device *ndev, 394 struct ethtool_drvinfo *info) 395 { 396 struct device *dev = ndev->dev.parent; 397 398 strlcpy(info->driver, dev->driver->name, sizeof(info->driver)); 399 strlcpy(info->bus_info, dev_name(dev), sizeof(info->bus_info)); 400 ave_hw_read_version(ndev, info->fw_version, sizeof(info->fw_version)); 401 } 402 403 static u32 ave_ethtool_get_msglevel(struct net_device *ndev) 404 { 405 struct ave_private *priv = netdev_priv(ndev); 406 407 return priv->msg_enable; 408 } 409 410 static void ave_ethtool_set_msglevel(struct net_device *ndev, u32 val) 411 { 412 struct ave_private *priv = netdev_priv(ndev); 413 414 priv->msg_enable = val; 415 } 416 417 static void ave_ethtool_get_wol(struct net_device *ndev, 418 struct ethtool_wolinfo *wol) 419 { 420 wol->supported = 0; 421 wol->wolopts = 0; 422 423 if (ndev->phydev) 424 phy_ethtool_get_wol(ndev->phydev, wol); 425 } 426 427 static int ave_ethtool_set_wol(struct net_device *ndev, 428 struct ethtool_wolinfo *wol) 429 { 430 int ret; 431 432 if (!ndev->phydev || 433 (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))) 434 return -EOPNOTSUPP; 435 436 ret = phy_ethtool_set_wol(ndev->phydev, wol); 437 if (!ret) 438 device_set_wakeup_enable(&ndev->dev, !!wol->wolopts); 439 440 return ret; 441 } 442 443 static void ave_ethtool_get_pauseparam(struct net_device *ndev, 444 struct ethtool_pauseparam *pause) 445 { 446 struct ave_private *priv = netdev_priv(ndev); 447 448 pause->autoneg = priv->pause_auto; 449 pause->rx_pause = priv->pause_rx; 450 pause->tx_pause = priv->pause_tx; 451 } 452 453 static int ave_ethtool_set_pauseparam(struct net_device *ndev, 454 struct ethtool_pauseparam *pause) 455 { 456 struct ave_private *priv = netdev_priv(ndev); 457 struct phy_device *phydev = ndev->phydev; 458 459 if (!phydev) 460 return -EINVAL; 461 462 priv->pause_auto = pause->autoneg; 463 priv->pause_rx = pause->rx_pause; 464 priv->pause_tx = pause->tx_pause; 465 466 phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause); 467 468 return 0; 469 } 470 471 static const struct ethtool_ops ave_ethtool_ops = { 472 .get_link_ksettings = phy_ethtool_get_link_ksettings, 473 .set_link_ksettings = phy_ethtool_set_link_ksettings, 474 .get_drvinfo = ave_ethtool_get_drvinfo, 475 .nway_reset = phy_ethtool_nway_reset, 476 .get_link = ethtool_op_get_link, 477 .get_msglevel = ave_ethtool_get_msglevel, 478 .set_msglevel = ave_ethtool_set_msglevel, 479 .get_wol = ave_ethtool_get_wol, 480 .set_wol = ave_ethtool_set_wol, 481 .get_pauseparam = ave_ethtool_get_pauseparam, 482 .set_pauseparam = ave_ethtool_set_pauseparam, 483 }; 484 485 static int ave_mdiobus_read(struct mii_bus *bus, int phyid, int regnum) 486 { 487 struct net_device *ndev = bus->priv; 488 struct ave_private *priv; 489 u32 mdioctl, mdiosr; 490 int ret; 491 492 priv = netdev_priv(ndev); 493 494 /* write address */ 495 writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR); 496 497 /* read request */ 498 mdioctl = readl(priv->base + AVE_MDIOCTR); 499 writel((mdioctl | AVE_MDIOCTR_RREQ) & ~AVE_MDIOCTR_WREQ, 500 priv->base + AVE_MDIOCTR); 501 502 ret = readl_poll_timeout(priv->base + AVE_MDIOSR, mdiosr, 503 !(mdiosr & AVE_MDIOSR_STS), 20, 2000); 504 if (ret) { 505 netdev_err(ndev, "failed to read (phy:%d reg:%x)\n", 506 phyid, regnum); 507 return ret; 508 } 509 510 return readl(priv->base + AVE_MDIORDR) & GENMASK(15, 0); 511 } 512 513 static int ave_mdiobus_write(struct mii_bus *bus, int phyid, int regnum, 514 u16 val) 515 { 516 struct net_device *ndev = bus->priv; 517 struct ave_private *priv; 518 u32 mdioctl, mdiosr; 519 int ret; 520 521 priv = netdev_priv(ndev); 522 523 /* write address */ 524 writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR); 525 526 /* write data */ 527 writel(val, priv->base + AVE_MDIOWDR); 528 529 /* write request */ 530 mdioctl = readl(priv->base + AVE_MDIOCTR); 531 writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ, 532 priv->base + AVE_MDIOCTR); 533 534 ret = readl_poll_timeout(priv->base + AVE_MDIOSR, mdiosr, 535 !(mdiosr & AVE_MDIOSR_STS), 20, 2000); 536 if (ret) 537 netdev_err(ndev, "failed to write (phy:%d reg:%x)\n", 538 phyid, regnum); 539 540 return ret; 541 } 542 543 static int ave_dma_map(struct net_device *ndev, struct ave_desc *desc, 544 void *ptr, size_t len, enum dma_data_direction dir, 545 dma_addr_t *paddr) 546 { 547 dma_addr_t map_addr; 548 549 map_addr = dma_map_single(ndev->dev.parent, ptr, len, dir); 550 if (unlikely(dma_mapping_error(ndev->dev.parent, map_addr))) 551 return -ENOMEM; 552 553 desc->skbs_dma = map_addr; 554 desc->skbs_dmalen = len; 555 *paddr = map_addr; 556 557 return 0; 558 } 559 560 static void ave_dma_unmap(struct net_device *ndev, struct ave_desc *desc, 561 enum dma_data_direction dir) 562 { 563 if (!desc->skbs_dma) 564 return; 565 566 dma_unmap_single(ndev->dev.parent, 567 desc->skbs_dma, desc->skbs_dmalen, dir); 568 desc->skbs_dma = 0; 569 } 570 571 /* Prepare Rx descriptor and memory */ 572 static int ave_rxdesc_prepare(struct net_device *ndev, int entry) 573 { 574 struct ave_private *priv = netdev_priv(ndev); 575 struct sk_buff *skb; 576 dma_addr_t paddr; 577 int ret; 578 579 skb = priv->rx.desc[entry].skbs; 580 if (!skb) { 581 skb = netdev_alloc_skb(ndev, AVE_MAX_ETHFRAME); 582 if (!skb) { 583 netdev_err(ndev, "can't allocate skb for Rx\n"); 584 return -ENOMEM; 585 } 586 skb->data += AVE_FRAME_HEADROOM; 587 skb->tail += AVE_FRAME_HEADROOM; 588 } 589 590 /* set disable to cmdsts */ 591 ave_desc_write_cmdsts(ndev, AVE_DESCID_RX, entry, 592 AVE_STS_INTR | AVE_STS_OWN); 593 594 /* map Rx buffer 595 * Rx buffer set to the Rx descriptor has two restrictions: 596 * - Rx buffer address is 4 byte aligned. 597 * - Rx buffer begins with 2 byte headroom, and data will be put from 598 * (buffer + 2). 599 * To satisfy this, specify the address to put back the buffer 600 * pointer advanced by AVE_FRAME_HEADROOM, and expand the map size 601 * by AVE_FRAME_HEADROOM. 602 */ 603 ret = ave_dma_map(ndev, &priv->rx.desc[entry], 604 skb->data - AVE_FRAME_HEADROOM, 605 AVE_MAX_ETHFRAME + AVE_FRAME_HEADROOM, 606 DMA_FROM_DEVICE, &paddr); 607 if (ret) { 608 netdev_err(ndev, "can't map skb for Rx\n"); 609 dev_kfree_skb_any(skb); 610 return ret; 611 } 612 priv->rx.desc[entry].skbs = skb; 613 614 /* set buffer pointer */ 615 ave_desc_write_addr(ndev, AVE_DESCID_RX, entry, paddr); 616 617 /* set enable to cmdsts */ 618 ave_desc_write_cmdsts(ndev, AVE_DESCID_RX, entry, 619 AVE_STS_INTR | AVE_MAX_ETHFRAME); 620 621 return ret; 622 } 623 624 /* Switch state of descriptor */ 625 static int ave_desc_switch(struct net_device *ndev, enum desc_state state) 626 { 627 struct ave_private *priv = netdev_priv(ndev); 628 int ret = 0; 629 u32 val; 630 631 switch (state) { 632 case AVE_DESC_START: 633 writel(AVE_DESCC_TD | AVE_DESCC_RD0, priv->base + AVE_DESCC); 634 break; 635 636 case AVE_DESC_STOP: 637 writel(0, priv->base + AVE_DESCC); 638 if (readl_poll_timeout(priv->base + AVE_DESCC, val, !val, 639 150, 15000)) { 640 netdev_err(ndev, "can't stop descriptor\n"); 641 ret = -EBUSY; 642 } 643 break; 644 645 case AVE_DESC_RX_SUSPEND: 646 val = readl(priv->base + AVE_DESCC); 647 val |= AVE_DESCC_RDSTP; 648 val &= ~AVE_DESCC_STATUS_MASK; 649 writel(val, priv->base + AVE_DESCC); 650 if (readl_poll_timeout(priv->base + AVE_DESCC, val, 651 val & (AVE_DESCC_RDSTP << 16), 652 150, 150000)) { 653 netdev_err(ndev, "can't suspend descriptor\n"); 654 ret = -EBUSY; 655 } 656 break; 657 658 case AVE_DESC_RX_PERMIT: 659 val = readl(priv->base + AVE_DESCC); 660 val &= ~AVE_DESCC_RDSTP; 661 val &= ~AVE_DESCC_STATUS_MASK; 662 writel(val, priv->base + AVE_DESCC); 663 break; 664 665 default: 666 ret = -EINVAL; 667 break; 668 } 669 670 return ret; 671 } 672 673 static int ave_tx_complete(struct net_device *ndev) 674 { 675 struct ave_private *priv = netdev_priv(ndev); 676 u32 proc_idx, done_idx, ndesc, cmdsts; 677 unsigned int nr_freebuf = 0; 678 unsigned int tx_packets = 0; 679 unsigned int tx_bytes = 0; 680 681 proc_idx = priv->tx.proc_idx; 682 done_idx = priv->tx.done_idx; 683 ndesc = priv->tx.ndesc; 684 685 /* free pre-stored skb from done_idx to proc_idx */ 686 while (proc_idx != done_idx) { 687 cmdsts = ave_desc_read_cmdsts(ndev, AVE_DESCID_TX, done_idx); 688 689 /* do nothing if owner is HW (==1 for Tx) */ 690 if (cmdsts & AVE_STS_OWN) 691 break; 692 693 /* check Tx status and updates statistics */ 694 if (cmdsts & AVE_STS_OK) { 695 tx_bytes += cmdsts & AVE_STS_PKTLEN_TX_MASK; 696 /* success */ 697 if (cmdsts & AVE_STS_LAST) 698 tx_packets++; 699 } else { 700 /* error */ 701 if (cmdsts & AVE_STS_LAST) { 702 priv->stats_tx.errors++; 703 if (cmdsts & (AVE_STS_OWC | AVE_STS_EC)) 704 priv->stats_tx.collisions++; 705 } 706 } 707 708 /* release skb */ 709 if (priv->tx.desc[done_idx].skbs) { 710 ave_dma_unmap(ndev, &priv->tx.desc[done_idx], 711 DMA_TO_DEVICE); 712 dev_consume_skb_any(priv->tx.desc[done_idx].skbs); 713 priv->tx.desc[done_idx].skbs = NULL; 714 nr_freebuf++; 715 } 716 done_idx = (done_idx + 1) % ndesc; 717 } 718 719 priv->tx.done_idx = done_idx; 720 721 /* update stats */ 722 u64_stats_update_begin(&priv->stats_tx.syncp); 723 priv->stats_tx.packets += tx_packets; 724 priv->stats_tx.bytes += tx_bytes; 725 u64_stats_update_end(&priv->stats_tx.syncp); 726 727 /* wake queue for freeing buffer */ 728 if (unlikely(netif_queue_stopped(ndev)) && nr_freebuf) 729 netif_wake_queue(ndev); 730 731 return nr_freebuf; 732 } 733 734 static int ave_rx_receive(struct net_device *ndev, int num) 735 { 736 struct ave_private *priv = netdev_priv(ndev); 737 unsigned int rx_packets = 0; 738 unsigned int rx_bytes = 0; 739 u32 proc_idx, done_idx; 740 struct sk_buff *skb; 741 unsigned int pktlen; 742 int restpkt, npkts; 743 u32 ndesc, cmdsts; 744 745 proc_idx = priv->rx.proc_idx; 746 done_idx = priv->rx.done_idx; 747 ndesc = priv->rx.ndesc; 748 restpkt = ((proc_idx + ndesc - 1) - done_idx) % ndesc; 749 750 for (npkts = 0; npkts < num; npkts++) { 751 /* we can't receive more packet, so fill desc quickly */ 752 if (--restpkt < 0) 753 break; 754 755 cmdsts = ave_desc_read_cmdsts(ndev, AVE_DESCID_RX, proc_idx); 756 757 /* do nothing if owner is HW (==0 for Rx) */ 758 if (!(cmdsts & AVE_STS_OWN)) 759 break; 760 761 if (!(cmdsts & AVE_STS_OK)) { 762 priv->stats_rx.errors++; 763 proc_idx = (proc_idx + 1) % ndesc; 764 continue; 765 } 766 767 pktlen = cmdsts & AVE_STS_PKTLEN_RX_MASK; 768 769 /* get skbuff for rx */ 770 skb = priv->rx.desc[proc_idx].skbs; 771 priv->rx.desc[proc_idx].skbs = NULL; 772 773 ave_dma_unmap(ndev, &priv->rx.desc[proc_idx], DMA_FROM_DEVICE); 774 775 skb->dev = ndev; 776 skb_put(skb, pktlen); 777 skb->protocol = eth_type_trans(skb, ndev); 778 779 if ((cmdsts & AVE_STS_CSSV) && (!(cmdsts & AVE_STS_CSER))) 780 skb->ip_summed = CHECKSUM_UNNECESSARY; 781 782 rx_packets++; 783 rx_bytes += pktlen; 784 785 netif_receive_skb(skb); 786 787 proc_idx = (proc_idx + 1) % ndesc; 788 } 789 790 priv->rx.proc_idx = proc_idx; 791 792 /* update stats */ 793 u64_stats_update_begin(&priv->stats_rx.syncp); 794 priv->stats_rx.packets += rx_packets; 795 priv->stats_rx.bytes += rx_bytes; 796 u64_stats_update_end(&priv->stats_rx.syncp); 797 798 /* refill the Rx buffers */ 799 while (proc_idx != done_idx) { 800 if (ave_rxdesc_prepare(ndev, done_idx)) 801 break; 802 done_idx = (done_idx + 1) % ndesc; 803 } 804 805 priv->rx.done_idx = done_idx; 806 807 return npkts; 808 } 809 810 static int ave_napi_poll_rx(struct napi_struct *napi, int budget) 811 { 812 struct ave_private *priv; 813 struct net_device *ndev; 814 int num; 815 816 priv = container_of(napi, struct ave_private, napi_rx); 817 ndev = priv->ndev; 818 819 num = ave_rx_receive(ndev, budget); 820 if (num < budget) { 821 napi_complete_done(napi, num); 822 823 /* enable Rx interrupt when NAPI finishes */ 824 ave_irq_enable(ndev, AVE_GI_RXIINT); 825 } 826 827 return num; 828 } 829 830 static int ave_napi_poll_tx(struct napi_struct *napi, int budget) 831 { 832 struct ave_private *priv; 833 struct net_device *ndev; 834 int num; 835 836 priv = container_of(napi, struct ave_private, napi_tx); 837 ndev = priv->ndev; 838 839 num = ave_tx_complete(ndev); 840 napi_complete(napi); 841 842 /* enable Tx interrupt when NAPI finishes */ 843 ave_irq_enable(ndev, AVE_GI_TX); 844 845 return num; 846 } 847 848 static void ave_global_reset(struct net_device *ndev) 849 { 850 struct ave_private *priv = netdev_priv(ndev); 851 u32 val; 852 853 /* set config register */ 854 val = AVE_CFGR_FLE | AVE_CFGR_IPFCEN | AVE_CFGR_CHE; 855 if (!phy_interface_mode_is_rgmii(priv->phy_mode)) 856 val |= AVE_CFGR_MII; 857 writel(val, priv->base + AVE_CFGR); 858 859 /* reset RMII register */ 860 val = readl(priv->base + AVE_RSTCTRL); 861 val &= ~AVE_RSTCTRL_RMIIRST; 862 writel(val, priv->base + AVE_RSTCTRL); 863 864 /* assert reset */ 865 writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->base + AVE_GRR); 866 msleep(20); 867 868 /* 1st, negate PHY reset only */ 869 writel(AVE_GRR_GRST, priv->base + AVE_GRR); 870 msleep(40); 871 872 /* negate reset */ 873 writel(0, priv->base + AVE_GRR); 874 msleep(40); 875 876 /* negate RMII register */ 877 val = readl(priv->base + AVE_RSTCTRL); 878 val |= AVE_RSTCTRL_RMIIRST; 879 writel(val, priv->base + AVE_RSTCTRL); 880 881 ave_irq_disable_all(ndev); 882 } 883 884 static void ave_rxfifo_reset(struct net_device *ndev) 885 { 886 struct ave_private *priv = netdev_priv(ndev); 887 u32 rxcr_org; 888 889 /* save and disable MAC receive op */ 890 rxcr_org = readl(priv->base + AVE_RXCR); 891 writel(rxcr_org & (~AVE_RXCR_RXEN), priv->base + AVE_RXCR); 892 893 /* suspend Rx descriptor */ 894 ave_desc_switch(ndev, AVE_DESC_RX_SUSPEND); 895 896 /* receive all packets before descriptor starts */ 897 ave_rx_receive(ndev, priv->rx.ndesc); 898 899 /* assert reset */ 900 writel(AVE_GRR_RXFFR, priv->base + AVE_GRR); 901 udelay(50); 902 903 /* negate reset */ 904 writel(0, priv->base + AVE_GRR); 905 udelay(20); 906 907 /* negate interrupt status */ 908 writel(AVE_GI_RXOVF, priv->base + AVE_GISR); 909 910 /* permit descriptor */ 911 ave_desc_switch(ndev, AVE_DESC_RX_PERMIT); 912 913 /* restore MAC reccieve op */ 914 writel(rxcr_org, priv->base + AVE_RXCR); 915 } 916 917 static irqreturn_t ave_irq_handler(int irq, void *netdev) 918 { 919 struct net_device *ndev = (struct net_device *)netdev; 920 struct ave_private *priv = netdev_priv(ndev); 921 u32 gimr_val, gisr_val; 922 923 gimr_val = ave_irq_disable_all(ndev); 924 925 /* get interrupt status */ 926 gisr_val = readl(priv->base + AVE_GISR); 927 928 /* PHY */ 929 if (gisr_val & AVE_GI_PHY) 930 writel(AVE_GI_PHY, priv->base + AVE_GISR); 931 932 /* check exceeding packet */ 933 if (gisr_val & AVE_GI_RXERR) { 934 writel(AVE_GI_RXERR, priv->base + AVE_GISR); 935 netdev_err(ndev, "receive a packet exceeding frame buffer\n"); 936 } 937 938 gisr_val &= gimr_val; 939 if (!gisr_val) 940 goto exit_isr; 941 942 /* RxFIFO overflow */ 943 if (gisr_val & AVE_GI_RXOVF) { 944 priv->stats_rx.fifo_errors++; 945 ave_rxfifo_reset(ndev); 946 goto exit_isr; 947 } 948 949 /* Rx drop */ 950 if (gisr_val & AVE_GI_RXDROP) { 951 priv->stats_rx.dropped++; 952 writel(AVE_GI_RXDROP, priv->base + AVE_GISR); 953 } 954 955 /* Rx interval */ 956 if (gisr_val & AVE_GI_RXIINT) { 957 napi_schedule(&priv->napi_rx); 958 /* still force to disable Rx interrupt until NAPI finishes */ 959 gimr_val &= ~AVE_GI_RXIINT; 960 } 961 962 /* Tx completed */ 963 if (gisr_val & AVE_GI_TX) { 964 napi_schedule(&priv->napi_tx); 965 /* still force to disable Tx interrupt until NAPI finishes */ 966 gimr_val &= ~AVE_GI_TX; 967 } 968 969 exit_isr: 970 ave_irq_restore(ndev, gimr_val); 971 972 return IRQ_HANDLED; 973 } 974 975 static int ave_pfsel_start(struct net_device *ndev, unsigned int entry) 976 { 977 struct ave_private *priv = netdev_priv(ndev); 978 u32 val; 979 980 if (WARN_ON(entry > AVE_PF_SIZE)) 981 return -EINVAL; 982 983 val = readl(priv->base + AVE_PFEN); 984 writel(val | BIT(entry), priv->base + AVE_PFEN); 985 986 return 0; 987 } 988 989 static int ave_pfsel_stop(struct net_device *ndev, unsigned int entry) 990 { 991 struct ave_private *priv = netdev_priv(ndev); 992 u32 val; 993 994 if (WARN_ON(entry > AVE_PF_SIZE)) 995 return -EINVAL; 996 997 val = readl(priv->base + AVE_PFEN); 998 writel(val & ~BIT(entry), priv->base + AVE_PFEN); 999 1000 return 0; 1001 } 1002 1003 static int ave_pfsel_set_macaddr(struct net_device *ndev, 1004 unsigned int entry, 1005 const unsigned char *mac_addr, 1006 unsigned int set_size) 1007 { 1008 struct ave_private *priv = netdev_priv(ndev); 1009 1010 if (WARN_ON(entry > AVE_PF_SIZE)) 1011 return -EINVAL; 1012 if (WARN_ON(set_size > 6)) 1013 return -EINVAL; 1014 1015 ave_pfsel_stop(ndev, entry); 1016 1017 /* set MAC address for the filter */ 1018 ave_hw_write_macaddr(ndev, mac_addr, 1019 AVE_PKTF(entry), AVE_PKTF(entry) + 4); 1020 1021 /* set byte mask */ 1022 writel(GENMASK(31, set_size) & AVE_PFMBYTE_MASK0, 1023 priv->base + AVE_PFMBYTE(entry)); 1024 writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4); 1025 1026 /* set bit mask filter */ 1027 writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry)); 1028 1029 /* set selector to ring 0 */ 1030 writel(0, priv->base + AVE_PFSEL(entry)); 1031 1032 /* restart filter */ 1033 ave_pfsel_start(ndev, entry); 1034 1035 return 0; 1036 } 1037 1038 static void ave_pfsel_set_promisc(struct net_device *ndev, 1039 unsigned int entry, u32 rxring) 1040 { 1041 struct ave_private *priv = netdev_priv(ndev); 1042 1043 if (WARN_ON(entry > AVE_PF_SIZE)) 1044 return; 1045 1046 ave_pfsel_stop(ndev, entry); 1047 1048 /* set byte mask */ 1049 writel(AVE_PFMBYTE_MASK0, priv->base + AVE_PFMBYTE(entry)); 1050 writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4); 1051 1052 /* set bit mask filter */ 1053 writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry)); 1054 1055 /* set selector to rxring */ 1056 writel(rxring, priv->base + AVE_PFSEL(entry)); 1057 1058 ave_pfsel_start(ndev, entry); 1059 } 1060 1061 static void ave_pfsel_init(struct net_device *ndev) 1062 { 1063 unsigned char bcast_mac[ETH_ALEN]; 1064 int i; 1065 1066 eth_broadcast_addr(bcast_mac); 1067 1068 for (i = 0; i < AVE_PF_SIZE; i++) 1069 ave_pfsel_stop(ndev, i); 1070 1071 /* promiscious entry, select ring 0 */ 1072 ave_pfsel_set_promisc(ndev, AVE_PFNUM_FILTER, 0); 1073 1074 /* unicast entry */ 1075 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_UNICAST, ndev->dev_addr, 6); 1076 1077 /* broadcast entry */ 1078 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_BROADCAST, bcast_mac, 6); 1079 } 1080 1081 static void ave_phy_adjust_link(struct net_device *ndev) 1082 { 1083 struct ave_private *priv = netdev_priv(ndev); 1084 struct phy_device *phydev = ndev->phydev; 1085 u32 val, txcr, rxcr, rxcr_org; 1086 u16 rmt_adv = 0, lcl_adv = 0; 1087 u8 cap; 1088 1089 /* set RGMII speed */ 1090 val = readl(priv->base + AVE_TXCR); 1091 val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G); 1092 1093 if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000) 1094 val |= AVE_TXCR_TXSPD_1G; 1095 else if (phydev->speed == SPEED_100) 1096 val |= AVE_TXCR_TXSPD_100; 1097 1098 writel(val, priv->base + AVE_TXCR); 1099 1100 /* set RMII speed (100M/10M only) */ 1101 if (!phy_interface_is_rgmii(phydev)) { 1102 val = readl(priv->base + AVE_LINKSEL); 1103 if (phydev->speed == SPEED_10) 1104 val &= ~AVE_LINKSEL_100M; 1105 else 1106 val |= AVE_LINKSEL_100M; 1107 writel(val, priv->base + AVE_LINKSEL); 1108 } 1109 1110 /* check current RXCR/TXCR */ 1111 rxcr = readl(priv->base + AVE_RXCR); 1112 txcr = readl(priv->base + AVE_TXCR); 1113 rxcr_org = rxcr; 1114 1115 if (phydev->duplex) { 1116 rxcr |= AVE_RXCR_FDUPEN; 1117 1118 if (phydev->pause) 1119 rmt_adv |= LPA_PAUSE_CAP; 1120 if (phydev->asym_pause) 1121 rmt_adv |= LPA_PAUSE_ASYM; 1122 1123 lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising); 1124 cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 1125 if (cap & FLOW_CTRL_TX) 1126 txcr |= AVE_TXCR_FLOCTR; 1127 else 1128 txcr &= ~AVE_TXCR_FLOCTR; 1129 if (cap & FLOW_CTRL_RX) 1130 rxcr |= AVE_RXCR_FLOCTR; 1131 else 1132 rxcr &= ~AVE_RXCR_FLOCTR; 1133 } else { 1134 rxcr &= ~AVE_RXCR_FDUPEN; 1135 rxcr &= ~AVE_RXCR_FLOCTR; 1136 txcr &= ~AVE_TXCR_FLOCTR; 1137 } 1138 1139 if (rxcr_org != rxcr) { 1140 /* disable Rx mac */ 1141 writel(rxcr & ~AVE_RXCR_RXEN, priv->base + AVE_RXCR); 1142 /* change and enable TX/Rx mac */ 1143 writel(txcr, priv->base + AVE_TXCR); 1144 writel(rxcr, priv->base + AVE_RXCR); 1145 } 1146 1147 phy_print_status(phydev); 1148 } 1149 1150 static void ave_macaddr_init(struct net_device *ndev) 1151 { 1152 ave_hw_write_macaddr(ndev, ndev->dev_addr, AVE_RXMAC1R, AVE_RXMAC2R); 1153 1154 /* pfsel unicast entry */ 1155 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_UNICAST, ndev->dev_addr, 6); 1156 } 1157 1158 static int ave_init(struct net_device *ndev) 1159 { 1160 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1161 struct ave_private *priv = netdev_priv(ndev); 1162 struct device *dev = ndev->dev.parent; 1163 struct device_node *np = dev->of_node; 1164 struct device_node *mdio_np; 1165 struct phy_device *phydev; 1166 int nc, nr, ret; 1167 1168 /* enable clk because of hw access until ndo_open */ 1169 for (nc = 0; nc < priv->nclks; nc++) { 1170 ret = clk_prepare_enable(priv->clk[nc]); 1171 if (ret) { 1172 dev_err(dev, "can't enable clock\n"); 1173 goto out_clk_disable; 1174 } 1175 } 1176 1177 for (nr = 0; nr < priv->nrsts; nr++) { 1178 ret = reset_control_deassert(priv->rst[nr]); 1179 if (ret) { 1180 dev_err(dev, "can't deassert reset\n"); 1181 goto out_reset_assert; 1182 } 1183 } 1184 1185 ret = regmap_update_bits(priv->regmap, SG_ETPINMODE, 1186 priv->pinmode_mask, priv->pinmode_val); 1187 if (ret) 1188 return ret; 1189 1190 ave_global_reset(ndev); 1191 1192 mdio_np = of_get_child_by_name(np, "mdio"); 1193 if (!mdio_np) { 1194 dev_err(dev, "mdio node not found\n"); 1195 ret = -EINVAL; 1196 goto out_reset_assert; 1197 } 1198 ret = of_mdiobus_register(priv->mdio, mdio_np); 1199 of_node_put(mdio_np); 1200 if (ret) { 1201 dev_err(dev, "failed to register mdiobus\n"); 1202 goto out_reset_assert; 1203 } 1204 1205 phydev = of_phy_get_and_connect(ndev, np, ave_phy_adjust_link); 1206 if (!phydev) { 1207 dev_err(dev, "could not attach to PHY\n"); 1208 ret = -ENODEV; 1209 goto out_mdio_unregister; 1210 } 1211 1212 priv->phydev = phydev; 1213 1214 ave_ethtool_get_wol(ndev, &wol); 1215 device_set_wakeup_capable(&ndev->dev, !!wol.supported); 1216 1217 /* set wol initial state disabled */ 1218 wol.wolopts = 0; 1219 ave_ethtool_set_wol(ndev, &wol); 1220 1221 if (!phy_interface_is_rgmii(phydev)) 1222 phy_set_max_speed(phydev, SPEED_100); 1223 1224 phy_support_asym_pause(phydev); 1225 1226 phy_attached_info(phydev); 1227 1228 return 0; 1229 1230 out_mdio_unregister: 1231 mdiobus_unregister(priv->mdio); 1232 out_reset_assert: 1233 while (--nr >= 0) 1234 reset_control_assert(priv->rst[nr]); 1235 out_clk_disable: 1236 while (--nc >= 0) 1237 clk_disable_unprepare(priv->clk[nc]); 1238 1239 return ret; 1240 } 1241 1242 static void ave_uninit(struct net_device *ndev) 1243 { 1244 struct ave_private *priv = netdev_priv(ndev); 1245 int i; 1246 1247 phy_disconnect(priv->phydev); 1248 mdiobus_unregister(priv->mdio); 1249 1250 /* disable clk because of hw access after ndo_stop */ 1251 for (i = 0; i < priv->nrsts; i++) 1252 reset_control_assert(priv->rst[i]); 1253 for (i = 0; i < priv->nclks; i++) 1254 clk_disable_unprepare(priv->clk[i]); 1255 } 1256 1257 static int ave_open(struct net_device *ndev) 1258 { 1259 struct ave_private *priv = netdev_priv(ndev); 1260 int entry; 1261 int ret; 1262 u32 val; 1263 1264 ret = request_irq(priv->irq, ave_irq_handler, IRQF_SHARED, ndev->name, 1265 ndev); 1266 if (ret) 1267 return ret; 1268 1269 priv->tx.desc = kcalloc(priv->tx.ndesc, sizeof(*priv->tx.desc), 1270 GFP_KERNEL); 1271 if (!priv->tx.desc) { 1272 ret = -ENOMEM; 1273 goto out_free_irq; 1274 } 1275 1276 priv->rx.desc = kcalloc(priv->rx.ndesc, sizeof(*priv->rx.desc), 1277 GFP_KERNEL); 1278 if (!priv->rx.desc) { 1279 kfree(priv->tx.desc); 1280 ret = -ENOMEM; 1281 goto out_free_irq; 1282 } 1283 1284 /* initialize Tx work and descriptor */ 1285 priv->tx.proc_idx = 0; 1286 priv->tx.done_idx = 0; 1287 for (entry = 0; entry < priv->tx.ndesc; entry++) { 1288 ave_desc_write_cmdsts(ndev, AVE_DESCID_TX, entry, 0); 1289 ave_desc_write_addr(ndev, AVE_DESCID_TX, entry, 0); 1290 } 1291 writel(AVE_TXDC_ADDR_START | 1292 (((priv->tx.ndesc * priv->desc_size) << 16) & AVE_TXDC_SIZE), 1293 priv->base + AVE_TXDC); 1294 1295 /* initialize Rx work and descriptor */ 1296 priv->rx.proc_idx = 0; 1297 priv->rx.done_idx = 0; 1298 for (entry = 0; entry < priv->rx.ndesc; entry++) { 1299 if (ave_rxdesc_prepare(ndev, entry)) 1300 break; 1301 } 1302 writel(AVE_RXDC0_ADDR_START | 1303 (((priv->rx.ndesc * priv->desc_size) << 16) & AVE_RXDC0_SIZE), 1304 priv->base + AVE_RXDC0); 1305 1306 ave_desc_switch(ndev, AVE_DESC_START); 1307 1308 ave_pfsel_init(ndev); 1309 ave_macaddr_init(ndev); 1310 1311 /* set Rx configuration */ 1312 /* full duplex, enable pause drop, enalbe flow control */ 1313 val = AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_DRPEN | 1314 AVE_RXCR_FLOCTR | (AVE_MAX_ETHFRAME & AVE_RXCR_MPSIZ_MASK); 1315 writel(val, priv->base + AVE_RXCR); 1316 1317 /* set Tx configuration */ 1318 /* enable flow control, disable loopback */ 1319 writel(AVE_TXCR_FLOCTR, priv->base + AVE_TXCR); 1320 1321 /* enable timer, clear EN,INTM, and mask interval unit(BSCK) */ 1322 val = readl(priv->base + AVE_IIRQC) & AVE_IIRQC_BSCK; 1323 val |= AVE_IIRQC_EN0 | (AVE_INTM_COUNT << 16); 1324 writel(val, priv->base + AVE_IIRQC); 1325 1326 val = AVE_GI_RXIINT | AVE_GI_RXOVF | AVE_GI_TX | AVE_GI_RXDROP; 1327 ave_irq_restore(ndev, val); 1328 1329 napi_enable(&priv->napi_rx); 1330 napi_enable(&priv->napi_tx); 1331 1332 phy_start(ndev->phydev); 1333 phy_start_aneg(ndev->phydev); 1334 netif_start_queue(ndev); 1335 1336 return 0; 1337 1338 out_free_irq: 1339 disable_irq(priv->irq); 1340 free_irq(priv->irq, ndev); 1341 1342 return ret; 1343 } 1344 1345 static int ave_stop(struct net_device *ndev) 1346 { 1347 struct ave_private *priv = netdev_priv(ndev); 1348 int entry; 1349 1350 ave_irq_disable_all(ndev); 1351 disable_irq(priv->irq); 1352 free_irq(priv->irq, ndev); 1353 1354 netif_tx_disable(ndev); 1355 phy_stop(ndev->phydev); 1356 napi_disable(&priv->napi_tx); 1357 napi_disable(&priv->napi_rx); 1358 1359 ave_desc_switch(ndev, AVE_DESC_STOP); 1360 1361 /* free Tx buffer */ 1362 for (entry = 0; entry < priv->tx.ndesc; entry++) { 1363 if (!priv->tx.desc[entry].skbs) 1364 continue; 1365 1366 ave_dma_unmap(ndev, &priv->tx.desc[entry], DMA_TO_DEVICE); 1367 dev_kfree_skb_any(priv->tx.desc[entry].skbs); 1368 priv->tx.desc[entry].skbs = NULL; 1369 } 1370 priv->tx.proc_idx = 0; 1371 priv->tx.done_idx = 0; 1372 1373 /* free Rx buffer */ 1374 for (entry = 0; entry < priv->rx.ndesc; entry++) { 1375 if (!priv->rx.desc[entry].skbs) 1376 continue; 1377 1378 ave_dma_unmap(ndev, &priv->rx.desc[entry], DMA_FROM_DEVICE); 1379 dev_kfree_skb_any(priv->rx.desc[entry].skbs); 1380 priv->rx.desc[entry].skbs = NULL; 1381 } 1382 priv->rx.proc_idx = 0; 1383 priv->rx.done_idx = 0; 1384 1385 kfree(priv->tx.desc); 1386 kfree(priv->rx.desc); 1387 1388 return 0; 1389 } 1390 1391 static int ave_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1392 { 1393 struct ave_private *priv = netdev_priv(ndev); 1394 u32 proc_idx, done_idx, ndesc, cmdsts; 1395 int ret, freepkt; 1396 dma_addr_t paddr; 1397 1398 proc_idx = priv->tx.proc_idx; 1399 done_idx = priv->tx.done_idx; 1400 ndesc = priv->tx.ndesc; 1401 freepkt = ((done_idx + ndesc - 1) - proc_idx) % ndesc; 1402 1403 /* stop queue when not enough entry */ 1404 if (unlikely(freepkt < 1)) { 1405 netif_stop_queue(ndev); 1406 return NETDEV_TX_BUSY; 1407 } 1408 1409 /* add padding for short packet */ 1410 if (skb_put_padto(skb, ETH_ZLEN)) { 1411 priv->stats_tx.dropped++; 1412 return NETDEV_TX_OK; 1413 } 1414 1415 /* map Tx buffer 1416 * Tx buffer set to the Tx descriptor doesn't have any restriction. 1417 */ 1418 ret = ave_dma_map(ndev, &priv->tx.desc[proc_idx], 1419 skb->data, skb->len, DMA_TO_DEVICE, &paddr); 1420 if (ret) { 1421 dev_kfree_skb_any(skb); 1422 priv->stats_tx.dropped++; 1423 return NETDEV_TX_OK; 1424 } 1425 1426 priv->tx.desc[proc_idx].skbs = skb; 1427 1428 ave_desc_write_addr(ndev, AVE_DESCID_TX, proc_idx, paddr); 1429 1430 cmdsts = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST | 1431 (skb->len & AVE_STS_PKTLEN_TX_MASK); 1432 1433 /* set interrupt per AVE_FORCE_TXINTCNT or when queue is stopped */ 1434 if (!(proc_idx % AVE_FORCE_TXINTCNT) || netif_queue_stopped(ndev)) 1435 cmdsts |= AVE_STS_INTR; 1436 1437 /* disable checksum calculation when skb doesn't calurate checksum */ 1438 if (skb->ip_summed == CHECKSUM_NONE || 1439 skb->ip_summed == CHECKSUM_UNNECESSARY) 1440 cmdsts |= AVE_STS_NOCSUM; 1441 1442 ave_desc_write_cmdsts(ndev, AVE_DESCID_TX, proc_idx, cmdsts); 1443 1444 priv->tx.proc_idx = (proc_idx + 1) % ndesc; 1445 1446 return NETDEV_TX_OK; 1447 } 1448 1449 static int ave_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) 1450 { 1451 return phy_mii_ioctl(ndev->phydev, ifr, cmd); 1452 } 1453 1454 static const u8 v4multi_macadr[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 1455 static const u8 v6multi_macadr[] = { 0x33, 0x00, 0x00, 0x00, 0x00, 0x00 }; 1456 1457 static void ave_set_rx_mode(struct net_device *ndev) 1458 { 1459 struct ave_private *priv = netdev_priv(ndev); 1460 struct netdev_hw_addr *hw_adr; 1461 int count, mc_cnt; 1462 u32 val; 1463 1464 /* MAC addr filter enable for promiscious mode */ 1465 mc_cnt = netdev_mc_count(ndev); 1466 val = readl(priv->base + AVE_RXCR); 1467 if (ndev->flags & IFF_PROMISC || !mc_cnt) 1468 val &= ~AVE_RXCR_AFEN; 1469 else 1470 val |= AVE_RXCR_AFEN; 1471 writel(val, priv->base + AVE_RXCR); 1472 1473 /* set all multicast address */ 1474 if ((ndev->flags & IFF_ALLMULTI) || mc_cnt > AVE_PF_MULTICAST_SIZE) { 1475 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_MULTICAST, 1476 v4multi_macadr, 1); 1477 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_MULTICAST + 1, 1478 v6multi_macadr, 1); 1479 } else { 1480 /* stop all multicast filter */ 1481 for (count = 0; count < AVE_PF_MULTICAST_SIZE; count++) 1482 ave_pfsel_stop(ndev, AVE_PFNUM_MULTICAST + count); 1483 1484 /* set multicast addresses */ 1485 count = 0; 1486 netdev_for_each_mc_addr(hw_adr, ndev) { 1487 if (count == mc_cnt) 1488 break; 1489 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_MULTICAST + count, 1490 hw_adr->addr, 6); 1491 count++; 1492 } 1493 } 1494 } 1495 1496 static void ave_get_stats64(struct net_device *ndev, 1497 struct rtnl_link_stats64 *stats) 1498 { 1499 struct ave_private *priv = netdev_priv(ndev); 1500 unsigned int start; 1501 1502 do { 1503 start = u64_stats_fetch_begin_irq(&priv->stats_rx.syncp); 1504 stats->rx_packets = priv->stats_rx.packets; 1505 stats->rx_bytes = priv->stats_rx.bytes; 1506 } while (u64_stats_fetch_retry_irq(&priv->stats_rx.syncp, start)); 1507 1508 do { 1509 start = u64_stats_fetch_begin_irq(&priv->stats_tx.syncp); 1510 stats->tx_packets = priv->stats_tx.packets; 1511 stats->tx_bytes = priv->stats_tx.bytes; 1512 } while (u64_stats_fetch_retry_irq(&priv->stats_tx.syncp, start)); 1513 1514 stats->rx_errors = priv->stats_rx.errors; 1515 stats->tx_errors = priv->stats_tx.errors; 1516 stats->rx_dropped = priv->stats_rx.dropped; 1517 stats->tx_dropped = priv->stats_tx.dropped; 1518 stats->rx_fifo_errors = priv->stats_rx.fifo_errors; 1519 stats->collisions = priv->stats_tx.collisions; 1520 } 1521 1522 static int ave_set_mac_address(struct net_device *ndev, void *p) 1523 { 1524 int ret = eth_mac_addr(ndev, p); 1525 1526 if (ret) 1527 return ret; 1528 1529 ave_macaddr_init(ndev); 1530 1531 return 0; 1532 } 1533 1534 static const struct net_device_ops ave_netdev_ops = { 1535 .ndo_init = ave_init, 1536 .ndo_uninit = ave_uninit, 1537 .ndo_open = ave_open, 1538 .ndo_stop = ave_stop, 1539 .ndo_start_xmit = ave_start_xmit, 1540 .ndo_do_ioctl = ave_ioctl, 1541 .ndo_set_rx_mode = ave_set_rx_mode, 1542 .ndo_get_stats64 = ave_get_stats64, 1543 .ndo_set_mac_address = ave_set_mac_address, 1544 }; 1545 1546 static int ave_probe(struct platform_device *pdev) 1547 { 1548 const struct ave_soc_data *data; 1549 struct device *dev = &pdev->dev; 1550 char buf[ETHTOOL_FWVERS_LEN]; 1551 struct of_phandle_args args; 1552 phy_interface_t phy_mode; 1553 struct ave_private *priv; 1554 struct net_device *ndev; 1555 struct device_node *np; 1556 const void *mac_addr; 1557 void __iomem *base; 1558 const char *name; 1559 int i, irq, ret; 1560 u64 dma_mask; 1561 u32 ave_id; 1562 1563 data = of_device_get_match_data(dev); 1564 if (WARN_ON(!data)) 1565 return -EINVAL; 1566 1567 np = dev->of_node; 1568 phy_mode = of_get_phy_mode(np); 1569 if ((int)phy_mode < 0) { 1570 dev_err(dev, "phy-mode not found\n"); 1571 return -EINVAL; 1572 } 1573 1574 irq = platform_get_irq(pdev, 0); 1575 if (irq < 0) 1576 return irq; 1577 1578 base = devm_platform_ioremap_resource(pdev, 0); 1579 if (IS_ERR(base)) 1580 return PTR_ERR(base); 1581 1582 ndev = alloc_etherdev(sizeof(struct ave_private)); 1583 if (!ndev) { 1584 dev_err(dev, "can't allocate ethernet device\n"); 1585 return -ENOMEM; 1586 } 1587 1588 ndev->netdev_ops = &ave_netdev_ops; 1589 ndev->ethtool_ops = &ave_ethtool_ops; 1590 SET_NETDEV_DEV(ndev, dev); 1591 1592 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_RXCSUM); 1593 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_RXCSUM); 1594 1595 ndev->max_mtu = AVE_MAX_ETHFRAME - (ETH_HLEN + ETH_FCS_LEN); 1596 1597 mac_addr = of_get_mac_address(np); 1598 if (!IS_ERR(mac_addr)) 1599 ether_addr_copy(ndev->dev_addr, mac_addr); 1600 1601 /* if the mac address is invalid, use random mac address */ 1602 if (!is_valid_ether_addr(ndev->dev_addr)) { 1603 eth_hw_addr_random(ndev); 1604 dev_warn(dev, "Using random MAC address: %pM\n", 1605 ndev->dev_addr); 1606 } 1607 1608 priv = netdev_priv(ndev); 1609 priv->base = base; 1610 priv->irq = irq; 1611 priv->ndev = ndev; 1612 priv->msg_enable = netif_msg_init(-1, AVE_DEFAULT_MSG_ENABLE); 1613 priv->phy_mode = phy_mode; 1614 priv->data = data; 1615 1616 if (IS_DESC_64BIT(priv)) { 1617 priv->desc_size = AVE_DESC_SIZE_64; 1618 priv->tx.daddr = AVE_TXDM_64; 1619 priv->rx.daddr = AVE_RXDM_64; 1620 dma_mask = DMA_BIT_MASK(64); 1621 } else { 1622 priv->desc_size = AVE_DESC_SIZE_32; 1623 priv->tx.daddr = AVE_TXDM_32; 1624 priv->rx.daddr = AVE_RXDM_32; 1625 dma_mask = DMA_BIT_MASK(32); 1626 } 1627 ret = dma_set_mask(dev, dma_mask); 1628 if (ret) 1629 goto out_free_netdev; 1630 1631 priv->tx.ndesc = AVE_NR_TXDESC; 1632 priv->rx.ndesc = AVE_NR_RXDESC; 1633 1634 u64_stats_init(&priv->stats_tx.syncp); 1635 u64_stats_init(&priv->stats_rx.syncp); 1636 1637 for (i = 0; i < AVE_MAX_CLKS; i++) { 1638 name = priv->data->clock_names[i]; 1639 if (!name) 1640 break; 1641 priv->clk[i] = devm_clk_get(dev, name); 1642 if (IS_ERR(priv->clk[i])) { 1643 ret = PTR_ERR(priv->clk[i]); 1644 goto out_free_netdev; 1645 } 1646 priv->nclks++; 1647 } 1648 1649 for (i = 0; i < AVE_MAX_RSTS; i++) { 1650 name = priv->data->reset_names[i]; 1651 if (!name) 1652 break; 1653 priv->rst[i] = devm_reset_control_get_shared(dev, name); 1654 if (IS_ERR(priv->rst[i])) { 1655 ret = PTR_ERR(priv->rst[i]); 1656 goto out_free_netdev; 1657 } 1658 priv->nrsts++; 1659 } 1660 1661 ret = of_parse_phandle_with_fixed_args(np, 1662 "socionext,syscon-phy-mode", 1663 1, 0, &args); 1664 if (ret) { 1665 dev_err(dev, "can't get syscon-phy-mode property\n"); 1666 goto out_free_netdev; 1667 } 1668 priv->regmap = syscon_node_to_regmap(args.np); 1669 of_node_put(args.np); 1670 if (IS_ERR(priv->regmap)) { 1671 dev_err(dev, "can't map syscon-phy-mode\n"); 1672 ret = PTR_ERR(priv->regmap); 1673 goto out_free_netdev; 1674 } 1675 ret = priv->data->get_pinmode(priv, phy_mode, args.args[0]); 1676 if (ret) { 1677 dev_err(dev, "invalid phy-mode setting\n"); 1678 goto out_free_netdev; 1679 } 1680 1681 priv->mdio = devm_mdiobus_alloc(dev); 1682 if (!priv->mdio) { 1683 ret = -ENOMEM; 1684 goto out_free_netdev; 1685 } 1686 priv->mdio->priv = ndev; 1687 priv->mdio->parent = dev; 1688 priv->mdio->read = ave_mdiobus_read; 1689 priv->mdio->write = ave_mdiobus_write; 1690 priv->mdio->name = "uniphier-mdio"; 1691 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%x", 1692 pdev->name, pdev->id); 1693 1694 /* Register as a NAPI supported driver */ 1695 netif_napi_add(ndev, &priv->napi_rx, ave_napi_poll_rx, 1696 NAPI_POLL_WEIGHT); 1697 netif_tx_napi_add(ndev, &priv->napi_tx, ave_napi_poll_tx, 1698 NAPI_POLL_WEIGHT); 1699 1700 platform_set_drvdata(pdev, ndev); 1701 1702 ret = register_netdev(ndev); 1703 if (ret) { 1704 dev_err(dev, "failed to register netdevice\n"); 1705 goto out_del_napi; 1706 } 1707 1708 /* get ID and version */ 1709 ave_id = readl(priv->base + AVE_IDR); 1710 ave_hw_read_version(ndev, buf, sizeof(buf)); 1711 1712 dev_info(dev, "Socionext %c%c%c%c Ethernet IP %s (irq=%d, phy=%s)\n", 1713 (ave_id >> 24) & 0xff, (ave_id >> 16) & 0xff, 1714 (ave_id >> 8) & 0xff, (ave_id >> 0) & 0xff, 1715 buf, priv->irq, phy_modes(phy_mode)); 1716 1717 return 0; 1718 1719 out_del_napi: 1720 netif_napi_del(&priv->napi_rx); 1721 netif_napi_del(&priv->napi_tx); 1722 out_free_netdev: 1723 free_netdev(ndev); 1724 1725 return ret; 1726 } 1727 1728 static int ave_remove(struct platform_device *pdev) 1729 { 1730 struct net_device *ndev = platform_get_drvdata(pdev); 1731 struct ave_private *priv = netdev_priv(ndev); 1732 1733 unregister_netdev(ndev); 1734 netif_napi_del(&priv->napi_rx); 1735 netif_napi_del(&priv->napi_tx); 1736 free_netdev(ndev); 1737 1738 return 0; 1739 } 1740 1741 #ifdef CONFIG_PM_SLEEP 1742 static int ave_suspend(struct device *dev) 1743 { 1744 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1745 struct net_device *ndev = dev_get_drvdata(dev); 1746 struct ave_private *priv = netdev_priv(ndev); 1747 int ret = 0; 1748 1749 if (netif_running(ndev)) { 1750 ret = ave_stop(ndev); 1751 netif_device_detach(ndev); 1752 } 1753 1754 ave_ethtool_get_wol(ndev, &wol); 1755 priv->wolopts = wol.wolopts; 1756 1757 return ret; 1758 } 1759 1760 static int ave_resume(struct device *dev) 1761 { 1762 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1763 struct net_device *ndev = dev_get_drvdata(dev); 1764 struct ave_private *priv = netdev_priv(ndev); 1765 int ret = 0; 1766 1767 ave_global_reset(ndev); 1768 1769 ave_ethtool_get_wol(ndev, &wol); 1770 wol.wolopts = priv->wolopts; 1771 ave_ethtool_set_wol(ndev, &wol); 1772 1773 if (ndev->phydev) { 1774 ret = phy_resume(ndev->phydev); 1775 if (ret) 1776 return ret; 1777 } 1778 1779 if (netif_running(ndev)) { 1780 ret = ave_open(ndev); 1781 netif_device_attach(ndev); 1782 } 1783 1784 return ret; 1785 } 1786 1787 static SIMPLE_DEV_PM_OPS(ave_pm_ops, ave_suspend, ave_resume); 1788 #define AVE_PM_OPS (&ave_pm_ops) 1789 #else 1790 #define AVE_PM_OPS NULL 1791 #endif 1792 1793 static int ave_pro4_get_pinmode(struct ave_private *priv, 1794 phy_interface_t phy_mode, u32 arg) 1795 { 1796 if (arg > 0) 1797 return -EINVAL; 1798 1799 priv->pinmode_mask = SG_ETPINMODE_RMII(0); 1800 1801 switch (phy_mode) { 1802 case PHY_INTERFACE_MODE_RMII: 1803 priv->pinmode_val = SG_ETPINMODE_RMII(0); 1804 break; 1805 case PHY_INTERFACE_MODE_MII: 1806 case PHY_INTERFACE_MODE_RGMII: 1807 priv->pinmode_val = 0; 1808 break; 1809 default: 1810 return -EINVAL; 1811 } 1812 1813 return 0; 1814 } 1815 1816 static int ave_ld11_get_pinmode(struct ave_private *priv, 1817 phy_interface_t phy_mode, u32 arg) 1818 { 1819 if (arg > 0) 1820 return -EINVAL; 1821 1822 priv->pinmode_mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); 1823 1824 switch (phy_mode) { 1825 case PHY_INTERFACE_MODE_INTERNAL: 1826 priv->pinmode_val = 0; 1827 break; 1828 case PHY_INTERFACE_MODE_RMII: 1829 priv->pinmode_val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); 1830 break; 1831 default: 1832 return -EINVAL; 1833 } 1834 1835 return 0; 1836 } 1837 1838 static int ave_ld20_get_pinmode(struct ave_private *priv, 1839 phy_interface_t phy_mode, u32 arg) 1840 { 1841 if (arg > 0) 1842 return -EINVAL; 1843 1844 priv->pinmode_mask = SG_ETPINMODE_RMII(0); 1845 1846 switch (phy_mode) { 1847 case PHY_INTERFACE_MODE_RMII: 1848 priv->pinmode_val = SG_ETPINMODE_RMII(0); 1849 break; 1850 case PHY_INTERFACE_MODE_RGMII: 1851 priv->pinmode_val = 0; 1852 break; 1853 default: 1854 return -EINVAL; 1855 } 1856 1857 return 0; 1858 } 1859 1860 static int ave_pxs3_get_pinmode(struct ave_private *priv, 1861 phy_interface_t phy_mode, u32 arg) 1862 { 1863 if (arg > 1) 1864 return -EINVAL; 1865 1866 priv->pinmode_mask = SG_ETPINMODE_RMII(arg); 1867 1868 switch (phy_mode) { 1869 case PHY_INTERFACE_MODE_RMII: 1870 priv->pinmode_val = SG_ETPINMODE_RMII(arg); 1871 break; 1872 case PHY_INTERFACE_MODE_RGMII: 1873 priv->pinmode_val = 0; 1874 break; 1875 default: 1876 return -EINVAL; 1877 } 1878 1879 return 0; 1880 } 1881 1882 static const struct ave_soc_data ave_pro4_data = { 1883 .is_desc_64bit = false, 1884 .clock_names = { 1885 "gio", "ether", "ether-gb", "ether-phy", 1886 }, 1887 .reset_names = { 1888 "gio", "ether", 1889 }, 1890 .get_pinmode = ave_pro4_get_pinmode, 1891 }; 1892 1893 static const struct ave_soc_data ave_pxs2_data = { 1894 .is_desc_64bit = false, 1895 .clock_names = { 1896 "ether", 1897 }, 1898 .reset_names = { 1899 "ether", 1900 }, 1901 .get_pinmode = ave_pro4_get_pinmode, 1902 }; 1903 1904 static const struct ave_soc_data ave_ld11_data = { 1905 .is_desc_64bit = false, 1906 .clock_names = { 1907 "ether", 1908 }, 1909 .reset_names = { 1910 "ether", 1911 }, 1912 .get_pinmode = ave_ld11_get_pinmode, 1913 }; 1914 1915 static const struct ave_soc_data ave_ld20_data = { 1916 .is_desc_64bit = true, 1917 .clock_names = { 1918 "ether", 1919 }, 1920 .reset_names = { 1921 "ether", 1922 }, 1923 .get_pinmode = ave_ld20_get_pinmode, 1924 }; 1925 1926 static const struct ave_soc_data ave_pxs3_data = { 1927 .is_desc_64bit = false, 1928 .clock_names = { 1929 "ether", 1930 }, 1931 .reset_names = { 1932 "ether", 1933 }, 1934 .get_pinmode = ave_pxs3_get_pinmode, 1935 }; 1936 1937 static const struct of_device_id of_ave_match[] = { 1938 { 1939 .compatible = "socionext,uniphier-pro4-ave4", 1940 .data = &ave_pro4_data, 1941 }, 1942 { 1943 .compatible = "socionext,uniphier-pxs2-ave4", 1944 .data = &ave_pxs2_data, 1945 }, 1946 { 1947 .compatible = "socionext,uniphier-ld11-ave4", 1948 .data = &ave_ld11_data, 1949 }, 1950 { 1951 .compatible = "socionext,uniphier-ld20-ave4", 1952 .data = &ave_ld20_data, 1953 }, 1954 { 1955 .compatible = "socionext,uniphier-pxs3-ave4", 1956 .data = &ave_pxs3_data, 1957 }, 1958 { /* Sentinel */ } 1959 }; 1960 MODULE_DEVICE_TABLE(of, of_ave_match); 1961 1962 static struct platform_driver ave_driver = { 1963 .probe = ave_probe, 1964 .remove = ave_remove, 1965 .driver = { 1966 .name = "ave", 1967 .pm = AVE_PM_OPS, 1968 .of_match_table = of_ave_match, 1969 }, 1970 }; 1971 module_platform_driver(ave_driver); 1972 1973 MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>"); 1974 MODULE_DESCRIPTION("Socionext UniPhier AVE ethernet driver"); 1975 MODULE_LICENSE("GPL v2"); 1976