1 // SPDX-License-Identifier: GPL-2.0+ 2 3 #include <linux/types.h> 4 #include <linux/clk.h> 5 #include <linux/platform_device.h> 6 #include <linux/pm_runtime.h> 7 #include <linux/acpi.h> 8 #include <linux/of_mdio.h> 9 #include <linux/etherdevice.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 13 #include <net/tcp.h> 14 #include <net/ip6_checksum.h> 15 16 #define NETSEC_REG_SOFT_RST 0x104 17 #define NETSEC_REG_COM_INIT 0x120 18 19 #define NETSEC_REG_TOP_STATUS 0x200 20 #define NETSEC_IRQ_RX BIT(1) 21 #define NETSEC_IRQ_TX BIT(0) 22 23 #define NETSEC_REG_TOP_INTEN 0x204 24 #define NETSEC_REG_INTEN_SET 0x234 25 #define NETSEC_REG_INTEN_CLR 0x238 26 27 #define NETSEC_REG_NRM_TX_STATUS 0x400 28 #define NETSEC_REG_NRM_TX_INTEN 0x404 29 #define NETSEC_REG_NRM_TX_INTEN_SET 0x428 30 #define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c 31 #define NRM_TX_ST_NTOWNR BIT(17) 32 #define NRM_TX_ST_TR_ERR BIT(16) 33 #define NRM_TX_ST_TXDONE BIT(15) 34 #define NRM_TX_ST_TMREXP BIT(14) 35 36 #define NETSEC_REG_NRM_RX_STATUS 0x440 37 #define NETSEC_REG_NRM_RX_INTEN 0x444 38 #define NETSEC_REG_NRM_RX_INTEN_SET 0x468 39 #define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c 40 #define NRM_RX_ST_RC_ERR BIT(16) 41 #define NRM_RX_ST_PKTCNT BIT(15) 42 #define NRM_RX_ST_TMREXP BIT(14) 43 44 #define NETSEC_REG_PKT_CMD_BUF 0xd0 45 46 #define NETSEC_REG_CLK_EN 0x100 47 48 #define NETSEC_REG_PKT_CTRL 0x140 49 50 #define NETSEC_REG_DMA_TMR_CTRL 0x20c 51 #define NETSEC_REG_F_TAIKI_MC_VER 0x22c 52 #define NETSEC_REG_F_TAIKI_VER 0x230 53 #define NETSEC_REG_DMA_HM_CTRL 0x214 54 #define NETSEC_REG_DMA_MH_CTRL 0x220 55 #define NETSEC_REG_ADDR_DIS_CORE 0x218 56 #define NETSEC_REG_DMAC_HM_CMD_BUF 0x210 57 #define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c 58 59 #define NETSEC_REG_NRM_TX_PKTCNT 0x410 60 61 #define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414 62 #define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418 63 64 #define NETSEC_REG_NRM_TX_TMR 0x41c 65 66 #define NETSEC_REG_NRM_RX_PKTCNT 0x454 67 #define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458 68 #define NETSEC_REG_NRM_TX_TXINT_TMR 0x420 69 #define NETSEC_REG_NRM_RX_RXINT_TMR 0x460 70 71 #define NETSEC_REG_NRM_RX_TMR 0x45c 72 73 #define NETSEC_REG_NRM_TX_DESC_START_UP 0x434 74 #define NETSEC_REG_NRM_TX_DESC_START_LW 0x408 75 #define NETSEC_REG_NRM_RX_DESC_START_UP 0x474 76 #define NETSEC_REG_NRM_RX_DESC_START_LW 0x448 77 78 #define NETSEC_REG_NRM_TX_CONFIG 0x430 79 #define NETSEC_REG_NRM_RX_CONFIG 0x470 80 81 #define MAC_REG_STATUS 0x1024 82 #define MAC_REG_DATA 0x11c0 83 #define MAC_REG_CMD 0x11c4 84 #define MAC_REG_FLOW_TH 0x11cc 85 #define MAC_REG_INTF_SEL 0x11d4 86 #define MAC_REG_DESC_INIT 0x11fc 87 #define MAC_REG_DESC_SOFT_RST 0x1204 88 #define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500 89 90 #define GMAC_REG_MCR 0x0000 91 #define GMAC_REG_MFFR 0x0004 92 #define GMAC_REG_GAR 0x0010 93 #define GMAC_REG_GDR 0x0014 94 #define GMAC_REG_FCR 0x0018 95 #define GMAC_REG_BMR 0x1000 96 #define GMAC_REG_RDLAR 0x100c 97 #define GMAC_REG_TDLAR 0x1010 98 #define GMAC_REG_OMR 0x1018 99 100 #define MHZ(n) ((n) * 1000 * 1000) 101 102 #define NETSEC_TX_SHIFT_OWN_FIELD 31 103 #define NETSEC_TX_SHIFT_LD_FIELD 30 104 #define NETSEC_TX_SHIFT_DRID_FIELD 24 105 #define NETSEC_TX_SHIFT_PT_FIELD 21 106 #define NETSEC_TX_SHIFT_TDRID_FIELD 16 107 #define NETSEC_TX_SHIFT_CC_FIELD 15 108 #define NETSEC_TX_SHIFT_FS_FIELD 9 109 #define NETSEC_TX_LAST 8 110 #define NETSEC_TX_SHIFT_CO 7 111 #define NETSEC_TX_SHIFT_SO 6 112 #define NETSEC_TX_SHIFT_TRS_FIELD 4 113 114 #define NETSEC_RX_PKT_OWN_FIELD 31 115 #define NETSEC_RX_PKT_LD_FIELD 30 116 #define NETSEC_RX_PKT_SDRID_FIELD 24 117 #define NETSEC_RX_PKT_FR_FIELD 23 118 #define NETSEC_RX_PKT_ER_FIELD 21 119 #define NETSEC_RX_PKT_ERR_FIELD 16 120 #define NETSEC_RX_PKT_TDRID_FIELD 12 121 #define NETSEC_RX_PKT_FS_FIELD 9 122 #define NETSEC_RX_PKT_LS_FIELD 8 123 #define NETSEC_RX_PKT_CO_FIELD 6 124 125 #define NETSEC_RX_PKT_ERR_MASK 3 126 127 #define NETSEC_MAX_TX_PKT_LEN 1518 128 #define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018 129 130 #define NETSEC_RING_GMAC 15 131 #define NETSEC_RING_MAX 2 132 133 #define NETSEC_TCP_SEG_LEN_MAX 1460 134 #define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960 135 136 #define NETSEC_RX_CKSUM_NOTAVAIL 0 137 #define NETSEC_RX_CKSUM_OK 1 138 #define NETSEC_RX_CKSUM_NG 2 139 140 #define NETSEC_TOP_IRQ_REG_CODE_LOAD_END BIT(20) 141 #define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4) 142 143 #define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20) 144 #define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19) 145 146 #define NETSEC_INT_PKTCNT_MAX 2047 147 148 #define NETSEC_FLOW_START_TH_MAX 95 149 #define NETSEC_FLOW_STOP_TH_MAX 95 150 #define NETSEC_FLOW_PAUSE_TIME_MIN 5 151 152 #define NETSEC_CLK_EN_REG_DOM_ALL 0x3f 153 154 #define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28) 155 #define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27) 156 #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3) 157 #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2) 158 #define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1) 159 #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0) 160 161 #define NETSEC_CLK_EN_REG_DOM_G BIT(5) 162 #define NETSEC_CLK_EN_REG_DOM_C BIT(1) 163 #define NETSEC_CLK_EN_REG_DOM_D BIT(0) 164 165 #define NETSEC_COM_INIT_REG_DB BIT(2) 166 #define NETSEC_COM_INIT_REG_CLS BIT(1) 167 #define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \ 168 NETSEC_COM_INIT_REG_DB) 169 170 #define NETSEC_SOFT_RST_REG_RESET 0 171 #define NETSEC_SOFT_RST_REG_RUN BIT(31) 172 173 #define NETSEC_DMA_CTRL_REG_STOP 1 174 #define MH_CTRL__MODE_TRANS BIT(20) 175 176 #define NETSEC_GMAC_CMD_ST_READ 0 177 #define NETSEC_GMAC_CMD_ST_WRITE BIT(28) 178 #define NETSEC_GMAC_CMD_ST_BUSY BIT(31) 179 180 #define NETSEC_GMAC_BMR_REG_COMMON 0x00412080 181 #define NETSEC_GMAC_BMR_REG_RESET 0x00020181 182 #define NETSEC_GMAC_BMR_REG_SWR 0x00000001 183 184 #define NETSEC_GMAC_OMR_REG_ST BIT(13) 185 #define NETSEC_GMAC_OMR_REG_SR BIT(1) 186 187 #define NETSEC_GMAC_MCR_REG_IBN BIT(30) 188 #define NETSEC_GMAC_MCR_REG_CST BIT(25) 189 #define NETSEC_GMAC_MCR_REG_JE BIT(20) 190 #define NETSEC_MCR_PS BIT(15) 191 #define NETSEC_GMAC_MCR_REG_FES BIT(14) 192 #define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c 193 #define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c 194 195 #define NETSEC_FCR_RFE BIT(2) 196 #define NETSEC_FCR_TFE BIT(1) 197 198 #define NETSEC_GMAC_GAR_REG_GW BIT(1) 199 #define NETSEC_GMAC_GAR_REG_GB BIT(0) 200 201 #define NETSEC_GMAC_GAR_REG_SHIFT_PA 11 202 #define NETSEC_GMAC_GAR_REG_SHIFT_GR 6 203 #define GMAC_REG_SHIFT_CR_GAR 2 204 205 #define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2 206 #define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3 207 #define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0 208 #define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1 209 #define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4 210 #define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5 211 212 #define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000 213 #define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000 214 215 #define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000 216 217 #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31) 218 #define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30) 219 #define NETSEC_REG_DESC_TMR_MODE 4 220 #define NETSEC_REG_DESC_ENDIAN 0 221 222 #define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1 223 #define NETSEC_MAC_DESC_INIT_REG_INIT 1 224 225 #define NETSEC_EEPROM_MAC_ADDRESS 0x00 226 #define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08 227 #define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C 228 #define NETSEC_EEPROM_HM_ME_SIZE 0x10 229 #define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14 230 #define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18 231 #define NETSEC_EEPROM_MH_ME_SIZE 0x1C 232 #define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20 233 #define NETSEC_EEPROM_PKT_ME_SIZE 0x24 234 235 #define DESC_NUM 256 236 237 #define NETSEC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 238 #define NETSEC_RX_BUF_SZ 1536 239 240 #define DESC_SZ sizeof(struct netsec_de) 241 242 #define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000) 243 244 enum ring_id { 245 NETSEC_RING_TX = 0, 246 NETSEC_RING_RX 247 }; 248 249 struct netsec_desc { 250 struct sk_buff *skb; 251 dma_addr_t dma_addr; 252 void *addr; 253 u16 len; 254 }; 255 256 struct netsec_desc_ring { 257 dma_addr_t desc_dma; 258 struct netsec_desc *desc; 259 void *vaddr; 260 u16 pkt_cnt; 261 u16 head, tail; 262 }; 263 264 struct netsec_priv { 265 struct netsec_desc_ring desc_ring[NETSEC_RING_MAX]; 266 struct ethtool_coalesce et_coalesce; 267 spinlock_t reglock; /* protect reg access */ 268 struct napi_struct napi; 269 phy_interface_t phy_interface; 270 struct net_device *ndev; 271 struct device_node *phy_np; 272 struct phy_device *phydev; 273 struct mii_bus *mii_bus; 274 void __iomem *ioaddr; 275 void __iomem *eeprom_base; 276 struct device *dev; 277 struct clk *clk; 278 u32 msg_enable; 279 u32 freq; 280 u32 phy_addr; 281 bool rx_cksum_offload_flag; 282 }; 283 284 struct netsec_de { /* Netsec Descriptor layout */ 285 u32 attr; 286 u32 data_buf_addr_up; 287 u32 data_buf_addr_lw; 288 u32 buf_len_info; 289 }; 290 291 struct netsec_tx_pkt_ctrl { 292 u16 tcp_seg_len; 293 bool tcp_seg_offload_flag; 294 bool cksum_offload_flag; 295 }; 296 297 struct netsec_rx_pkt_info { 298 int rx_cksum_result; 299 int err_code; 300 bool err_flag; 301 }; 302 303 static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val) 304 { 305 writel(val, priv->ioaddr + reg_addr); 306 } 307 308 static u32 netsec_read(struct netsec_priv *priv, u32 reg_addr) 309 { 310 return readl(priv->ioaddr + reg_addr); 311 } 312 313 /************* MDIO BUS OPS FOLLOW *************/ 314 315 #define TIMEOUT_SPINS_MAC 1000 316 #define TIMEOUT_SECONDARY_MS_MAC 100 317 318 static u32 netsec_clk_type(u32 freq) 319 { 320 if (freq < MHZ(35)) 321 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ; 322 if (freq < MHZ(60)) 323 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ; 324 if (freq < MHZ(100)) 325 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ; 326 if (freq < MHZ(150)) 327 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ; 328 if (freq < MHZ(250)) 329 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ; 330 331 return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ; 332 } 333 334 static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask) 335 { 336 u32 timeout = TIMEOUT_SPINS_MAC; 337 338 while (--timeout && netsec_read(priv, addr) & mask) 339 cpu_relax(); 340 if (timeout) 341 return 0; 342 343 timeout = TIMEOUT_SECONDARY_MS_MAC; 344 while (--timeout && netsec_read(priv, addr) & mask) 345 usleep_range(1000, 2000); 346 347 if (timeout) 348 return 0; 349 350 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 351 352 return -ETIMEDOUT; 353 } 354 355 static int netsec_mac_write(struct netsec_priv *priv, u32 addr, u32 value) 356 { 357 netsec_write(priv, MAC_REG_DATA, value); 358 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE); 359 return netsec_wait_while_busy(priv, 360 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 361 } 362 363 static int netsec_mac_read(struct netsec_priv *priv, u32 addr, u32 *read) 364 { 365 int ret; 366 367 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ); 368 ret = netsec_wait_while_busy(priv, 369 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 370 if (ret) 371 return ret; 372 373 *read = netsec_read(priv, MAC_REG_DATA); 374 375 return 0; 376 } 377 378 static int netsec_mac_wait_while_busy(struct netsec_priv *priv, 379 u32 addr, u32 mask) 380 { 381 u32 timeout = TIMEOUT_SPINS_MAC; 382 int ret, data; 383 384 do { 385 ret = netsec_mac_read(priv, addr, &data); 386 if (ret) 387 break; 388 cpu_relax(); 389 } while (--timeout && (data & mask)); 390 391 if (timeout) 392 return 0; 393 394 timeout = TIMEOUT_SECONDARY_MS_MAC; 395 do { 396 usleep_range(1000, 2000); 397 398 ret = netsec_mac_read(priv, addr, &data); 399 if (ret) 400 break; 401 cpu_relax(); 402 } while (--timeout && (data & mask)); 403 404 if (timeout && !ret) 405 return 0; 406 407 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 408 409 return -ETIMEDOUT; 410 } 411 412 static int netsec_mac_update_to_phy_state(struct netsec_priv *priv) 413 { 414 struct phy_device *phydev = priv->ndev->phydev; 415 u32 value = 0; 416 417 value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON : 418 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON; 419 420 if (phydev->speed != SPEED_1000) 421 value |= NETSEC_MCR_PS; 422 423 if (priv->phy_interface != PHY_INTERFACE_MODE_GMII && 424 phydev->speed == SPEED_100) 425 value |= NETSEC_GMAC_MCR_REG_FES; 426 427 value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE; 428 429 if (phy_interface_mode_is_rgmii(priv->phy_interface)) 430 value |= NETSEC_GMAC_MCR_REG_IBN; 431 432 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 433 return -ETIMEDOUT; 434 435 return 0; 436 } 437 438 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr); 439 440 static int netsec_phy_write(struct mii_bus *bus, 441 int phy_addr, int reg, u16 val) 442 { 443 int status; 444 struct netsec_priv *priv = bus->priv; 445 446 if (netsec_mac_write(priv, GMAC_REG_GDR, val)) 447 return -ETIMEDOUT; 448 if (netsec_mac_write(priv, GMAC_REG_GAR, 449 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 450 reg << NETSEC_GMAC_GAR_REG_SHIFT_GR | 451 NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB | 452 (netsec_clk_type(priv->freq) << 453 GMAC_REG_SHIFT_CR_GAR))) 454 return -ETIMEDOUT; 455 456 status = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 457 NETSEC_GMAC_GAR_REG_GB); 458 459 /* Developerbox implements RTL8211E PHY and there is 460 * a compatibility problem with F_GMAC4. 461 * RTL8211E expects MDC clock must be kept toggling for several 462 * clock cycle with MDIO high before entering the IDLE state. 463 * To meet this requirement, netsec driver needs to issue dummy 464 * read(e.g. read PHYID1(offset 0x2) register) right after write. 465 */ 466 netsec_phy_read(bus, phy_addr, MII_PHYSID1); 467 468 return status; 469 } 470 471 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr) 472 { 473 struct netsec_priv *priv = bus->priv; 474 u32 data; 475 int ret; 476 477 if (netsec_mac_write(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB | 478 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 479 reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR | 480 (netsec_clk_type(priv->freq) << 481 GMAC_REG_SHIFT_CR_GAR))) 482 return -ETIMEDOUT; 483 484 ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 485 NETSEC_GMAC_GAR_REG_GB); 486 if (ret) 487 return ret; 488 489 ret = netsec_mac_read(priv, GMAC_REG_GDR, &data); 490 if (ret) 491 return ret; 492 493 return data; 494 } 495 496 /************* ETHTOOL_OPS FOLLOW *************/ 497 498 static void netsec_et_get_drvinfo(struct net_device *net_device, 499 struct ethtool_drvinfo *info) 500 { 501 strlcpy(info->driver, "netsec", sizeof(info->driver)); 502 strlcpy(info->bus_info, dev_name(net_device->dev.parent), 503 sizeof(info->bus_info)); 504 } 505 506 static int netsec_et_get_coalesce(struct net_device *net_device, 507 struct ethtool_coalesce *et_coalesce) 508 { 509 struct netsec_priv *priv = netdev_priv(net_device); 510 511 *et_coalesce = priv->et_coalesce; 512 513 return 0; 514 } 515 516 static int netsec_et_set_coalesce(struct net_device *net_device, 517 struct ethtool_coalesce *et_coalesce) 518 { 519 struct netsec_priv *priv = netdev_priv(net_device); 520 521 priv->et_coalesce = *et_coalesce; 522 523 if (priv->et_coalesce.tx_coalesce_usecs < 50) 524 priv->et_coalesce.tx_coalesce_usecs = 50; 525 if (priv->et_coalesce.tx_max_coalesced_frames < 1) 526 priv->et_coalesce.tx_max_coalesced_frames = 1; 527 528 netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT, 529 priv->et_coalesce.tx_max_coalesced_frames); 530 netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR, 531 priv->et_coalesce.tx_coalesce_usecs); 532 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE); 533 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP); 534 535 if (priv->et_coalesce.rx_coalesce_usecs < 50) 536 priv->et_coalesce.rx_coalesce_usecs = 50; 537 if (priv->et_coalesce.rx_max_coalesced_frames < 1) 538 priv->et_coalesce.rx_max_coalesced_frames = 1; 539 540 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT, 541 priv->et_coalesce.rx_max_coalesced_frames); 542 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR, 543 priv->et_coalesce.rx_coalesce_usecs); 544 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT); 545 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP); 546 547 return 0; 548 } 549 550 static u32 netsec_et_get_msglevel(struct net_device *dev) 551 { 552 struct netsec_priv *priv = netdev_priv(dev); 553 554 return priv->msg_enable; 555 } 556 557 static void netsec_et_set_msglevel(struct net_device *dev, u32 datum) 558 { 559 struct netsec_priv *priv = netdev_priv(dev); 560 561 priv->msg_enable = datum; 562 } 563 564 static const struct ethtool_ops netsec_ethtool_ops = { 565 .get_drvinfo = netsec_et_get_drvinfo, 566 .get_link_ksettings = phy_ethtool_get_link_ksettings, 567 .set_link_ksettings = phy_ethtool_set_link_ksettings, 568 .get_link = ethtool_op_get_link, 569 .get_coalesce = netsec_et_get_coalesce, 570 .set_coalesce = netsec_et_set_coalesce, 571 .get_msglevel = netsec_et_get_msglevel, 572 .set_msglevel = netsec_et_set_msglevel, 573 }; 574 575 /************* NETDEV_OPS FOLLOW *************/ 576 577 578 static void netsec_set_rx_de(struct netsec_priv *priv, 579 struct netsec_desc_ring *dring, u16 idx, 580 const struct netsec_desc *desc) 581 { 582 struct netsec_de *de = dring->vaddr + DESC_SZ * idx; 583 u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) | 584 (1 << NETSEC_RX_PKT_FS_FIELD) | 585 (1 << NETSEC_RX_PKT_LS_FIELD); 586 587 if (idx == DESC_NUM - 1) 588 attr |= (1 << NETSEC_RX_PKT_LD_FIELD); 589 590 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 591 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 592 de->buf_len_info = desc->len; 593 de->attr = attr; 594 dma_wmb(); 595 596 dring->desc[idx].dma_addr = desc->dma_addr; 597 dring->desc[idx].addr = desc->addr; 598 dring->desc[idx].len = desc->len; 599 } 600 601 static int netsec_clean_tx_dring(struct netsec_priv *priv, int budget) 602 { 603 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 604 unsigned int pkts, bytes; 605 606 dring->pkt_cnt += netsec_read(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT); 607 608 if (dring->pkt_cnt < budget) 609 budget = dring->pkt_cnt; 610 611 pkts = 0; 612 bytes = 0; 613 614 while (pkts < budget) { 615 struct netsec_desc *desc; 616 struct netsec_de *entry; 617 int tail, eop; 618 619 tail = dring->tail; 620 621 /* move tail ahead */ 622 dring->tail = (tail + 1) % DESC_NUM; 623 624 desc = &dring->desc[tail]; 625 entry = dring->vaddr + DESC_SZ * tail; 626 627 eop = (entry->attr >> NETSEC_TX_LAST) & 1; 628 629 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 630 DMA_TO_DEVICE); 631 if (eop) { 632 pkts++; 633 bytes += desc->skb->len; 634 dev_kfree_skb(desc->skb); 635 } 636 *desc = (struct netsec_desc){}; 637 } 638 dring->pkt_cnt -= budget; 639 640 priv->ndev->stats.tx_packets += budget; 641 priv->ndev->stats.tx_bytes += bytes; 642 643 netdev_completed_queue(priv->ndev, budget, bytes); 644 645 return budget; 646 } 647 648 static int netsec_process_tx(struct netsec_priv *priv, int budget) 649 { 650 struct net_device *ndev = priv->ndev; 651 int new, done = 0; 652 653 do { 654 new = netsec_clean_tx_dring(priv, budget); 655 done += new; 656 budget -= new; 657 } while (new); 658 659 if (done && netif_queue_stopped(ndev)) 660 netif_wake_queue(ndev); 661 662 return done; 663 } 664 665 static void *netsec_alloc_rx_data(struct netsec_priv *priv, 666 dma_addr_t *dma_handle, u16 *desc_len) 667 { 668 size_t total_len = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 669 size_t payload_len = NETSEC_RX_BUF_SZ; 670 dma_addr_t mapping; 671 void *buf; 672 673 total_len += SKB_DATA_ALIGN(payload_len + NETSEC_SKB_PAD); 674 675 buf = napi_alloc_frag(total_len); 676 if (!buf) 677 return NULL; 678 679 mapping = dma_map_single(priv->dev, buf + NETSEC_SKB_PAD, payload_len, 680 DMA_FROM_DEVICE); 681 if (unlikely(dma_mapping_error(priv->dev, mapping))) 682 goto err_out; 683 684 *dma_handle = mapping; 685 *desc_len = payload_len; 686 687 return buf; 688 689 err_out: 690 skb_free_frag(buf); 691 return NULL; 692 } 693 694 static void netsec_rx_fill(struct netsec_priv *priv, u16 from, u16 num) 695 { 696 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 697 u16 idx = from; 698 699 while (num) { 700 netsec_set_rx_de(priv, dring, idx, &dring->desc[idx]); 701 idx++; 702 if (idx >= DESC_NUM) 703 idx = 0; 704 num--; 705 } 706 } 707 708 static int netsec_process_rx(struct netsec_priv *priv, int budget) 709 { 710 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 711 struct net_device *ndev = priv->ndev; 712 struct netsec_rx_pkt_info rx_info; 713 struct sk_buff *skb; 714 int done = 0; 715 716 while (done < budget) { 717 u16 idx = dring->tail; 718 struct netsec_de *de = dring->vaddr + (DESC_SZ * idx); 719 struct netsec_desc *desc = &dring->desc[idx]; 720 u16 pkt_len, desc_len; 721 dma_addr_t dma_handle; 722 void *buf_addr; 723 u32 truesize; 724 725 if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD)) { 726 /* reading the register clears the irq */ 727 netsec_read(priv, NETSEC_REG_NRM_RX_PKTCNT); 728 break; 729 } 730 731 /* This barrier is needed to keep us from reading 732 * any other fields out of the netsec_de until we have 733 * verified the descriptor has been written back 734 */ 735 dma_rmb(); 736 done++; 737 738 pkt_len = de->buf_len_info >> 16; 739 rx_info.err_code = (de->attr >> NETSEC_RX_PKT_ERR_FIELD) & 740 NETSEC_RX_PKT_ERR_MASK; 741 rx_info.err_flag = (de->attr >> NETSEC_RX_PKT_ER_FIELD) & 1; 742 if (rx_info.err_flag) { 743 netif_err(priv, drv, priv->ndev, 744 "%s: rx fail err(%d)\n", __func__, 745 rx_info.err_code); 746 ndev->stats.rx_dropped++; 747 dring->tail = (dring->tail + 1) % DESC_NUM; 748 /* reuse buffer page frag */ 749 netsec_rx_fill(priv, idx, 1); 750 continue; 751 } 752 rx_info.rx_cksum_result = 753 (de->attr >> NETSEC_RX_PKT_CO_FIELD) & 3; 754 755 /* allocate a fresh buffer and map it to the hardware. 756 * This will eventually replace the old buffer in the hardware 757 */ 758 buf_addr = netsec_alloc_rx_data(priv, &dma_handle, &desc_len); 759 if (unlikely(!buf_addr)) 760 break; 761 762 dma_sync_single_for_cpu(priv->dev, desc->dma_addr, pkt_len, 763 DMA_FROM_DEVICE); 764 prefetch(desc->addr); 765 766 truesize = SKB_DATA_ALIGN(desc->len + NETSEC_SKB_PAD) + 767 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 768 skb = build_skb(desc->addr, truesize); 769 if (unlikely(!skb)) { 770 /* free the newly allocated buffer, we are not going to 771 * use it 772 */ 773 dma_unmap_single(priv->dev, dma_handle, desc_len, 774 DMA_FROM_DEVICE); 775 skb_free_frag(buf_addr); 776 netif_err(priv, drv, priv->ndev, 777 "rx failed to build skb\n"); 778 break; 779 } 780 dma_unmap_single_attrs(priv->dev, desc->dma_addr, desc->len, 781 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 782 783 /* Update the descriptor with the new buffer we allocated */ 784 desc->len = desc_len; 785 desc->dma_addr = dma_handle; 786 desc->addr = buf_addr; 787 788 skb_reserve(skb, NETSEC_SKB_PAD); 789 skb_put(skb, pkt_len); 790 skb->protocol = eth_type_trans(skb, priv->ndev); 791 792 if (priv->rx_cksum_offload_flag && 793 rx_info.rx_cksum_result == NETSEC_RX_CKSUM_OK) 794 skb->ip_summed = CHECKSUM_UNNECESSARY; 795 796 if (napi_gro_receive(&priv->napi, skb) != GRO_DROP) { 797 ndev->stats.rx_packets++; 798 ndev->stats.rx_bytes += pkt_len; 799 } 800 801 netsec_rx_fill(priv, idx, 1); 802 dring->tail = (dring->tail + 1) % DESC_NUM; 803 } 804 805 return done; 806 } 807 808 static int netsec_napi_poll(struct napi_struct *napi, int budget) 809 { 810 struct netsec_priv *priv; 811 int tx, rx, done, todo; 812 813 priv = container_of(napi, struct netsec_priv, napi); 814 815 todo = budget; 816 do { 817 if (!todo) 818 break; 819 820 tx = netsec_process_tx(priv, todo); 821 todo -= tx; 822 823 if (!todo) 824 break; 825 826 rx = netsec_process_rx(priv, todo); 827 todo -= rx; 828 } while (rx || tx); 829 830 done = budget - todo; 831 832 if (done < budget && napi_complete_done(napi, done)) { 833 unsigned long flags; 834 835 spin_lock_irqsave(&priv->reglock, flags); 836 netsec_write(priv, NETSEC_REG_INTEN_SET, 837 NETSEC_IRQ_RX | NETSEC_IRQ_TX); 838 spin_unlock_irqrestore(&priv->reglock, flags); 839 } 840 841 return done; 842 } 843 844 static void netsec_set_tx_de(struct netsec_priv *priv, 845 struct netsec_desc_ring *dring, 846 const struct netsec_tx_pkt_ctrl *tx_ctrl, 847 const struct netsec_desc *desc, 848 struct sk_buff *skb) 849 { 850 int idx = dring->head; 851 struct netsec_de *de; 852 u32 attr; 853 854 de = dring->vaddr + (DESC_SZ * idx); 855 856 attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) | 857 (1 << NETSEC_TX_SHIFT_PT_FIELD) | 858 (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) | 859 (1 << NETSEC_TX_SHIFT_FS_FIELD) | 860 (1 << NETSEC_TX_LAST) | 861 (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) | 862 (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) | 863 (1 << NETSEC_TX_SHIFT_TRS_FIELD); 864 if (idx == DESC_NUM - 1) 865 attr |= (1 << NETSEC_TX_SHIFT_LD_FIELD); 866 867 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 868 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 869 de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len; 870 de->attr = attr; 871 dma_wmb(); 872 873 dring->desc[idx] = *desc; 874 dring->desc[idx].skb = skb; 875 876 /* move head ahead */ 877 dring->head = (dring->head + 1) % DESC_NUM; 878 } 879 880 static netdev_tx_t netsec_netdev_start_xmit(struct sk_buff *skb, 881 struct net_device *ndev) 882 { 883 struct netsec_priv *priv = netdev_priv(ndev); 884 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 885 struct netsec_tx_pkt_ctrl tx_ctrl = {}; 886 struct netsec_desc tx_desc; 887 u16 tso_seg_len = 0; 888 int filled; 889 890 /* differentiate between full/emtpy ring */ 891 if (dring->head >= dring->tail) 892 filled = dring->head - dring->tail; 893 else 894 filled = dring->head + DESC_NUM - dring->tail; 895 896 if (DESC_NUM - filled < 2) { /* if less than 2 available */ 897 netif_err(priv, drv, priv->ndev, "%s: TxQFull!\n", __func__); 898 netif_stop_queue(priv->ndev); 899 dma_wmb(); 900 return NETDEV_TX_BUSY; 901 } 902 903 if (skb->ip_summed == CHECKSUM_PARTIAL) 904 tx_ctrl.cksum_offload_flag = true; 905 906 if (skb_is_gso(skb)) 907 tso_seg_len = skb_shinfo(skb)->gso_size; 908 909 if (tso_seg_len > 0) { 910 if (skb->protocol == htons(ETH_P_IP)) { 911 ip_hdr(skb)->tot_len = 0; 912 tcp_hdr(skb)->check = 913 ~tcp_v4_check(0, ip_hdr(skb)->saddr, 914 ip_hdr(skb)->daddr, 0); 915 } else { 916 ipv6_hdr(skb)->payload_len = 0; 917 tcp_hdr(skb)->check = 918 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 919 &ipv6_hdr(skb)->daddr, 920 0, IPPROTO_TCP, 0); 921 } 922 923 tx_ctrl.tcp_seg_offload_flag = true; 924 tx_ctrl.tcp_seg_len = tso_seg_len; 925 } 926 927 tx_desc.dma_addr = dma_map_single(priv->dev, skb->data, 928 skb_headlen(skb), DMA_TO_DEVICE); 929 if (dma_mapping_error(priv->dev, tx_desc.dma_addr)) { 930 netif_err(priv, drv, priv->ndev, 931 "%s: DMA mapping failed\n", __func__); 932 ndev->stats.tx_dropped++; 933 dev_kfree_skb_any(skb); 934 return NETDEV_TX_OK; 935 } 936 tx_desc.addr = skb->data; 937 tx_desc.len = skb_headlen(skb); 938 939 skb_tx_timestamp(skb); 940 netdev_sent_queue(priv->ndev, skb->len); 941 942 netsec_set_tx_de(priv, dring, &tx_ctrl, &tx_desc, skb); 943 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */ 944 945 return NETDEV_TX_OK; 946 } 947 948 static void netsec_uninit_pkt_dring(struct netsec_priv *priv, int id) 949 { 950 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 951 struct netsec_desc *desc; 952 u16 idx; 953 954 if (!dring->vaddr || !dring->desc) 955 return; 956 957 for (idx = 0; idx < DESC_NUM; idx++) { 958 desc = &dring->desc[idx]; 959 if (!desc->addr) 960 continue; 961 962 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 963 id == NETSEC_RING_RX ? DMA_FROM_DEVICE : 964 DMA_TO_DEVICE); 965 if (id == NETSEC_RING_RX) 966 skb_free_frag(desc->addr); 967 else if (id == NETSEC_RING_TX) 968 dev_kfree_skb(desc->skb); 969 } 970 971 memset(dring->desc, 0, sizeof(struct netsec_desc) * DESC_NUM); 972 memset(dring->vaddr, 0, DESC_SZ * DESC_NUM); 973 974 dring->head = 0; 975 dring->tail = 0; 976 dring->pkt_cnt = 0; 977 978 if (id == NETSEC_RING_TX) 979 netdev_reset_queue(priv->ndev); 980 } 981 982 static void netsec_free_dring(struct netsec_priv *priv, int id) 983 { 984 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 985 986 if (dring->vaddr) { 987 dma_free_coherent(priv->dev, DESC_SZ * DESC_NUM, 988 dring->vaddr, dring->desc_dma); 989 dring->vaddr = NULL; 990 } 991 992 kfree(dring->desc); 993 dring->desc = NULL; 994 } 995 996 static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id) 997 { 998 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 999 1000 dring->vaddr = dma_zalloc_coherent(priv->dev, DESC_SZ * DESC_NUM, 1001 &dring->desc_dma, GFP_KERNEL); 1002 if (!dring->vaddr) 1003 goto err; 1004 1005 dring->desc = kcalloc(DESC_NUM, sizeof(*dring->desc), GFP_KERNEL); 1006 if (!dring->desc) 1007 goto err; 1008 1009 return 0; 1010 err: 1011 netsec_free_dring(priv, id); 1012 1013 return -ENOMEM; 1014 } 1015 1016 static int netsec_setup_rx_dring(struct netsec_priv *priv) 1017 { 1018 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 1019 int i; 1020 1021 for (i = 0; i < DESC_NUM; i++) { 1022 struct netsec_desc *desc = &dring->desc[i]; 1023 dma_addr_t dma_handle; 1024 void *buf; 1025 u16 len; 1026 1027 buf = netsec_alloc_rx_data(priv, &dma_handle, &len); 1028 if (!buf) { 1029 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1030 goto err_out; 1031 } 1032 desc->dma_addr = dma_handle; 1033 desc->addr = buf; 1034 desc->len = len; 1035 } 1036 1037 netsec_rx_fill(priv, 0, DESC_NUM); 1038 1039 return 0; 1040 1041 err_out: 1042 return -ENOMEM; 1043 } 1044 1045 static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg, 1046 u32 addr_h, u32 addr_l, u32 size) 1047 { 1048 u64 base = (u64)addr_h << 32 | addr_l; 1049 void __iomem *ucode; 1050 u32 i; 1051 1052 ucode = ioremap(base, size * sizeof(u32)); 1053 if (!ucode) 1054 return -ENOMEM; 1055 1056 for (i = 0; i < size; i++) 1057 netsec_write(priv, reg, readl(ucode + i * 4)); 1058 1059 iounmap(ucode); 1060 return 0; 1061 } 1062 1063 static int netsec_netdev_load_microcode(struct netsec_priv *priv) 1064 { 1065 u32 addr_h, addr_l, size; 1066 int err; 1067 1068 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_H); 1069 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_L); 1070 size = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_SIZE); 1071 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF, 1072 addr_h, addr_l, size); 1073 if (err) 1074 return err; 1075 1076 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_H); 1077 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_L); 1078 size = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_SIZE); 1079 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF, 1080 addr_h, addr_l, size); 1081 if (err) 1082 return err; 1083 1084 addr_h = 0; 1085 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_ADDRESS); 1086 size = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_SIZE); 1087 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF, 1088 addr_h, addr_l, size); 1089 if (err) 1090 return err; 1091 1092 return 0; 1093 } 1094 1095 static int netsec_reset_hardware(struct netsec_priv *priv, 1096 bool load_ucode) 1097 { 1098 u32 value; 1099 int err; 1100 1101 /* stop DMA engines */ 1102 if (!netsec_read(priv, NETSEC_REG_ADDR_DIS_CORE)) { 1103 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL, 1104 NETSEC_DMA_CTRL_REG_STOP); 1105 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, 1106 NETSEC_DMA_CTRL_REG_STOP); 1107 1108 while (netsec_read(priv, NETSEC_REG_DMA_HM_CTRL) & 1109 NETSEC_DMA_CTRL_REG_STOP) 1110 cpu_relax(); 1111 1112 while (netsec_read(priv, NETSEC_REG_DMA_MH_CTRL) & 1113 NETSEC_DMA_CTRL_REG_STOP) 1114 cpu_relax(); 1115 } 1116 1117 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET); 1118 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN); 1119 netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL); 1120 1121 while (netsec_read(priv, NETSEC_REG_COM_INIT) != 0) 1122 cpu_relax(); 1123 1124 /* set desc_start addr */ 1125 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP, 1126 upper_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1127 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW, 1128 lower_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1129 1130 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP, 1131 upper_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1132 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW, 1133 lower_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1134 1135 /* set normal tx dring ring config */ 1136 netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG, 1137 1 << NETSEC_REG_DESC_ENDIAN); 1138 netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG, 1139 1 << NETSEC_REG_DESC_ENDIAN); 1140 1141 if (load_ucode) { 1142 err = netsec_netdev_load_microcode(priv); 1143 if (err) { 1144 netif_err(priv, probe, priv->ndev, 1145 "%s: failed to load microcode (%d)\n", 1146 __func__, err); 1147 return err; 1148 } 1149 } 1150 1151 /* start DMA engines */ 1152 netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1); 1153 netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0); 1154 1155 usleep_range(1000, 2000); 1156 1157 if (!(netsec_read(priv, NETSEC_REG_TOP_STATUS) & 1158 NETSEC_TOP_IRQ_REG_CODE_LOAD_END)) { 1159 netif_err(priv, probe, priv->ndev, 1160 "microengine start failed\n"); 1161 return -ENXIO; 1162 } 1163 netsec_write(priv, NETSEC_REG_TOP_STATUS, 1164 NETSEC_TOP_IRQ_REG_CODE_LOAD_END); 1165 1166 value = NETSEC_PKT_CTRL_REG_MODE_NRM; 1167 if (priv->ndev->mtu > ETH_DATA_LEN) 1168 value |= NETSEC_PKT_CTRL_REG_EN_JUMBO; 1169 1170 /* change to normal mode */ 1171 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS); 1172 netsec_write(priv, NETSEC_REG_PKT_CTRL, value); 1173 1174 while ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) & 1175 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) 1176 cpu_relax(); 1177 1178 /* clear any pending EMPTY/ERR irq status */ 1179 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0); 1180 1181 /* Disable TX & RX intr */ 1182 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1183 1184 return 0; 1185 } 1186 1187 static int netsec_start_gmac(struct netsec_priv *priv) 1188 { 1189 struct phy_device *phydev = priv->ndev->phydev; 1190 u32 value = 0; 1191 int ret; 1192 1193 if (phydev->speed != SPEED_1000) 1194 value = (NETSEC_GMAC_MCR_REG_CST | 1195 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON); 1196 1197 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 1198 return -ETIMEDOUT; 1199 if (netsec_mac_write(priv, GMAC_REG_BMR, 1200 NETSEC_GMAC_BMR_REG_RESET)) 1201 return -ETIMEDOUT; 1202 1203 /* Wait soft reset */ 1204 usleep_range(1000, 5000); 1205 1206 ret = netsec_mac_read(priv, GMAC_REG_BMR, &value); 1207 if (ret) 1208 return ret; 1209 if (value & NETSEC_GMAC_BMR_REG_SWR) 1210 return -EAGAIN; 1211 1212 netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1); 1213 if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1)) 1214 return -ETIMEDOUT; 1215 1216 netsec_write(priv, MAC_REG_DESC_INIT, 1); 1217 if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1)) 1218 return -ETIMEDOUT; 1219 1220 if (netsec_mac_write(priv, GMAC_REG_BMR, 1221 NETSEC_GMAC_BMR_REG_COMMON)) 1222 return -ETIMEDOUT; 1223 if (netsec_mac_write(priv, GMAC_REG_RDLAR, 1224 NETSEC_GMAC_RDLAR_REG_COMMON)) 1225 return -ETIMEDOUT; 1226 if (netsec_mac_write(priv, GMAC_REG_TDLAR, 1227 NETSEC_GMAC_TDLAR_REG_COMMON)) 1228 return -ETIMEDOUT; 1229 if (netsec_mac_write(priv, GMAC_REG_MFFR, 0x80000001)) 1230 return -ETIMEDOUT; 1231 1232 ret = netsec_mac_update_to_phy_state(priv); 1233 if (ret) 1234 return ret; 1235 1236 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1237 if (ret) 1238 return ret; 1239 1240 value |= NETSEC_GMAC_OMR_REG_SR; 1241 value |= NETSEC_GMAC_OMR_REG_ST; 1242 1243 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1244 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1245 1246 netsec_et_set_coalesce(priv->ndev, &priv->et_coalesce); 1247 1248 if (netsec_mac_write(priv, GMAC_REG_OMR, value)) 1249 return -ETIMEDOUT; 1250 1251 return 0; 1252 } 1253 1254 static int netsec_stop_gmac(struct netsec_priv *priv) 1255 { 1256 u32 value; 1257 int ret; 1258 1259 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1260 if (ret) 1261 return ret; 1262 value &= ~NETSEC_GMAC_OMR_REG_SR; 1263 value &= ~NETSEC_GMAC_OMR_REG_ST; 1264 1265 /* disable all interrupts */ 1266 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1267 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1268 1269 return netsec_mac_write(priv, GMAC_REG_OMR, value); 1270 } 1271 1272 static void netsec_phy_adjust_link(struct net_device *ndev) 1273 { 1274 struct netsec_priv *priv = netdev_priv(ndev); 1275 1276 if (ndev->phydev->link) 1277 netsec_start_gmac(priv); 1278 else 1279 netsec_stop_gmac(priv); 1280 1281 phy_print_status(ndev->phydev); 1282 } 1283 1284 static irqreturn_t netsec_irq_handler(int irq, void *dev_id) 1285 { 1286 struct netsec_priv *priv = dev_id; 1287 u32 val, status = netsec_read(priv, NETSEC_REG_TOP_STATUS); 1288 unsigned long flags; 1289 1290 /* Disable interrupts */ 1291 if (status & NETSEC_IRQ_TX) { 1292 val = netsec_read(priv, NETSEC_REG_NRM_TX_STATUS); 1293 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val); 1294 } 1295 if (status & NETSEC_IRQ_RX) { 1296 val = netsec_read(priv, NETSEC_REG_NRM_RX_STATUS); 1297 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val); 1298 } 1299 1300 spin_lock_irqsave(&priv->reglock, flags); 1301 netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1302 spin_unlock_irqrestore(&priv->reglock, flags); 1303 1304 napi_schedule(&priv->napi); 1305 1306 return IRQ_HANDLED; 1307 } 1308 1309 static int netsec_netdev_open(struct net_device *ndev) 1310 { 1311 struct netsec_priv *priv = netdev_priv(ndev); 1312 int ret; 1313 1314 pm_runtime_get_sync(priv->dev); 1315 1316 ret = netsec_setup_rx_dring(priv); 1317 if (ret) { 1318 netif_err(priv, probe, priv->ndev, 1319 "%s: fail setup ring\n", __func__); 1320 goto err1; 1321 } 1322 1323 ret = request_irq(priv->ndev->irq, netsec_irq_handler, 1324 IRQF_SHARED, "netsec", priv); 1325 if (ret) { 1326 netif_err(priv, drv, priv->ndev, "request_irq failed\n"); 1327 goto err2; 1328 } 1329 1330 if (dev_of_node(priv->dev)) { 1331 if (!of_phy_connect(priv->ndev, priv->phy_np, 1332 netsec_phy_adjust_link, 0, 1333 priv->phy_interface)) { 1334 netif_err(priv, link, priv->ndev, "missing PHY\n"); 1335 ret = -ENODEV; 1336 goto err3; 1337 } 1338 } else { 1339 ret = phy_connect_direct(priv->ndev, priv->phydev, 1340 netsec_phy_adjust_link, 1341 priv->phy_interface); 1342 if (ret) { 1343 netif_err(priv, link, priv->ndev, 1344 "phy_connect_direct() failed (%d)\n", ret); 1345 goto err3; 1346 } 1347 } 1348 1349 phy_start(ndev->phydev); 1350 1351 netsec_start_gmac(priv); 1352 napi_enable(&priv->napi); 1353 netif_start_queue(ndev); 1354 1355 /* Enable TX+RX intr. */ 1356 netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1357 1358 return 0; 1359 err3: 1360 free_irq(priv->ndev->irq, priv); 1361 err2: 1362 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1363 err1: 1364 pm_runtime_put_sync(priv->dev); 1365 return ret; 1366 } 1367 1368 static int netsec_netdev_stop(struct net_device *ndev) 1369 { 1370 int ret; 1371 struct netsec_priv *priv = netdev_priv(ndev); 1372 1373 netif_stop_queue(priv->ndev); 1374 dma_wmb(); 1375 1376 napi_disable(&priv->napi); 1377 1378 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1379 netsec_stop_gmac(priv); 1380 1381 free_irq(priv->ndev->irq, priv); 1382 1383 netsec_uninit_pkt_dring(priv, NETSEC_RING_TX); 1384 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1385 1386 phy_stop(ndev->phydev); 1387 phy_disconnect(ndev->phydev); 1388 1389 ret = netsec_reset_hardware(priv, false); 1390 1391 pm_runtime_put_sync(priv->dev); 1392 1393 return ret; 1394 } 1395 1396 static int netsec_netdev_init(struct net_device *ndev) 1397 { 1398 struct netsec_priv *priv = netdev_priv(ndev); 1399 int ret; 1400 u16 data; 1401 1402 BUILD_BUG_ON_NOT_POWER_OF_2(DESC_NUM); 1403 1404 ret = netsec_alloc_dring(priv, NETSEC_RING_TX); 1405 if (ret) 1406 return ret; 1407 1408 ret = netsec_alloc_dring(priv, NETSEC_RING_RX); 1409 if (ret) 1410 goto err1; 1411 1412 /* set phy power down */ 1413 data = netsec_phy_read(priv->mii_bus, priv->phy_addr, MII_BMCR) | 1414 BMCR_PDOWN; 1415 netsec_phy_write(priv->mii_bus, priv->phy_addr, MII_BMCR, data); 1416 1417 ret = netsec_reset_hardware(priv, true); 1418 if (ret) 1419 goto err2; 1420 1421 return 0; 1422 err2: 1423 netsec_free_dring(priv, NETSEC_RING_RX); 1424 err1: 1425 netsec_free_dring(priv, NETSEC_RING_TX); 1426 return ret; 1427 } 1428 1429 static void netsec_netdev_uninit(struct net_device *ndev) 1430 { 1431 struct netsec_priv *priv = netdev_priv(ndev); 1432 1433 netsec_free_dring(priv, NETSEC_RING_RX); 1434 netsec_free_dring(priv, NETSEC_RING_TX); 1435 } 1436 1437 static int netsec_netdev_set_features(struct net_device *ndev, 1438 netdev_features_t features) 1439 { 1440 struct netsec_priv *priv = netdev_priv(ndev); 1441 1442 priv->rx_cksum_offload_flag = !!(features & NETIF_F_RXCSUM); 1443 1444 return 0; 1445 } 1446 1447 static int netsec_netdev_ioctl(struct net_device *ndev, struct ifreq *ifr, 1448 int cmd) 1449 { 1450 return phy_mii_ioctl(ndev->phydev, ifr, cmd); 1451 } 1452 1453 static const struct net_device_ops netsec_netdev_ops = { 1454 .ndo_init = netsec_netdev_init, 1455 .ndo_uninit = netsec_netdev_uninit, 1456 .ndo_open = netsec_netdev_open, 1457 .ndo_stop = netsec_netdev_stop, 1458 .ndo_start_xmit = netsec_netdev_start_xmit, 1459 .ndo_set_features = netsec_netdev_set_features, 1460 .ndo_set_mac_address = eth_mac_addr, 1461 .ndo_validate_addr = eth_validate_addr, 1462 .ndo_do_ioctl = netsec_netdev_ioctl, 1463 }; 1464 1465 static int netsec_of_probe(struct platform_device *pdev, 1466 struct netsec_priv *priv, u32 *phy_addr) 1467 { 1468 priv->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); 1469 if (!priv->phy_np) { 1470 dev_err(&pdev->dev, "missing required property 'phy-handle'\n"); 1471 return -EINVAL; 1472 } 1473 1474 *phy_addr = of_mdio_parse_addr(&pdev->dev, priv->phy_np); 1475 1476 priv->clk = devm_clk_get(&pdev->dev, NULL); /* get by 'phy_ref_clk' */ 1477 if (IS_ERR(priv->clk)) { 1478 dev_err(&pdev->dev, "phy_ref_clk not found\n"); 1479 return PTR_ERR(priv->clk); 1480 } 1481 priv->freq = clk_get_rate(priv->clk); 1482 1483 return 0; 1484 } 1485 1486 static int netsec_acpi_probe(struct platform_device *pdev, 1487 struct netsec_priv *priv, u32 *phy_addr) 1488 { 1489 int ret; 1490 1491 if (!IS_ENABLED(CONFIG_ACPI)) 1492 return -ENODEV; 1493 1494 ret = device_property_read_u32(&pdev->dev, "phy-channel", phy_addr); 1495 if (ret) { 1496 dev_err(&pdev->dev, 1497 "missing required property 'phy-channel'\n"); 1498 return ret; 1499 } 1500 1501 ret = device_property_read_u32(&pdev->dev, 1502 "socionext,phy-clock-frequency", 1503 &priv->freq); 1504 if (ret) 1505 dev_err(&pdev->dev, 1506 "missing required property 'socionext,phy-clock-frequency'\n"); 1507 return ret; 1508 } 1509 1510 static void netsec_unregister_mdio(struct netsec_priv *priv) 1511 { 1512 struct phy_device *phydev = priv->phydev; 1513 1514 if (!dev_of_node(priv->dev) && phydev) { 1515 phy_device_remove(phydev); 1516 phy_device_free(phydev); 1517 } 1518 1519 mdiobus_unregister(priv->mii_bus); 1520 } 1521 1522 static int netsec_register_mdio(struct netsec_priv *priv, u32 phy_addr) 1523 { 1524 struct mii_bus *bus; 1525 int ret; 1526 1527 bus = devm_mdiobus_alloc(priv->dev); 1528 if (!bus) 1529 return -ENOMEM; 1530 1531 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(priv->dev)); 1532 bus->priv = priv; 1533 bus->name = "SNI NETSEC MDIO"; 1534 bus->read = netsec_phy_read; 1535 bus->write = netsec_phy_write; 1536 bus->parent = priv->dev; 1537 priv->mii_bus = bus; 1538 1539 if (dev_of_node(priv->dev)) { 1540 struct device_node *mdio_node, *parent = dev_of_node(priv->dev); 1541 1542 mdio_node = of_get_child_by_name(parent, "mdio"); 1543 if (mdio_node) { 1544 parent = mdio_node; 1545 } else { 1546 /* older f/w doesn't populate the mdio subnode, 1547 * allow relaxed upgrade of f/w in due time. 1548 */ 1549 dev_info(priv->dev, "Upgrade f/w for mdio subnode!\n"); 1550 } 1551 1552 ret = of_mdiobus_register(bus, parent); 1553 of_node_put(mdio_node); 1554 1555 if (ret) { 1556 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1557 return ret; 1558 } 1559 } else { 1560 /* Mask out all PHYs from auto probing. */ 1561 bus->phy_mask = ~0; 1562 ret = mdiobus_register(bus); 1563 if (ret) { 1564 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1565 return ret; 1566 } 1567 1568 priv->phydev = get_phy_device(bus, phy_addr, false); 1569 if (IS_ERR(priv->phydev)) { 1570 ret = PTR_ERR(priv->phydev); 1571 dev_err(priv->dev, "get_phy_device err(%d)\n", ret); 1572 priv->phydev = NULL; 1573 return -ENODEV; 1574 } 1575 1576 ret = phy_device_register(priv->phydev); 1577 if (ret) { 1578 mdiobus_unregister(bus); 1579 dev_err(priv->dev, 1580 "phy_device_register err(%d)\n", ret); 1581 } 1582 } 1583 1584 return ret; 1585 } 1586 1587 static int netsec_probe(struct platform_device *pdev) 1588 { 1589 struct resource *mmio_res, *eeprom_res, *irq_res; 1590 u8 *mac, macbuf[ETH_ALEN]; 1591 struct netsec_priv *priv; 1592 u32 hw_ver, phy_addr = 0; 1593 struct net_device *ndev; 1594 int ret; 1595 1596 mmio_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1597 if (!mmio_res) { 1598 dev_err(&pdev->dev, "No MMIO resource found.\n"); 1599 return -ENODEV; 1600 } 1601 1602 eeprom_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1603 if (!eeprom_res) { 1604 dev_info(&pdev->dev, "No EEPROM resource found.\n"); 1605 return -ENODEV; 1606 } 1607 1608 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1609 if (!irq_res) { 1610 dev_err(&pdev->dev, "No IRQ resource found.\n"); 1611 return -ENODEV; 1612 } 1613 1614 ndev = alloc_etherdev(sizeof(*priv)); 1615 if (!ndev) 1616 return -ENOMEM; 1617 1618 priv = netdev_priv(ndev); 1619 1620 spin_lock_init(&priv->reglock); 1621 SET_NETDEV_DEV(ndev, &pdev->dev); 1622 platform_set_drvdata(pdev, priv); 1623 ndev->irq = irq_res->start; 1624 priv->dev = &pdev->dev; 1625 priv->ndev = ndev; 1626 1627 priv->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | 1628 NETIF_MSG_LINK | NETIF_MSG_PROBE; 1629 1630 priv->phy_interface = device_get_phy_mode(&pdev->dev); 1631 if (priv->phy_interface < 0) { 1632 dev_err(&pdev->dev, "missing required property 'phy-mode'\n"); 1633 ret = -ENODEV; 1634 goto free_ndev; 1635 } 1636 1637 priv->ioaddr = devm_ioremap(&pdev->dev, mmio_res->start, 1638 resource_size(mmio_res)); 1639 if (!priv->ioaddr) { 1640 dev_err(&pdev->dev, "devm_ioremap() failed\n"); 1641 ret = -ENXIO; 1642 goto free_ndev; 1643 } 1644 1645 priv->eeprom_base = devm_ioremap(&pdev->dev, eeprom_res->start, 1646 resource_size(eeprom_res)); 1647 if (!priv->eeprom_base) { 1648 dev_err(&pdev->dev, "devm_ioremap() failed for EEPROM\n"); 1649 ret = -ENXIO; 1650 goto free_ndev; 1651 } 1652 1653 mac = device_get_mac_address(&pdev->dev, macbuf, sizeof(macbuf)); 1654 if (mac) 1655 ether_addr_copy(ndev->dev_addr, mac); 1656 1657 if (priv->eeprom_base && 1658 (!mac || !is_valid_ether_addr(ndev->dev_addr))) { 1659 void __iomem *macp = priv->eeprom_base + 1660 NETSEC_EEPROM_MAC_ADDRESS; 1661 1662 ndev->dev_addr[0] = readb(macp + 3); 1663 ndev->dev_addr[1] = readb(macp + 2); 1664 ndev->dev_addr[2] = readb(macp + 1); 1665 ndev->dev_addr[3] = readb(macp + 0); 1666 ndev->dev_addr[4] = readb(macp + 7); 1667 ndev->dev_addr[5] = readb(macp + 6); 1668 } 1669 1670 if (!is_valid_ether_addr(ndev->dev_addr)) { 1671 dev_warn(&pdev->dev, "No MAC address found, using random\n"); 1672 eth_hw_addr_random(ndev); 1673 } 1674 1675 if (dev_of_node(&pdev->dev)) 1676 ret = netsec_of_probe(pdev, priv, &phy_addr); 1677 else 1678 ret = netsec_acpi_probe(pdev, priv, &phy_addr); 1679 if (ret) 1680 goto free_ndev; 1681 1682 priv->phy_addr = phy_addr; 1683 1684 if (!priv->freq) { 1685 dev_err(&pdev->dev, "missing PHY reference clock frequency\n"); 1686 ret = -ENODEV; 1687 goto free_ndev; 1688 } 1689 1690 /* default for throughput */ 1691 priv->et_coalesce.rx_coalesce_usecs = 500; 1692 priv->et_coalesce.rx_max_coalesced_frames = 8; 1693 priv->et_coalesce.tx_coalesce_usecs = 500; 1694 priv->et_coalesce.tx_max_coalesced_frames = 8; 1695 1696 ret = device_property_read_u32(&pdev->dev, "max-frame-size", 1697 &ndev->max_mtu); 1698 if (ret < 0) 1699 ndev->max_mtu = ETH_DATA_LEN; 1700 1701 /* runtime_pm coverage just for probe, open/close also cover it */ 1702 pm_runtime_enable(&pdev->dev); 1703 pm_runtime_get_sync(&pdev->dev); 1704 1705 hw_ver = netsec_read(priv, NETSEC_REG_F_TAIKI_VER); 1706 /* this driver only supports F_TAIKI style NETSEC */ 1707 if (NETSEC_F_NETSEC_VER_MAJOR_NUM(hw_ver) != 1708 NETSEC_F_NETSEC_VER_MAJOR_NUM(NETSEC_REG_NETSEC_VER_F_TAIKI)) { 1709 ret = -ENODEV; 1710 goto pm_disable; 1711 } 1712 1713 dev_info(&pdev->dev, "hardware revision %d.%d\n", 1714 hw_ver >> 16, hw_ver & 0xffff); 1715 1716 netif_napi_add(ndev, &priv->napi, netsec_napi_poll, NAPI_POLL_WEIGHT); 1717 1718 ndev->netdev_ops = &netsec_netdev_ops; 1719 ndev->ethtool_ops = &netsec_ethtool_ops; 1720 1721 ndev->features |= NETIF_F_HIGHDMA | NETIF_F_RXCSUM | NETIF_F_GSO | 1722 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1723 ndev->hw_features = ndev->features; 1724 1725 priv->rx_cksum_offload_flag = true; 1726 1727 ret = netsec_register_mdio(priv, phy_addr); 1728 if (ret) 1729 goto unreg_napi; 1730 1731 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40))) 1732 dev_warn(&pdev->dev, "Failed to set DMA mask\n"); 1733 1734 ret = register_netdev(ndev); 1735 if (ret) { 1736 netif_err(priv, probe, ndev, "register_netdev() failed\n"); 1737 goto unreg_mii; 1738 } 1739 1740 pm_runtime_put_sync(&pdev->dev); 1741 return 0; 1742 1743 unreg_mii: 1744 netsec_unregister_mdio(priv); 1745 unreg_napi: 1746 netif_napi_del(&priv->napi); 1747 pm_disable: 1748 pm_runtime_put_sync(&pdev->dev); 1749 pm_runtime_disable(&pdev->dev); 1750 free_ndev: 1751 free_netdev(ndev); 1752 dev_err(&pdev->dev, "init failed\n"); 1753 1754 return ret; 1755 } 1756 1757 static int netsec_remove(struct platform_device *pdev) 1758 { 1759 struct netsec_priv *priv = platform_get_drvdata(pdev); 1760 1761 unregister_netdev(priv->ndev); 1762 1763 netsec_unregister_mdio(priv); 1764 1765 netif_napi_del(&priv->napi); 1766 1767 pm_runtime_disable(&pdev->dev); 1768 free_netdev(priv->ndev); 1769 1770 return 0; 1771 } 1772 1773 #ifdef CONFIG_PM 1774 static int netsec_runtime_suspend(struct device *dev) 1775 { 1776 struct netsec_priv *priv = dev_get_drvdata(dev); 1777 1778 netsec_write(priv, NETSEC_REG_CLK_EN, 0); 1779 1780 clk_disable_unprepare(priv->clk); 1781 1782 return 0; 1783 } 1784 1785 static int netsec_runtime_resume(struct device *dev) 1786 { 1787 struct netsec_priv *priv = dev_get_drvdata(dev); 1788 1789 clk_prepare_enable(priv->clk); 1790 1791 netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D | 1792 NETSEC_CLK_EN_REG_DOM_C | 1793 NETSEC_CLK_EN_REG_DOM_G); 1794 return 0; 1795 } 1796 #endif 1797 1798 static const struct dev_pm_ops netsec_pm_ops = { 1799 SET_RUNTIME_PM_OPS(netsec_runtime_suspend, netsec_runtime_resume, NULL) 1800 }; 1801 1802 static const struct of_device_id netsec_dt_ids[] = { 1803 { .compatible = "socionext,synquacer-netsec" }, 1804 { } 1805 }; 1806 MODULE_DEVICE_TABLE(of, netsec_dt_ids); 1807 1808 #ifdef CONFIG_ACPI 1809 static const struct acpi_device_id netsec_acpi_ids[] = { 1810 { "SCX0001" }, 1811 { } 1812 }; 1813 MODULE_DEVICE_TABLE(acpi, netsec_acpi_ids); 1814 #endif 1815 1816 static struct platform_driver netsec_driver = { 1817 .probe = netsec_probe, 1818 .remove = netsec_remove, 1819 .driver = { 1820 .name = "netsec", 1821 .pm = &netsec_pm_ops, 1822 .of_match_table = netsec_dt_ids, 1823 .acpi_match_table = ACPI_PTR(netsec_acpi_ids), 1824 }, 1825 }; 1826 module_platform_driver(netsec_driver); 1827 1828 MODULE_AUTHOR("Jassi Brar <jaswinder.singh@linaro.org>"); 1829 MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); 1830 MODULE_DESCRIPTION("NETSEC Ethernet driver"); 1831 MODULE_LICENSE("GPL"); 1832