1 // SPDX-License-Identifier: GPL-2.0+ 2 3 #include <linux/types.h> 4 #include <linux/clk.h> 5 #include <linux/platform_device.h> 6 #include <linux/pm_runtime.h> 7 #include <linux/acpi.h> 8 #include <linux/of_mdio.h> 9 #include <linux/etherdevice.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 13 #include <net/tcp.h> 14 #include <net/ip6_checksum.h> 15 16 #define NETSEC_REG_SOFT_RST 0x104 17 #define NETSEC_REG_COM_INIT 0x120 18 19 #define NETSEC_REG_TOP_STATUS 0x200 20 #define NETSEC_IRQ_RX BIT(1) 21 #define NETSEC_IRQ_TX BIT(0) 22 23 #define NETSEC_REG_TOP_INTEN 0x204 24 #define NETSEC_REG_INTEN_SET 0x234 25 #define NETSEC_REG_INTEN_CLR 0x238 26 27 #define NETSEC_REG_NRM_TX_STATUS 0x400 28 #define NETSEC_REG_NRM_TX_INTEN 0x404 29 #define NETSEC_REG_NRM_TX_INTEN_SET 0x428 30 #define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c 31 #define NRM_TX_ST_NTOWNR BIT(17) 32 #define NRM_TX_ST_TR_ERR BIT(16) 33 #define NRM_TX_ST_TXDONE BIT(15) 34 #define NRM_TX_ST_TMREXP BIT(14) 35 36 #define NETSEC_REG_NRM_RX_STATUS 0x440 37 #define NETSEC_REG_NRM_RX_INTEN 0x444 38 #define NETSEC_REG_NRM_RX_INTEN_SET 0x468 39 #define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c 40 #define NRM_RX_ST_RC_ERR BIT(16) 41 #define NRM_RX_ST_PKTCNT BIT(15) 42 #define NRM_RX_ST_TMREXP BIT(14) 43 44 #define NETSEC_REG_PKT_CMD_BUF 0xd0 45 46 #define NETSEC_REG_CLK_EN 0x100 47 48 #define NETSEC_REG_PKT_CTRL 0x140 49 50 #define NETSEC_REG_DMA_TMR_CTRL 0x20c 51 #define NETSEC_REG_F_TAIKI_MC_VER 0x22c 52 #define NETSEC_REG_F_TAIKI_VER 0x230 53 #define NETSEC_REG_DMA_HM_CTRL 0x214 54 #define NETSEC_REG_DMA_MH_CTRL 0x220 55 #define NETSEC_REG_ADDR_DIS_CORE 0x218 56 #define NETSEC_REG_DMAC_HM_CMD_BUF 0x210 57 #define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c 58 59 #define NETSEC_REG_NRM_TX_PKTCNT 0x410 60 61 #define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414 62 #define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418 63 64 #define NETSEC_REG_NRM_TX_TMR 0x41c 65 66 #define NETSEC_REG_NRM_RX_PKTCNT 0x454 67 #define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458 68 #define NETSEC_REG_NRM_TX_TXINT_TMR 0x420 69 #define NETSEC_REG_NRM_RX_RXINT_TMR 0x460 70 71 #define NETSEC_REG_NRM_RX_TMR 0x45c 72 73 #define NETSEC_REG_NRM_TX_DESC_START_UP 0x434 74 #define NETSEC_REG_NRM_TX_DESC_START_LW 0x408 75 #define NETSEC_REG_NRM_RX_DESC_START_UP 0x474 76 #define NETSEC_REG_NRM_RX_DESC_START_LW 0x448 77 78 #define NETSEC_REG_NRM_TX_CONFIG 0x430 79 #define NETSEC_REG_NRM_RX_CONFIG 0x470 80 81 #define MAC_REG_STATUS 0x1024 82 #define MAC_REG_DATA 0x11c0 83 #define MAC_REG_CMD 0x11c4 84 #define MAC_REG_FLOW_TH 0x11cc 85 #define MAC_REG_INTF_SEL 0x11d4 86 #define MAC_REG_DESC_INIT 0x11fc 87 #define MAC_REG_DESC_SOFT_RST 0x1204 88 #define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500 89 90 #define GMAC_REG_MCR 0x0000 91 #define GMAC_REG_MFFR 0x0004 92 #define GMAC_REG_GAR 0x0010 93 #define GMAC_REG_GDR 0x0014 94 #define GMAC_REG_FCR 0x0018 95 #define GMAC_REG_BMR 0x1000 96 #define GMAC_REG_RDLAR 0x100c 97 #define GMAC_REG_TDLAR 0x1010 98 #define GMAC_REG_OMR 0x1018 99 100 #define MHZ(n) ((n) * 1000 * 1000) 101 102 #define NETSEC_TX_SHIFT_OWN_FIELD 31 103 #define NETSEC_TX_SHIFT_LD_FIELD 30 104 #define NETSEC_TX_SHIFT_DRID_FIELD 24 105 #define NETSEC_TX_SHIFT_PT_FIELD 21 106 #define NETSEC_TX_SHIFT_TDRID_FIELD 16 107 #define NETSEC_TX_SHIFT_CC_FIELD 15 108 #define NETSEC_TX_SHIFT_FS_FIELD 9 109 #define NETSEC_TX_LAST 8 110 #define NETSEC_TX_SHIFT_CO 7 111 #define NETSEC_TX_SHIFT_SO 6 112 #define NETSEC_TX_SHIFT_TRS_FIELD 4 113 114 #define NETSEC_RX_PKT_OWN_FIELD 31 115 #define NETSEC_RX_PKT_LD_FIELD 30 116 #define NETSEC_RX_PKT_SDRID_FIELD 24 117 #define NETSEC_RX_PKT_FR_FIELD 23 118 #define NETSEC_RX_PKT_ER_FIELD 21 119 #define NETSEC_RX_PKT_ERR_FIELD 16 120 #define NETSEC_RX_PKT_TDRID_FIELD 12 121 #define NETSEC_RX_PKT_FS_FIELD 9 122 #define NETSEC_RX_PKT_LS_FIELD 8 123 #define NETSEC_RX_PKT_CO_FIELD 6 124 125 #define NETSEC_RX_PKT_ERR_MASK 3 126 127 #define NETSEC_MAX_TX_PKT_LEN 1518 128 #define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018 129 130 #define NETSEC_RING_GMAC 15 131 #define NETSEC_RING_MAX 2 132 133 #define NETSEC_TCP_SEG_LEN_MAX 1460 134 #define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960 135 136 #define NETSEC_RX_CKSUM_NOTAVAIL 0 137 #define NETSEC_RX_CKSUM_OK 1 138 #define NETSEC_RX_CKSUM_NG 2 139 140 #define NETSEC_TOP_IRQ_REG_CODE_LOAD_END BIT(20) 141 #define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4) 142 143 #define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20) 144 #define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19) 145 146 #define NETSEC_INT_PKTCNT_MAX 2047 147 148 #define NETSEC_FLOW_START_TH_MAX 95 149 #define NETSEC_FLOW_STOP_TH_MAX 95 150 #define NETSEC_FLOW_PAUSE_TIME_MIN 5 151 152 #define NETSEC_CLK_EN_REG_DOM_ALL 0x3f 153 154 #define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28) 155 #define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27) 156 #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3) 157 #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2) 158 #define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1) 159 #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0) 160 161 #define NETSEC_CLK_EN_REG_DOM_G BIT(5) 162 #define NETSEC_CLK_EN_REG_DOM_C BIT(1) 163 #define NETSEC_CLK_EN_REG_DOM_D BIT(0) 164 165 #define NETSEC_COM_INIT_REG_DB BIT(2) 166 #define NETSEC_COM_INIT_REG_CLS BIT(1) 167 #define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \ 168 NETSEC_COM_INIT_REG_DB) 169 170 #define NETSEC_SOFT_RST_REG_RESET 0 171 #define NETSEC_SOFT_RST_REG_RUN BIT(31) 172 173 #define NETSEC_DMA_CTRL_REG_STOP 1 174 #define MH_CTRL__MODE_TRANS BIT(20) 175 176 #define NETSEC_GMAC_CMD_ST_READ 0 177 #define NETSEC_GMAC_CMD_ST_WRITE BIT(28) 178 #define NETSEC_GMAC_CMD_ST_BUSY BIT(31) 179 180 #define NETSEC_GMAC_BMR_REG_COMMON 0x00412080 181 #define NETSEC_GMAC_BMR_REG_RESET 0x00020181 182 #define NETSEC_GMAC_BMR_REG_SWR 0x00000001 183 184 #define NETSEC_GMAC_OMR_REG_ST BIT(13) 185 #define NETSEC_GMAC_OMR_REG_SR BIT(1) 186 187 #define NETSEC_GMAC_MCR_REG_IBN BIT(30) 188 #define NETSEC_GMAC_MCR_REG_CST BIT(25) 189 #define NETSEC_GMAC_MCR_REG_JE BIT(20) 190 #define NETSEC_MCR_PS BIT(15) 191 #define NETSEC_GMAC_MCR_REG_FES BIT(14) 192 #define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c 193 #define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c 194 195 #define NETSEC_FCR_RFE BIT(2) 196 #define NETSEC_FCR_TFE BIT(1) 197 198 #define NETSEC_GMAC_GAR_REG_GW BIT(1) 199 #define NETSEC_GMAC_GAR_REG_GB BIT(0) 200 201 #define NETSEC_GMAC_GAR_REG_SHIFT_PA 11 202 #define NETSEC_GMAC_GAR_REG_SHIFT_GR 6 203 #define GMAC_REG_SHIFT_CR_GAR 2 204 205 #define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2 206 #define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3 207 #define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0 208 #define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1 209 #define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4 210 #define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5 211 212 #define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000 213 #define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000 214 215 #define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000 216 217 #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31) 218 #define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30) 219 #define NETSEC_REG_DESC_TMR_MODE 4 220 #define NETSEC_REG_DESC_ENDIAN 0 221 222 #define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1 223 #define NETSEC_MAC_DESC_INIT_REG_INIT 1 224 225 #define NETSEC_EEPROM_MAC_ADDRESS 0x00 226 #define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08 227 #define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C 228 #define NETSEC_EEPROM_HM_ME_SIZE 0x10 229 #define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14 230 #define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18 231 #define NETSEC_EEPROM_MH_ME_SIZE 0x1C 232 #define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20 233 #define NETSEC_EEPROM_PKT_ME_SIZE 0x24 234 235 #define DESC_NUM 256 236 237 #define DESC_SZ sizeof(struct netsec_de) 238 239 #define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000) 240 241 enum ring_id { 242 NETSEC_RING_TX = 0, 243 NETSEC_RING_RX 244 }; 245 246 struct netsec_desc { 247 struct sk_buff *skb; 248 dma_addr_t dma_addr; 249 void *addr; 250 u16 len; 251 }; 252 253 struct netsec_desc_ring { 254 dma_addr_t desc_dma; 255 struct netsec_desc *desc; 256 void *vaddr; 257 u16 pkt_cnt; 258 u16 head, tail; 259 }; 260 261 struct netsec_priv { 262 struct netsec_desc_ring desc_ring[NETSEC_RING_MAX]; 263 struct ethtool_coalesce et_coalesce; 264 spinlock_t reglock; /* protect reg access */ 265 struct napi_struct napi; 266 phy_interface_t phy_interface; 267 struct net_device *ndev; 268 struct device_node *phy_np; 269 struct phy_device *phydev; 270 struct mii_bus *mii_bus; 271 void __iomem *ioaddr; 272 void __iomem *eeprom_base; 273 struct device *dev; 274 struct clk *clk; 275 u32 msg_enable; 276 u32 freq; 277 bool rx_cksum_offload_flag; 278 }; 279 280 struct netsec_de { /* Netsec Descriptor layout */ 281 u32 attr; 282 u32 data_buf_addr_up; 283 u32 data_buf_addr_lw; 284 u32 buf_len_info; 285 }; 286 287 struct netsec_tx_pkt_ctrl { 288 u16 tcp_seg_len; 289 bool tcp_seg_offload_flag; 290 bool cksum_offload_flag; 291 }; 292 293 struct netsec_rx_pkt_info { 294 int rx_cksum_result; 295 int err_code; 296 bool err_flag; 297 }; 298 299 static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val) 300 { 301 writel(val, priv->ioaddr + reg_addr); 302 } 303 304 static u32 netsec_read(struct netsec_priv *priv, u32 reg_addr) 305 { 306 return readl(priv->ioaddr + reg_addr); 307 } 308 309 /************* MDIO BUS OPS FOLLOW *************/ 310 311 #define TIMEOUT_SPINS_MAC 1000 312 #define TIMEOUT_SECONDARY_MS_MAC 100 313 314 static u32 netsec_clk_type(u32 freq) 315 { 316 if (freq < MHZ(35)) 317 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ; 318 if (freq < MHZ(60)) 319 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ; 320 if (freq < MHZ(100)) 321 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ; 322 if (freq < MHZ(150)) 323 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ; 324 if (freq < MHZ(250)) 325 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ; 326 327 return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ; 328 } 329 330 static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask) 331 { 332 u32 timeout = TIMEOUT_SPINS_MAC; 333 334 while (--timeout && netsec_read(priv, addr) & mask) 335 cpu_relax(); 336 if (timeout) 337 return 0; 338 339 timeout = TIMEOUT_SECONDARY_MS_MAC; 340 while (--timeout && netsec_read(priv, addr) & mask) 341 usleep_range(1000, 2000); 342 343 if (timeout) 344 return 0; 345 346 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 347 348 return -ETIMEDOUT; 349 } 350 351 static int netsec_mac_write(struct netsec_priv *priv, u32 addr, u32 value) 352 { 353 netsec_write(priv, MAC_REG_DATA, value); 354 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE); 355 return netsec_wait_while_busy(priv, 356 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 357 } 358 359 static int netsec_mac_read(struct netsec_priv *priv, u32 addr, u32 *read) 360 { 361 int ret; 362 363 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ); 364 ret = netsec_wait_while_busy(priv, 365 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 366 if (ret) 367 return ret; 368 369 *read = netsec_read(priv, MAC_REG_DATA); 370 371 return 0; 372 } 373 374 static int netsec_mac_wait_while_busy(struct netsec_priv *priv, 375 u32 addr, u32 mask) 376 { 377 u32 timeout = TIMEOUT_SPINS_MAC; 378 int ret, data; 379 380 do { 381 ret = netsec_mac_read(priv, addr, &data); 382 if (ret) 383 break; 384 cpu_relax(); 385 } while (--timeout && (data & mask)); 386 387 if (timeout) 388 return 0; 389 390 timeout = TIMEOUT_SECONDARY_MS_MAC; 391 do { 392 usleep_range(1000, 2000); 393 394 ret = netsec_mac_read(priv, addr, &data); 395 if (ret) 396 break; 397 cpu_relax(); 398 } while (--timeout && (data & mask)); 399 400 if (timeout && !ret) 401 return 0; 402 403 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 404 405 return -ETIMEDOUT; 406 } 407 408 static int netsec_mac_update_to_phy_state(struct netsec_priv *priv) 409 { 410 struct phy_device *phydev = priv->ndev->phydev; 411 u32 value = 0; 412 413 value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON : 414 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON; 415 416 if (phydev->speed != SPEED_1000) 417 value |= NETSEC_MCR_PS; 418 419 if (priv->phy_interface != PHY_INTERFACE_MODE_GMII && 420 phydev->speed == SPEED_100) 421 value |= NETSEC_GMAC_MCR_REG_FES; 422 423 value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE; 424 425 if (phy_interface_mode_is_rgmii(priv->phy_interface)) 426 value |= NETSEC_GMAC_MCR_REG_IBN; 427 428 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 429 return -ETIMEDOUT; 430 431 return 0; 432 } 433 434 static int netsec_phy_write(struct mii_bus *bus, 435 int phy_addr, int reg, u16 val) 436 { 437 struct netsec_priv *priv = bus->priv; 438 439 if (netsec_mac_write(priv, GMAC_REG_GDR, val)) 440 return -ETIMEDOUT; 441 if (netsec_mac_write(priv, GMAC_REG_GAR, 442 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 443 reg << NETSEC_GMAC_GAR_REG_SHIFT_GR | 444 NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB | 445 (netsec_clk_type(priv->freq) << 446 GMAC_REG_SHIFT_CR_GAR))) 447 return -ETIMEDOUT; 448 449 return netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 450 NETSEC_GMAC_GAR_REG_GB); 451 } 452 453 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr) 454 { 455 struct netsec_priv *priv = bus->priv; 456 u32 data; 457 int ret; 458 459 if (netsec_mac_write(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB | 460 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 461 reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR | 462 (netsec_clk_type(priv->freq) << 463 GMAC_REG_SHIFT_CR_GAR))) 464 return -ETIMEDOUT; 465 466 ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 467 NETSEC_GMAC_GAR_REG_GB); 468 if (ret) 469 return ret; 470 471 ret = netsec_mac_read(priv, GMAC_REG_GDR, &data); 472 if (ret) 473 return ret; 474 475 return data; 476 } 477 478 /************* ETHTOOL_OPS FOLLOW *************/ 479 480 static void netsec_et_get_drvinfo(struct net_device *net_device, 481 struct ethtool_drvinfo *info) 482 { 483 strlcpy(info->driver, "netsec", sizeof(info->driver)); 484 strlcpy(info->bus_info, dev_name(net_device->dev.parent), 485 sizeof(info->bus_info)); 486 } 487 488 static int netsec_et_get_coalesce(struct net_device *net_device, 489 struct ethtool_coalesce *et_coalesce) 490 { 491 struct netsec_priv *priv = netdev_priv(net_device); 492 493 *et_coalesce = priv->et_coalesce; 494 495 return 0; 496 } 497 498 static int netsec_et_set_coalesce(struct net_device *net_device, 499 struct ethtool_coalesce *et_coalesce) 500 { 501 struct netsec_priv *priv = netdev_priv(net_device); 502 503 priv->et_coalesce = *et_coalesce; 504 505 if (priv->et_coalesce.tx_coalesce_usecs < 50) 506 priv->et_coalesce.tx_coalesce_usecs = 50; 507 if (priv->et_coalesce.tx_max_coalesced_frames < 1) 508 priv->et_coalesce.tx_max_coalesced_frames = 1; 509 510 netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT, 511 priv->et_coalesce.tx_max_coalesced_frames); 512 netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR, 513 priv->et_coalesce.tx_coalesce_usecs); 514 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE); 515 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP); 516 517 if (priv->et_coalesce.rx_coalesce_usecs < 50) 518 priv->et_coalesce.rx_coalesce_usecs = 50; 519 if (priv->et_coalesce.rx_max_coalesced_frames < 1) 520 priv->et_coalesce.rx_max_coalesced_frames = 1; 521 522 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT, 523 priv->et_coalesce.rx_max_coalesced_frames); 524 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR, 525 priv->et_coalesce.rx_coalesce_usecs); 526 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT); 527 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP); 528 529 return 0; 530 } 531 532 static u32 netsec_et_get_msglevel(struct net_device *dev) 533 { 534 struct netsec_priv *priv = netdev_priv(dev); 535 536 return priv->msg_enable; 537 } 538 539 static void netsec_et_set_msglevel(struct net_device *dev, u32 datum) 540 { 541 struct netsec_priv *priv = netdev_priv(dev); 542 543 priv->msg_enable = datum; 544 } 545 546 static const struct ethtool_ops netsec_ethtool_ops = { 547 .get_drvinfo = netsec_et_get_drvinfo, 548 .get_link_ksettings = phy_ethtool_get_link_ksettings, 549 .set_link_ksettings = phy_ethtool_set_link_ksettings, 550 .get_link = ethtool_op_get_link, 551 .get_coalesce = netsec_et_get_coalesce, 552 .set_coalesce = netsec_et_set_coalesce, 553 .get_msglevel = netsec_et_get_msglevel, 554 .set_msglevel = netsec_et_set_msglevel, 555 }; 556 557 /************* NETDEV_OPS FOLLOW *************/ 558 559 static struct sk_buff *netsec_alloc_skb(struct netsec_priv *priv, 560 struct netsec_desc *desc) 561 { 562 struct sk_buff *skb; 563 564 if (device_get_dma_attr(priv->dev) == DEV_DMA_COHERENT) { 565 skb = netdev_alloc_skb_ip_align(priv->ndev, desc->len); 566 } else { 567 desc->len = L1_CACHE_ALIGN(desc->len); 568 skb = netdev_alloc_skb(priv->ndev, desc->len); 569 } 570 if (!skb) 571 return NULL; 572 573 desc->addr = skb->data; 574 desc->dma_addr = dma_map_single(priv->dev, desc->addr, desc->len, 575 DMA_FROM_DEVICE); 576 if (dma_mapping_error(priv->dev, desc->dma_addr)) { 577 dev_kfree_skb_any(skb); 578 return NULL; 579 } 580 return skb; 581 } 582 583 static void netsec_set_rx_de(struct netsec_priv *priv, 584 struct netsec_desc_ring *dring, u16 idx, 585 const struct netsec_desc *desc, 586 struct sk_buff *skb) 587 { 588 struct netsec_de *de = dring->vaddr + DESC_SZ * idx; 589 u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) | 590 (1 << NETSEC_RX_PKT_FS_FIELD) | 591 (1 << NETSEC_RX_PKT_LS_FIELD); 592 593 if (idx == DESC_NUM - 1) 594 attr |= (1 << NETSEC_RX_PKT_LD_FIELD); 595 596 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 597 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 598 de->buf_len_info = desc->len; 599 de->attr = attr; 600 dma_wmb(); 601 602 dring->desc[idx].dma_addr = desc->dma_addr; 603 dring->desc[idx].addr = desc->addr; 604 dring->desc[idx].len = desc->len; 605 dring->desc[idx].skb = skb; 606 } 607 608 static struct sk_buff *netsec_get_rx_de(struct netsec_priv *priv, 609 struct netsec_desc_ring *dring, 610 u16 idx, 611 struct netsec_rx_pkt_info *rxpi, 612 struct netsec_desc *desc, u16 *len) 613 { 614 struct netsec_de de = {}; 615 616 memcpy(&de, dring->vaddr + DESC_SZ * idx, DESC_SZ); 617 618 *len = de.buf_len_info >> 16; 619 620 rxpi->err_flag = (de.attr >> NETSEC_RX_PKT_ER_FIELD) & 1; 621 rxpi->rx_cksum_result = (de.attr >> NETSEC_RX_PKT_CO_FIELD) & 3; 622 rxpi->err_code = (de.attr >> NETSEC_RX_PKT_ERR_FIELD) & 623 NETSEC_RX_PKT_ERR_MASK; 624 *desc = dring->desc[idx]; 625 return desc->skb; 626 } 627 628 static struct sk_buff *netsec_get_rx_pkt_data(struct netsec_priv *priv, 629 struct netsec_rx_pkt_info *rxpi, 630 struct netsec_desc *desc, 631 u16 *len) 632 { 633 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 634 struct sk_buff *tmp_skb, *skb = NULL; 635 struct netsec_desc td; 636 int tail; 637 638 *rxpi = (struct netsec_rx_pkt_info){}; 639 640 td.len = priv->ndev->mtu + 22; 641 642 tmp_skb = netsec_alloc_skb(priv, &td); 643 644 tail = dring->tail; 645 646 if (!tmp_skb) { 647 netsec_set_rx_de(priv, dring, tail, &dring->desc[tail], 648 dring->desc[tail].skb); 649 } else { 650 skb = netsec_get_rx_de(priv, dring, tail, rxpi, desc, len); 651 netsec_set_rx_de(priv, dring, tail, &td, tmp_skb); 652 } 653 654 /* move tail ahead */ 655 dring->tail = (dring->tail + 1) % DESC_NUM; 656 657 return skb; 658 } 659 660 static int netsec_clean_tx_dring(struct netsec_priv *priv, int budget) 661 { 662 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 663 unsigned int pkts, bytes; 664 665 dring->pkt_cnt += netsec_read(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT); 666 667 if (dring->pkt_cnt < budget) 668 budget = dring->pkt_cnt; 669 670 pkts = 0; 671 bytes = 0; 672 673 while (pkts < budget) { 674 struct netsec_desc *desc; 675 struct netsec_de *entry; 676 int tail, eop; 677 678 tail = dring->tail; 679 680 /* move tail ahead */ 681 dring->tail = (tail + 1) % DESC_NUM; 682 683 desc = &dring->desc[tail]; 684 entry = dring->vaddr + DESC_SZ * tail; 685 686 eop = (entry->attr >> NETSEC_TX_LAST) & 1; 687 688 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 689 DMA_TO_DEVICE); 690 if (eop) { 691 pkts++; 692 bytes += desc->skb->len; 693 dev_kfree_skb(desc->skb); 694 } 695 *desc = (struct netsec_desc){}; 696 } 697 dring->pkt_cnt -= budget; 698 699 priv->ndev->stats.tx_packets += budget; 700 priv->ndev->stats.tx_bytes += bytes; 701 702 netdev_completed_queue(priv->ndev, budget, bytes); 703 704 return budget; 705 } 706 707 static int netsec_process_tx(struct netsec_priv *priv, int budget) 708 { 709 struct net_device *ndev = priv->ndev; 710 int new, done = 0; 711 712 do { 713 new = netsec_clean_tx_dring(priv, budget); 714 done += new; 715 budget -= new; 716 } while (new); 717 718 if (done && netif_queue_stopped(ndev)) 719 netif_wake_queue(ndev); 720 721 return done; 722 } 723 724 static int netsec_process_rx(struct netsec_priv *priv, int budget) 725 { 726 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 727 struct net_device *ndev = priv->ndev; 728 struct netsec_rx_pkt_info rx_info; 729 int done = 0; 730 struct netsec_desc desc; 731 struct sk_buff *skb; 732 u16 len; 733 734 while (done < budget) { 735 u16 idx = dring->tail; 736 struct netsec_de *de = dring->vaddr + (DESC_SZ * idx); 737 738 if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD)) { 739 /* reading the register clears the irq */ 740 netsec_read(priv, NETSEC_REG_NRM_RX_PKTCNT); 741 break; 742 } 743 744 /* This barrier is needed to keep us from reading 745 * any other fields out of the netsec_de until we have 746 * verified the descriptor has been written back 747 */ 748 dma_rmb(); 749 done++; 750 skb = netsec_get_rx_pkt_data(priv, &rx_info, &desc, &len); 751 if (unlikely(!skb) || rx_info.err_flag) { 752 netif_err(priv, drv, priv->ndev, 753 "%s: rx fail err(%d)\n", 754 __func__, rx_info.err_code); 755 ndev->stats.rx_dropped++; 756 continue; 757 } 758 759 dma_unmap_single(priv->dev, desc.dma_addr, desc.len, 760 DMA_FROM_DEVICE); 761 skb_put(skb, len); 762 skb->protocol = eth_type_trans(skb, priv->ndev); 763 764 if (priv->rx_cksum_offload_flag && 765 rx_info.rx_cksum_result == NETSEC_RX_CKSUM_OK) 766 skb->ip_summed = CHECKSUM_UNNECESSARY; 767 768 if (napi_gro_receive(&priv->napi, skb) != GRO_DROP) { 769 ndev->stats.rx_packets++; 770 ndev->stats.rx_bytes += len; 771 } 772 } 773 774 return done; 775 } 776 777 static int netsec_napi_poll(struct napi_struct *napi, int budget) 778 { 779 struct netsec_priv *priv; 780 int tx, rx, done, todo; 781 782 priv = container_of(napi, struct netsec_priv, napi); 783 784 todo = budget; 785 do { 786 if (!todo) 787 break; 788 789 tx = netsec_process_tx(priv, todo); 790 todo -= tx; 791 792 if (!todo) 793 break; 794 795 rx = netsec_process_rx(priv, todo); 796 todo -= rx; 797 } while (rx || tx); 798 799 done = budget - todo; 800 801 if (done < budget && napi_complete_done(napi, done)) { 802 unsigned long flags; 803 804 spin_lock_irqsave(&priv->reglock, flags); 805 netsec_write(priv, NETSEC_REG_INTEN_SET, 806 NETSEC_IRQ_RX | NETSEC_IRQ_TX); 807 spin_unlock_irqrestore(&priv->reglock, flags); 808 } 809 810 return done; 811 } 812 813 static void netsec_set_tx_de(struct netsec_priv *priv, 814 struct netsec_desc_ring *dring, 815 const struct netsec_tx_pkt_ctrl *tx_ctrl, 816 const struct netsec_desc *desc, 817 struct sk_buff *skb) 818 { 819 int idx = dring->head; 820 struct netsec_de *de; 821 u32 attr; 822 823 de = dring->vaddr + (DESC_SZ * idx); 824 825 attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) | 826 (1 << NETSEC_TX_SHIFT_PT_FIELD) | 827 (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) | 828 (1 << NETSEC_TX_SHIFT_FS_FIELD) | 829 (1 << NETSEC_TX_LAST) | 830 (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) | 831 (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) | 832 (1 << NETSEC_TX_SHIFT_TRS_FIELD); 833 if (idx == DESC_NUM - 1) 834 attr |= (1 << NETSEC_TX_SHIFT_LD_FIELD); 835 836 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 837 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 838 de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len; 839 de->attr = attr; 840 dma_wmb(); 841 842 dring->desc[idx] = *desc; 843 dring->desc[idx].skb = skb; 844 845 /* move head ahead */ 846 dring->head = (dring->head + 1) % DESC_NUM; 847 } 848 849 static netdev_tx_t netsec_netdev_start_xmit(struct sk_buff *skb, 850 struct net_device *ndev) 851 { 852 struct netsec_priv *priv = netdev_priv(ndev); 853 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 854 struct netsec_tx_pkt_ctrl tx_ctrl = {}; 855 struct netsec_desc tx_desc; 856 u16 tso_seg_len = 0; 857 int filled; 858 859 /* differentiate between full/emtpy ring */ 860 if (dring->head >= dring->tail) 861 filled = dring->head - dring->tail; 862 else 863 filled = dring->head + DESC_NUM - dring->tail; 864 865 if (DESC_NUM - filled < 2) { /* if less than 2 available */ 866 netif_err(priv, drv, priv->ndev, "%s: TxQFull!\n", __func__); 867 netif_stop_queue(priv->ndev); 868 dma_wmb(); 869 return NETDEV_TX_BUSY; 870 } 871 872 if (skb->ip_summed == CHECKSUM_PARTIAL) 873 tx_ctrl.cksum_offload_flag = true; 874 875 if (skb_is_gso(skb)) 876 tso_seg_len = skb_shinfo(skb)->gso_size; 877 878 if (tso_seg_len > 0) { 879 if (skb->protocol == htons(ETH_P_IP)) { 880 ip_hdr(skb)->tot_len = 0; 881 tcp_hdr(skb)->check = 882 ~tcp_v4_check(0, ip_hdr(skb)->saddr, 883 ip_hdr(skb)->daddr, 0); 884 } else { 885 ipv6_hdr(skb)->payload_len = 0; 886 tcp_hdr(skb)->check = 887 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 888 &ipv6_hdr(skb)->daddr, 889 0, IPPROTO_TCP, 0); 890 } 891 892 tx_ctrl.tcp_seg_offload_flag = true; 893 tx_ctrl.tcp_seg_len = tso_seg_len; 894 } 895 896 tx_desc.dma_addr = dma_map_single(priv->dev, skb->data, 897 skb_headlen(skb), DMA_TO_DEVICE); 898 if (dma_mapping_error(priv->dev, tx_desc.dma_addr)) { 899 netif_err(priv, drv, priv->ndev, 900 "%s: DMA mapping failed\n", __func__); 901 ndev->stats.tx_dropped++; 902 dev_kfree_skb_any(skb); 903 return NETDEV_TX_OK; 904 } 905 tx_desc.addr = skb->data; 906 tx_desc.len = skb_headlen(skb); 907 908 skb_tx_timestamp(skb); 909 netdev_sent_queue(priv->ndev, skb->len); 910 911 netsec_set_tx_de(priv, dring, &tx_ctrl, &tx_desc, skb); 912 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */ 913 914 return NETDEV_TX_OK; 915 } 916 917 static void netsec_uninit_pkt_dring(struct netsec_priv *priv, int id) 918 { 919 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 920 struct netsec_desc *desc; 921 u16 idx; 922 923 if (!dring->vaddr || !dring->desc) 924 return; 925 926 for (idx = 0; idx < DESC_NUM; idx++) { 927 desc = &dring->desc[idx]; 928 if (!desc->addr) 929 continue; 930 931 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 932 id == NETSEC_RING_RX ? DMA_FROM_DEVICE : 933 DMA_TO_DEVICE); 934 dev_kfree_skb(desc->skb); 935 } 936 937 memset(dring->desc, 0, sizeof(struct netsec_desc) * DESC_NUM); 938 memset(dring->vaddr, 0, DESC_SZ * DESC_NUM); 939 940 dring->head = 0; 941 dring->tail = 0; 942 dring->pkt_cnt = 0; 943 } 944 945 static void netsec_free_dring(struct netsec_priv *priv, int id) 946 { 947 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 948 949 if (dring->vaddr) { 950 dma_free_coherent(priv->dev, DESC_SZ * DESC_NUM, 951 dring->vaddr, dring->desc_dma); 952 dring->vaddr = NULL; 953 } 954 955 kfree(dring->desc); 956 dring->desc = NULL; 957 } 958 959 static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id) 960 { 961 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 962 int ret = 0; 963 964 dring->vaddr = dma_zalloc_coherent(priv->dev, DESC_SZ * DESC_NUM, 965 &dring->desc_dma, GFP_KERNEL); 966 if (!dring->vaddr) { 967 ret = -ENOMEM; 968 goto err; 969 } 970 971 dring->desc = kcalloc(DESC_NUM, sizeof(*dring->desc), GFP_KERNEL); 972 if (!dring->desc) { 973 ret = -ENOMEM; 974 goto err; 975 } 976 977 return 0; 978 err: 979 netsec_free_dring(priv, id); 980 981 return ret; 982 } 983 984 static int netsec_setup_rx_dring(struct netsec_priv *priv) 985 { 986 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 987 struct netsec_desc desc; 988 struct sk_buff *skb; 989 int n; 990 991 desc.len = priv->ndev->mtu + 22; 992 993 for (n = 0; n < DESC_NUM; n++) { 994 skb = netsec_alloc_skb(priv, &desc); 995 if (!skb) { 996 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 997 return -ENOMEM; 998 } 999 netsec_set_rx_de(priv, dring, n, &desc, skb); 1000 } 1001 1002 return 0; 1003 } 1004 1005 static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg, 1006 u32 addr_h, u32 addr_l, u32 size) 1007 { 1008 u64 base = (u64)addr_h << 32 | addr_l; 1009 void __iomem *ucode; 1010 u32 i; 1011 1012 ucode = ioremap(base, size * sizeof(u32)); 1013 if (!ucode) 1014 return -ENOMEM; 1015 1016 for (i = 0; i < size; i++) 1017 netsec_write(priv, reg, readl(ucode + i * 4)); 1018 1019 iounmap(ucode); 1020 return 0; 1021 } 1022 1023 static int netsec_netdev_load_microcode(struct netsec_priv *priv) 1024 { 1025 u32 addr_h, addr_l, size; 1026 int err; 1027 1028 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_H); 1029 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_L); 1030 size = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_SIZE); 1031 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF, 1032 addr_h, addr_l, size); 1033 if (err) 1034 return err; 1035 1036 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_H); 1037 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_L); 1038 size = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_SIZE); 1039 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF, 1040 addr_h, addr_l, size); 1041 if (err) 1042 return err; 1043 1044 addr_h = 0; 1045 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_ADDRESS); 1046 size = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_SIZE); 1047 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF, 1048 addr_h, addr_l, size); 1049 if (err) 1050 return err; 1051 1052 return 0; 1053 } 1054 1055 static int netsec_reset_hardware(struct netsec_priv *priv, 1056 bool load_ucode) 1057 { 1058 u32 value; 1059 int err; 1060 1061 /* stop DMA engines */ 1062 if (!netsec_read(priv, NETSEC_REG_ADDR_DIS_CORE)) { 1063 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL, 1064 NETSEC_DMA_CTRL_REG_STOP); 1065 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, 1066 NETSEC_DMA_CTRL_REG_STOP); 1067 1068 while (netsec_read(priv, NETSEC_REG_DMA_HM_CTRL) & 1069 NETSEC_DMA_CTRL_REG_STOP) 1070 cpu_relax(); 1071 1072 while (netsec_read(priv, NETSEC_REG_DMA_MH_CTRL) & 1073 NETSEC_DMA_CTRL_REG_STOP) 1074 cpu_relax(); 1075 } 1076 1077 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET); 1078 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN); 1079 netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL); 1080 1081 while (netsec_read(priv, NETSEC_REG_COM_INIT) != 0) 1082 cpu_relax(); 1083 1084 /* set desc_start addr */ 1085 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP, 1086 upper_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1087 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW, 1088 lower_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1089 1090 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP, 1091 upper_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1092 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW, 1093 lower_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1094 1095 /* set normal tx dring ring config */ 1096 netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG, 1097 1 << NETSEC_REG_DESC_ENDIAN); 1098 netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG, 1099 1 << NETSEC_REG_DESC_ENDIAN); 1100 1101 if (load_ucode) { 1102 err = netsec_netdev_load_microcode(priv); 1103 if (err) { 1104 netif_err(priv, probe, priv->ndev, 1105 "%s: failed to load microcode (%d)\n", 1106 __func__, err); 1107 return err; 1108 } 1109 } 1110 1111 /* start DMA engines */ 1112 netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1); 1113 netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0); 1114 1115 usleep_range(1000, 2000); 1116 1117 if (!(netsec_read(priv, NETSEC_REG_TOP_STATUS) & 1118 NETSEC_TOP_IRQ_REG_CODE_LOAD_END)) { 1119 netif_err(priv, probe, priv->ndev, 1120 "microengine start failed\n"); 1121 return -ENXIO; 1122 } 1123 netsec_write(priv, NETSEC_REG_TOP_STATUS, 1124 NETSEC_TOP_IRQ_REG_CODE_LOAD_END); 1125 1126 value = NETSEC_PKT_CTRL_REG_MODE_NRM; 1127 if (priv->ndev->mtu > ETH_DATA_LEN) 1128 value |= NETSEC_PKT_CTRL_REG_EN_JUMBO; 1129 1130 /* change to normal mode */ 1131 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS); 1132 netsec_write(priv, NETSEC_REG_PKT_CTRL, value); 1133 1134 while ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) & 1135 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) 1136 cpu_relax(); 1137 1138 /* clear any pending EMPTY/ERR irq status */ 1139 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0); 1140 1141 /* Disable TX & RX intr */ 1142 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1143 1144 return 0; 1145 } 1146 1147 static int netsec_start_gmac(struct netsec_priv *priv) 1148 { 1149 struct phy_device *phydev = priv->ndev->phydev; 1150 u32 value = 0; 1151 int ret; 1152 1153 if (phydev->speed != SPEED_1000) 1154 value = (NETSEC_GMAC_MCR_REG_CST | 1155 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON); 1156 1157 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 1158 return -ETIMEDOUT; 1159 if (netsec_mac_write(priv, GMAC_REG_BMR, 1160 NETSEC_GMAC_BMR_REG_RESET)) 1161 return -ETIMEDOUT; 1162 1163 /* Wait soft reset */ 1164 usleep_range(1000, 5000); 1165 1166 ret = netsec_mac_read(priv, GMAC_REG_BMR, &value); 1167 if (ret) 1168 return ret; 1169 if (value & NETSEC_GMAC_BMR_REG_SWR) 1170 return -EAGAIN; 1171 1172 netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1); 1173 if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1)) 1174 return -ETIMEDOUT; 1175 1176 netsec_write(priv, MAC_REG_DESC_INIT, 1); 1177 if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1)) 1178 return -ETIMEDOUT; 1179 1180 if (netsec_mac_write(priv, GMAC_REG_BMR, 1181 NETSEC_GMAC_BMR_REG_COMMON)) 1182 return -ETIMEDOUT; 1183 if (netsec_mac_write(priv, GMAC_REG_RDLAR, 1184 NETSEC_GMAC_RDLAR_REG_COMMON)) 1185 return -ETIMEDOUT; 1186 if (netsec_mac_write(priv, GMAC_REG_TDLAR, 1187 NETSEC_GMAC_TDLAR_REG_COMMON)) 1188 return -ETIMEDOUT; 1189 if (netsec_mac_write(priv, GMAC_REG_MFFR, 0x80000001)) 1190 return -ETIMEDOUT; 1191 1192 ret = netsec_mac_update_to_phy_state(priv); 1193 if (ret) 1194 return ret; 1195 1196 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1197 if (ret) 1198 return ret; 1199 1200 value |= NETSEC_GMAC_OMR_REG_SR; 1201 value |= NETSEC_GMAC_OMR_REG_ST; 1202 1203 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1204 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1205 1206 netsec_et_set_coalesce(priv->ndev, &priv->et_coalesce); 1207 1208 if (netsec_mac_write(priv, GMAC_REG_OMR, value)) 1209 return -ETIMEDOUT; 1210 1211 return 0; 1212 } 1213 1214 static int netsec_stop_gmac(struct netsec_priv *priv) 1215 { 1216 u32 value; 1217 int ret; 1218 1219 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1220 if (ret) 1221 return ret; 1222 value &= ~NETSEC_GMAC_OMR_REG_SR; 1223 value &= ~NETSEC_GMAC_OMR_REG_ST; 1224 1225 /* disable all interrupts */ 1226 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1227 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1228 1229 return netsec_mac_write(priv, GMAC_REG_OMR, value); 1230 } 1231 1232 static void netsec_phy_adjust_link(struct net_device *ndev) 1233 { 1234 struct netsec_priv *priv = netdev_priv(ndev); 1235 1236 if (ndev->phydev->link) 1237 netsec_start_gmac(priv); 1238 else 1239 netsec_stop_gmac(priv); 1240 1241 phy_print_status(ndev->phydev); 1242 } 1243 1244 static irqreturn_t netsec_irq_handler(int irq, void *dev_id) 1245 { 1246 struct netsec_priv *priv = dev_id; 1247 u32 val, status = netsec_read(priv, NETSEC_REG_TOP_STATUS); 1248 unsigned long flags; 1249 1250 /* Disable interrupts */ 1251 if (status & NETSEC_IRQ_TX) { 1252 val = netsec_read(priv, NETSEC_REG_NRM_TX_STATUS); 1253 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val); 1254 } 1255 if (status & NETSEC_IRQ_RX) { 1256 val = netsec_read(priv, NETSEC_REG_NRM_RX_STATUS); 1257 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val); 1258 } 1259 1260 spin_lock_irqsave(&priv->reglock, flags); 1261 netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1262 spin_unlock_irqrestore(&priv->reglock, flags); 1263 1264 napi_schedule(&priv->napi); 1265 1266 return IRQ_HANDLED; 1267 } 1268 1269 static int netsec_netdev_open(struct net_device *ndev) 1270 { 1271 struct netsec_priv *priv = netdev_priv(ndev); 1272 int ret; 1273 1274 pm_runtime_get_sync(priv->dev); 1275 1276 ret = netsec_setup_rx_dring(priv); 1277 if (ret) { 1278 netif_err(priv, probe, priv->ndev, 1279 "%s: fail setup ring\n", __func__); 1280 goto err1; 1281 } 1282 1283 ret = request_irq(priv->ndev->irq, netsec_irq_handler, 1284 IRQF_SHARED, "netsec", priv); 1285 if (ret) { 1286 netif_err(priv, drv, priv->ndev, "request_irq failed\n"); 1287 goto err2; 1288 } 1289 1290 if (dev_of_node(priv->dev)) { 1291 if (!of_phy_connect(priv->ndev, priv->phy_np, 1292 netsec_phy_adjust_link, 0, 1293 priv->phy_interface)) { 1294 netif_err(priv, link, priv->ndev, "missing PHY\n"); 1295 ret = -ENODEV; 1296 goto err3; 1297 } 1298 } else { 1299 ret = phy_connect_direct(priv->ndev, priv->phydev, 1300 netsec_phy_adjust_link, 1301 priv->phy_interface); 1302 if (ret) { 1303 netif_err(priv, link, priv->ndev, 1304 "phy_connect_direct() failed (%d)\n", ret); 1305 goto err3; 1306 } 1307 } 1308 1309 phy_start(ndev->phydev); 1310 1311 netsec_start_gmac(priv); 1312 napi_enable(&priv->napi); 1313 netif_start_queue(ndev); 1314 1315 /* Enable TX+RX intr. */ 1316 netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1317 1318 return 0; 1319 err3: 1320 free_irq(priv->ndev->irq, priv); 1321 err2: 1322 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1323 err1: 1324 pm_runtime_put_sync(priv->dev); 1325 return ret; 1326 } 1327 1328 static int netsec_netdev_stop(struct net_device *ndev) 1329 { 1330 int ret; 1331 struct netsec_priv *priv = netdev_priv(ndev); 1332 1333 netif_stop_queue(priv->ndev); 1334 dma_wmb(); 1335 1336 napi_disable(&priv->napi); 1337 1338 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1339 netsec_stop_gmac(priv); 1340 1341 free_irq(priv->ndev->irq, priv); 1342 1343 netsec_uninit_pkt_dring(priv, NETSEC_RING_TX); 1344 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1345 1346 ret = netsec_reset_hardware(priv, false); 1347 1348 phy_stop(ndev->phydev); 1349 phy_disconnect(ndev->phydev); 1350 1351 pm_runtime_put_sync(priv->dev); 1352 1353 return ret; 1354 } 1355 1356 static int netsec_netdev_init(struct net_device *ndev) 1357 { 1358 struct netsec_priv *priv = netdev_priv(ndev); 1359 int ret; 1360 1361 ret = netsec_alloc_dring(priv, NETSEC_RING_TX); 1362 if (ret) 1363 return ret; 1364 1365 ret = netsec_alloc_dring(priv, NETSEC_RING_RX); 1366 if (ret) 1367 goto err1; 1368 1369 ret = netsec_reset_hardware(priv, true); 1370 if (ret) 1371 goto err2; 1372 1373 return 0; 1374 err2: 1375 netsec_free_dring(priv, NETSEC_RING_RX); 1376 err1: 1377 netsec_free_dring(priv, NETSEC_RING_TX); 1378 return ret; 1379 } 1380 1381 static void netsec_netdev_uninit(struct net_device *ndev) 1382 { 1383 struct netsec_priv *priv = netdev_priv(ndev); 1384 1385 netsec_free_dring(priv, NETSEC_RING_RX); 1386 netsec_free_dring(priv, NETSEC_RING_TX); 1387 } 1388 1389 static int netsec_netdev_set_features(struct net_device *ndev, 1390 netdev_features_t features) 1391 { 1392 struct netsec_priv *priv = netdev_priv(ndev); 1393 1394 priv->rx_cksum_offload_flag = !!(features & NETIF_F_RXCSUM); 1395 1396 return 0; 1397 } 1398 1399 static int netsec_netdev_ioctl(struct net_device *ndev, struct ifreq *ifr, 1400 int cmd) 1401 { 1402 return phy_mii_ioctl(ndev->phydev, ifr, cmd); 1403 } 1404 1405 static const struct net_device_ops netsec_netdev_ops = { 1406 .ndo_init = netsec_netdev_init, 1407 .ndo_uninit = netsec_netdev_uninit, 1408 .ndo_open = netsec_netdev_open, 1409 .ndo_stop = netsec_netdev_stop, 1410 .ndo_start_xmit = netsec_netdev_start_xmit, 1411 .ndo_set_features = netsec_netdev_set_features, 1412 .ndo_set_mac_address = eth_mac_addr, 1413 .ndo_validate_addr = eth_validate_addr, 1414 .ndo_do_ioctl = netsec_netdev_ioctl, 1415 }; 1416 1417 static int netsec_of_probe(struct platform_device *pdev, 1418 struct netsec_priv *priv) 1419 { 1420 priv->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); 1421 if (!priv->phy_np) { 1422 dev_err(&pdev->dev, "missing required property 'phy-handle'\n"); 1423 return -EINVAL; 1424 } 1425 1426 priv->clk = devm_clk_get(&pdev->dev, NULL); /* get by 'phy_ref_clk' */ 1427 if (IS_ERR(priv->clk)) { 1428 dev_err(&pdev->dev, "phy_ref_clk not found\n"); 1429 return PTR_ERR(priv->clk); 1430 } 1431 priv->freq = clk_get_rate(priv->clk); 1432 1433 return 0; 1434 } 1435 1436 static int netsec_acpi_probe(struct platform_device *pdev, 1437 struct netsec_priv *priv, u32 *phy_addr) 1438 { 1439 int ret; 1440 1441 if (!IS_ENABLED(CONFIG_ACPI)) 1442 return -ENODEV; 1443 1444 ret = device_property_read_u32(&pdev->dev, "phy-channel", phy_addr); 1445 if (ret) { 1446 dev_err(&pdev->dev, 1447 "missing required property 'phy-channel'\n"); 1448 return ret; 1449 } 1450 1451 ret = device_property_read_u32(&pdev->dev, 1452 "socionext,phy-clock-frequency", 1453 &priv->freq); 1454 if (ret) 1455 dev_err(&pdev->dev, 1456 "missing required property 'socionext,phy-clock-frequency'\n"); 1457 return ret; 1458 } 1459 1460 static void netsec_unregister_mdio(struct netsec_priv *priv) 1461 { 1462 struct phy_device *phydev = priv->phydev; 1463 1464 if (!dev_of_node(priv->dev) && phydev) { 1465 phy_device_remove(phydev); 1466 phy_device_free(phydev); 1467 } 1468 1469 mdiobus_unregister(priv->mii_bus); 1470 } 1471 1472 static int netsec_register_mdio(struct netsec_priv *priv, u32 phy_addr) 1473 { 1474 struct mii_bus *bus; 1475 int ret; 1476 1477 bus = devm_mdiobus_alloc(priv->dev); 1478 if (!bus) 1479 return -ENOMEM; 1480 1481 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(priv->dev)); 1482 bus->priv = priv; 1483 bus->name = "SNI NETSEC MDIO"; 1484 bus->read = netsec_phy_read; 1485 bus->write = netsec_phy_write; 1486 bus->parent = priv->dev; 1487 priv->mii_bus = bus; 1488 1489 if (dev_of_node(priv->dev)) { 1490 struct device_node *mdio_node, *parent = dev_of_node(priv->dev); 1491 1492 mdio_node = of_get_child_by_name(parent, "mdio"); 1493 if (mdio_node) { 1494 parent = mdio_node; 1495 } else { 1496 /* older f/w doesn't populate the mdio subnode, 1497 * allow relaxed upgrade of f/w in due time. 1498 */ 1499 dev_info(priv->dev, "Upgrade f/w for mdio subnode!\n"); 1500 } 1501 1502 ret = of_mdiobus_register(bus, parent); 1503 of_node_put(mdio_node); 1504 1505 if (ret) { 1506 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1507 return ret; 1508 } 1509 } else { 1510 /* Mask out all PHYs from auto probing. */ 1511 bus->phy_mask = ~0; 1512 ret = mdiobus_register(bus); 1513 if (ret) { 1514 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1515 return ret; 1516 } 1517 1518 priv->phydev = get_phy_device(bus, phy_addr, false); 1519 if (IS_ERR(priv->phydev)) { 1520 ret = PTR_ERR(priv->phydev); 1521 dev_err(priv->dev, "get_phy_device err(%d)\n", ret); 1522 priv->phydev = NULL; 1523 return -ENODEV; 1524 } 1525 1526 ret = phy_device_register(priv->phydev); 1527 if (ret) { 1528 mdiobus_unregister(bus); 1529 dev_err(priv->dev, 1530 "phy_device_register err(%d)\n", ret); 1531 } 1532 } 1533 1534 return ret; 1535 } 1536 1537 static int netsec_probe(struct platform_device *pdev) 1538 { 1539 struct resource *mmio_res, *eeprom_res, *irq_res; 1540 u8 *mac, macbuf[ETH_ALEN]; 1541 struct netsec_priv *priv; 1542 u32 hw_ver, phy_addr = 0; 1543 struct net_device *ndev; 1544 int ret; 1545 1546 mmio_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1547 if (!mmio_res) { 1548 dev_err(&pdev->dev, "No MMIO resource found.\n"); 1549 return -ENODEV; 1550 } 1551 1552 eeprom_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1553 if (!eeprom_res) { 1554 dev_info(&pdev->dev, "No EEPROM resource found.\n"); 1555 return -ENODEV; 1556 } 1557 1558 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1559 if (!irq_res) { 1560 dev_err(&pdev->dev, "No IRQ resource found.\n"); 1561 return -ENODEV; 1562 } 1563 1564 ndev = alloc_etherdev(sizeof(*priv)); 1565 if (!ndev) 1566 return -ENOMEM; 1567 1568 priv = netdev_priv(ndev); 1569 1570 spin_lock_init(&priv->reglock); 1571 SET_NETDEV_DEV(ndev, &pdev->dev); 1572 platform_set_drvdata(pdev, priv); 1573 ndev->irq = irq_res->start; 1574 priv->dev = &pdev->dev; 1575 priv->ndev = ndev; 1576 1577 priv->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | 1578 NETIF_MSG_LINK | NETIF_MSG_PROBE; 1579 1580 priv->phy_interface = device_get_phy_mode(&pdev->dev); 1581 if (priv->phy_interface < 0) { 1582 dev_err(&pdev->dev, "missing required property 'phy-mode'\n"); 1583 ret = -ENODEV; 1584 goto free_ndev; 1585 } 1586 1587 priv->ioaddr = devm_ioremap(&pdev->dev, mmio_res->start, 1588 resource_size(mmio_res)); 1589 if (!priv->ioaddr) { 1590 dev_err(&pdev->dev, "devm_ioremap() failed\n"); 1591 ret = -ENXIO; 1592 goto free_ndev; 1593 } 1594 1595 priv->eeprom_base = devm_ioremap(&pdev->dev, eeprom_res->start, 1596 resource_size(eeprom_res)); 1597 if (!priv->eeprom_base) { 1598 dev_err(&pdev->dev, "devm_ioremap() failed for EEPROM\n"); 1599 ret = -ENXIO; 1600 goto free_ndev; 1601 } 1602 1603 mac = device_get_mac_address(&pdev->dev, macbuf, sizeof(macbuf)); 1604 if (mac) 1605 ether_addr_copy(ndev->dev_addr, mac); 1606 1607 if (priv->eeprom_base && 1608 (!mac || !is_valid_ether_addr(ndev->dev_addr))) { 1609 void __iomem *macp = priv->eeprom_base + 1610 NETSEC_EEPROM_MAC_ADDRESS; 1611 1612 ndev->dev_addr[0] = readb(macp + 3); 1613 ndev->dev_addr[1] = readb(macp + 2); 1614 ndev->dev_addr[2] = readb(macp + 1); 1615 ndev->dev_addr[3] = readb(macp + 0); 1616 ndev->dev_addr[4] = readb(macp + 7); 1617 ndev->dev_addr[5] = readb(macp + 6); 1618 } 1619 1620 if (!is_valid_ether_addr(ndev->dev_addr)) { 1621 dev_warn(&pdev->dev, "No MAC address found, using random\n"); 1622 eth_hw_addr_random(ndev); 1623 } 1624 1625 if (dev_of_node(&pdev->dev)) 1626 ret = netsec_of_probe(pdev, priv); 1627 else 1628 ret = netsec_acpi_probe(pdev, priv, &phy_addr); 1629 if (ret) 1630 goto free_ndev; 1631 1632 if (!priv->freq) { 1633 dev_err(&pdev->dev, "missing PHY reference clock frequency\n"); 1634 ret = -ENODEV; 1635 goto free_ndev; 1636 } 1637 1638 /* default for throughput */ 1639 priv->et_coalesce.rx_coalesce_usecs = 500; 1640 priv->et_coalesce.rx_max_coalesced_frames = 8; 1641 priv->et_coalesce.tx_coalesce_usecs = 500; 1642 priv->et_coalesce.tx_max_coalesced_frames = 8; 1643 1644 ret = device_property_read_u32(&pdev->dev, "max-frame-size", 1645 &ndev->max_mtu); 1646 if (ret < 0) 1647 ndev->max_mtu = ETH_DATA_LEN; 1648 1649 /* runtime_pm coverage just for probe, open/close also cover it */ 1650 pm_runtime_enable(&pdev->dev); 1651 pm_runtime_get_sync(&pdev->dev); 1652 1653 hw_ver = netsec_read(priv, NETSEC_REG_F_TAIKI_VER); 1654 /* this driver only supports F_TAIKI style NETSEC */ 1655 if (NETSEC_F_NETSEC_VER_MAJOR_NUM(hw_ver) != 1656 NETSEC_F_NETSEC_VER_MAJOR_NUM(NETSEC_REG_NETSEC_VER_F_TAIKI)) { 1657 ret = -ENODEV; 1658 goto pm_disable; 1659 } 1660 1661 dev_info(&pdev->dev, "hardware revision %d.%d\n", 1662 hw_ver >> 16, hw_ver & 0xffff); 1663 1664 netif_napi_add(ndev, &priv->napi, netsec_napi_poll, NAPI_POLL_WEIGHT); 1665 1666 ndev->netdev_ops = &netsec_netdev_ops; 1667 ndev->ethtool_ops = &netsec_ethtool_ops; 1668 1669 ndev->features |= NETIF_F_HIGHDMA | NETIF_F_RXCSUM | NETIF_F_GSO | 1670 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1671 ndev->hw_features = ndev->features; 1672 1673 priv->rx_cksum_offload_flag = true; 1674 1675 ret = netsec_register_mdio(priv, phy_addr); 1676 if (ret) 1677 goto unreg_napi; 1678 1679 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40))) 1680 dev_warn(&pdev->dev, "Failed to set DMA mask\n"); 1681 1682 ret = register_netdev(ndev); 1683 if (ret) { 1684 netif_err(priv, probe, ndev, "register_netdev() failed\n"); 1685 goto unreg_mii; 1686 } 1687 1688 pm_runtime_put_sync(&pdev->dev); 1689 return 0; 1690 1691 unreg_mii: 1692 netsec_unregister_mdio(priv); 1693 unreg_napi: 1694 netif_napi_del(&priv->napi); 1695 pm_disable: 1696 pm_runtime_put_sync(&pdev->dev); 1697 pm_runtime_disable(&pdev->dev); 1698 free_ndev: 1699 free_netdev(ndev); 1700 dev_err(&pdev->dev, "init failed\n"); 1701 1702 return ret; 1703 } 1704 1705 static int netsec_remove(struct platform_device *pdev) 1706 { 1707 struct netsec_priv *priv = platform_get_drvdata(pdev); 1708 1709 unregister_netdev(priv->ndev); 1710 1711 netsec_unregister_mdio(priv); 1712 1713 netif_napi_del(&priv->napi); 1714 1715 pm_runtime_disable(&pdev->dev); 1716 free_netdev(priv->ndev); 1717 1718 return 0; 1719 } 1720 1721 #ifdef CONFIG_PM 1722 static int netsec_runtime_suspend(struct device *dev) 1723 { 1724 struct netsec_priv *priv = dev_get_drvdata(dev); 1725 1726 netsec_write(priv, NETSEC_REG_CLK_EN, 0); 1727 1728 clk_disable_unprepare(priv->clk); 1729 1730 return 0; 1731 } 1732 1733 static int netsec_runtime_resume(struct device *dev) 1734 { 1735 struct netsec_priv *priv = dev_get_drvdata(dev); 1736 1737 clk_prepare_enable(priv->clk); 1738 1739 netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D | 1740 NETSEC_CLK_EN_REG_DOM_C | 1741 NETSEC_CLK_EN_REG_DOM_G); 1742 return 0; 1743 } 1744 #endif 1745 1746 static const struct dev_pm_ops netsec_pm_ops = { 1747 SET_RUNTIME_PM_OPS(netsec_runtime_suspend, netsec_runtime_resume, NULL) 1748 }; 1749 1750 static const struct of_device_id netsec_dt_ids[] = { 1751 { .compatible = "socionext,synquacer-netsec" }, 1752 { } 1753 }; 1754 MODULE_DEVICE_TABLE(of, netsec_dt_ids); 1755 1756 #ifdef CONFIG_ACPI 1757 static const struct acpi_device_id netsec_acpi_ids[] = { 1758 { "SCX0001" }, 1759 { } 1760 }; 1761 MODULE_DEVICE_TABLE(acpi, netsec_acpi_ids); 1762 #endif 1763 1764 static struct platform_driver netsec_driver = { 1765 .probe = netsec_probe, 1766 .remove = netsec_remove, 1767 .driver = { 1768 .name = "netsec", 1769 .pm = &netsec_pm_ops, 1770 .of_match_table = netsec_dt_ids, 1771 .acpi_match_table = ACPI_PTR(netsec_acpi_ids), 1772 }, 1773 }; 1774 module_platform_driver(netsec_driver); 1775 1776 MODULE_AUTHOR("Jassi Brar <jaswinder.singh@linaro.org>"); 1777 MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); 1778 MODULE_DESCRIPTION("NETSEC Ethernet driver"); 1779 MODULE_LICENSE("GPL"); 1780