1 // SPDX-License-Identifier: GPL-2.0+ 2 3 #include <linux/types.h> 4 #include <linux/clk.h> 5 #include <linux/platform_device.h> 6 #include <linux/pm_runtime.h> 7 #include <linux/acpi.h> 8 #include <linux/of_mdio.h> 9 #include <linux/etherdevice.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/netlink.h> 13 #include <linux/bpf.h> 14 #include <linux/bpf_trace.h> 15 16 #include <net/tcp.h> 17 #include <net/page_pool.h> 18 #include <net/ip6_checksum.h> 19 20 #define NETSEC_REG_SOFT_RST 0x104 21 #define NETSEC_REG_COM_INIT 0x120 22 23 #define NETSEC_REG_TOP_STATUS 0x200 24 #define NETSEC_IRQ_RX BIT(1) 25 #define NETSEC_IRQ_TX BIT(0) 26 27 #define NETSEC_REG_TOP_INTEN 0x204 28 #define NETSEC_REG_INTEN_SET 0x234 29 #define NETSEC_REG_INTEN_CLR 0x238 30 31 #define NETSEC_REG_NRM_TX_STATUS 0x400 32 #define NETSEC_REG_NRM_TX_INTEN 0x404 33 #define NETSEC_REG_NRM_TX_INTEN_SET 0x428 34 #define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c 35 #define NRM_TX_ST_NTOWNR BIT(17) 36 #define NRM_TX_ST_TR_ERR BIT(16) 37 #define NRM_TX_ST_TXDONE BIT(15) 38 #define NRM_TX_ST_TMREXP BIT(14) 39 40 #define NETSEC_REG_NRM_RX_STATUS 0x440 41 #define NETSEC_REG_NRM_RX_INTEN 0x444 42 #define NETSEC_REG_NRM_RX_INTEN_SET 0x468 43 #define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c 44 #define NRM_RX_ST_RC_ERR BIT(16) 45 #define NRM_RX_ST_PKTCNT BIT(15) 46 #define NRM_RX_ST_TMREXP BIT(14) 47 48 #define NETSEC_REG_PKT_CMD_BUF 0xd0 49 50 #define NETSEC_REG_CLK_EN 0x100 51 52 #define NETSEC_REG_PKT_CTRL 0x140 53 54 #define NETSEC_REG_DMA_TMR_CTRL 0x20c 55 #define NETSEC_REG_F_TAIKI_MC_VER 0x22c 56 #define NETSEC_REG_F_TAIKI_VER 0x230 57 #define NETSEC_REG_DMA_HM_CTRL 0x214 58 #define NETSEC_REG_DMA_MH_CTRL 0x220 59 #define NETSEC_REG_ADDR_DIS_CORE 0x218 60 #define NETSEC_REG_DMAC_HM_CMD_BUF 0x210 61 #define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c 62 63 #define NETSEC_REG_NRM_TX_PKTCNT 0x410 64 65 #define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414 66 #define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418 67 68 #define NETSEC_REG_NRM_TX_TMR 0x41c 69 70 #define NETSEC_REG_NRM_RX_PKTCNT 0x454 71 #define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458 72 #define NETSEC_REG_NRM_TX_TXINT_TMR 0x420 73 #define NETSEC_REG_NRM_RX_RXINT_TMR 0x460 74 75 #define NETSEC_REG_NRM_RX_TMR 0x45c 76 77 #define NETSEC_REG_NRM_TX_DESC_START_UP 0x434 78 #define NETSEC_REG_NRM_TX_DESC_START_LW 0x408 79 #define NETSEC_REG_NRM_RX_DESC_START_UP 0x474 80 #define NETSEC_REG_NRM_RX_DESC_START_LW 0x448 81 82 #define NETSEC_REG_NRM_TX_CONFIG 0x430 83 #define NETSEC_REG_NRM_RX_CONFIG 0x470 84 85 #define MAC_REG_STATUS 0x1024 86 #define MAC_REG_DATA 0x11c0 87 #define MAC_REG_CMD 0x11c4 88 #define MAC_REG_FLOW_TH 0x11cc 89 #define MAC_REG_INTF_SEL 0x11d4 90 #define MAC_REG_DESC_INIT 0x11fc 91 #define MAC_REG_DESC_SOFT_RST 0x1204 92 #define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500 93 94 #define GMAC_REG_MCR 0x0000 95 #define GMAC_REG_MFFR 0x0004 96 #define GMAC_REG_GAR 0x0010 97 #define GMAC_REG_GDR 0x0014 98 #define GMAC_REG_FCR 0x0018 99 #define GMAC_REG_BMR 0x1000 100 #define GMAC_REG_RDLAR 0x100c 101 #define GMAC_REG_TDLAR 0x1010 102 #define GMAC_REG_OMR 0x1018 103 104 #define MHZ(n) ((n) * 1000 * 1000) 105 106 #define NETSEC_TX_SHIFT_OWN_FIELD 31 107 #define NETSEC_TX_SHIFT_LD_FIELD 30 108 #define NETSEC_TX_SHIFT_DRID_FIELD 24 109 #define NETSEC_TX_SHIFT_PT_FIELD 21 110 #define NETSEC_TX_SHIFT_TDRID_FIELD 16 111 #define NETSEC_TX_SHIFT_CC_FIELD 15 112 #define NETSEC_TX_SHIFT_FS_FIELD 9 113 #define NETSEC_TX_LAST 8 114 #define NETSEC_TX_SHIFT_CO 7 115 #define NETSEC_TX_SHIFT_SO 6 116 #define NETSEC_TX_SHIFT_TRS_FIELD 4 117 118 #define NETSEC_RX_PKT_OWN_FIELD 31 119 #define NETSEC_RX_PKT_LD_FIELD 30 120 #define NETSEC_RX_PKT_SDRID_FIELD 24 121 #define NETSEC_RX_PKT_FR_FIELD 23 122 #define NETSEC_RX_PKT_ER_FIELD 21 123 #define NETSEC_RX_PKT_ERR_FIELD 16 124 #define NETSEC_RX_PKT_TDRID_FIELD 12 125 #define NETSEC_RX_PKT_FS_FIELD 9 126 #define NETSEC_RX_PKT_LS_FIELD 8 127 #define NETSEC_RX_PKT_CO_FIELD 6 128 129 #define NETSEC_RX_PKT_ERR_MASK 3 130 131 #define NETSEC_MAX_TX_PKT_LEN 1518 132 #define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018 133 134 #define NETSEC_RING_GMAC 15 135 #define NETSEC_RING_MAX 2 136 137 #define NETSEC_TCP_SEG_LEN_MAX 1460 138 #define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960 139 140 #define NETSEC_RX_CKSUM_NOTAVAIL 0 141 #define NETSEC_RX_CKSUM_OK 1 142 #define NETSEC_RX_CKSUM_NG 2 143 144 #define NETSEC_TOP_IRQ_REG_CODE_LOAD_END BIT(20) 145 #define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4) 146 147 #define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20) 148 #define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19) 149 150 #define NETSEC_INT_PKTCNT_MAX 2047 151 152 #define NETSEC_FLOW_START_TH_MAX 95 153 #define NETSEC_FLOW_STOP_TH_MAX 95 154 #define NETSEC_FLOW_PAUSE_TIME_MIN 5 155 156 #define NETSEC_CLK_EN_REG_DOM_ALL 0x3f 157 158 #define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28) 159 #define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27) 160 #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3) 161 #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2) 162 #define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1) 163 #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0) 164 165 #define NETSEC_CLK_EN_REG_DOM_G BIT(5) 166 #define NETSEC_CLK_EN_REG_DOM_C BIT(1) 167 #define NETSEC_CLK_EN_REG_DOM_D BIT(0) 168 169 #define NETSEC_COM_INIT_REG_DB BIT(2) 170 #define NETSEC_COM_INIT_REG_CLS BIT(1) 171 #define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \ 172 NETSEC_COM_INIT_REG_DB) 173 174 #define NETSEC_SOFT_RST_REG_RESET 0 175 #define NETSEC_SOFT_RST_REG_RUN BIT(31) 176 177 #define NETSEC_DMA_CTRL_REG_STOP 1 178 #define MH_CTRL__MODE_TRANS BIT(20) 179 180 #define NETSEC_GMAC_CMD_ST_READ 0 181 #define NETSEC_GMAC_CMD_ST_WRITE BIT(28) 182 #define NETSEC_GMAC_CMD_ST_BUSY BIT(31) 183 184 #define NETSEC_GMAC_BMR_REG_COMMON 0x00412080 185 #define NETSEC_GMAC_BMR_REG_RESET 0x00020181 186 #define NETSEC_GMAC_BMR_REG_SWR 0x00000001 187 188 #define NETSEC_GMAC_OMR_REG_ST BIT(13) 189 #define NETSEC_GMAC_OMR_REG_SR BIT(1) 190 191 #define NETSEC_GMAC_MCR_REG_IBN BIT(30) 192 #define NETSEC_GMAC_MCR_REG_CST BIT(25) 193 #define NETSEC_GMAC_MCR_REG_JE BIT(20) 194 #define NETSEC_MCR_PS BIT(15) 195 #define NETSEC_GMAC_MCR_REG_FES BIT(14) 196 #define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c 197 #define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c 198 199 #define NETSEC_FCR_RFE BIT(2) 200 #define NETSEC_FCR_TFE BIT(1) 201 202 #define NETSEC_GMAC_GAR_REG_GW BIT(1) 203 #define NETSEC_GMAC_GAR_REG_GB BIT(0) 204 205 #define NETSEC_GMAC_GAR_REG_SHIFT_PA 11 206 #define NETSEC_GMAC_GAR_REG_SHIFT_GR 6 207 #define GMAC_REG_SHIFT_CR_GAR 2 208 209 #define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2 210 #define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3 211 #define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0 212 #define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1 213 #define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4 214 #define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5 215 216 #define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000 217 #define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000 218 219 #define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000 220 221 #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31) 222 #define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30) 223 #define NETSEC_REG_DESC_TMR_MODE 4 224 #define NETSEC_REG_DESC_ENDIAN 0 225 226 #define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1 227 #define NETSEC_MAC_DESC_INIT_REG_INIT 1 228 229 #define NETSEC_EEPROM_MAC_ADDRESS 0x00 230 #define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08 231 #define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C 232 #define NETSEC_EEPROM_HM_ME_SIZE 0x10 233 #define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14 234 #define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18 235 #define NETSEC_EEPROM_MH_ME_SIZE 0x1C 236 #define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20 237 #define NETSEC_EEPROM_PKT_ME_SIZE 0x24 238 239 #define DESC_NUM 256 240 241 #define NETSEC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 242 #define NETSEC_RXBUF_HEADROOM (max(XDP_PACKET_HEADROOM, NET_SKB_PAD) + \ 243 NET_IP_ALIGN) 244 #define NETSEC_RX_BUF_NON_DATA (NETSEC_RXBUF_HEADROOM + \ 245 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 246 247 #define DESC_SZ sizeof(struct netsec_de) 248 249 #define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000) 250 251 #define NETSEC_XDP_PASS 0 252 #define NETSEC_XDP_CONSUMED BIT(0) 253 #define NETSEC_XDP_TX BIT(1) 254 #define NETSEC_XDP_REDIR BIT(2) 255 #define NETSEC_XDP_RX_OK (NETSEC_XDP_PASS | NETSEC_XDP_TX | NETSEC_XDP_REDIR) 256 257 enum ring_id { 258 NETSEC_RING_TX = 0, 259 NETSEC_RING_RX 260 }; 261 262 enum buf_type { 263 TYPE_NETSEC_SKB = 0, 264 TYPE_NETSEC_XDP_TX, 265 TYPE_NETSEC_XDP_NDO, 266 }; 267 268 struct netsec_desc { 269 union { 270 struct sk_buff *skb; 271 struct xdp_frame *xdpf; 272 }; 273 dma_addr_t dma_addr; 274 void *addr; 275 u16 len; 276 u8 buf_type; 277 }; 278 279 struct netsec_desc_ring { 280 dma_addr_t desc_dma; 281 struct netsec_desc *desc; 282 void *vaddr; 283 u16 head, tail; 284 u16 xdp_xmit; /* netsec_xdp_xmit packets */ 285 bool is_xdp; 286 struct page_pool *page_pool; 287 struct xdp_rxq_info xdp_rxq; 288 spinlock_t lock; /* XDP tx queue locking */ 289 }; 290 291 struct netsec_priv { 292 struct netsec_desc_ring desc_ring[NETSEC_RING_MAX]; 293 struct ethtool_coalesce et_coalesce; 294 struct bpf_prog *xdp_prog; 295 spinlock_t reglock; /* protect reg access */ 296 struct napi_struct napi; 297 phy_interface_t phy_interface; 298 struct net_device *ndev; 299 struct device_node *phy_np; 300 struct phy_device *phydev; 301 struct mii_bus *mii_bus; 302 void __iomem *ioaddr; 303 void __iomem *eeprom_base; 304 struct device *dev; 305 struct clk *clk; 306 u32 msg_enable; 307 u32 freq; 308 u32 phy_addr; 309 bool rx_cksum_offload_flag; 310 }; 311 312 struct netsec_de { /* Netsec Descriptor layout */ 313 u32 attr; 314 u32 data_buf_addr_up; 315 u32 data_buf_addr_lw; 316 u32 buf_len_info; 317 }; 318 319 struct netsec_tx_pkt_ctrl { 320 u16 tcp_seg_len; 321 bool tcp_seg_offload_flag; 322 bool cksum_offload_flag; 323 }; 324 325 struct netsec_rx_pkt_info { 326 int rx_cksum_result; 327 int err_code; 328 bool err_flag; 329 }; 330 331 static void netsec_set_tx_de(struct netsec_priv *priv, 332 struct netsec_desc_ring *dring, 333 const struct netsec_tx_pkt_ctrl *tx_ctrl, 334 const struct netsec_desc *desc, void *buf); 335 336 static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val) 337 { 338 writel(val, priv->ioaddr + reg_addr); 339 } 340 341 static u32 netsec_read(struct netsec_priv *priv, u32 reg_addr) 342 { 343 return readl(priv->ioaddr + reg_addr); 344 } 345 346 /************* MDIO BUS OPS FOLLOW *************/ 347 348 #define TIMEOUT_SPINS_MAC 1000 349 #define TIMEOUT_SECONDARY_MS_MAC 100 350 351 static u32 netsec_clk_type(u32 freq) 352 { 353 if (freq < MHZ(35)) 354 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ; 355 if (freq < MHZ(60)) 356 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ; 357 if (freq < MHZ(100)) 358 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ; 359 if (freq < MHZ(150)) 360 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ; 361 if (freq < MHZ(250)) 362 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ; 363 364 return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ; 365 } 366 367 static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask) 368 { 369 u32 timeout = TIMEOUT_SPINS_MAC; 370 371 while (--timeout && netsec_read(priv, addr) & mask) 372 cpu_relax(); 373 if (timeout) 374 return 0; 375 376 timeout = TIMEOUT_SECONDARY_MS_MAC; 377 while (--timeout && netsec_read(priv, addr) & mask) 378 usleep_range(1000, 2000); 379 380 if (timeout) 381 return 0; 382 383 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 384 385 return -ETIMEDOUT; 386 } 387 388 static int netsec_mac_write(struct netsec_priv *priv, u32 addr, u32 value) 389 { 390 netsec_write(priv, MAC_REG_DATA, value); 391 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE); 392 return netsec_wait_while_busy(priv, 393 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 394 } 395 396 static int netsec_mac_read(struct netsec_priv *priv, u32 addr, u32 *read) 397 { 398 int ret; 399 400 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ); 401 ret = netsec_wait_while_busy(priv, 402 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 403 if (ret) 404 return ret; 405 406 *read = netsec_read(priv, MAC_REG_DATA); 407 408 return 0; 409 } 410 411 static int netsec_mac_wait_while_busy(struct netsec_priv *priv, 412 u32 addr, u32 mask) 413 { 414 u32 timeout = TIMEOUT_SPINS_MAC; 415 int ret, data; 416 417 do { 418 ret = netsec_mac_read(priv, addr, &data); 419 if (ret) 420 break; 421 cpu_relax(); 422 } while (--timeout && (data & mask)); 423 424 if (timeout) 425 return 0; 426 427 timeout = TIMEOUT_SECONDARY_MS_MAC; 428 do { 429 usleep_range(1000, 2000); 430 431 ret = netsec_mac_read(priv, addr, &data); 432 if (ret) 433 break; 434 cpu_relax(); 435 } while (--timeout && (data & mask)); 436 437 if (timeout && !ret) 438 return 0; 439 440 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 441 442 return -ETIMEDOUT; 443 } 444 445 static int netsec_mac_update_to_phy_state(struct netsec_priv *priv) 446 { 447 struct phy_device *phydev = priv->ndev->phydev; 448 u32 value = 0; 449 450 value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON : 451 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON; 452 453 if (phydev->speed != SPEED_1000) 454 value |= NETSEC_MCR_PS; 455 456 if (priv->phy_interface != PHY_INTERFACE_MODE_GMII && 457 phydev->speed == SPEED_100) 458 value |= NETSEC_GMAC_MCR_REG_FES; 459 460 value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE; 461 462 if (phy_interface_mode_is_rgmii(priv->phy_interface)) 463 value |= NETSEC_GMAC_MCR_REG_IBN; 464 465 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 466 return -ETIMEDOUT; 467 468 return 0; 469 } 470 471 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr); 472 473 static int netsec_phy_write(struct mii_bus *bus, 474 int phy_addr, int reg, u16 val) 475 { 476 int status; 477 struct netsec_priv *priv = bus->priv; 478 479 if (netsec_mac_write(priv, GMAC_REG_GDR, val)) 480 return -ETIMEDOUT; 481 if (netsec_mac_write(priv, GMAC_REG_GAR, 482 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 483 reg << NETSEC_GMAC_GAR_REG_SHIFT_GR | 484 NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB | 485 (netsec_clk_type(priv->freq) << 486 GMAC_REG_SHIFT_CR_GAR))) 487 return -ETIMEDOUT; 488 489 status = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 490 NETSEC_GMAC_GAR_REG_GB); 491 492 /* Developerbox implements RTL8211E PHY and there is 493 * a compatibility problem with F_GMAC4. 494 * RTL8211E expects MDC clock must be kept toggling for several 495 * clock cycle with MDIO high before entering the IDLE state. 496 * To meet this requirement, netsec driver needs to issue dummy 497 * read(e.g. read PHYID1(offset 0x2) register) right after write. 498 */ 499 netsec_phy_read(bus, phy_addr, MII_PHYSID1); 500 501 return status; 502 } 503 504 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr) 505 { 506 struct netsec_priv *priv = bus->priv; 507 u32 data; 508 int ret; 509 510 if (netsec_mac_write(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB | 511 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 512 reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR | 513 (netsec_clk_type(priv->freq) << 514 GMAC_REG_SHIFT_CR_GAR))) 515 return -ETIMEDOUT; 516 517 ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 518 NETSEC_GMAC_GAR_REG_GB); 519 if (ret) 520 return ret; 521 522 ret = netsec_mac_read(priv, GMAC_REG_GDR, &data); 523 if (ret) 524 return ret; 525 526 return data; 527 } 528 529 /************* ETHTOOL_OPS FOLLOW *************/ 530 531 static void netsec_et_get_drvinfo(struct net_device *net_device, 532 struct ethtool_drvinfo *info) 533 { 534 strlcpy(info->driver, "netsec", sizeof(info->driver)); 535 strlcpy(info->bus_info, dev_name(net_device->dev.parent), 536 sizeof(info->bus_info)); 537 } 538 539 static int netsec_et_get_coalesce(struct net_device *net_device, 540 struct ethtool_coalesce *et_coalesce) 541 { 542 struct netsec_priv *priv = netdev_priv(net_device); 543 544 *et_coalesce = priv->et_coalesce; 545 546 return 0; 547 } 548 549 static int netsec_et_set_coalesce(struct net_device *net_device, 550 struct ethtool_coalesce *et_coalesce) 551 { 552 struct netsec_priv *priv = netdev_priv(net_device); 553 554 priv->et_coalesce = *et_coalesce; 555 556 if (priv->et_coalesce.tx_coalesce_usecs < 50) 557 priv->et_coalesce.tx_coalesce_usecs = 50; 558 if (priv->et_coalesce.tx_max_coalesced_frames < 1) 559 priv->et_coalesce.tx_max_coalesced_frames = 1; 560 561 netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT, 562 priv->et_coalesce.tx_max_coalesced_frames); 563 netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR, 564 priv->et_coalesce.tx_coalesce_usecs); 565 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE); 566 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP); 567 568 if (priv->et_coalesce.rx_coalesce_usecs < 50) 569 priv->et_coalesce.rx_coalesce_usecs = 50; 570 if (priv->et_coalesce.rx_max_coalesced_frames < 1) 571 priv->et_coalesce.rx_max_coalesced_frames = 1; 572 573 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT, 574 priv->et_coalesce.rx_max_coalesced_frames); 575 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR, 576 priv->et_coalesce.rx_coalesce_usecs); 577 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT); 578 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP); 579 580 return 0; 581 } 582 583 static u32 netsec_et_get_msglevel(struct net_device *dev) 584 { 585 struct netsec_priv *priv = netdev_priv(dev); 586 587 return priv->msg_enable; 588 } 589 590 static void netsec_et_set_msglevel(struct net_device *dev, u32 datum) 591 { 592 struct netsec_priv *priv = netdev_priv(dev); 593 594 priv->msg_enable = datum; 595 } 596 597 static const struct ethtool_ops netsec_ethtool_ops = { 598 .get_drvinfo = netsec_et_get_drvinfo, 599 .get_link_ksettings = phy_ethtool_get_link_ksettings, 600 .set_link_ksettings = phy_ethtool_set_link_ksettings, 601 .get_link = ethtool_op_get_link, 602 .get_coalesce = netsec_et_get_coalesce, 603 .set_coalesce = netsec_et_set_coalesce, 604 .get_msglevel = netsec_et_get_msglevel, 605 .set_msglevel = netsec_et_set_msglevel, 606 }; 607 608 /************* NETDEV_OPS FOLLOW *************/ 609 610 611 static void netsec_set_rx_de(struct netsec_priv *priv, 612 struct netsec_desc_ring *dring, u16 idx, 613 const struct netsec_desc *desc) 614 { 615 struct netsec_de *de = dring->vaddr + DESC_SZ * idx; 616 u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) | 617 (1 << NETSEC_RX_PKT_FS_FIELD) | 618 (1 << NETSEC_RX_PKT_LS_FIELD); 619 620 if (idx == DESC_NUM - 1) 621 attr |= (1 << NETSEC_RX_PKT_LD_FIELD); 622 623 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 624 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 625 de->buf_len_info = desc->len; 626 de->attr = attr; 627 dma_wmb(); 628 629 dring->desc[idx].dma_addr = desc->dma_addr; 630 dring->desc[idx].addr = desc->addr; 631 dring->desc[idx].len = desc->len; 632 } 633 634 static bool netsec_clean_tx_dring(struct netsec_priv *priv) 635 { 636 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 637 unsigned int pkts, bytes; 638 struct netsec_de *entry; 639 int tail = dring->tail; 640 int cnt = 0; 641 642 if (dring->is_xdp) 643 spin_lock(&dring->lock); 644 645 pkts = 0; 646 bytes = 0; 647 entry = dring->vaddr + DESC_SZ * tail; 648 649 while (!(entry->attr & (1U << NETSEC_TX_SHIFT_OWN_FIELD)) && 650 cnt < DESC_NUM) { 651 struct netsec_desc *desc; 652 int eop; 653 654 desc = &dring->desc[tail]; 655 eop = (entry->attr >> NETSEC_TX_LAST) & 1; 656 dma_rmb(); 657 658 if (desc->buf_type == TYPE_NETSEC_SKB) 659 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 660 DMA_TO_DEVICE); 661 else if (desc->buf_type == TYPE_NETSEC_XDP_NDO) 662 dma_unmap_single(priv->dev, desc->dma_addr, 663 desc->len, DMA_TO_DEVICE); 664 665 if (!eop) 666 goto next; 667 668 if (desc->buf_type == TYPE_NETSEC_SKB) { 669 bytes += desc->skb->len; 670 dev_kfree_skb(desc->skb); 671 } else { 672 xdp_return_frame(desc->xdpf); 673 } 674 next: 675 /* clean up so netsec_uninit_pkt_dring() won't free the skb 676 * again 677 */ 678 *desc = (struct netsec_desc){}; 679 680 /* entry->attr is not going to be accessed by the NIC until 681 * netsec_set_tx_de() is called. No need for a dma_wmb() here 682 */ 683 entry->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD; 684 /* move tail ahead */ 685 dring->tail = (tail + 1) % DESC_NUM; 686 687 tail = dring->tail; 688 entry = dring->vaddr + DESC_SZ * tail; 689 cnt++; 690 } 691 if (dring->is_xdp) 692 spin_unlock(&dring->lock); 693 694 if (!cnt) 695 return false; 696 697 /* reading the register clears the irq */ 698 netsec_read(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT); 699 700 priv->ndev->stats.tx_packets += cnt; 701 priv->ndev->stats.tx_bytes += bytes; 702 703 netdev_completed_queue(priv->ndev, cnt, bytes); 704 705 return true; 706 } 707 708 static void netsec_process_tx(struct netsec_priv *priv) 709 { 710 struct net_device *ndev = priv->ndev; 711 bool cleaned; 712 713 cleaned = netsec_clean_tx_dring(priv); 714 715 if (cleaned && netif_queue_stopped(ndev)) { 716 /* Make sure we update the value, anyone stopping the queue 717 * after this will read the proper consumer idx 718 */ 719 smp_wmb(); 720 netif_wake_queue(ndev); 721 } 722 } 723 724 static void *netsec_alloc_rx_data(struct netsec_priv *priv, 725 dma_addr_t *dma_handle, u16 *desc_len) 726 727 { 728 729 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 730 struct page *page; 731 732 page = page_pool_dev_alloc_pages(dring->page_pool); 733 if (!page) 734 return NULL; 735 736 /* We allocate the same buffer length for XDP and non-XDP cases. 737 * page_pool API will map the whole page, skip what's needed for 738 * network payloads and/or XDP 739 */ 740 *dma_handle = page_pool_get_dma_addr(page) + NETSEC_RXBUF_HEADROOM; 741 /* Make sure the incoming payload fits in the page for XDP and non-XDP 742 * cases and reserve enough space for headroom + skb_shared_info 743 */ 744 *desc_len = PAGE_SIZE - NETSEC_RX_BUF_NON_DATA; 745 746 return page_address(page); 747 } 748 749 static void netsec_rx_fill(struct netsec_priv *priv, u16 from, u16 num) 750 { 751 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 752 u16 idx = from; 753 754 while (num) { 755 netsec_set_rx_de(priv, dring, idx, &dring->desc[idx]); 756 idx++; 757 if (idx >= DESC_NUM) 758 idx = 0; 759 num--; 760 } 761 } 762 763 static void netsec_xdp_ring_tx_db(struct netsec_priv *priv, u16 pkts) 764 { 765 if (likely(pkts)) 766 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, pkts); 767 } 768 769 static void netsec_finalize_xdp_rx(struct netsec_priv *priv, u32 xdp_res, 770 u16 pkts) 771 { 772 if (xdp_res & NETSEC_XDP_REDIR) 773 xdp_do_flush_map(); 774 775 if (xdp_res & NETSEC_XDP_TX) 776 netsec_xdp_ring_tx_db(priv, pkts); 777 } 778 779 /* The current driver only supports 1 Txq, this should run under spin_lock() */ 780 static u32 netsec_xdp_queue_one(struct netsec_priv *priv, 781 struct xdp_frame *xdpf, bool is_ndo) 782 783 { 784 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX]; 785 struct page *page = virt_to_page(xdpf->data); 786 struct netsec_tx_pkt_ctrl tx_ctrl = {}; 787 struct netsec_desc tx_desc; 788 dma_addr_t dma_handle; 789 u16 filled; 790 791 if (tx_ring->head >= tx_ring->tail) 792 filled = tx_ring->head - tx_ring->tail; 793 else 794 filled = tx_ring->head + DESC_NUM - tx_ring->tail; 795 796 if (DESC_NUM - filled <= 1) 797 return NETSEC_XDP_CONSUMED; 798 799 if (is_ndo) { 800 /* this is for ndo_xdp_xmit, the buffer needs mapping before 801 * sending 802 */ 803 dma_handle = dma_map_single(priv->dev, xdpf->data, xdpf->len, 804 DMA_TO_DEVICE); 805 if (dma_mapping_error(priv->dev, dma_handle)) 806 return NETSEC_XDP_CONSUMED; 807 tx_desc.buf_type = TYPE_NETSEC_XDP_NDO; 808 } else { 809 /* This is the device Rx buffer from page_pool. No need to remap 810 * just sync and send it 811 */ 812 struct netsec_desc_ring *rx_ring = 813 &priv->desc_ring[NETSEC_RING_RX]; 814 enum dma_data_direction dma_dir = 815 page_pool_get_dma_dir(rx_ring->page_pool); 816 817 dma_handle = page_pool_get_dma_addr(page) + 818 NETSEC_RXBUF_HEADROOM; 819 dma_sync_single_for_device(priv->dev, dma_handle, xdpf->len, 820 dma_dir); 821 tx_desc.buf_type = TYPE_NETSEC_XDP_TX; 822 } 823 824 tx_desc.dma_addr = dma_handle; 825 tx_desc.addr = xdpf->data; 826 tx_desc.len = xdpf->len; 827 828 netsec_set_tx_de(priv, tx_ring, &tx_ctrl, &tx_desc, xdpf); 829 830 return NETSEC_XDP_TX; 831 } 832 833 static u32 netsec_xdp_xmit_back(struct netsec_priv *priv, struct xdp_buff *xdp) 834 { 835 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX]; 836 struct xdp_frame *xdpf = convert_to_xdp_frame(xdp); 837 u32 ret; 838 839 if (unlikely(!xdpf)) 840 return NETSEC_XDP_CONSUMED; 841 842 spin_lock(&tx_ring->lock); 843 ret = netsec_xdp_queue_one(priv, xdpf, false); 844 spin_unlock(&tx_ring->lock); 845 846 return ret; 847 } 848 849 static u32 netsec_run_xdp(struct netsec_priv *priv, struct bpf_prog *prog, 850 struct xdp_buff *xdp) 851 { 852 u32 ret = NETSEC_XDP_PASS; 853 int err; 854 u32 act; 855 856 act = bpf_prog_run_xdp(prog, xdp); 857 858 switch (act) { 859 case XDP_PASS: 860 ret = NETSEC_XDP_PASS; 861 break; 862 case XDP_TX: 863 ret = netsec_xdp_xmit_back(priv, xdp); 864 if (ret != NETSEC_XDP_TX) 865 xdp_return_buff(xdp); 866 break; 867 case XDP_REDIRECT: 868 err = xdp_do_redirect(priv->ndev, xdp, prog); 869 if (!err) { 870 ret = NETSEC_XDP_REDIR; 871 } else { 872 ret = NETSEC_XDP_CONSUMED; 873 xdp_return_buff(xdp); 874 } 875 break; 876 default: 877 bpf_warn_invalid_xdp_action(act); 878 /* fall through */ 879 case XDP_ABORTED: 880 trace_xdp_exception(priv->ndev, prog, act); 881 /* fall through -- handle aborts by dropping packet */ 882 case XDP_DROP: 883 ret = NETSEC_XDP_CONSUMED; 884 xdp_return_buff(xdp); 885 break; 886 } 887 888 return ret; 889 } 890 891 static int netsec_process_rx(struct netsec_priv *priv, int budget) 892 { 893 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 894 struct net_device *ndev = priv->ndev; 895 struct netsec_rx_pkt_info rx_info; 896 enum dma_data_direction dma_dir; 897 struct bpf_prog *xdp_prog; 898 struct sk_buff *skb = NULL; 899 u16 xdp_xmit = 0; 900 u32 xdp_act = 0; 901 int done = 0; 902 903 rcu_read_lock(); 904 xdp_prog = READ_ONCE(priv->xdp_prog); 905 dma_dir = page_pool_get_dma_dir(dring->page_pool); 906 907 while (done < budget) { 908 u16 idx = dring->tail; 909 struct netsec_de *de = dring->vaddr + (DESC_SZ * idx); 910 struct netsec_desc *desc = &dring->desc[idx]; 911 struct page *page = virt_to_page(desc->addr); 912 u32 xdp_result = XDP_PASS; 913 u16 pkt_len, desc_len; 914 dma_addr_t dma_handle; 915 struct xdp_buff xdp; 916 void *buf_addr; 917 918 if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD)) { 919 /* reading the register clears the irq */ 920 netsec_read(priv, NETSEC_REG_NRM_RX_PKTCNT); 921 break; 922 } 923 924 /* This barrier is needed to keep us from reading 925 * any other fields out of the netsec_de until we have 926 * verified the descriptor has been written back 927 */ 928 dma_rmb(); 929 done++; 930 931 pkt_len = de->buf_len_info >> 16; 932 rx_info.err_code = (de->attr >> NETSEC_RX_PKT_ERR_FIELD) & 933 NETSEC_RX_PKT_ERR_MASK; 934 rx_info.err_flag = (de->attr >> NETSEC_RX_PKT_ER_FIELD) & 1; 935 if (rx_info.err_flag) { 936 netif_err(priv, drv, priv->ndev, 937 "%s: rx fail err(%d)\n", __func__, 938 rx_info.err_code); 939 ndev->stats.rx_dropped++; 940 dring->tail = (dring->tail + 1) % DESC_NUM; 941 /* reuse buffer page frag */ 942 netsec_rx_fill(priv, idx, 1); 943 continue; 944 } 945 rx_info.rx_cksum_result = 946 (de->attr >> NETSEC_RX_PKT_CO_FIELD) & 3; 947 948 /* allocate a fresh buffer and map it to the hardware. 949 * This will eventually replace the old buffer in the hardware 950 */ 951 buf_addr = netsec_alloc_rx_data(priv, &dma_handle, &desc_len); 952 953 if (unlikely(!buf_addr)) 954 break; 955 956 dma_sync_single_for_cpu(priv->dev, desc->dma_addr, pkt_len, 957 dma_dir); 958 prefetch(desc->addr); 959 960 xdp.data_hard_start = desc->addr; 961 xdp.data = desc->addr + NETSEC_RXBUF_HEADROOM; 962 xdp_set_data_meta_invalid(&xdp); 963 xdp.data_end = xdp.data + pkt_len; 964 xdp.rxq = &dring->xdp_rxq; 965 966 if (xdp_prog) { 967 xdp_result = netsec_run_xdp(priv, xdp_prog, &xdp); 968 if (xdp_result != NETSEC_XDP_PASS) { 969 xdp_act |= xdp_result; 970 if (xdp_result == NETSEC_XDP_TX) 971 xdp_xmit++; 972 goto next; 973 } 974 } 975 skb = build_skb(desc->addr, desc->len + NETSEC_RX_BUF_NON_DATA); 976 977 if (unlikely(!skb)) { 978 /* If skb fails recycle_direct will either unmap and 979 * free the page or refill the cache depending on the 980 * cache state. Since we paid the allocation cost if 981 * building an skb fails try to put the page into cache 982 */ 983 page_pool_recycle_direct(dring->page_pool, page); 984 netif_err(priv, drv, priv->ndev, 985 "rx failed to build skb\n"); 986 break; 987 } 988 page_pool_release_page(dring->page_pool, page); 989 990 skb_reserve(skb, xdp.data - xdp.data_hard_start); 991 skb_put(skb, xdp.data_end - xdp.data); 992 skb->protocol = eth_type_trans(skb, priv->ndev); 993 994 if (priv->rx_cksum_offload_flag && 995 rx_info.rx_cksum_result == NETSEC_RX_CKSUM_OK) 996 skb->ip_summed = CHECKSUM_UNNECESSARY; 997 998 next: 999 if ((skb && napi_gro_receive(&priv->napi, skb) != GRO_DROP) || 1000 xdp_result & NETSEC_XDP_RX_OK) { 1001 ndev->stats.rx_packets++; 1002 ndev->stats.rx_bytes += xdp.data_end - xdp.data; 1003 } 1004 1005 /* Update the descriptor with fresh buffers */ 1006 desc->len = desc_len; 1007 desc->dma_addr = dma_handle; 1008 desc->addr = buf_addr; 1009 1010 netsec_rx_fill(priv, idx, 1); 1011 dring->tail = (dring->tail + 1) % DESC_NUM; 1012 } 1013 netsec_finalize_xdp_rx(priv, xdp_act, xdp_xmit); 1014 1015 rcu_read_unlock(); 1016 1017 return done; 1018 } 1019 1020 static int netsec_napi_poll(struct napi_struct *napi, int budget) 1021 { 1022 struct netsec_priv *priv; 1023 int done; 1024 1025 priv = container_of(napi, struct netsec_priv, napi); 1026 1027 netsec_process_tx(priv); 1028 done = netsec_process_rx(priv, budget); 1029 1030 if (done < budget && napi_complete_done(napi, done)) { 1031 unsigned long flags; 1032 1033 spin_lock_irqsave(&priv->reglock, flags); 1034 netsec_write(priv, NETSEC_REG_INTEN_SET, 1035 NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1036 spin_unlock_irqrestore(&priv->reglock, flags); 1037 } 1038 1039 return done; 1040 } 1041 1042 static void netsec_set_tx_de(struct netsec_priv *priv, 1043 struct netsec_desc_ring *dring, 1044 const struct netsec_tx_pkt_ctrl *tx_ctrl, 1045 const struct netsec_desc *desc, void *buf) 1046 { 1047 int idx = dring->head; 1048 struct netsec_de *de; 1049 u32 attr; 1050 1051 de = dring->vaddr + (DESC_SZ * idx); 1052 1053 attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) | 1054 (1 << NETSEC_TX_SHIFT_PT_FIELD) | 1055 (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) | 1056 (1 << NETSEC_TX_SHIFT_FS_FIELD) | 1057 (1 << NETSEC_TX_LAST) | 1058 (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) | 1059 (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) | 1060 (1 << NETSEC_TX_SHIFT_TRS_FIELD); 1061 if (idx == DESC_NUM - 1) 1062 attr |= (1 << NETSEC_TX_SHIFT_LD_FIELD); 1063 1064 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 1065 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 1066 de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len; 1067 de->attr = attr; 1068 /* under spin_lock if using XDP */ 1069 if (!dring->is_xdp) 1070 dma_wmb(); 1071 1072 dring->desc[idx] = *desc; 1073 if (desc->buf_type == TYPE_NETSEC_SKB) 1074 dring->desc[idx].skb = buf; 1075 else if (desc->buf_type == TYPE_NETSEC_XDP_TX || 1076 desc->buf_type == TYPE_NETSEC_XDP_NDO) 1077 dring->desc[idx].xdpf = buf; 1078 1079 /* move head ahead */ 1080 dring->head = (dring->head + 1) % DESC_NUM; 1081 } 1082 1083 static int netsec_desc_used(struct netsec_desc_ring *dring) 1084 { 1085 int used; 1086 1087 if (dring->head >= dring->tail) 1088 used = dring->head - dring->tail; 1089 else 1090 used = dring->head + DESC_NUM - dring->tail; 1091 1092 return used; 1093 } 1094 1095 static int netsec_check_stop_tx(struct netsec_priv *priv, int used) 1096 { 1097 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 1098 1099 /* keep tail from touching the queue */ 1100 if (DESC_NUM - used < 2) { 1101 netif_stop_queue(priv->ndev); 1102 1103 /* Make sure we read the updated value in case 1104 * descriptors got freed 1105 */ 1106 smp_rmb(); 1107 1108 used = netsec_desc_used(dring); 1109 if (DESC_NUM - used < 2) 1110 return NETDEV_TX_BUSY; 1111 1112 netif_wake_queue(priv->ndev); 1113 } 1114 1115 return 0; 1116 } 1117 1118 static netdev_tx_t netsec_netdev_start_xmit(struct sk_buff *skb, 1119 struct net_device *ndev) 1120 { 1121 struct netsec_priv *priv = netdev_priv(ndev); 1122 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 1123 struct netsec_tx_pkt_ctrl tx_ctrl = {}; 1124 struct netsec_desc tx_desc; 1125 u16 tso_seg_len = 0; 1126 int filled; 1127 1128 if (dring->is_xdp) 1129 spin_lock_bh(&dring->lock); 1130 filled = netsec_desc_used(dring); 1131 if (netsec_check_stop_tx(priv, filled)) { 1132 if (dring->is_xdp) 1133 spin_unlock_bh(&dring->lock); 1134 net_warn_ratelimited("%s %s Tx queue full\n", 1135 dev_name(priv->dev), ndev->name); 1136 return NETDEV_TX_BUSY; 1137 } 1138 1139 if (skb->ip_summed == CHECKSUM_PARTIAL) 1140 tx_ctrl.cksum_offload_flag = true; 1141 1142 if (skb_is_gso(skb)) 1143 tso_seg_len = skb_shinfo(skb)->gso_size; 1144 1145 if (tso_seg_len > 0) { 1146 if (skb->protocol == htons(ETH_P_IP)) { 1147 ip_hdr(skb)->tot_len = 0; 1148 tcp_hdr(skb)->check = 1149 ~tcp_v4_check(0, ip_hdr(skb)->saddr, 1150 ip_hdr(skb)->daddr, 0); 1151 } else { 1152 ipv6_hdr(skb)->payload_len = 0; 1153 tcp_hdr(skb)->check = 1154 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 1155 &ipv6_hdr(skb)->daddr, 1156 0, IPPROTO_TCP, 0); 1157 } 1158 1159 tx_ctrl.tcp_seg_offload_flag = true; 1160 tx_ctrl.tcp_seg_len = tso_seg_len; 1161 } 1162 1163 tx_desc.dma_addr = dma_map_single(priv->dev, skb->data, 1164 skb_headlen(skb), DMA_TO_DEVICE); 1165 if (dma_mapping_error(priv->dev, tx_desc.dma_addr)) { 1166 if (dring->is_xdp) 1167 spin_unlock_bh(&dring->lock); 1168 netif_err(priv, drv, priv->ndev, 1169 "%s: DMA mapping failed\n", __func__); 1170 ndev->stats.tx_dropped++; 1171 dev_kfree_skb_any(skb); 1172 return NETDEV_TX_OK; 1173 } 1174 tx_desc.addr = skb->data; 1175 tx_desc.len = skb_headlen(skb); 1176 tx_desc.buf_type = TYPE_NETSEC_SKB; 1177 1178 skb_tx_timestamp(skb); 1179 netdev_sent_queue(priv->ndev, skb->len); 1180 1181 netsec_set_tx_de(priv, dring, &tx_ctrl, &tx_desc, skb); 1182 if (dring->is_xdp) 1183 spin_unlock_bh(&dring->lock); 1184 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */ 1185 1186 return NETDEV_TX_OK; 1187 } 1188 1189 static void netsec_uninit_pkt_dring(struct netsec_priv *priv, int id) 1190 { 1191 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 1192 struct netsec_desc *desc; 1193 u16 idx; 1194 1195 if (!dring->vaddr || !dring->desc) 1196 return; 1197 for (idx = 0; idx < DESC_NUM; idx++) { 1198 desc = &dring->desc[idx]; 1199 if (!desc->addr) 1200 continue; 1201 1202 if (id == NETSEC_RING_RX) { 1203 struct page *page = virt_to_page(desc->addr); 1204 1205 page_pool_put_page(dring->page_pool, page, false); 1206 } else if (id == NETSEC_RING_TX) { 1207 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 1208 DMA_TO_DEVICE); 1209 dev_kfree_skb(desc->skb); 1210 } 1211 } 1212 1213 /* Rx is currently using page_pool 1214 * since the pool is created during netsec_setup_rx_dring(), we need to 1215 * free the pool manually if the registration failed 1216 */ 1217 if (id == NETSEC_RING_RX) { 1218 if (xdp_rxq_info_is_reg(&dring->xdp_rxq)) 1219 xdp_rxq_info_unreg(&dring->xdp_rxq); 1220 else 1221 page_pool_free(dring->page_pool); 1222 } 1223 1224 memset(dring->desc, 0, sizeof(struct netsec_desc) * DESC_NUM); 1225 memset(dring->vaddr, 0, DESC_SZ * DESC_NUM); 1226 1227 dring->head = 0; 1228 dring->tail = 0; 1229 1230 if (id == NETSEC_RING_TX) 1231 netdev_reset_queue(priv->ndev); 1232 } 1233 1234 static void netsec_free_dring(struct netsec_priv *priv, int id) 1235 { 1236 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 1237 1238 if (dring->vaddr) { 1239 dma_free_coherent(priv->dev, DESC_SZ * DESC_NUM, 1240 dring->vaddr, dring->desc_dma); 1241 dring->vaddr = NULL; 1242 } 1243 1244 kfree(dring->desc); 1245 dring->desc = NULL; 1246 } 1247 1248 static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id) 1249 { 1250 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 1251 1252 dring->vaddr = dma_alloc_coherent(priv->dev, DESC_SZ * DESC_NUM, 1253 &dring->desc_dma, GFP_KERNEL); 1254 if (!dring->vaddr) 1255 goto err; 1256 1257 dring->desc = kcalloc(DESC_NUM, sizeof(*dring->desc), GFP_KERNEL); 1258 if (!dring->desc) 1259 goto err; 1260 1261 return 0; 1262 err: 1263 netsec_free_dring(priv, id); 1264 1265 return -ENOMEM; 1266 } 1267 1268 static void netsec_setup_tx_dring(struct netsec_priv *priv) 1269 { 1270 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 1271 struct bpf_prog *xdp_prog = READ_ONCE(priv->xdp_prog); 1272 int i; 1273 1274 for (i = 0; i < DESC_NUM; i++) { 1275 struct netsec_de *de; 1276 1277 de = dring->vaddr + (DESC_SZ * i); 1278 /* de->attr is not going to be accessed by the NIC 1279 * until netsec_set_tx_de() is called. 1280 * No need for a dma_wmb() here 1281 */ 1282 de->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD; 1283 } 1284 1285 if (xdp_prog) 1286 dring->is_xdp = true; 1287 else 1288 dring->is_xdp = false; 1289 1290 } 1291 1292 static int netsec_setup_rx_dring(struct netsec_priv *priv) 1293 { 1294 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 1295 struct bpf_prog *xdp_prog = READ_ONCE(priv->xdp_prog); 1296 struct page_pool_params pp_params = { 0 }; 1297 int i, err; 1298 1299 pp_params.order = 0; 1300 /* internal DMA mapping in page_pool */ 1301 pp_params.flags = PP_FLAG_DMA_MAP; 1302 pp_params.pool_size = DESC_NUM; 1303 pp_params.nid = cpu_to_node(0); 1304 pp_params.dev = priv->dev; 1305 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 1306 1307 dring->page_pool = page_pool_create(&pp_params); 1308 if (IS_ERR(dring->page_pool)) { 1309 err = PTR_ERR(dring->page_pool); 1310 dring->page_pool = NULL; 1311 goto err_out; 1312 } 1313 1314 for (i = 0; i < DESC_NUM; i++) { 1315 struct netsec_desc *desc = &dring->desc[i]; 1316 dma_addr_t dma_handle; 1317 void *buf; 1318 u16 len; 1319 1320 buf = netsec_alloc_rx_data(priv, &dma_handle, &len); 1321 1322 if (!buf) { 1323 err = -ENOMEM; 1324 goto err_out; 1325 } 1326 desc->dma_addr = dma_handle; 1327 desc->addr = buf; 1328 desc->len = len; 1329 } 1330 1331 netsec_rx_fill(priv, 0, DESC_NUM); 1332 err = xdp_rxq_info_reg(&dring->xdp_rxq, priv->ndev, 0); 1333 if (err) 1334 goto err_out; 1335 1336 err = xdp_rxq_info_reg_mem_model(&dring->xdp_rxq, MEM_TYPE_PAGE_POOL, 1337 dring->page_pool); 1338 if (err) 1339 goto err_out; 1340 1341 return 0; 1342 1343 err_out: 1344 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1345 return err; 1346 } 1347 1348 static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg, 1349 u32 addr_h, u32 addr_l, u32 size) 1350 { 1351 u64 base = (u64)addr_h << 32 | addr_l; 1352 void __iomem *ucode; 1353 u32 i; 1354 1355 ucode = ioremap(base, size * sizeof(u32)); 1356 if (!ucode) 1357 return -ENOMEM; 1358 1359 for (i = 0; i < size; i++) 1360 netsec_write(priv, reg, readl(ucode + i * 4)); 1361 1362 iounmap(ucode); 1363 return 0; 1364 } 1365 1366 static int netsec_netdev_load_microcode(struct netsec_priv *priv) 1367 { 1368 u32 addr_h, addr_l, size; 1369 int err; 1370 1371 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_H); 1372 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_L); 1373 size = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_SIZE); 1374 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF, 1375 addr_h, addr_l, size); 1376 if (err) 1377 return err; 1378 1379 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_H); 1380 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_L); 1381 size = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_SIZE); 1382 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF, 1383 addr_h, addr_l, size); 1384 if (err) 1385 return err; 1386 1387 addr_h = 0; 1388 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_ADDRESS); 1389 size = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_SIZE); 1390 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF, 1391 addr_h, addr_l, size); 1392 if (err) 1393 return err; 1394 1395 return 0; 1396 } 1397 1398 static int netsec_reset_hardware(struct netsec_priv *priv, 1399 bool load_ucode) 1400 { 1401 u32 value; 1402 int err; 1403 1404 /* stop DMA engines */ 1405 if (!netsec_read(priv, NETSEC_REG_ADDR_DIS_CORE)) { 1406 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL, 1407 NETSEC_DMA_CTRL_REG_STOP); 1408 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, 1409 NETSEC_DMA_CTRL_REG_STOP); 1410 1411 while (netsec_read(priv, NETSEC_REG_DMA_HM_CTRL) & 1412 NETSEC_DMA_CTRL_REG_STOP) 1413 cpu_relax(); 1414 1415 while (netsec_read(priv, NETSEC_REG_DMA_MH_CTRL) & 1416 NETSEC_DMA_CTRL_REG_STOP) 1417 cpu_relax(); 1418 } 1419 1420 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET); 1421 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN); 1422 netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL); 1423 1424 while (netsec_read(priv, NETSEC_REG_COM_INIT) != 0) 1425 cpu_relax(); 1426 1427 /* set desc_start addr */ 1428 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP, 1429 upper_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1430 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW, 1431 lower_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1432 1433 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP, 1434 upper_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1435 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW, 1436 lower_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1437 1438 /* set normal tx dring ring config */ 1439 netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG, 1440 1 << NETSEC_REG_DESC_ENDIAN); 1441 netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG, 1442 1 << NETSEC_REG_DESC_ENDIAN); 1443 1444 if (load_ucode) { 1445 err = netsec_netdev_load_microcode(priv); 1446 if (err) { 1447 netif_err(priv, probe, priv->ndev, 1448 "%s: failed to load microcode (%d)\n", 1449 __func__, err); 1450 return err; 1451 } 1452 } 1453 1454 /* start DMA engines */ 1455 netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1); 1456 netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0); 1457 1458 usleep_range(1000, 2000); 1459 1460 if (!(netsec_read(priv, NETSEC_REG_TOP_STATUS) & 1461 NETSEC_TOP_IRQ_REG_CODE_LOAD_END)) { 1462 netif_err(priv, probe, priv->ndev, 1463 "microengine start failed\n"); 1464 return -ENXIO; 1465 } 1466 netsec_write(priv, NETSEC_REG_TOP_STATUS, 1467 NETSEC_TOP_IRQ_REG_CODE_LOAD_END); 1468 1469 value = NETSEC_PKT_CTRL_REG_MODE_NRM; 1470 if (priv->ndev->mtu > ETH_DATA_LEN) 1471 value |= NETSEC_PKT_CTRL_REG_EN_JUMBO; 1472 1473 /* change to normal mode */ 1474 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS); 1475 netsec_write(priv, NETSEC_REG_PKT_CTRL, value); 1476 1477 while ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) & 1478 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) 1479 cpu_relax(); 1480 1481 /* clear any pending EMPTY/ERR irq status */ 1482 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0); 1483 1484 /* Disable TX & RX intr */ 1485 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1486 1487 return 0; 1488 } 1489 1490 static int netsec_start_gmac(struct netsec_priv *priv) 1491 { 1492 struct phy_device *phydev = priv->ndev->phydev; 1493 u32 value = 0; 1494 int ret; 1495 1496 if (phydev->speed != SPEED_1000) 1497 value = (NETSEC_GMAC_MCR_REG_CST | 1498 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON); 1499 1500 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 1501 return -ETIMEDOUT; 1502 if (netsec_mac_write(priv, GMAC_REG_BMR, 1503 NETSEC_GMAC_BMR_REG_RESET)) 1504 return -ETIMEDOUT; 1505 1506 /* Wait soft reset */ 1507 usleep_range(1000, 5000); 1508 1509 ret = netsec_mac_read(priv, GMAC_REG_BMR, &value); 1510 if (ret) 1511 return ret; 1512 if (value & NETSEC_GMAC_BMR_REG_SWR) 1513 return -EAGAIN; 1514 1515 netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1); 1516 if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1)) 1517 return -ETIMEDOUT; 1518 1519 netsec_write(priv, MAC_REG_DESC_INIT, 1); 1520 if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1)) 1521 return -ETIMEDOUT; 1522 1523 if (netsec_mac_write(priv, GMAC_REG_BMR, 1524 NETSEC_GMAC_BMR_REG_COMMON)) 1525 return -ETIMEDOUT; 1526 if (netsec_mac_write(priv, GMAC_REG_RDLAR, 1527 NETSEC_GMAC_RDLAR_REG_COMMON)) 1528 return -ETIMEDOUT; 1529 if (netsec_mac_write(priv, GMAC_REG_TDLAR, 1530 NETSEC_GMAC_TDLAR_REG_COMMON)) 1531 return -ETIMEDOUT; 1532 if (netsec_mac_write(priv, GMAC_REG_MFFR, 0x80000001)) 1533 return -ETIMEDOUT; 1534 1535 ret = netsec_mac_update_to_phy_state(priv); 1536 if (ret) 1537 return ret; 1538 1539 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1540 if (ret) 1541 return ret; 1542 1543 value |= NETSEC_GMAC_OMR_REG_SR; 1544 value |= NETSEC_GMAC_OMR_REG_ST; 1545 1546 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1547 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1548 1549 netsec_et_set_coalesce(priv->ndev, &priv->et_coalesce); 1550 1551 if (netsec_mac_write(priv, GMAC_REG_OMR, value)) 1552 return -ETIMEDOUT; 1553 1554 return 0; 1555 } 1556 1557 static int netsec_stop_gmac(struct netsec_priv *priv) 1558 { 1559 u32 value; 1560 int ret; 1561 1562 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1563 if (ret) 1564 return ret; 1565 value &= ~NETSEC_GMAC_OMR_REG_SR; 1566 value &= ~NETSEC_GMAC_OMR_REG_ST; 1567 1568 /* disable all interrupts */ 1569 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1570 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1571 1572 return netsec_mac_write(priv, GMAC_REG_OMR, value); 1573 } 1574 1575 static void netsec_phy_adjust_link(struct net_device *ndev) 1576 { 1577 struct netsec_priv *priv = netdev_priv(ndev); 1578 1579 if (ndev->phydev->link) 1580 netsec_start_gmac(priv); 1581 else 1582 netsec_stop_gmac(priv); 1583 1584 phy_print_status(ndev->phydev); 1585 } 1586 1587 static irqreturn_t netsec_irq_handler(int irq, void *dev_id) 1588 { 1589 struct netsec_priv *priv = dev_id; 1590 u32 val, status = netsec_read(priv, NETSEC_REG_TOP_STATUS); 1591 unsigned long flags; 1592 1593 /* Disable interrupts */ 1594 if (status & NETSEC_IRQ_TX) { 1595 val = netsec_read(priv, NETSEC_REG_NRM_TX_STATUS); 1596 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val); 1597 } 1598 if (status & NETSEC_IRQ_RX) { 1599 val = netsec_read(priv, NETSEC_REG_NRM_RX_STATUS); 1600 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val); 1601 } 1602 1603 spin_lock_irqsave(&priv->reglock, flags); 1604 netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1605 spin_unlock_irqrestore(&priv->reglock, flags); 1606 1607 napi_schedule(&priv->napi); 1608 1609 return IRQ_HANDLED; 1610 } 1611 1612 static int netsec_netdev_open(struct net_device *ndev) 1613 { 1614 struct netsec_priv *priv = netdev_priv(ndev); 1615 int ret; 1616 1617 pm_runtime_get_sync(priv->dev); 1618 1619 netsec_setup_tx_dring(priv); 1620 ret = netsec_setup_rx_dring(priv); 1621 if (ret) { 1622 netif_err(priv, probe, priv->ndev, 1623 "%s: fail setup ring\n", __func__); 1624 goto err1; 1625 } 1626 1627 ret = request_irq(priv->ndev->irq, netsec_irq_handler, 1628 IRQF_SHARED, "netsec", priv); 1629 if (ret) { 1630 netif_err(priv, drv, priv->ndev, "request_irq failed\n"); 1631 goto err2; 1632 } 1633 1634 if (dev_of_node(priv->dev)) { 1635 if (!of_phy_connect(priv->ndev, priv->phy_np, 1636 netsec_phy_adjust_link, 0, 1637 priv->phy_interface)) { 1638 netif_err(priv, link, priv->ndev, "missing PHY\n"); 1639 ret = -ENODEV; 1640 goto err3; 1641 } 1642 } else { 1643 ret = phy_connect_direct(priv->ndev, priv->phydev, 1644 netsec_phy_adjust_link, 1645 priv->phy_interface); 1646 if (ret) { 1647 netif_err(priv, link, priv->ndev, 1648 "phy_connect_direct() failed (%d)\n", ret); 1649 goto err3; 1650 } 1651 } 1652 1653 phy_start(ndev->phydev); 1654 1655 netsec_start_gmac(priv); 1656 napi_enable(&priv->napi); 1657 netif_start_queue(ndev); 1658 1659 /* Enable TX+RX intr. */ 1660 netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1661 1662 return 0; 1663 err3: 1664 free_irq(priv->ndev->irq, priv); 1665 err2: 1666 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1667 err1: 1668 pm_runtime_put_sync(priv->dev); 1669 return ret; 1670 } 1671 1672 static int netsec_netdev_stop(struct net_device *ndev) 1673 { 1674 int ret; 1675 struct netsec_priv *priv = netdev_priv(ndev); 1676 1677 netif_stop_queue(priv->ndev); 1678 dma_wmb(); 1679 1680 napi_disable(&priv->napi); 1681 1682 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1683 netsec_stop_gmac(priv); 1684 1685 free_irq(priv->ndev->irq, priv); 1686 1687 netsec_uninit_pkt_dring(priv, NETSEC_RING_TX); 1688 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1689 1690 phy_stop(ndev->phydev); 1691 phy_disconnect(ndev->phydev); 1692 1693 ret = netsec_reset_hardware(priv, false); 1694 1695 pm_runtime_put_sync(priv->dev); 1696 1697 return ret; 1698 } 1699 1700 static int netsec_netdev_init(struct net_device *ndev) 1701 { 1702 struct netsec_priv *priv = netdev_priv(ndev); 1703 int ret; 1704 u16 data; 1705 1706 BUILD_BUG_ON_NOT_POWER_OF_2(DESC_NUM); 1707 1708 ret = netsec_alloc_dring(priv, NETSEC_RING_TX); 1709 if (ret) 1710 return ret; 1711 1712 ret = netsec_alloc_dring(priv, NETSEC_RING_RX); 1713 if (ret) 1714 goto err1; 1715 1716 /* set phy power down */ 1717 data = netsec_phy_read(priv->mii_bus, priv->phy_addr, MII_BMCR) | 1718 BMCR_PDOWN; 1719 netsec_phy_write(priv->mii_bus, priv->phy_addr, MII_BMCR, data); 1720 1721 ret = netsec_reset_hardware(priv, true); 1722 if (ret) 1723 goto err2; 1724 1725 spin_lock_init(&priv->desc_ring[NETSEC_RING_TX].lock); 1726 spin_lock_init(&priv->desc_ring[NETSEC_RING_RX].lock); 1727 1728 return 0; 1729 err2: 1730 netsec_free_dring(priv, NETSEC_RING_RX); 1731 err1: 1732 netsec_free_dring(priv, NETSEC_RING_TX); 1733 return ret; 1734 } 1735 1736 static void netsec_netdev_uninit(struct net_device *ndev) 1737 { 1738 struct netsec_priv *priv = netdev_priv(ndev); 1739 1740 netsec_free_dring(priv, NETSEC_RING_RX); 1741 netsec_free_dring(priv, NETSEC_RING_TX); 1742 } 1743 1744 static int netsec_netdev_set_features(struct net_device *ndev, 1745 netdev_features_t features) 1746 { 1747 struct netsec_priv *priv = netdev_priv(ndev); 1748 1749 priv->rx_cksum_offload_flag = !!(features & NETIF_F_RXCSUM); 1750 1751 return 0; 1752 } 1753 1754 static int netsec_netdev_ioctl(struct net_device *ndev, struct ifreq *ifr, 1755 int cmd) 1756 { 1757 return phy_mii_ioctl(ndev->phydev, ifr, cmd); 1758 } 1759 1760 static int netsec_xdp_xmit(struct net_device *ndev, int n, 1761 struct xdp_frame **frames, u32 flags) 1762 { 1763 struct netsec_priv *priv = netdev_priv(ndev); 1764 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX]; 1765 int drops = 0; 1766 int i; 1767 1768 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1769 return -EINVAL; 1770 1771 spin_lock(&tx_ring->lock); 1772 for (i = 0; i < n; i++) { 1773 struct xdp_frame *xdpf = frames[i]; 1774 int err; 1775 1776 err = netsec_xdp_queue_one(priv, xdpf, true); 1777 if (err != NETSEC_XDP_TX) { 1778 xdp_return_frame_rx_napi(xdpf); 1779 drops++; 1780 } else { 1781 tx_ring->xdp_xmit++; 1782 } 1783 } 1784 spin_unlock(&tx_ring->lock); 1785 1786 if (unlikely(flags & XDP_XMIT_FLUSH)) { 1787 netsec_xdp_ring_tx_db(priv, tx_ring->xdp_xmit); 1788 tx_ring->xdp_xmit = 0; 1789 } 1790 1791 return n - drops; 1792 } 1793 1794 static int netsec_xdp_setup(struct netsec_priv *priv, struct bpf_prog *prog, 1795 struct netlink_ext_ack *extack) 1796 { 1797 struct net_device *dev = priv->ndev; 1798 struct bpf_prog *old_prog; 1799 1800 /* For now just support only the usual MTU sized frames */ 1801 if (prog && dev->mtu > 1500) { 1802 NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP"); 1803 return -EOPNOTSUPP; 1804 } 1805 1806 if (netif_running(dev)) 1807 netsec_netdev_stop(dev); 1808 1809 /* Detach old prog, if any */ 1810 old_prog = xchg(&priv->xdp_prog, prog); 1811 if (old_prog) 1812 bpf_prog_put(old_prog); 1813 1814 if (netif_running(dev)) 1815 netsec_netdev_open(dev); 1816 1817 return 0; 1818 } 1819 1820 static int netsec_xdp(struct net_device *ndev, struct netdev_bpf *xdp) 1821 { 1822 struct netsec_priv *priv = netdev_priv(ndev); 1823 1824 switch (xdp->command) { 1825 case XDP_SETUP_PROG: 1826 return netsec_xdp_setup(priv, xdp->prog, xdp->extack); 1827 case XDP_QUERY_PROG: 1828 xdp->prog_id = priv->xdp_prog ? priv->xdp_prog->aux->id : 0; 1829 return 0; 1830 default: 1831 return -EINVAL; 1832 } 1833 } 1834 1835 static const struct net_device_ops netsec_netdev_ops = { 1836 .ndo_init = netsec_netdev_init, 1837 .ndo_uninit = netsec_netdev_uninit, 1838 .ndo_open = netsec_netdev_open, 1839 .ndo_stop = netsec_netdev_stop, 1840 .ndo_start_xmit = netsec_netdev_start_xmit, 1841 .ndo_set_features = netsec_netdev_set_features, 1842 .ndo_set_mac_address = eth_mac_addr, 1843 .ndo_validate_addr = eth_validate_addr, 1844 .ndo_do_ioctl = netsec_netdev_ioctl, 1845 .ndo_xdp_xmit = netsec_xdp_xmit, 1846 .ndo_bpf = netsec_xdp, 1847 }; 1848 1849 static int netsec_of_probe(struct platform_device *pdev, 1850 struct netsec_priv *priv, u32 *phy_addr) 1851 { 1852 priv->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); 1853 if (!priv->phy_np) { 1854 dev_err(&pdev->dev, "missing required property 'phy-handle'\n"); 1855 return -EINVAL; 1856 } 1857 1858 *phy_addr = of_mdio_parse_addr(&pdev->dev, priv->phy_np); 1859 1860 priv->clk = devm_clk_get(&pdev->dev, NULL); /* get by 'phy_ref_clk' */ 1861 if (IS_ERR(priv->clk)) { 1862 dev_err(&pdev->dev, "phy_ref_clk not found\n"); 1863 return PTR_ERR(priv->clk); 1864 } 1865 priv->freq = clk_get_rate(priv->clk); 1866 1867 return 0; 1868 } 1869 1870 static int netsec_acpi_probe(struct platform_device *pdev, 1871 struct netsec_priv *priv, u32 *phy_addr) 1872 { 1873 int ret; 1874 1875 if (!IS_ENABLED(CONFIG_ACPI)) 1876 return -ENODEV; 1877 1878 ret = device_property_read_u32(&pdev->dev, "phy-channel", phy_addr); 1879 if (ret) { 1880 dev_err(&pdev->dev, 1881 "missing required property 'phy-channel'\n"); 1882 return ret; 1883 } 1884 1885 ret = device_property_read_u32(&pdev->dev, 1886 "socionext,phy-clock-frequency", 1887 &priv->freq); 1888 if (ret) 1889 dev_err(&pdev->dev, 1890 "missing required property 'socionext,phy-clock-frequency'\n"); 1891 return ret; 1892 } 1893 1894 static void netsec_unregister_mdio(struct netsec_priv *priv) 1895 { 1896 struct phy_device *phydev = priv->phydev; 1897 1898 if (!dev_of_node(priv->dev) && phydev) { 1899 phy_device_remove(phydev); 1900 phy_device_free(phydev); 1901 } 1902 1903 mdiobus_unregister(priv->mii_bus); 1904 } 1905 1906 static int netsec_register_mdio(struct netsec_priv *priv, u32 phy_addr) 1907 { 1908 struct mii_bus *bus; 1909 int ret; 1910 1911 bus = devm_mdiobus_alloc(priv->dev); 1912 if (!bus) 1913 return -ENOMEM; 1914 1915 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(priv->dev)); 1916 bus->priv = priv; 1917 bus->name = "SNI NETSEC MDIO"; 1918 bus->read = netsec_phy_read; 1919 bus->write = netsec_phy_write; 1920 bus->parent = priv->dev; 1921 priv->mii_bus = bus; 1922 1923 if (dev_of_node(priv->dev)) { 1924 struct device_node *mdio_node, *parent = dev_of_node(priv->dev); 1925 1926 mdio_node = of_get_child_by_name(parent, "mdio"); 1927 if (mdio_node) { 1928 parent = mdio_node; 1929 } else { 1930 /* older f/w doesn't populate the mdio subnode, 1931 * allow relaxed upgrade of f/w in due time. 1932 */ 1933 dev_info(priv->dev, "Upgrade f/w for mdio subnode!\n"); 1934 } 1935 1936 ret = of_mdiobus_register(bus, parent); 1937 of_node_put(mdio_node); 1938 1939 if (ret) { 1940 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1941 return ret; 1942 } 1943 } else { 1944 /* Mask out all PHYs from auto probing. */ 1945 bus->phy_mask = ~0; 1946 ret = mdiobus_register(bus); 1947 if (ret) { 1948 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1949 return ret; 1950 } 1951 1952 priv->phydev = get_phy_device(bus, phy_addr, false); 1953 if (IS_ERR(priv->phydev)) { 1954 ret = PTR_ERR(priv->phydev); 1955 dev_err(priv->dev, "get_phy_device err(%d)\n", ret); 1956 priv->phydev = NULL; 1957 return -ENODEV; 1958 } 1959 1960 ret = phy_device_register(priv->phydev); 1961 if (ret) { 1962 mdiobus_unregister(bus); 1963 dev_err(priv->dev, 1964 "phy_device_register err(%d)\n", ret); 1965 } 1966 } 1967 1968 return ret; 1969 } 1970 1971 static int netsec_probe(struct platform_device *pdev) 1972 { 1973 struct resource *mmio_res, *eeprom_res, *irq_res; 1974 u8 *mac, macbuf[ETH_ALEN]; 1975 struct netsec_priv *priv; 1976 u32 hw_ver, phy_addr = 0; 1977 struct net_device *ndev; 1978 int ret; 1979 1980 mmio_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1981 if (!mmio_res) { 1982 dev_err(&pdev->dev, "No MMIO resource found.\n"); 1983 return -ENODEV; 1984 } 1985 1986 eeprom_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1987 if (!eeprom_res) { 1988 dev_info(&pdev->dev, "No EEPROM resource found.\n"); 1989 return -ENODEV; 1990 } 1991 1992 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1993 if (!irq_res) { 1994 dev_err(&pdev->dev, "No IRQ resource found.\n"); 1995 return -ENODEV; 1996 } 1997 1998 ndev = alloc_etherdev(sizeof(*priv)); 1999 if (!ndev) 2000 return -ENOMEM; 2001 2002 priv = netdev_priv(ndev); 2003 2004 spin_lock_init(&priv->reglock); 2005 SET_NETDEV_DEV(ndev, &pdev->dev); 2006 platform_set_drvdata(pdev, priv); 2007 ndev->irq = irq_res->start; 2008 priv->dev = &pdev->dev; 2009 priv->ndev = ndev; 2010 2011 priv->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | 2012 NETIF_MSG_LINK | NETIF_MSG_PROBE; 2013 2014 priv->phy_interface = device_get_phy_mode(&pdev->dev); 2015 if (priv->phy_interface < 0) { 2016 dev_err(&pdev->dev, "missing required property 'phy-mode'\n"); 2017 ret = -ENODEV; 2018 goto free_ndev; 2019 } 2020 2021 priv->ioaddr = devm_ioremap(&pdev->dev, mmio_res->start, 2022 resource_size(mmio_res)); 2023 if (!priv->ioaddr) { 2024 dev_err(&pdev->dev, "devm_ioremap() failed\n"); 2025 ret = -ENXIO; 2026 goto free_ndev; 2027 } 2028 2029 priv->eeprom_base = devm_ioremap(&pdev->dev, eeprom_res->start, 2030 resource_size(eeprom_res)); 2031 if (!priv->eeprom_base) { 2032 dev_err(&pdev->dev, "devm_ioremap() failed for EEPROM\n"); 2033 ret = -ENXIO; 2034 goto free_ndev; 2035 } 2036 2037 mac = device_get_mac_address(&pdev->dev, macbuf, sizeof(macbuf)); 2038 if (mac) 2039 ether_addr_copy(ndev->dev_addr, mac); 2040 2041 if (priv->eeprom_base && 2042 (!mac || !is_valid_ether_addr(ndev->dev_addr))) { 2043 void __iomem *macp = priv->eeprom_base + 2044 NETSEC_EEPROM_MAC_ADDRESS; 2045 2046 ndev->dev_addr[0] = readb(macp + 3); 2047 ndev->dev_addr[1] = readb(macp + 2); 2048 ndev->dev_addr[2] = readb(macp + 1); 2049 ndev->dev_addr[3] = readb(macp + 0); 2050 ndev->dev_addr[4] = readb(macp + 7); 2051 ndev->dev_addr[5] = readb(macp + 6); 2052 } 2053 2054 if (!is_valid_ether_addr(ndev->dev_addr)) { 2055 dev_warn(&pdev->dev, "No MAC address found, using random\n"); 2056 eth_hw_addr_random(ndev); 2057 } 2058 2059 if (dev_of_node(&pdev->dev)) 2060 ret = netsec_of_probe(pdev, priv, &phy_addr); 2061 else 2062 ret = netsec_acpi_probe(pdev, priv, &phy_addr); 2063 if (ret) 2064 goto free_ndev; 2065 2066 priv->phy_addr = phy_addr; 2067 2068 if (!priv->freq) { 2069 dev_err(&pdev->dev, "missing PHY reference clock frequency\n"); 2070 ret = -ENODEV; 2071 goto free_ndev; 2072 } 2073 2074 /* default for throughput */ 2075 priv->et_coalesce.rx_coalesce_usecs = 500; 2076 priv->et_coalesce.rx_max_coalesced_frames = 8; 2077 priv->et_coalesce.tx_coalesce_usecs = 500; 2078 priv->et_coalesce.tx_max_coalesced_frames = 8; 2079 2080 ret = device_property_read_u32(&pdev->dev, "max-frame-size", 2081 &ndev->max_mtu); 2082 if (ret < 0) 2083 ndev->max_mtu = ETH_DATA_LEN; 2084 2085 /* runtime_pm coverage just for probe, open/close also cover it */ 2086 pm_runtime_enable(&pdev->dev); 2087 pm_runtime_get_sync(&pdev->dev); 2088 2089 hw_ver = netsec_read(priv, NETSEC_REG_F_TAIKI_VER); 2090 /* this driver only supports F_TAIKI style NETSEC */ 2091 if (NETSEC_F_NETSEC_VER_MAJOR_NUM(hw_ver) != 2092 NETSEC_F_NETSEC_VER_MAJOR_NUM(NETSEC_REG_NETSEC_VER_F_TAIKI)) { 2093 ret = -ENODEV; 2094 goto pm_disable; 2095 } 2096 2097 dev_info(&pdev->dev, "hardware revision %d.%d\n", 2098 hw_ver >> 16, hw_ver & 0xffff); 2099 2100 netif_napi_add(ndev, &priv->napi, netsec_napi_poll, NAPI_POLL_WEIGHT); 2101 2102 ndev->netdev_ops = &netsec_netdev_ops; 2103 ndev->ethtool_ops = &netsec_ethtool_ops; 2104 2105 ndev->features |= NETIF_F_HIGHDMA | NETIF_F_RXCSUM | NETIF_F_GSO | 2106 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2107 ndev->hw_features = ndev->features; 2108 2109 priv->rx_cksum_offload_flag = true; 2110 2111 ret = netsec_register_mdio(priv, phy_addr); 2112 if (ret) 2113 goto unreg_napi; 2114 2115 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40))) 2116 dev_warn(&pdev->dev, "Failed to set DMA mask\n"); 2117 2118 ret = register_netdev(ndev); 2119 if (ret) { 2120 netif_err(priv, probe, ndev, "register_netdev() failed\n"); 2121 goto unreg_mii; 2122 } 2123 2124 pm_runtime_put_sync(&pdev->dev); 2125 return 0; 2126 2127 unreg_mii: 2128 netsec_unregister_mdio(priv); 2129 unreg_napi: 2130 netif_napi_del(&priv->napi); 2131 pm_disable: 2132 pm_runtime_put_sync(&pdev->dev); 2133 pm_runtime_disable(&pdev->dev); 2134 free_ndev: 2135 free_netdev(ndev); 2136 dev_err(&pdev->dev, "init failed\n"); 2137 2138 return ret; 2139 } 2140 2141 static int netsec_remove(struct platform_device *pdev) 2142 { 2143 struct netsec_priv *priv = platform_get_drvdata(pdev); 2144 2145 unregister_netdev(priv->ndev); 2146 2147 netsec_unregister_mdio(priv); 2148 2149 netif_napi_del(&priv->napi); 2150 2151 pm_runtime_disable(&pdev->dev); 2152 free_netdev(priv->ndev); 2153 2154 return 0; 2155 } 2156 2157 #ifdef CONFIG_PM 2158 static int netsec_runtime_suspend(struct device *dev) 2159 { 2160 struct netsec_priv *priv = dev_get_drvdata(dev); 2161 2162 netsec_write(priv, NETSEC_REG_CLK_EN, 0); 2163 2164 clk_disable_unprepare(priv->clk); 2165 2166 return 0; 2167 } 2168 2169 static int netsec_runtime_resume(struct device *dev) 2170 { 2171 struct netsec_priv *priv = dev_get_drvdata(dev); 2172 2173 clk_prepare_enable(priv->clk); 2174 2175 netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D | 2176 NETSEC_CLK_EN_REG_DOM_C | 2177 NETSEC_CLK_EN_REG_DOM_G); 2178 return 0; 2179 } 2180 #endif 2181 2182 static const struct dev_pm_ops netsec_pm_ops = { 2183 SET_RUNTIME_PM_OPS(netsec_runtime_suspend, netsec_runtime_resume, NULL) 2184 }; 2185 2186 static const struct of_device_id netsec_dt_ids[] = { 2187 { .compatible = "socionext,synquacer-netsec" }, 2188 { } 2189 }; 2190 MODULE_DEVICE_TABLE(of, netsec_dt_ids); 2191 2192 #ifdef CONFIG_ACPI 2193 static const struct acpi_device_id netsec_acpi_ids[] = { 2194 { "SCX0001" }, 2195 { } 2196 }; 2197 MODULE_DEVICE_TABLE(acpi, netsec_acpi_ids); 2198 #endif 2199 2200 static struct platform_driver netsec_driver = { 2201 .probe = netsec_probe, 2202 .remove = netsec_remove, 2203 .driver = { 2204 .name = "netsec", 2205 .pm = &netsec_pm_ops, 2206 .of_match_table = netsec_dt_ids, 2207 .acpi_match_table = ACPI_PTR(netsec_acpi_ids), 2208 }, 2209 }; 2210 module_platform_driver(netsec_driver); 2211 2212 MODULE_AUTHOR("Jassi Brar <jaswinder.singh@linaro.org>"); 2213 MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); 2214 MODULE_DESCRIPTION("NETSEC Ethernet driver"); 2215 MODULE_LICENSE("GPL"); 2216