1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /*************************************************************************** 3 * 4 * Copyright (C) 2007,2008 SMSC 5 * 6 *************************************************************************** 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/netdevice.h> 14 #include <linux/phy.h> 15 #include <linux/pci.h> 16 #include <linux/if_vlan.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/crc32.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <asm/unaligned.h> 22 #include "smsc9420.h" 23 24 #define DRV_NAME "smsc9420" 25 #define DRV_MDIONAME "smsc9420-mdio" 26 #define DRV_DESCRIPTION "SMSC LAN9420 driver" 27 #define DRV_VERSION "1.01" 28 29 MODULE_LICENSE("GPL"); 30 MODULE_VERSION(DRV_VERSION); 31 32 struct smsc9420_dma_desc { 33 u32 status; 34 u32 length; 35 u32 buffer1; 36 u32 buffer2; 37 }; 38 39 struct smsc9420_ring_info { 40 struct sk_buff *skb; 41 dma_addr_t mapping; 42 }; 43 44 struct smsc9420_pdata { 45 void __iomem *ioaddr; 46 struct pci_dev *pdev; 47 struct net_device *dev; 48 49 struct smsc9420_dma_desc *rx_ring; 50 struct smsc9420_dma_desc *tx_ring; 51 struct smsc9420_ring_info *tx_buffers; 52 struct smsc9420_ring_info *rx_buffers; 53 dma_addr_t rx_dma_addr; 54 dma_addr_t tx_dma_addr; 55 int tx_ring_head, tx_ring_tail; 56 int rx_ring_head, rx_ring_tail; 57 58 spinlock_t int_lock; 59 spinlock_t phy_lock; 60 61 struct napi_struct napi; 62 63 bool software_irq_signal; 64 bool rx_csum; 65 u32 msg_enable; 66 67 struct mii_bus *mii_bus; 68 int last_duplex; 69 int last_carrier; 70 }; 71 72 static const struct pci_device_id smsc9420_id_table[] = { 73 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, }, 74 { 0, } 75 }; 76 77 MODULE_DEVICE_TABLE(pci, smsc9420_id_table); 78 79 #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 80 81 static uint smsc_debug; 82 static uint debug = -1; 83 module_param(debug, uint, 0); 84 MODULE_PARM_DESC(debug, "debug level"); 85 86 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset) 87 { 88 return ioread32(pd->ioaddr + offset); 89 } 90 91 static inline void 92 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value) 93 { 94 iowrite32(value, pd->ioaddr + offset); 95 } 96 97 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd) 98 { 99 /* to ensure PCI write completion, we must perform a PCI read */ 100 smsc9420_reg_read(pd, ID_REV); 101 } 102 103 static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx) 104 { 105 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv; 106 unsigned long flags; 107 u32 addr; 108 int i, reg = -EIO; 109 110 spin_lock_irqsave(&pd->phy_lock, flags); 111 112 /* confirm MII not busy */ 113 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) { 114 netif_warn(pd, drv, pd->dev, "MII is busy???\n"); 115 goto out; 116 } 117 118 /* set the address, index & direction (read from PHY) */ 119 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | 120 MII_ACCESS_MII_READ_; 121 smsc9420_reg_write(pd, MII_ACCESS, addr); 122 123 /* wait for read to complete with 50us timeout */ 124 for (i = 0; i < 5; i++) { 125 if (!(smsc9420_reg_read(pd, MII_ACCESS) & 126 MII_ACCESS_MII_BUSY_)) { 127 reg = (u16)smsc9420_reg_read(pd, MII_DATA); 128 goto out; 129 } 130 udelay(10); 131 } 132 133 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n"); 134 135 out: 136 spin_unlock_irqrestore(&pd->phy_lock, flags); 137 return reg; 138 } 139 140 static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx, 141 u16 val) 142 { 143 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv; 144 unsigned long flags; 145 u32 addr; 146 int i, reg = -EIO; 147 148 spin_lock_irqsave(&pd->phy_lock, flags); 149 150 /* confirm MII not busy */ 151 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) { 152 netif_warn(pd, drv, pd->dev, "MII is busy???\n"); 153 goto out; 154 } 155 156 /* put the data to write in the MAC */ 157 smsc9420_reg_write(pd, MII_DATA, (u32)val); 158 159 /* set the address, index & direction (write to PHY) */ 160 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | 161 MII_ACCESS_MII_WRITE_; 162 smsc9420_reg_write(pd, MII_ACCESS, addr); 163 164 /* wait for write to complete with 50us timeout */ 165 for (i = 0; i < 5; i++) { 166 if (!(smsc9420_reg_read(pd, MII_ACCESS) & 167 MII_ACCESS_MII_BUSY_)) { 168 reg = 0; 169 goto out; 170 } 171 udelay(10); 172 } 173 174 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n"); 175 176 out: 177 spin_unlock_irqrestore(&pd->phy_lock, flags); 178 return reg; 179 } 180 181 /* Returns hash bit number for given MAC address 182 * Example: 183 * 01 00 5E 00 00 01 -> returns bit number 31 */ 184 static u32 smsc9420_hash(u8 addr[ETH_ALEN]) 185 { 186 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; 187 } 188 189 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd) 190 { 191 int timeout = 100000; 192 193 BUG_ON(!pd); 194 195 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) { 196 netif_dbg(pd, drv, pd->dev, "%s: Eeprom busy\n", __func__); 197 return -EIO; 198 } 199 200 smsc9420_reg_write(pd, E2P_CMD, 201 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_)); 202 203 do { 204 udelay(10); 205 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_)) 206 return 0; 207 } while (timeout--); 208 209 netif_warn(pd, drv, pd->dev, "%s: Eeprom timed out\n", __func__); 210 return -EIO; 211 } 212 213 /* Standard ioctls for mii-tool */ 214 static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 215 { 216 if (!netif_running(dev) || !dev->phydev) 217 return -EINVAL; 218 219 return phy_mii_ioctl(dev->phydev, ifr, cmd); 220 } 221 222 static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev, 223 struct ethtool_drvinfo *drvinfo) 224 { 225 struct smsc9420_pdata *pd = netdev_priv(netdev); 226 227 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver)); 228 strlcpy(drvinfo->bus_info, pci_name(pd->pdev), 229 sizeof(drvinfo->bus_info)); 230 strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version)); 231 } 232 233 static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev) 234 { 235 struct smsc9420_pdata *pd = netdev_priv(netdev); 236 return pd->msg_enable; 237 } 238 239 static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data) 240 { 241 struct smsc9420_pdata *pd = netdev_priv(netdev); 242 pd->msg_enable = data; 243 } 244 245 static int smsc9420_ethtool_getregslen(struct net_device *dev) 246 { 247 /* all smsc9420 registers plus all phy registers */ 248 return 0x100 + (32 * sizeof(u32)); 249 } 250 251 static void 252 smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs, 253 void *buf) 254 { 255 struct smsc9420_pdata *pd = netdev_priv(dev); 256 struct phy_device *phy_dev = dev->phydev; 257 unsigned int i, j = 0; 258 u32 *data = buf; 259 260 regs->version = smsc9420_reg_read(pd, ID_REV); 261 for (i = 0; i < 0x100; i += (sizeof(u32))) 262 data[j++] = smsc9420_reg_read(pd, i); 263 264 // cannot read phy registers if the net device is down 265 if (!phy_dev) 266 return; 267 268 for (i = 0; i <= 31; i++) 269 data[j++] = smsc9420_mii_read(phy_dev->mdio.bus, 270 phy_dev->mdio.addr, i); 271 } 272 273 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd) 274 { 275 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG); 276 temp &= ~GPIO_CFG_EEPR_EN_; 277 smsc9420_reg_write(pd, GPIO_CFG, temp); 278 msleep(1); 279 } 280 281 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op) 282 { 283 int timeout = 100; 284 u32 e2cmd; 285 286 netif_dbg(pd, hw, pd->dev, "op 0x%08x\n", op); 287 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) { 288 netif_warn(pd, hw, pd->dev, "Busy at start\n"); 289 return -EBUSY; 290 } 291 292 e2cmd = op | E2P_CMD_EPC_BUSY_; 293 smsc9420_reg_write(pd, E2P_CMD, e2cmd); 294 295 do { 296 msleep(1); 297 e2cmd = smsc9420_reg_read(pd, E2P_CMD); 298 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout)); 299 300 if (!timeout) { 301 netif_info(pd, hw, pd->dev, "TIMED OUT\n"); 302 return -EAGAIN; 303 } 304 305 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) { 306 netif_info(pd, hw, pd->dev, 307 "Error occurred during eeprom operation\n"); 308 return -EINVAL; 309 } 310 311 return 0; 312 } 313 314 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd, 315 u8 address, u8 *data) 316 { 317 u32 op = E2P_CMD_EPC_CMD_READ_ | address; 318 int ret; 319 320 netif_dbg(pd, hw, pd->dev, "address 0x%x\n", address); 321 ret = smsc9420_eeprom_send_cmd(pd, op); 322 323 if (!ret) 324 data[address] = smsc9420_reg_read(pd, E2P_DATA); 325 326 return ret; 327 } 328 329 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd, 330 u8 address, u8 data) 331 { 332 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address; 333 int ret; 334 335 netif_dbg(pd, hw, pd->dev, "address 0x%x, data 0x%x\n", address, data); 336 ret = smsc9420_eeprom_send_cmd(pd, op); 337 338 if (!ret) { 339 op = E2P_CMD_EPC_CMD_WRITE_ | address; 340 smsc9420_reg_write(pd, E2P_DATA, (u32)data); 341 ret = smsc9420_eeprom_send_cmd(pd, op); 342 } 343 344 return ret; 345 } 346 347 static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev) 348 { 349 return SMSC9420_EEPROM_SIZE; 350 } 351 352 static int smsc9420_ethtool_get_eeprom(struct net_device *dev, 353 struct ethtool_eeprom *eeprom, u8 *data) 354 { 355 struct smsc9420_pdata *pd = netdev_priv(dev); 356 u8 eeprom_data[SMSC9420_EEPROM_SIZE]; 357 int len, i; 358 359 smsc9420_eeprom_enable_access(pd); 360 361 len = min(eeprom->len, SMSC9420_EEPROM_SIZE); 362 for (i = 0; i < len; i++) { 363 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data); 364 if (ret < 0) { 365 eeprom->len = 0; 366 return ret; 367 } 368 } 369 370 memcpy(data, &eeprom_data[eeprom->offset], len); 371 eeprom->magic = SMSC9420_EEPROM_MAGIC; 372 eeprom->len = len; 373 return 0; 374 } 375 376 static int smsc9420_ethtool_set_eeprom(struct net_device *dev, 377 struct ethtool_eeprom *eeprom, u8 *data) 378 { 379 struct smsc9420_pdata *pd = netdev_priv(dev); 380 int ret; 381 382 if (eeprom->magic != SMSC9420_EEPROM_MAGIC) 383 return -EINVAL; 384 385 smsc9420_eeprom_enable_access(pd); 386 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_); 387 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data); 388 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_); 389 390 /* Single byte write, according to man page */ 391 eeprom->len = 1; 392 393 return ret; 394 } 395 396 static const struct ethtool_ops smsc9420_ethtool_ops = { 397 .get_drvinfo = smsc9420_ethtool_get_drvinfo, 398 .get_msglevel = smsc9420_ethtool_get_msglevel, 399 .set_msglevel = smsc9420_ethtool_set_msglevel, 400 .nway_reset = phy_ethtool_nway_reset, 401 .get_link = ethtool_op_get_link, 402 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len, 403 .get_eeprom = smsc9420_ethtool_get_eeprom, 404 .set_eeprom = smsc9420_ethtool_set_eeprom, 405 .get_regs_len = smsc9420_ethtool_getregslen, 406 .get_regs = smsc9420_ethtool_getregs, 407 .get_ts_info = ethtool_op_get_ts_info, 408 .get_link_ksettings = phy_ethtool_get_link_ksettings, 409 .set_link_ksettings = phy_ethtool_set_link_ksettings, 410 }; 411 412 /* Sets the device MAC address to dev_addr */ 413 static void smsc9420_set_mac_address(struct net_device *dev) 414 { 415 struct smsc9420_pdata *pd = netdev_priv(dev); 416 u8 *dev_addr = dev->dev_addr; 417 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4]; 418 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | 419 (dev_addr[1] << 8) | dev_addr[0]; 420 421 smsc9420_reg_write(pd, ADDRH, mac_high16); 422 smsc9420_reg_write(pd, ADDRL, mac_low32); 423 } 424 425 static void smsc9420_check_mac_address(struct net_device *dev) 426 { 427 struct smsc9420_pdata *pd = netdev_priv(dev); 428 429 /* Check if mac address has been specified when bringing interface up */ 430 if (is_valid_ether_addr(dev->dev_addr)) { 431 smsc9420_set_mac_address(dev); 432 netif_dbg(pd, probe, pd->dev, 433 "MAC Address is specified by configuration\n"); 434 } else { 435 /* Try reading mac address from device. if EEPROM is present 436 * it will already have been set */ 437 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH); 438 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL); 439 dev->dev_addr[0] = (u8)(mac_low32); 440 dev->dev_addr[1] = (u8)(mac_low32 >> 8); 441 dev->dev_addr[2] = (u8)(mac_low32 >> 16); 442 dev->dev_addr[3] = (u8)(mac_low32 >> 24); 443 dev->dev_addr[4] = (u8)(mac_high16); 444 dev->dev_addr[5] = (u8)(mac_high16 >> 8); 445 446 if (is_valid_ether_addr(dev->dev_addr)) { 447 /* eeprom values are valid so use them */ 448 netif_dbg(pd, probe, pd->dev, 449 "Mac Address is read from EEPROM\n"); 450 } else { 451 /* eeprom values are invalid, generate random MAC */ 452 eth_hw_addr_random(dev); 453 smsc9420_set_mac_address(dev); 454 netif_dbg(pd, probe, pd->dev, 455 "MAC Address is set to random\n"); 456 } 457 } 458 } 459 460 static void smsc9420_stop_tx(struct smsc9420_pdata *pd) 461 { 462 u32 dmac_control, mac_cr, dma_intr_ena; 463 int timeout = 1000; 464 465 /* disable TX DMAC */ 466 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); 467 dmac_control &= (~DMAC_CONTROL_ST_); 468 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); 469 470 /* Wait max 10ms for transmit process to stop */ 471 while (--timeout) { 472 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_) 473 break; 474 udelay(10); 475 } 476 477 if (!timeout) 478 netif_warn(pd, ifdown, pd->dev, "TX DMAC failed to stop\n"); 479 480 /* ACK Tx DMAC stop bit */ 481 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_); 482 483 /* mask TX DMAC interrupts */ 484 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 485 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_); 486 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 487 smsc9420_pci_flush_write(pd); 488 489 /* stop MAC TX */ 490 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_); 491 smsc9420_reg_write(pd, MAC_CR, mac_cr); 492 smsc9420_pci_flush_write(pd); 493 } 494 495 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd) 496 { 497 int i; 498 499 BUG_ON(!pd->tx_ring); 500 501 if (!pd->tx_buffers) 502 return; 503 504 for (i = 0; i < TX_RING_SIZE; i++) { 505 struct sk_buff *skb = pd->tx_buffers[i].skb; 506 507 if (skb) { 508 BUG_ON(!pd->tx_buffers[i].mapping); 509 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping, 510 skb->len, PCI_DMA_TODEVICE); 511 dev_kfree_skb_any(skb); 512 } 513 514 pd->tx_ring[i].status = 0; 515 pd->tx_ring[i].length = 0; 516 pd->tx_ring[i].buffer1 = 0; 517 pd->tx_ring[i].buffer2 = 0; 518 } 519 wmb(); 520 521 kfree(pd->tx_buffers); 522 pd->tx_buffers = NULL; 523 524 pd->tx_ring_head = 0; 525 pd->tx_ring_tail = 0; 526 } 527 528 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd) 529 { 530 int i; 531 532 BUG_ON(!pd->rx_ring); 533 534 if (!pd->rx_buffers) 535 return; 536 537 for (i = 0; i < RX_RING_SIZE; i++) { 538 if (pd->rx_buffers[i].skb) 539 dev_kfree_skb_any(pd->rx_buffers[i].skb); 540 541 if (pd->rx_buffers[i].mapping) 542 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping, 543 PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 544 545 pd->rx_ring[i].status = 0; 546 pd->rx_ring[i].length = 0; 547 pd->rx_ring[i].buffer1 = 0; 548 pd->rx_ring[i].buffer2 = 0; 549 } 550 wmb(); 551 552 kfree(pd->rx_buffers); 553 pd->rx_buffers = NULL; 554 555 pd->rx_ring_head = 0; 556 pd->rx_ring_tail = 0; 557 } 558 559 static void smsc9420_stop_rx(struct smsc9420_pdata *pd) 560 { 561 int timeout = 1000; 562 u32 mac_cr, dmac_control, dma_intr_ena; 563 564 /* mask RX DMAC interrupts */ 565 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 566 dma_intr_ena &= (~DMAC_INTR_ENA_RX_); 567 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 568 smsc9420_pci_flush_write(pd); 569 570 /* stop RX MAC prior to stoping DMA */ 571 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_); 572 smsc9420_reg_write(pd, MAC_CR, mac_cr); 573 smsc9420_pci_flush_write(pd); 574 575 /* stop RX DMAC */ 576 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); 577 dmac_control &= (~DMAC_CONTROL_SR_); 578 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); 579 smsc9420_pci_flush_write(pd); 580 581 /* wait up to 10ms for receive to stop */ 582 while (--timeout) { 583 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_) 584 break; 585 udelay(10); 586 } 587 588 if (!timeout) 589 netif_warn(pd, ifdown, pd->dev, 590 "RX DMAC did not stop! timeout\n"); 591 592 /* ACK the Rx DMAC stop bit */ 593 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_); 594 } 595 596 static irqreturn_t smsc9420_isr(int irq, void *dev_id) 597 { 598 struct smsc9420_pdata *pd = dev_id; 599 u32 int_cfg, int_sts, int_ctl; 600 irqreturn_t ret = IRQ_NONE; 601 ulong flags; 602 603 BUG_ON(!pd); 604 BUG_ON(!pd->ioaddr); 605 606 int_cfg = smsc9420_reg_read(pd, INT_CFG); 607 608 /* check if it's our interrupt */ 609 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) != 610 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) 611 return IRQ_NONE; 612 613 int_sts = smsc9420_reg_read(pd, INT_STAT); 614 615 if (likely(INT_STAT_DMAC_INT_ & int_sts)) { 616 u32 status = smsc9420_reg_read(pd, DMAC_STATUS); 617 u32 ints_to_clear = 0; 618 619 if (status & DMAC_STS_TX_) { 620 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_); 621 netif_wake_queue(pd->dev); 622 } 623 624 if (status & DMAC_STS_RX_) { 625 /* mask RX DMAC interrupts */ 626 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 627 dma_intr_ena &= (~DMAC_INTR_ENA_RX_); 628 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 629 smsc9420_pci_flush_write(pd); 630 631 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_); 632 napi_schedule(&pd->napi); 633 } 634 635 if (ints_to_clear) 636 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear); 637 638 ret = IRQ_HANDLED; 639 } 640 641 if (unlikely(INT_STAT_SW_INT_ & int_sts)) { 642 /* mask software interrupt */ 643 spin_lock_irqsave(&pd->int_lock, flags); 644 int_ctl = smsc9420_reg_read(pd, INT_CTL); 645 int_ctl &= (~INT_CTL_SW_INT_EN_); 646 smsc9420_reg_write(pd, INT_CTL, int_ctl); 647 spin_unlock_irqrestore(&pd->int_lock, flags); 648 649 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_); 650 pd->software_irq_signal = true; 651 smp_wmb(); 652 653 ret = IRQ_HANDLED; 654 } 655 656 /* to ensure PCI write completion, we must perform a PCI read */ 657 smsc9420_pci_flush_write(pd); 658 659 return ret; 660 } 661 662 #ifdef CONFIG_NET_POLL_CONTROLLER 663 static void smsc9420_poll_controller(struct net_device *dev) 664 { 665 struct smsc9420_pdata *pd = netdev_priv(dev); 666 const int irq = pd->pdev->irq; 667 668 disable_irq(irq); 669 smsc9420_isr(0, dev); 670 enable_irq(irq); 671 } 672 #endif /* CONFIG_NET_POLL_CONTROLLER */ 673 674 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd) 675 { 676 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_); 677 smsc9420_reg_read(pd, BUS_MODE); 678 udelay(2); 679 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_) 680 netif_warn(pd, drv, pd->dev, "Software reset not cleared\n"); 681 } 682 683 static int smsc9420_stop(struct net_device *dev) 684 { 685 struct smsc9420_pdata *pd = netdev_priv(dev); 686 u32 int_cfg; 687 ulong flags; 688 689 BUG_ON(!pd); 690 BUG_ON(!dev->phydev); 691 692 /* disable master interrupt */ 693 spin_lock_irqsave(&pd->int_lock, flags); 694 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 695 smsc9420_reg_write(pd, INT_CFG, int_cfg); 696 spin_unlock_irqrestore(&pd->int_lock, flags); 697 698 netif_tx_disable(dev); 699 napi_disable(&pd->napi); 700 701 smsc9420_stop_tx(pd); 702 smsc9420_free_tx_ring(pd); 703 704 smsc9420_stop_rx(pd); 705 smsc9420_free_rx_ring(pd); 706 707 free_irq(pd->pdev->irq, pd); 708 709 smsc9420_dmac_soft_reset(pd); 710 711 phy_stop(dev->phydev); 712 713 phy_disconnect(dev->phydev); 714 mdiobus_unregister(pd->mii_bus); 715 mdiobus_free(pd->mii_bus); 716 717 return 0; 718 } 719 720 static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status) 721 { 722 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) { 723 dev->stats.rx_errors++; 724 if (desc_status & RDES0_DESCRIPTOR_ERROR_) 725 dev->stats.rx_over_errors++; 726 else if (desc_status & (RDES0_FRAME_TOO_LONG_ | 727 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_)) 728 dev->stats.rx_frame_errors++; 729 else if (desc_status & RDES0_CRC_ERROR_) 730 dev->stats.rx_crc_errors++; 731 } 732 733 if (unlikely(desc_status & RDES0_LENGTH_ERROR_)) 734 dev->stats.rx_length_errors++; 735 736 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) && 737 (desc_status & RDES0_FIRST_DESCRIPTOR_)))) 738 dev->stats.rx_length_errors++; 739 740 if (desc_status & RDES0_MULTICAST_FRAME_) 741 dev->stats.multicast++; 742 } 743 744 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index, 745 const u32 status) 746 { 747 struct net_device *dev = pd->dev; 748 struct sk_buff *skb; 749 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_) 750 >> RDES0_FRAME_LENGTH_SHFT_; 751 752 /* remove crc from packet lendth */ 753 packet_length -= 4; 754 755 if (pd->rx_csum) 756 packet_length -= 2; 757 758 dev->stats.rx_packets++; 759 dev->stats.rx_bytes += packet_length; 760 761 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping, 762 PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 763 pd->rx_buffers[index].mapping = 0; 764 765 skb = pd->rx_buffers[index].skb; 766 pd->rx_buffers[index].skb = NULL; 767 768 if (pd->rx_csum) { 769 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) + 770 NET_IP_ALIGN + packet_length + 4); 771 put_unaligned_le16(hw_csum, &skb->csum); 772 skb->ip_summed = CHECKSUM_COMPLETE; 773 } 774 775 skb_reserve(skb, NET_IP_ALIGN); 776 skb_put(skb, packet_length); 777 778 skb->protocol = eth_type_trans(skb, dev); 779 780 netif_receive_skb(skb); 781 } 782 783 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index) 784 { 785 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ); 786 dma_addr_t mapping; 787 788 BUG_ON(pd->rx_buffers[index].skb); 789 BUG_ON(pd->rx_buffers[index].mapping); 790 791 if (unlikely(!skb)) 792 return -ENOMEM; 793 794 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb), 795 PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 796 if (pci_dma_mapping_error(pd->pdev, mapping)) { 797 dev_kfree_skb_any(skb); 798 netif_warn(pd, rx_err, pd->dev, "pci_map_single failed!\n"); 799 return -ENOMEM; 800 } 801 802 pd->rx_buffers[index].skb = skb; 803 pd->rx_buffers[index].mapping = mapping; 804 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN; 805 pd->rx_ring[index].status = RDES0_OWN_; 806 wmb(); 807 808 return 0; 809 } 810 811 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd) 812 { 813 while (pd->rx_ring_tail != pd->rx_ring_head) { 814 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail)) 815 break; 816 817 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE; 818 } 819 } 820 821 static int smsc9420_rx_poll(struct napi_struct *napi, int budget) 822 { 823 struct smsc9420_pdata *pd = 824 container_of(napi, struct smsc9420_pdata, napi); 825 struct net_device *dev = pd->dev; 826 u32 drop_frame_cnt, dma_intr_ena, status; 827 int work_done; 828 829 for (work_done = 0; work_done < budget; work_done++) { 830 rmb(); 831 status = pd->rx_ring[pd->rx_ring_head].status; 832 833 /* stop if DMAC owns this dma descriptor */ 834 if (status & RDES0_OWN_) 835 break; 836 837 smsc9420_rx_count_stats(dev, status); 838 smsc9420_rx_handoff(pd, pd->rx_ring_head, status); 839 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE; 840 smsc9420_alloc_new_rx_buffers(pd); 841 } 842 843 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR); 844 dev->stats.rx_dropped += 845 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF); 846 847 /* Kick RXDMA */ 848 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1); 849 smsc9420_pci_flush_write(pd); 850 851 if (work_done < budget) { 852 napi_complete_done(&pd->napi, work_done); 853 854 /* re-enable RX DMA interrupts */ 855 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 856 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_); 857 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 858 smsc9420_pci_flush_write(pd); 859 } 860 return work_done; 861 } 862 863 static void 864 smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length) 865 { 866 if (unlikely(status & TDES0_ERROR_SUMMARY_)) { 867 dev->stats.tx_errors++; 868 if (status & (TDES0_EXCESSIVE_DEFERRAL_ | 869 TDES0_EXCESSIVE_COLLISIONS_)) 870 dev->stats.tx_aborted_errors++; 871 872 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_)) 873 dev->stats.tx_carrier_errors++; 874 } else { 875 dev->stats.tx_packets++; 876 dev->stats.tx_bytes += (length & 0x7FF); 877 } 878 879 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) { 880 dev->stats.collisions += 16; 881 } else { 882 dev->stats.collisions += 883 (status & TDES0_COLLISION_COUNT_MASK_) >> 884 TDES0_COLLISION_COUNT_SHFT_; 885 } 886 887 if (unlikely(status & TDES0_HEARTBEAT_FAIL_)) 888 dev->stats.tx_heartbeat_errors++; 889 } 890 891 /* Check for completed dma transfers, update stats and free skbs */ 892 static void smsc9420_complete_tx(struct net_device *dev) 893 { 894 struct smsc9420_pdata *pd = netdev_priv(dev); 895 896 while (pd->tx_ring_tail != pd->tx_ring_head) { 897 int index = pd->tx_ring_tail; 898 u32 status, length; 899 900 rmb(); 901 status = pd->tx_ring[index].status; 902 length = pd->tx_ring[index].length; 903 904 /* Check if DMA still owns this descriptor */ 905 if (unlikely(TDES0_OWN_ & status)) 906 break; 907 908 smsc9420_tx_update_stats(dev, status, length); 909 910 BUG_ON(!pd->tx_buffers[index].skb); 911 BUG_ON(!pd->tx_buffers[index].mapping); 912 913 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping, 914 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE); 915 pd->tx_buffers[index].mapping = 0; 916 917 dev_kfree_skb_any(pd->tx_buffers[index].skb); 918 pd->tx_buffers[index].skb = NULL; 919 920 pd->tx_ring[index].buffer1 = 0; 921 wmb(); 922 923 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE; 924 } 925 } 926 927 static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb, 928 struct net_device *dev) 929 { 930 struct smsc9420_pdata *pd = netdev_priv(dev); 931 dma_addr_t mapping; 932 int index = pd->tx_ring_head; 933 u32 tmp_desc1; 934 bool about_to_take_last_desc = 935 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail); 936 937 smsc9420_complete_tx(dev); 938 939 rmb(); 940 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_); 941 BUG_ON(pd->tx_buffers[index].skb); 942 BUG_ON(pd->tx_buffers[index].mapping); 943 944 mapping = pci_map_single(pd->pdev, skb->data, 945 skb->len, PCI_DMA_TODEVICE); 946 if (pci_dma_mapping_error(pd->pdev, mapping)) { 947 netif_warn(pd, tx_err, pd->dev, 948 "pci_map_single failed, dropping packet\n"); 949 return NETDEV_TX_BUSY; 950 } 951 952 pd->tx_buffers[index].skb = skb; 953 pd->tx_buffers[index].mapping = mapping; 954 955 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF)); 956 if (unlikely(about_to_take_last_desc)) { 957 tmp_desc1 |= TDES1_IC_; 958 netif_stop_queue(pd->dev); 959 } 960 961 /* check if we are at the last descriptor and need to set EOR */ 962 if (unlikely(index == (TX_RING_SIZE - 1))) 963 tmp_desc1 |= TDES1_TER_; 964 965 pd->tx_ring[index].buffer1 = mapping; 966 pd->tx_ring[index].length = tmp_desc1; 967 wmb(); 968 969 /* increment head */ 970 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE; 971 972 /* assign ownership to DMAC */ 973 pd->tx_ring[index].status = TDES0_OWN_; 974 wmb(); 975 976 skb_tx_timestamp(skb); 977 978 /* kick the DMA */ 979 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1); 980 smsc9420_pci_flush_write(pd); 981 982 return NETDEV_TX_OK; 983 } 984 985 static struct net_device_stats *smsc9420_get_stats(struct net_device *dev) 986 { 987 struct smsc9420_pdata *pd = netdev_priv(dev); 988 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR); 989 dev->stats.rx_dropped += 990 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF); 991 return &dev->stats; 992 } 993 994 static void smsc9420_set_multicast_list(struct net_device *dev) 995 { 996 struct smsc9420_pdata *pd = netdev_priv(dev); 997 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR); 998 999 if (dev->flags & IFF_PROMISC) { 1000 netif_dbg(pd, hw, pd->dev, "Promiscuous Mode Enabled\n"); 1001 mac_cr |= MAC_CR_PRMS_; 1002 mac_cr &= (~MAC_CR_MCPAS_); 1003 mac_cr &= (~MAC_CR_HPFILT_); 1004 } else if (dev->flags & IFF_ALLMULTI) { 1005 netif_dbg(pd, hw, pd->dev, "Receive all Multicast Enabled\n"); 1006 mac_cr &= (~MAC_CR_PRMS_); 1007 mac_cr |= MAC_CR_MCPAS_; 1008 mac_cr &= (~MAC_CR_HPFILT_); 1009 } else if (!netdev_mc_empty(dev)) { 1010 struct netdev_hw_addr *ha; 1011 u32 hash_lo = 0, hash_hi = 0; 1012 1013 netif_dbg(pd, hw, pd->dev, "Multicast filter enabled\n"); 1014 netdev_for_each_mc_addr(ha, dev) { 1015 u32 bit_num = smsc9420_hash(ha->addr); 1016 u32 mask = 1 << (bit_num & 0x1F); 1017 1018 if (bit_num & 0x20) 1019 hash_hi |= mask; 1020 else 1021 hash_lo |= mask; 1022 1023 } 1024 smsc9420_reg_write(pd, HASHH, hash_hi); 1025 smsc9420_reg_write(pd, HASHL, hash_lo); 1026 1027 mac_cr &= (~MAC_CR_PRMS_); 1028 mac_cr &= (~MAC_CR_MCPAS_); 1029 mac_cr |= MAC_CR_HPFILT_; 1030 } else { 1031 netif_dbg(pd, hw, pd->dev, "Receive own packets only\n"); 1032 smsc9420_reg_write(pd, HASHH, 0); 1033 smsc9420_reg_write(pd, HASHL, 0); 1034 1035 mac_cr &= (~MAC_CR_PRMS_); 1036 mac_cr &= (~MAC_CR_MCPAS_); 1037 mac_cr &= (~MAC_CR_HPFILT_); 1038 } 1039 1040 smsc9420_reg_write(pd, MAC_CR, mac_cr); 1041 smsc9420_pci_flush_write(pd); 1042 } 1043 1044 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd) 1045 { 1046 struct net_device *dev = pd->dev; 1047 struct phy_device *phy_dev = dev->phydev; 1048 u32 flow; 1049 1050 if (phy_dev->duplex == DUPLEX_FULL) { 1051 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE); 1052 u16 rmtadv = phy_read(phy_dev, MII_LPA); 1053 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); 1054 1055 if (cap & FLOW_CTRL_RX) 1056 flow = 0xFFFF0002; 1057 else 1058 flow = 0; 1059 1060 netif_info(pd, link, pd->dev, "rx pause %s, tx pause %s\n", 1061 cap & FLOW_CTRL_RX ? "enabled" : "disabled", 1062 cap & FLOW_CTRL_TX ? "enabled" : "disabled"); 1063 } else { 1064 netif_info(pd, link, pd->dev, "half duplex\n"); 1065 flow = 0; 1066 } 1067 1068 smsc9420_reg_write(pd, FLOW, flow); 1069 } 1070 1071 /* Update link mode if anything has changed. Called periodically when the 1072 * PHY is in polling mode, even if nothing has changed. */ 1073 static void smsc9420_phy_adjust_link(struct net_device *dev) 1074 { 1075 struct smsc9420_pdata *pd = netdev_priv(dev); 1076 struct phy_device *phy_dev = dev->phydev; 1077 int carrier; 1078 1079 if (phy_dev->duplex != pd->last_duplex) { 1080 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR); 1081 if (phy_dev->duplex) { 1082 netif_dbg(pd, link, pd->dev, "full duplex mode\n"); 1083 mac_cr |= MAC_CR_FDPX_; 1084 } else { 1085 netif_dbg(pd, link, pd->dev, "half duplex mode\n"); 1086 mac_cr &= ~MAC_CR_FDPX_; 1087 } 1088 smsc9420_reg_write(pd, MAC_CR, mac_cr); 1089 1090 smsc9420_phy_update_flowcontrol(pd); 1091 pd->last_duplex = phy_dev->duplex; 1092 } 1093 1094 carrier = netif_carrier_ok(dev); 1095 if (carrier != pd->last_carrier) { 1096 if (carrier) 1097 netif_dbg(pd, link, pd->dev, "carrier OK\n"); 1098 else 1099 netif_dbg(pd, link, pd->dev, "no carrier\n"); 1100 pd->last_carrier = carrier; 1101 } 1102 } 1103 1104 static int smsc9420_mii_probe(struct net_device *dev) 1105 { 1106 struct smsc9420_pdata *pd = netdev_priv(dev); 1107 struct phy_device *phydev = NULL; 1108 1109 BUG_ON(dev->phydev); 1110 1111 /* Device only supports internal PHY at address 1 */ 1112 phydev = mdiobus_get_phy(pd->mii_bus, 1); 1113 if (!phydev) { 1114 netdev_err(dev, "no PHY found at address 1\n"); 1115 return -ENODEV; 1116 } 1117 1118 phydev = phy_connect(dev, phydev_name(phydev), 1119 smsc9420_phy_adjust_link, PHY_INTERFACE_MODE_MII); 1120 1121 if (IS_ERR(phydev)) { 1122 netdev_err(dev, "Could not attach to PHY\n"); 1123 return PTR_ERR(phydev); 1124 } 1125 1126 phy_set_max_speed(phydev, SPEED_100); 1127 1128 /* mask with MAC supported features */ 1129 phy_support_asym_pause(phydev); 1130 1131 phy_attached_info(phydev); 1132 1133 pd->last_duplex = -1; 1134 pd->last_carrier = -1; 1135 1136 return 0; 1137 } 1138 1139 static int smsc9420_mii_init(struct net_device *dev) 1140 { 1141 struct smsc9420_pdata *pd = netdev_priv(dev); 1142 int err = -ENXIO; 1143 1144 pd->mii_bus = mdiobus_alloc(); 1145 if (!pd->mii_bus) { 1146 err = -ENOMEM; 1147 goto err_out_1; 1148 } 1149 pd->mii_bus->name = DRV_MDIONAME; 1150 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x", 1151 (pd->pdev->bus->number << 8) | pd->pdev->devfn); 1152 pd->mii_bus->priv = pd; 1153 pd->mii_bus->read = smsc9420_mii_read; 1154 pd->mii_bus->write = smsc9420_mii_write; 1155 1156 /* Mask all PHYs except ID 1 (internal) */ 1157 pd->mii_bus->phy_mask = ~(1 << 1); 1158 1159 if (mdiobus_register(pd->mii_bus)) { 1160 netif_warn(pd, probe, pd->dev, "Error registering mii bus\n"); 1161 goto err_out_free_bus_2; 1162 } 1163 1164 if (smsc9420_mii_probe(dev) < 0) { 1165 netif_warn(pd, probe, pd->dev, "Error probing mii bus\n"); 1166 goto err_out_unregister_bus_3; 1167 } 1168 1169 return 0; 1170 1171 err_out_unregister_bus_3: 1172 mdiobus_unregister(pd->mii_bus); 1173 err_out_free_bus_2: 1174 mdiobus_free(pd->mii_bus); 1175 err_out_1: 1176 return err; 1177 } 1178 1179 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd) 1180 { 1181 int i; 1182 1183 BUG_ON(!pd->tx_ring); 1184 1185 pd->tx_buffers = kmalloc_array(TX_RING_SIZE, 1186 sizeof(struct smsc9420_ring_info), 1187 GFP_KERNEL); 1188 if (!pd->tx_buffers) 1189 return -ENOMEM; 1190 1191 /* Initialize the TX Ring */ 1192 for (i = 0; i < TX_RING_SIZE; i++) { 1193 pd->tx_buffers[i].skb = NULL; 1194 pd->tx_buffers[i].mapping = 0; 1195 pd->tx_ring[i].status = 0; 1196 pd->tx_ring[i].length = 0; 1197 pd->tx_ring[i].buffer1 = 0; 1198 pd->tx_ring[i].buffer2 = 0; 1199 } 1200 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_; 1201 wmb(); 1202 1203 pd->tx_ring_head = 0; 1204 pd->tx_ring_tail = 0; 1205 1206 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr); 1207 smsc9420_pci_flush_write(pd); 1208 1209 return 0; 1210 } 1211 1212 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd) 1213 { 1214 int i; 1215 1216 BUG_ON(!pd->rx_ring); 1217 1218 pd->rx_buffers = kmalloc_array(RX_RING_SIZE, 1219 sizeof(struct smsc9420_ring_info), 1220 GFP_KERNEL); 1221 if (pd->rx_buffers == NULL) 1222 goto out; 1223 1224 /* initialize the rx ring */ 1225 for (i = 0; i < RX_RING_SIZE; i++) { 1226 pd->rx_ring[i].status = 0; 1227 pd->rx_ring[i].length = PKT_BUF_SZ; 1228 pd->rx_ring[i].buffer2 = 0; 1229 pd->rx_buffers[i].skb = NULL; 1230 pd->rx_buffers[i].mapping = 0; 1231 } 1232 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_); 1233 1234 /* now allocate the entire ring of skbs */ 1235 for (i = 0; i < RX_RING_SIZE; i++) { 1236 if (smsc9420_alloc_rx_buffer(pd, i)) { 1237 netif_warn(pd, ifup, pd->dev, 1238 "failed to allocate rx skb %d\n", i); 1239 goto out_free_rx_skbs; 1240 } 1241 } 1242 1243 pd->rx_ring_head = 0; 1244 pd->rx_ring_tail = 0; 1245 1246 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q); 1247 netif_dbg(pd, ifup, pd->dev, "VLAN1 = 0x%08x\n", 1248 smsc9420_reg_read(pd, VLAN1)); 1249 1250 if (pd->rx_csum) { 1251 /* Enable RX COE */ 1252 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN; 1253 smsc9420_reg_write(pd, COE_CR, coe); 1254 netif_dbg(pd, ifup, pd->dev, "COE_CR = 0x%08x\n", coe); 1255 } 1256 1257 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr); 1258 smsc9420_pci_flush_write(pd); 1259 1260 return 0; 1261 1262 out_free_rx_skbs: 1263 smsc9420_free_rx_ring(pd); 1264 out: 1265 return -ENOMEM; 1266 } 1267 1268 static int smsc9420_open(struct net_device *dev) 1269 { 1270 struct smsc9420_pdata *pd = netdev_priv(dev); 1271 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl; 1272 const int irq = pd->pdev->irq; 1273 unsigned long flags; 1274 int result = 0, timeout; 1275 1276 if (!is_valid_ether_addr(dev->dev_addr)) { 1277 netif_warn(pd, ifup, pd->dev, 1278 "dev_addr is not a valid MAC address\n"); 1279 result = -EADDRNOTAVAIL; 1280 goto out_0; 1281 } 1282 1283 netif_carrier_off(dev); 1284 1285 /* disable, mask and acknowledge all interrupts */ 1286 spin_lock_irqsave(&pd->int_lock, flags); 1287 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 1288 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1289 smsc9420_reg_write(pd, INT_CTL, 0); 1290 spin_unlock_irqrestore(&pd->int_lock, flags); 1291 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0); 1292 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF); 1293 smsc9420_pci_flush_write(pd); 1294 1295 result = request_irq(irq, smsc9420_isr, IRQF_SHARED, DRV_NAME, pd); 1296 if (result) { 1297 netif_warn(pd, ifup, pd->dev, "Unable to use IRQ = %d\n", irq); 1298 result = -ENODEV; 1299 goto out_0; 1300 } 1301 1302 smsc9420_dmac_soft_reset(pd); 1303 1304 /* make sure MAC_CR is sane */ 1305 smsc9420_reg_write(pd, MAC_CR, 0); 1306 1307 smsc9420_set_mac_address(dev); 1308 1309 /* Configure GPIO pins to drive LEDs */ 1310 smsc9420_reg_write(pd, GPIO_CFG, 1311 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_)); 1312 1313 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16; 1314 1315 #ifdef __BIG_ENDIAN 1316 bus_mode |= BUS_MODE_DBO_; 1317 #endif 1318 1319 smsc9420_reg_write(pd, BUS_MODE, bus_mode); 1320 1321 smsc9420_pci_flush_write(pd); 1322 1323 /* set bus master bridge arbitration priority for Rx and TX DMA */ 1324 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1); 1325 1326 smsc9420_reg_write(pd, DMAC_CONTROL, 1327 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_)); 1328 1329 smsc9420_pci_flush_write(pd); 1330 1331 /* test the IRQ connection to the ISR */ 1332 netif_dbg(pd, ifup, pd->dev, "Testing ISR using IRQ %d\n", irq); 1333 pd->software_irq_signal = false; 1334 1335 spin_lock_irqsave(&pd->int_lock, flags); 1336 /* configure interrupt deassertion timer and enable interrupts */ 1337 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_; 1338 int_cfg &= ~(INT_CFG_INT_DEAS_MASK); 1339 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK); 1340 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1341 1342 /* unmask software interrupt */ 1343 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_; 1344 smsc9420_reg_write(pd, INT_CTL, int_ctl); 1345 spin_unlock_irqrestore(&pd->int_lock, flags); 1346 smsc9420_pci_flush_write(pd); 1347 1348 timeout = 1000; 1349 while (timeout--) { 1350 if (pd->software_irq_signal) 1351 break; 1352 msleep(1); 1353 } 1354 1355 /* disable interrupts */ 1356 spin_lock_irqsave(&pd->int_lock, flags); 1357 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 1358 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1359 spin_unlock_irqrestore(&pd->int_lock, flags); 1360 1361 if (!pd->software_irq_signal) { 1362 netif_warn(pd, ifup, pd->dev, "ISR failed signaling test\n"); 1363 result = -ENODEV; 1364 goto out_free_irq_1; 1365 } 1366 1367 netif_dbg(pd, ifup, pd->dev, "ISR passed test using IRQ %d\n", irq); 1368 1369 result = smsc9420_alloc_tx_ring(pd); 1370 if (result) { 1371 netif_warn(pd, ifup, pd->dev, 1372 "Failed to Initialize tx dma ring\n"); 1373 result = -ENOMEM; 1374 goto out_free_irq_1; 1375 } 1376 1377 result = smsc9420_alloc_rx_ring(pd); 1378 if (result) { 1379 netif_warn(pd, ifup, pd->dev, 1380 "Failed to Initialize rx dma ring\n"); 1381 result = -ENOMEM; 1382 goto out_free_tx_ring_2; 1383 } 1384 1385 result = smsc9420_mii_init(dev); 1386 if (result) { 1387 netif_warn(pd, ifup, pd->dev, "Failed to initialize Phy\n"); 1388 result = -ENODEV; 1389 goto out_free_rx_ring_3; 1390 } 1391 1392 /* Bring the PHY up */ 1393 phy_start(dev->phydev); 1394 1395 napi_enable(&pd->napi); 1396 1397 /* start tx and rx */ 1398 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_; 1399 smsc9420_reg_write(pd, MAC_CR, mac_cr); 1400 1401 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); 1402 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_; 1403 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); 1404 smsc9420_pci_flush_write(pd); 1405 1406 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 1407 dma_intr_ena |= 1408 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_); 1409 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 1410 smsc9420_pci_flush_write(pd); 1411 1412 netif_wake_queue(dev); 1413 1414 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1); 1415 1416 /* enable interrupts */ 1417 spin_lock_irqsave(&pd->int_lock, flags); 1418 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_; 1419 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1420 spin_unlock_irqrestore(&pd->int_lock, flags); 1421 1422 return 0; 1423 1424 out_free_rx_ring_3: 1425 smsc9420_free_rx_ring(pd); 1426 out_free_tx_ring_2: 1427 smsc9420_free_tx_ring(pd); 1428 out_free_irq_1: 1429 free_irq(irq, pd); 1430 out_0: 1431 return result; 1432 } 1433 1434 #ifdef CONFIG_PM 1435 1436 static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state) 1437 { 1438 struct net_device *dev = pci_get_drvdata(pdev); 1439 struct smsc9420_pdata *pd = netdev_priv(dev); 1440 u32 int_cfg; 1441 ulong flags; 1442 1443 /* disable interrupts */ 1444 spin_lock_irqsave(&pd->int_lock, flags); 1445 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 1446 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1447 spin_unlock_irqrestore(&pd->int_lock, flags); 1448 1449 if (netif_running(dev)) { 1450 netif_tx_disable(dev); 1451 smsc9420_stop_tx(pd); 1452 smsc9420_free_tx_ring(pd); 1453 1454 napi_disable(&pd->napi); 1455 smsc9420_stop_rx(pd); 1456 smsc9420_free_rx_ring(pd); 1457 1458 free_irq(pd->pdev->irq, pd); 1459 1460 netif_device_detach(dev); 1461 } 1462 1463 pci_save_state(pdev); 1464 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); 1465 pci_disable_device(pdev); 1466 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1467 1468 return 0; 1469 } 1470 1471 static int smsc9420_resume(struct pci_dev *pdev) 1472 { 1473 struct net_device *dev = pci_get_drvdata(pdev); 1474 struct smsc9420_pdata *pd = netdev_priv(dev); 1475 int err; 1476 1477 pci_set_power_state(pdev, PCI_D0); 1478 pci_restore_state(pdev); 1479 1480 err = pci_enable_device(pdev); 1481 if (err) 1482 return err; 1483 1484 pci_set_master(pdev); 1485 1486 err = pci_enable_wake(pdev, PCI_D0, 0); 1487 if (err) 1488 netif_warn(pd, ifup, pd->dev, "pci_enable_wake failed: %d\n", 1489 err); 1490 1491 if (netif_running(dev)) { 1492 /* FIXME: gross. It looks like ancient PM relic.*/ 1493 err = smsc9420_open(dev); 1494 netif_device_attach(dev); 1495 } 1496 return err; 1497 } 1498 1499 #endif /* CONFIG_PM */ 1500 1501 static const struct net_device_ops smsc9420_netdev_ops = { 1502 .ndo_open = smsc9420_open, 1503 .ndo_stop = smsc9420_stop, 1504 .ndo_start_xmit = smsc9420_hard_start_xmit, 1505 .ndo_get_stats = smsc9420_get_stats, 1506 .ndo_set_rx_mode = smsc9420_set_multicast_list, 1507 .ndo_do_ioctl = smsc9420_do_ioctl, 1508 .ndo_validate_addr = eth_validate_addr, 1509 .ndo_set_mac_address = eth_mac_addr, 1510 #ifdef CONFIG_NET_POLL_CONTROLLER 1511 .ndo_poll_controller = smsc9420_poll_controller, 1512 #endif /* CONFIG_NET_POLL_CONTROLLER */ 1513 }; 1514 1515 static int 1516 smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1517 { 1518 struct net_device *dev; 1519 struct smsc9420_pdata *pd; 1520 void __iomem *virt_addr; 1521 int result = 0; 1522 u32 id_rev; 1523 1524 pr_info("%s version %s\n", DRV_DESCRIPTION, DRV_VERSION); 1525 1526 /* First do the PCI initialisation */ 1527 result = pci_enable_device(pdev); 1528 if (unlikely(result)) { 1529 pr_err("Cannot enable smsc9420\n"); 1530 goto out_0; 1531 } 1532 1533 pci_set_master(pdev); 1534 1535 dev = alloc_etherdev(sizeof(*pd)); 1536 if (!dev) 1537 goto out_disable_pci_device_1; 1538 1539 SET_NETDEV_DEV(dev, &pdev->dev); 1540 1541 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) { 1542 netdev_err(dev, "Cannot find PCI device base address\n"); 1543 goto out_free_netdev_2; 1544 } 1545 1546 if ((pci_request_regions(pdev, DRV_NAME))) { 1547 netdev_err(dev, "Cannot obtain PCI resources, aborting\n"); 1548 goto out_free_netdev_2; 1549 } 1550 1551 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 1552 netdev_err(dev, "No usable DMA configuration, aborting\n"); 1553 goto out_free_regions_3; 1554 } 1555 1556 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR), 1557 pci_resource_len(pdev, SMSC_BAR)); 1558 if (!virt_addr) { 1559 netdev_err(dev, "Cannot map device registers, aborting\n"); 1560 goto out_free_regions_3; 1561 } 1562 1563 /* registers are double mapped with 0 offset for LE and 0x200 for BE */ 1564 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET; 1565 1566 pd = netdev_priv(dev); 1567 1568 /* pci descriptors are created in the PCI consistent area */ 1569 pd->rx_ring = pci_alloc_consistent(pdev, 1570 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE + 1571 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE, 1572 &pd->rx_dma_addr); 1573 1574 if (!pd->rx_ring) 1575 goto out_free_io_4; 1576 1577 /* descriptors are aligned due to the nature of pci_alloc_consistent */ 1578 pd->tx_ring = (pd->rx_ring + RX_RING_SIZE); 1579 pd->tx_dma_addr = pd->rx_dma_addr + 1580 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE; 1581 1582 pd->pdev = pdev; 1583 pd->dev = dev; 1584 pd->ioaddr = virt_addr; 1585 pd->msg_enable = smsc_debug; 1586 pd->rx_csum = true; 1587 1588 netif_dbg(pd, probe, pd->dev, "lan_base=0x%08lx\n", (ulong)virt_addr); 1589 1590 id_rev = smsc9420_reg_read(pd, ID_REV); 1591 switch (id_rev & 0xFFFF0000) { 1592 case 0x94200000: 1593 netif_info(pd, probe, pd->dev, 1594 "LAN9420 identified, ID_REV=0x%08X\n", id_rev); 1595 break; 1596 default: 1597 netif_warn(pd, probe, pd->dev, "LAN9420 NOT identified\n"); 1598 netif_warn(pd, probe, pd->dev, "ID_REV=0x%08X\n", id_rev); 1599 goto out_free_dmadesc_5; 1600 } 1601 1602 smsc9420_dmac_soft_reset(pd); 1603 smsc9420_eeprom_reload(pd); 1604 smsc9420_check_mac_address(dev); 1605 1606 dev->netdev_ops = &smsc9420_netdev_ops; 1607 dev->ethtool_ops = &smsc9420_ethtool_ops; 1608 1609 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT); 1610 1611 result = register_netdev(dev); 1612 if (result) { 1613 netif_warn(pd, probe, pd->dev, "error %i registering device\n", 1614 result); 1615 goto out_free_dmadesc_5; 1616 } 1617 1618 pci_set_drvdata(pdev, dev); 1619 1620 spin_lock_init(&pd->int_lock); 1621 spin_lock_init(&pd->phy_lock); 1622 1623 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr); 1624 1625 return 0; 1626 1627 out_free_dmadesc_5: 1628 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) * 1629 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr); 1630 out_free_io_4: 1631 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET); 1632 out_free_regions_3: 1633 pci_release_regions(pdev); 1634 out_free_netdev_2: 1635 free_netdev(dev); 1636 out_disable_pci_device_1: 1637 pci_disable_device(pdev); 1638 out_0: 1639 return -ENODEV; 1640 } 1641 1642 static void smsc9420_remove(struct pci_dev *pdev) 1643 { 1644 struct net_device *dev; 1645 struct smsc9420_pdata *pd; 1646 1647 dev = pci_get_drvdata(pdev); 1648 if (!dev) 1649 return; 1650 1651 pd = netdev_priv(dev); 1652 unregister_netdev(dev); 1653 1654 /* tx_buffers and rx_buffers are freed in stop */ 1655 BUG_ON(pd->tx_buffers); 1656 BUG_ON(pd->rx_buffers); 1657 1658 BUG_ON(!pd->tx_ring); 1659 BUG_ON(!pd->rx_ring); 1660 1661 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) * 1662 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr); 1663 1664 iounmap(pd->ioaddr - LAN9420_CPSR_ENDIAN_OFFSET); 1665 pci_release_regions(pdev); 1666 free_netdev(dev); 1667 pci_disable_device(pdev); 1668 } 1669 1670 static struct pci_driver smsc9420_driver = { 1671 .name = DRV_NAME, 1672 .id_table = smsc9420_id_table, 1673 .probe = smsc9420_probe, 1674 .remove = smsc9420_remove, 1675 #ifdef CONFIG_PM 1676 .suspend = smsc9420_suspend, 1677 .resume = smsc9420_resume, 1678 #endif /* CONFIG_PM */ 1679 }; 1680 1681 static int __init smsc9420_init_module(void) 1682 { 1683 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT); 1684 1685 return pci_register_driver(&smsc9420_driver); 1686 } 1687 1688 static void __exit smsc9420_exit_module(void) 1689 { 1690 pci_unregister_driver(&smsc9420_driver); 1691 } 1692 1693 module_init(smsc9420_init_module); 1694 module_exit(smsc9420_exit_module); 1695