1 /*************************************************************************** 2 * 3 * Copyright (C) 2007,2008 SMSC 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 18 * 19 *************************************************************************** 20 */ 21 22 #include <linux/interrupt.h> 23 #include <linux/kernel.h> 24 #include <linux/netdevice.h> 25 #include <linux/phy.h> 26 #include <linux/pci.h> 27 #include <linux/if_vlan.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/crc32.h> 30 #include <linux/slab.h> 31 #include <linux/module.h> 32 #include <asm/unaligned.h> 33 #include "smsc9420.h" 34 35 #define DRV_NAME "smsc9420" 36 #define PFX DRV_NAME ": " 37 #define DRV_MDIONAME "smsc9420-mdio" 38 #define DRV_DESCRIPTION "SMSC LAN9420 driver" 39 #define DRV_VERSION "1.01" 40 41 MODULE_LICENSE("GPL"); 42 MODULE_VERSION(DRV_VERSION); 43 44 struct smsc9420_dma_desc { 45 u32 status; 46 u32 length; 47 u32 buffer1; 48 u32 buffer2; 49 }; 50 51 struct smsc9420_ring_info { 52 struct sk_buff *skb; 53 dma_addr_t mapping; 54 }; 55 56 struct smsc9420_pdata { 57 void __iomem *base_addr; 58 struct pci_dev *pdev; 59 struct net_device *dev; 60 61 struct smsc9420_dma_desc *rx_ring; 62 struct smsc9420_dma_desc *tx_ring; 63 struct smsc9420_ring_info *tx_buffers; 64 struct smsc9420_ring_info *rx_buffers; 65 dma_addr_t rx_dma_addr; 66 dma_addr_t tx_dma_addr; 67 int tx_ring_head, tx_ring_tail; 68 int rx_ring_head, rx_ring_tail; 69 70 spinlock_t int_lock; 71 spinlock_t phy_lock; 72 73 struct napi_struct napi; 74 75 bool software_irq_signal; 76 bool rx_csum; 77 u32 msg_enable; 78 79 struct phy_device *phy_dev; 80 struct mii_bus *mii_bus; 81 int phy_irq[PHY_MAX_ADDR]; 82 int last_duplex; 83 int last_carrier; 84 }; 85 86 static DEFINE_PCI_DEVICE_TABLE(smsc9420_id_table) = { 87 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, }, 88 { 0, } 89 }; 90 91 MODULE_DEVICE_TABLE(pci, smsc9420_id_table); 92 93 #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 94 95 static uint smsc_debug; 96 static uint debug = -1; 97 module_param(debug, uint, 0); 98 MODULE_PARM_DESC(debug, "debug level"); 99 100 #define smsc_dbg(TYPE, f, a...) \ 101 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \ 102 printk(KERN_DEBUG PFX f "\n", ## a); \ 103 } while (0) 104 105 #define smsc_info(TYPE, f, a...) \ 106 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \ 107 printk(KERN_INFO PFX f "\n", ## a); \ 108 } while (0) 109 110 #define smsc_warn(TYPE, f, a...) \ 111 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \ 112 printk(KERN_WARNING PFX f "\n", ## a); \ 113 } while (0) 114 115 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset) 116 { 117 return ioread32(pd->base_addr + offset); 118 } 119 120 static inline void 121 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value) 122 { 123 iowrite32(value, pd->base_addr + offset); 124 } 125 126 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd) 127 { 128 /* to ensure PCI write completion, we must perform a PCI read */ 129 smsc9420_reg_read(pd, ID_REV); 130 } 131 132 static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx) 133 { 134 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv; 135 unsigned long flags; 136 u32 addr; 137 int i, reg = -EIO; 138 139 spin_lock_irqsave(&pd->phy_lock, flags); 140 141 /* confirm MII not busy */ 142 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) { 143 smsc_warn(DRV, "MII is busy???"); 144 goto out; 145 } 146 147 /* set the address, index & direction (read from PHY) */ 148 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | 149 MII_ACCESS_MII_READ_; 150 smsc9420_reg_write(pd, MII_ACCESS, addr); 151 152 /* wait for read to complete with 50us timeout */ 153 for (i = 0; i < 5; i++) { 154 if (!(smsc9420_reg_read(pd, MII_ACCESS) & 155 MII_ACCESS_MII_BUSY_)) { 156 reg = (u16)smsc9420_reg_read(pd, MII_DATA); 157 goto out; 158 } 159 udelay(10); 160 } 161 162 smsc_warn(DRV, "MII busy timeout!"); 163 164 out: 165 spin_unlock_irqrestore(&pd->phy_lock, flags); 166 return reg; 167 } 168 169 static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx, 170 u16 val) 171 { 172 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv; 173 unsigned long flags; 174 u32 addr; 175 int i, reg = -EIO; 176 177 spin_lock_irqsave(&pd->phy_lock, flags); 178 179 /* confirm MII not busy */ 180 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) { 181 smsc_warn(DRV, "MII is busy???"); 182 goto out; 183 } 184 185 /* put the data to write in the MAC */ 186 smsc9420_reg_write(pd, MII_DATA, (u32)val); 187 188 /* set the address, index & direction (write to PHY) */ 189 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | 190 MII_ACCESS_MII_WRITE_; 191 smsc9420_reg_write(pd, MII_ACCESS, addr); 192 193 /* wait for write to complete with 50us timeout */ 194 for (i = 0; i < 5; i++) { 195 if (!(smsc9420_reg_read(pd, MII_ACCESS) & 196 MII_ACCESS_MII_BUSY_)) { 197 reg = 0; 198 goto out; 199 } 200 udelay(10); 201 } 202 203 smsc_warn(DRV, "MII busy timeout!"); 204 205 out: 206 spin_unlock_irqrestore(&pd->phy_lock, flags); 207 return reg; 208 } 209 210 /* Returns hash bit number for given MAC address 211 * Example: 212 * 01 00 5E 00 00 01 -> returns bit number 31 */ 213 static u32 smsc9420_hash(u8 addr[ETH_ALEN]) 214 { 215 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; 216 } 217 218 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd) 219 { 220 int timeout = 100000; 221 222 BUG_ON(!pd); 223 224 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) { 225 smsc_dbg(DRV, "smsc9420_eeprom_reload: Eeprom busy"); 226 return -EIO; 227 } 228 229 smsc9420_reg_write(pd, E2P_CMD, 230 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_)); 231 232 do { 233 udelay(10); 234 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_)) 235 return 0; 236 } while (timeout--); 237 238 smsc_warn(DRV, "smsc9420_eeprom_reload: Eeprom timed out"); 239 return -EIO; 240 } 241 242 /* Standard ioctls for mii-tool */ 243 static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 244 { 245 struct smsc9420_pdata *pd = netdev_priv(dev); 246 247 if (!netif_running(dev) || !pd->phy_dev) 248 return -EINVAL; 249 250 return phy_mii_ioctl(pd->phy_dev, ifr, cmd); 251 } 252 253 static int smsc9420_ethtool_get_settings(struct net_device *dev, 254 struct ethtool_cmd *cmd) 255 { 256 struct smsc9420_pdata *pd = netdev_priv(dev); 257 258 if (!pd->phy_dev) 259 return -ENODEV; 260 261 cmd->maxtxpkt = 1; 262 cmd->maxrxpkt = 1; 263 return phy_ethtool_gset(pd->phy_dev, cmd); 264 } 265 266 static int smsc9420_ethtool_set_settings(struct net_device *dev, 267 struct ethtool_cmd *cmd) 268 { 269 struct smsc9420_pdata *pd = netdev_priv(dev); 270 271 if (!pd->phy_dev) 272 return -ENODEV; 273 274 return phy_ethtool_sset(pd->phy_dev, cmd); 275 } 276 277 static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev, 278 struct ethtool_drvinfo *drvinfo) 279 { 280 struct smsc9420_pdata *pd = netdev_priv(netdev); 281 282 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver)); 283 strlcpy(drvinfo->bus_info, pci_name(pd->pdev), 284 sizeof(drvinfo->bus_info)); 285 strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version)); 286 } 287 288 static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev) 289 { 290 struct smsc9420_pdata *pd = netdev_priv(netdev); 291 return pd->msg_enable; 292 } 293 294 static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data) 295 { 296 struct smsc9420_pdata *pd = netdev_priv(netdev); 297 pd->msg_enable = data; 298 } 299 300 static int smsc9420_ethtool_nway_reset(struct net_device *netdev) 301 { 302 struct smsc9420_pdata *pd = netdev_priv(netdev); 303 304 if (!pd->phy_dev) 305 return -ENODEV; 306 307 return phy_start_aneg(pd->phy_dev); 308 } 309 310 static int smsc9420_ethtool_getregslen(struct net_device *dev) 311 { 312 /* all smsc9420 registers plus all phy registers */ 313 return 0x100 + (32 * sizeof(u32)); 314 } 315 316 static void 317 smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs, 318 void *buf) 319 { 320 struct smsc9420_pdata *pd = netdev_priv(dev); 321 struct phy_device *phy_dev = pd->phy_dev; 322 unsigned int i, j = 0; 323 u32 *data = buf; 324 325 regs->version = smsc9420_reg_read(pd, ID_REV); 326 for (i = 0; i < 0x100; i += (sizeof(u32))) 327 data[j++] = smsc9420_reg_read(pd, i); 328 329 // cannot read phy registers if the net device is down 330 if (!phy_dev) 331 return; 332 333 for (i = 0; i <= 31; i++) 334 data[j++] = smsc9420_mii_read(phy_dev->bus, phy_dev->addr, i); 335 } 336 337 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd) 338 { 339 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG); 340 temp &= ~GPIO_CFG_EEPR_EN_; 341 smsc9420_reg_write(pd, GPIO_CFG, temp); 342 msleep(1); 343 } 344 345 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op) 346 { 347 int timeout = 100; 348 u32 e2cmd; 349 350 smsc_dbg(HW, "op 0x%08x", op); 351 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) { 352 smsc_warn(HW, "Busy at start"); 353 return -EBUSY; 354 } 355 356 e2cmd = op | E2P_CMD_EPC_BUSY_; 357 smsc9420_reg_write(pd, E2P_CMD, e2cmd); 358 359 do { 360 msleep(1); 361 e2cmd = smsc9420_reg_read(pd, E2P_CMD); 362 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout)); 363 364 if (!timeout) { 365 smsc_info(HW, "TIMED OUT"); 366 return -EAGAIN; 367 } 368 369 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) { 370 smsc_info(HW, "Error occurred during eeprom operation"); 371 return -EINVAL; 372 } 373 374 return 0; 375 } 376 377 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd, 378 u8 address, u8 *data) 379 { 380 u32 op = E2P_CMD_EPC_CMD_READ_ | address; 381 int ret; 382 383 smsc_dbg(HW, "address 0x%x", address); 384 ret = smsc9420_eeprom_send_cmd(pd, op); 385 386 if (!ret) 387 data[address] = smsc9420_reg_read(pd, E2P_DATA); 388 389 return ret; 390 } 391 392 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd, 393 u8 address, u8 data) 394 { 395 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address; 396 int ret; 397 398 smsc_dbg(HW, "address 0x%x, data 0x%x", address, data); 399 ret = smsc9420_eeprom_send_cmd(pd, op); 400 401 if (!ret) { 402 op = E2P_CMD_EPC_CMD_WRITE_ | address; 403 smsc9420_reg_write(pd, E2P_DATA, (u32)data); 404 ret = smsc9420_eeprom_send_cmd(pd, op); 405 } 406 407 return ret; 408 } 409 410 static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev) 411 { 412 return SMSC9420_EEPROM_SIZE; 413 } 414 415 static int smsc9420_ethtool_get_eeprom(struct net_device *dev, 416 struct ethtool_eeprom *eeprom, u8 *data) 417 { 418 struct smsc9420_pdata *pd = netdev_priv(dev); 419 u8 eeprom_data[SMSC9420_EEPROM_SIZE]; 420 int len, i; 421 422 smsc9420_eeprom_enable_access(pd); 423 424 len = min(eeprom->len, SMSC9420_EEPROM_SIZE); 425 for (i = 0; i < len; i++) { 426 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data); 427 if (ret < 0) { 428 eeprom->len = 0; 429 return ret; 430 } 431 } 432 433 memcpy(data, &eeprom_data[eeprom->offset], len); 434 eeprom->magic = SMSC9420_EEPROM_MAGIC; 435 eeprom->len = len; 436 return 0; 437 } 438 439 static int smsc9420_ethtool_set_eeprom(struct net_device *dev, 440 struct ethtool_eeprom *eeprom, u8 *data) 441 { 442 struct smsc9420_pdata *pd = netdev_priv(dev); 443 int ret; 444 445 if (eeprom->magic != SMSC9420_EEPROM_MAGIC) 446 return -EINVAL; 447 448 smsc9420_eeprom_enable_access(pd); 449 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_); 450 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data); 451 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_); 452 453 /* Single byte write, according to man page */ 454 eeprom->len = 1; 455 456 return ret; 457 } 458 459 static const struct ethtool_ops smsc9420_ethtool_ops = { 460 .get_settings = smsc9420_ethtool_get_settings, 461 .set_settings = smsc9420_ethtool_set_settings, 462 .get_drvinfo = smsc9420_ethtool_get_drvinfo, 463 .get_msglevel = smsc9420_ethtool_get_msglevel, 464 .set_msglevel = smsc9420_ethtool_set_msglevel, 465 .nway_reset = smsc9420_ethtool_nway_reset, 466 .get_link = ethtool_op_get_link, 467 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len, 468 .get_eeprom = smsc9420_ethtool_get_eeprom, 469 .set_eeprom = smsc9420_ethtool_set_eeprom, 470 .get_regs_len = smsc9420_ethtool_getregslen, 471 .get_regs = smsc9420_ethtool_getregs, 472 }; 473 474 /* Sets the device MAC address to dev_addr */ 475 static void smsc9420_set_mac_address(struct net_device *dev) 476 { 477 struct smsc9420_pdata *pd = netdev_priv(dev); 478 u8 *dev_addr = dev->dev_addr; 479 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4]; 480 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | 481 (dev_addr[1] << 8) | dev_addr[0]; 482 483 smsc9420_reg_write(pd, ADDRH, mac_high16); 484 smsc9420_reg_write(pd, ADDRL, mac_low32); 485 } 486 487 static void smsc9420_check_mac_address(struct net_device *dev) 488 { 489 struct smsc9420_pdata *pd = netdev_priv(dev); 490 491 /* Check if mac address has been specified when bringing interface up */ 492 if (is_valid_ether_addr(dev->dev_addr)) { 493 smsc9420_set_mac_address(dev); 494 smsc_dbg(PROBE, "MAC Address is specified by configuration"); 495 } else { 496 /* Try reading mac address from device. if EEPROM is present 497 * it will already have been set */ 498 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH); 499 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL); 500 dev->dev_addr[0] = (u8)(mac_low32); 501 dev->dev_addr[1] = (u8)(mac_low32 >> 8); 502 dev->dev_addr[2] = (u8)(mac_low32 >> 16); 503 dev->dev_addr[3] = (u8)(mac_low32 >> 24); 504 dev->dev_addr[4] = (u8)(mac_high16); 505 dev->dev_addr[5] = (u8)(mac_high16 >> 8); 506 507 if (is_valid_ether_addr(dev->dev_addr)) { 508 /* eeprom values are valid so use them */ 509 smsc_dbg(PROBE, "Mac Address is read from EEPROM"); 510 } else { 511 /* eeprom values are invalid, generate random MAC */ 512 random_ether_addr(dev->dev_addr); 513 smsc9420_set_mac_address(dev); 514 smsc_dbg(PROBE, 515 "MAC Address is set to random_ether_addr"); 516 } 517 } 518 } 519 520 static void smsc9420_stop_tx(struct smsc9420_pdata *pd) 521 { 522 u32 dmac_control, mac_cr, dma_intr_ena; 523 int timeout = 1000; 524 525 /* disable TX DMAC */ 526 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); 527 dmac_control &= (~DMAC_CONTROL_ST_); 528 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); 529 530 /* Wait max 10ms for transmit process to stop */ 531 while (--timeout) { 532 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_) 533 break; 534 udelay(10); 535 } 536 537 if (!timeout) 538 smsc_warn(IFDOWN, "TX DMAC failed to stop"); 539 540 /* ACK Tx DMAC stop bit */ 541 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_); 542 543 /* mask TX DMAC interrupts */ 544 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 545 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_); 546 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 547 smsc9420_pci_flush_write(pd); 548 549 /* stop MAC TX */ 550 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_); 551 smsc9420_reg_write(pd, MAC_CR, mac_cr); 552 smsc9420_pci_flush_write(pd); 553 } 554 555 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd) 556 { 557 int i; 558 559 BUG_ON(!pd->tx_ring); 560 561 if (!pd->tx_buffers) 562 return; 563 564 for (i = 0; i < TX_RING_SIZE; i++) { 565 struct sk_buff *skb = pd->tx_buffers[i].skb; 566 567 if (skb) { 568 BUG_ON(!pd->tx_buffers[i].mapping); 569 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping, 570 skb->len, PCI_DMA_TODEVICE); 571 dev_kfree_skb_any(skb); 572 } 573 574 pd->tx_ring[i].status = 0; 575 pd->tx_ring[i].length = 0; 576 pd->tx_ring[i].buffer1 = 0; 577 pd->tx_ring[i].buffer2 = 0; 578 } 579 wmb(); 580 581 kfree(pd->tx_buffers); 582 pd->tx_buffers = NULL; 583 584 pd->tx_ring_head = 0; 585 pd->tx_ring_tail = 0; 586 } 587 588 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd) 589 { 590 int i; 591 592 BUG_ON(!pd->rx_ring); 593 594 if (!pd->rx_buffers) 595 return; 596 597 for (i = 0; i < RX_RING_SIZE; i++) { 598 if (pd->rx_buffers[i].skb) 599 dev_kfree_skb_any(pd->rx_buffers[i].skb); 600 601 if (pd->rx_buffers[i].mapping) 602 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping, 603 PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 604 605 pd->rx_ring[i].status = 0; 606 pd->rx_ring[i].length = 0; 607 pd->rx_ring[i].buffer1 = 0; 608 pd->rx_ring[i].buffer2 = 0; 609 } 610 wmb(); 611 612 kfree(pd->rx_buffers); 613 pd->rx_buffers = NULL; 614 615 pd->rx_ring_head = 0; 616 pd->rx_ring_tail = 0; 617 } 618 619 static void smsc9420_stop_rx(struct smsc9420_pdata *pd) 620 { 621 int timeout = 1000; 622 u32 mac_cr, dmac_control, dma_intr_ena; 623 624 /* mask RX DMAC interrupts */ 625 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 626 dma_intr_ena &= (~DMAC_INTR_ENA_RX_); 627 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 628 smsc9420_pci_flush_write(pd); 629 630 /* stop RX MAC prior to stoping DMA */ 631 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_); 632 smsc9420_reg_write(pd, MAC_CR, mac_cr); 633 smsc9420_pci_flush_write(pd); 634 635 /* stop RX DMAC */ 636 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); 637 dmac_control &= (~DMAC_CONTROL_SR_); 638 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); 639 smsc9420_pci_flush_write(pd); 640 641 /* wait up to 10ms for receive to stop */ 642 while (--timeout) { 643 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_) 644 break; 645 udelay(10); 646 } 647 648 if (!timeout) 649 smsc_warn(IFDOWN, "RX DMAC did not stop! timeout."); 650 651 /* ACK the Rx DMAC stop bit */ 652 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_); 653 } 654 655 static irqreturn_t smsc9420_isr(int irq, void *dev_id) 656 { 657 struct smsc9420_pdata *pd = dev_id; 658 u32 int_cfg, int_sts, int_ctl; 659 irqreturn_t ret = IRQ_NONE; 660 ulong flags; 661 662 BUG_ON(!pd); 663 BUG_ON(!pd->base_addr); 664 665 int_cfg = smsc9420_reg_read(pd, INT_CFG); 666 667 /* check if it's our interrupt */ 668 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) != 669 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) 670 return IRQ_NONE; 671 672 int_sts = smsc9420_reg_read(pd, INT_STAT); 673 674 if (likely(INT_STAT_DMAC_INT_ & int_sts)) { 675 u32 status = smsc9420_reg_read(pd, DMAC_STATUS); 676 u32 ints_to_clear = 0; 677 678 if (status & DMAC_STS_TX_) { 679 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_); 680 netif_wake_queue(pd->dev); 681 } 682 683 if (status & DMAC_STS_RX_) { 684 /* mask RX DMAC interrupts */ 685 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 686 dma_intr_ena &= (~DMAC_INTR_ENA_RX_); 687 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 688 smsc9420_pci_flush_write(pd); 689 690 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_); 691 napi_schedule(&pd->napi); 692 } 693 694 if (ints_to_clear) 695 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear); 696 697 ret = IRQ_HANDLED; 698 } 699 700 if (unlikely(INT_STAT_SW_INT_ & int_sts)) { 701 /* mask software interrupt */ 702 spin_lock_irqsave(&pd->int_lock, flags); 703 int_ctl = smsc9420_reg_read(pd, INT_CTL); 704 int_ctl &= (~INT_CTL_SW_INT_EN_); 705 smsc9420_reg_write(pd, INT_CTL, int_ctl); 706 spin_unlock_irqrestore(&pd->int_lock, flags); 707 708 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_); 709 pd->software_irq_signal = true; 710 smp_wmb(); 711 712 ret = IRQ_HANDLED; 713 } 714 715 /* to ensure PCI write completion, we must perform a PCI read */ 716 smsc9420_pci_flush_write(pd); 717 718 return ret; 719 } 720 721 #ifdef CONFIG_NET_POLL_CONTROLLER 722 static void smsc9420_poll_controller(struct net_device *dev) 723 { 724 disable_irq(dev->irq); 725 smsc9420_isr(0, dev); 726 enable_irq(dev->irq); 727 } 728 #endif /* CONFIG_NET_POLL_CONTROLLER */ 729 730 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd) 731 { 732 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_); 733 smsc9420_reg_read(pd, BUS_MODE); 734 udelay(2); 735 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_) 736 smsc_warn(DRV, "Software reset not cleared"); 737 } 738 739 static int smsc9420_stop(struct net_device *dev) 740 { 741 struct smsc9420_pdata *pd = netdev_priv(dev); 742 u32 int_cfg; 743 ulong flags; 744 745 BUG_ON(!pd); 746 BUG_ON(!pd->phy_dev); 747 748 /* disable master interrupt */ 749 spin_lock_irqsave(&pd->int_lock, flags); 750 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 751 smsc9420_reg_write(pd, INT_CFG, int_cfg); 752 spin_unlock_irqrestore(&pd->int_lock, flags); 753 754 netif_tx_disable(dev); 755 napi_disable(&pd->napi); 756 757 smsc9420_stop_tx(pd); 758 smsc9420_free_tx_ring(pd); 759 760 smsc9420_stop_rx(pd); 761 smsc9420_free_rx_ring(pd); 762 763 free_irq(dev->irq, pd); 764 765 smsc9420_dmac_soft_reset(pd); 766 767 phy_stop(pd->phy_dev); 768 769 phy_disconnect(pd->phy_dev); 770 pd->phy_dev = NULL; 771 mdiobus_unregister(pd->mii_bus); 772 mdiobus_free(pd->mii_bus); 773 774 return 0; 775 } 776 777 static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status) 778 { 779 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) { 780 dev->stats.rx_errors++; 781 if (desc_status & RDES0_DESCRIPTOR_ERROR_) 782 dev->stats.rx_over_errors++; 783 else if (desc_status & (RDES0_FRAME_TOO_LONG_ | 784 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_)) 785 dev->stats.rx_frame_errors++; 786 else if (desc_status & RDES0_CRC_ERROR_) 787 dev->stats.rx_crc_errors++; 788 } 789 790 if (unlikely(desc_status & RDES0_LENGTH_ERROR_)) 791 dev->stats.rx_length_errors++; 792 793 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) && 794 (desc_status & RDES0_FIRST_DESCRIPTOR_)))) 795 dev->stats.rx_length_errors++; 796 797 if (desc_status & RDES0_MULTICAST_FRAME_) 798 dev->stats.multicast++; 799 } 800 801 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index, 802 const u32 status) 803 { 804 struct net_device *dev = pd->dev; 805 struct sk_buff *skb; 806 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_) 807 >> RDES0_FRAME_LENGTH_SHFT_; 808 809 /* remove crc from packet lendth */ 810 packet_length -= 4; 811 812 if (pd->rx_csum) 813 packet_length -= 2; 814 815 dev->stats.rx_packets++; 816 dev->stats.rx_bytes += packet_length; 817 818 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping, 819 PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 820 pd->rx_buffers[index].mapping = 0; 821 822 skb = pd->rx_buffers[index].skb; 823 pd->rx_buffers[index].skb = NULL; 824 825 if (pd->rx_csum) { 826 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) + 827 NET_IP_ALIGN + packet_length + 4); 828 put_unaligned_le16(hw_csum, &skb->csum); 829 skb->ip_summed = CHECKSUM_COMPLETE; 830 } 831 832 skb_reserve(skb, NET_IP_ALIGN); 833 skb_put(skb, packet_length); 834 835 skb->protocol = eth_type_trans(skb, dev); 836 837 netif_receive_skb(skb); 838 } 839 840 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index) 841 { 842 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ); 843 dma_addr_t mapping; 844 845 BUG_ON(pd->rx_buffers[index].skb); 846 BUG_ON(pd->rx_buffers[index].mapping); 847 848 if (unlikely(!skb)) { 849 smsc_warn(RX_ERR, "Failed to allocate new skb!"); 850 return -ENOMEM; 851 } 852 853 skb->dev = pd->dev; 854 855 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb), 856 PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 857 if (pci_dma_mapping_error(pd->pdev, mapping)) { 858 dev_kfree_skb_any(skb); 859 smsc_warn(RX_ERR, "pci_map_single failed!"); 860 return -ENOMEM; 861 } 862 863 pd->rx_buffers[index].skb = skb; 864 pd->rx_buffers[index].mapping = mapping; 865 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN; 866 pd->rx_ring[index].status = RDES0_OWN_; 867 wmb(); 868 869 return 0; 870 } 871 872 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd) 873 { 874 while (pd->rx_ring_tail != pd->rx_ring_head) { 875 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail)) 876 break; 877 878 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE; 879 } 880 } 881 882 static int smsc9420_rx_poll(struct napi_struct *napi, int budget) 883 { 884 struct smsc9420_pdata *pd = 885 container_of(napi, struct smsc9420_pdata, napi); 886 struct net_device *dev = pd->dev; 887 u32 drop_frame_cnt, dma_intr_ena, status; 888 int work_done; 889 890 for (work_done = 0; work_done < budget; work_done++) { 891 rmb(); 892 status = pd->rx_ring[pd->rx_ring_head].status; 893 894 /* stop if DMAC owns this dma descriptor */ 895 if (status & RDES0_OWN_) 896 break; 897 898 smsc9420_rx_count_stats(dev, status); 899 smsc9420_rx_handoff(pd, pd->rx_ring_head, status); 900 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE; 901 smsc9420_alloc_new_rx_buffers(pd); 902 } 903 904 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR); 905 dev->stats.rx_dropped += 906 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF); 907 908 /* Kick RXDMA */ 909 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1); 910 smsc9420_pci_flush_write(pd); 911 912 if (work_done < budget) { 913 napi_complete(&pd->napi); 914 915 /* re-enable RX DMA interrupts */ 916 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 917 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_); 918 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 919 smsc9420_pci_flush_write(pd); 920 } 921 return work_done; 922 } 923 924 static void 925 smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length) 926 { 927 if (unlikely(status & TDES0_ERROR_SUMMARY_)) { 928 dev->stats.tx_errors++; 929 if (status & (TDES0_EXCESSIVE_DEFERRAL_ | 930 TDES0_EXCESSIVE_COLLISIONS_)) 931 dev->stats.tx_aborted_errors++; 932 933 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_)) 934 dev->stats.tx_carrier_errors++; 935 } else { 936 dev->stats.tx_packets++; 937 dev->stats.tx_bytes += (length & 0x7FF); 938 } 939 940 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) { 941 dev->stats.collisions += 16; 942 } else { 943 dev->stats.collisions += 944 (status & TDES0_COLLISION_COUNT_MASK_) >> 945 TDES0_COLLISION_COUNT_SHFT_; 946 } 947 948 if (unlikely(status & TDES0_HEARTBEAT_FAIL_)) 949 dev->stats.tx_heartbeat_errors++; 950 } 951 952 /* Check for completed dma transfers, update stats and free skbs */ 953 static void smsc9420_complete_tx(struct net_device *dev) 954 { 955 struct smsc9420_pdata *pd = netdev_priv(dev); 956 957 while (pd->tx_ring_tail != pd->tx_ring_head) { 958 int index = pd->tx_ring_tail; 959 u32 status, length; 960 961 rmb(); 962 status = pd->tx_ring[index].status; 963 length = pd->tx_ring[index].length; 964 965 /* Check if DMA still owns this descriptor */ 966 if (unlikely(TDES0_OWN_ & status)) 967 break; 968 969 smsc9420_tx_update_stats(dev, status, length); 970 971 BUG_ON(!pd->tx_buffers[index].skb); 972 BUG_ON(!pd->tx_buffers[index].mapping); 973 974 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping, 975 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE); 976 pd->tx_buffers[index].mapping = 0; 977 978 dev_kfree_skb_any(pd->tx_buffers[index].skb); 979 pd->tx_buffers[index].skb = NULL; 980 981 pd->tx_ring[index].buffer1 = 0; 982 wmb(); 983 984 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE; 985 } 986 } 987 988 static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb, 989 struct net_device *dev) 990 { 991 struct smsc9420_pdata *pd = netdev_priv(dev); 992 dma_addr_t mapping; 993 int index = pd->tx_ring_head; 994 u32 tmp_desc1; 995 bool about_to_take_last_desc = 996 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail); 997 998 smsc9420_complete_tx(dev); 999 1000 rmb(); 1001 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_); 1002 BUG_ON(pd->tx_buffers[index].skb); 1003 BUG_ON(pd->tx_buffers[index].mapping); 1004 1005 mapping = pci_map_single(pd->pdev, skb->data, 1006 skb->len, PCI_DMA_TODEVICE); 1007 if (pci_dma_mapping_error(pd->pdev, mapping)) { 1008 smsc_warn(TX_ERR, "pci_map_single failed, dropping packet"); 1009 return NETDEV_TX_BUSY; 1010 } 1011 1012 pd->tx_buffers[index].skb = skb; 1013 pd->tx_buffers[index].mapping = mapping; 1014 1015 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF)); 1016 if (unlikely(about_to_take_last_desc)) { 1017 tmp_desc1 |= TDES1_IC_; 1018 netif_stop_queue(pd->dev); 1019 } 1020 1021 /* check if we are at the last descriptor and need to set EOR */ 1022 if (unlikely(index == (TX_RING_SIZE - 1))) 1023 tmp_desc1 |= TDES1_TER_; 1024 1025 pd->tx_ring[index].buffer1 = mapping; 1026 pd->tx_ring[index].length = tmp_desc1; 1027 wmb(); 1028 1029 /* increment head */ 1030 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE; 1031 1032 /* assign ownership to DMAC */ 1033 pd->tx_ring[index].status = TDES0_OWN_; 1034 wmb(); 1035 1036 skb_tx_timestamp(skb); 1037 1038 /* kick the DMA */ 1039 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1); 1040 smsc9420_pci_flush_write(pd); 1041 1042 return NETDEV_TX_OK; 1043 } 1044 1045 static struct net_device_stats *smsc9420_get_stats(struct net_device *dev) 1046 { 1047 struct smsc9420_pdata *pd = netdev_priv(dev); 1048 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR); 1049 dev->stats.rx_dropped += 1050 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF); 1051 return &dev->stats; 1052 } 1053 1054 static void smsc9420_set_multicast_list(struct net_device *dev) 1055 { 1056 struct smsc9420_pdata *pd = netdev_priv(dev); 1057 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR); 1058 1059 if (dev->flags & IFF_PROMISC) { 1060 smsc_dbg(HW, "Promiscuous Mode Enabled"); 1061 mac_cr |= MAC_CR_PRMS_; 1062 mac_cr &= (~MAC_CR_MCPAS_); 1063 mac_cr &= (~MAC_CR_HPFILT_); 1064 } else if (dev->flags & IFF_ALLMULTI) { 1065 smsc_dbg(HW, "Receive all Multicast Enabled"); 1066 mac_cr &= (~MAC_CR_PRMS_); 1067 mac_cr |= MAC_CR_MCPAS_; 1068 mac_cr &= (~MAC_CR_HPFILT_); 1069 } else if (!netdev_mc_empty(dev)) { 1070 struct netdev_hw_addr *ha; 1071 u32 hash_lo = 0, hash_hi = 0; 1072 1073 smsc_dbg(HW, "Multicast filter enabled"); 1074 netdev_for_each_mc_addr(ha, dev) { 1075 u32 bit_num = smsc9420_hash(ha->addr); 1076 u32 mask = 1 << (bit_num & 0x1F); 1077 1078 if (bit_num & 0x20) 1079 hash_hi |= mask; 1080 else 1081 hash_lo |= mask; 1082 1083 } 1084 smsc9420_reg_write(pd, HASHH, hash_hi); 1085 smsc9420_reg_write(pd, HASHL, hash_lo); 1086 1087 mac_cr &= (~MAC_CR_PRMS_); 1088 mac_cr &= (~MAC_CR_MCPAS_); 1089 mac_cr |= MAC_CR_HPFILT_; 1090 } else { 1091 smsc_dbg(HW, "Receive own packets only."); 1092 smsc9420_reg_write(pd, HASHH, 0); 1093 smsc9420_reg_write(pd, HASHL, 0); 1094 1095 mac_cr &= (~MAC_CR_PRMS_); 1096 mac_cr &= (~MAC_CR_MCPAS_); 1097 mac_cr &= (~MAC_CR_HPFILT_); 1098 } 1099 1100 smsc9420_reg_write(pd, MAC_CR, mac_cr); 1101 smsc9420_pci_flush_write(pd); 1102 } 1103 1104 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd) 1105 { 1106 struct phy_device *phy_dev = pd->phy_dev; 1107 u32 flow; 1108 1109 if (phy_dev->duplex == DUPLEX_FULL) { 1110 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE); 1111 u16 rmtadv = phy_read(phy_dev, MII_LPA); 1112 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); 1113 1114 if (cap & FLOW_CTRL_RX) 1115 flow = 0xFFFF0002; 1116 else 1117 flow = 0; 1118 1119 smsc_info(LINK, "rx pause %s, tx pause %s", 1120 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"), 1121 (cap & FLOW_CTRL_TX ? "enabled" : "disabled")); 1122 } else { 1123 smsc_info(LINK, "half duplex"); 1124 flow = 0; 1125 } 1126 1127 smsc9420_reg_write(pd, FLOW, flow); 1128 } 1129 1130 /* Update link mode if anything has changed. Called periodically when the 1131 * PHY is in polling mode, even if nothing has changed. */ 1132 static void smsc9420_phy_adjust_link(struct net_device *dev) 1133 { 1134 struct smsc9420_pdata *pd = netdev_priv(dev); 1135 struct phy_device *phy_dev = pd->phy_dev; 1136 int carrier; 1137 1138 if (phy_dev->duplex != pd->last_duplex) { 1139 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR); 1140 if (phy_dev->duplex) { 1141 smsc_dbg(LINK, "full duplex mode"); 1142 mac_cr |= MAC_CR_FDPX_; 1143 } else { 1144 smsc_dbg(LINK, "half duplex mode"); 1145 mac_cr &= ~MAC_CR_FDPX_; 1146 } 1147 smsc9420_reg_write(pd, MAC_CR, mac_cr); 1148 1149 smsc9420_phy_update_flowcontrol(pd); 1150 pd->last_duplex = phy_dev->duplex; 1151 } 1152 1153 carrier = netif_carrier_ok(dev); 1154 if (carrier != pd->last_carrier) { 1155 if (carrier) 1156 smsc_dbg(LINK, "carrier OK"); 1157 else 1158 smsc_dbg(LINK, "no carrier"); 1159 pd->last_carrier = carrier; 1160 } 1161 } 1162 1163 static int smsc9420_mii_probe(struct net_device *dev) 1164 { 1165 struct smsc9420_pdata *pd = netdev_priv(dev); 1166 struct phy_device *phydev = NULL; 1167 1168 BUG_ON(pd->phy_dev); 1169 1170 /* Device only supports internal PHY at address 1 */ 1171 if (!pd->mii_bus->phy_map[1]) { 1172 pr_err("%s: no PHY found at address 1\n", dev->name); 1173 return -ENODEV; 1174 } 1175 1176 phydev = pd->mii_bus->phy_map[1]; 1177 smsc_info(PROBE, "PHY addr %d, phy_id 0x%08X", phydev->addr, 1178 phydev->phy_id); 1179 1180 phydev = phy_connect(dev, dev_name(&phydev->dev), 1181 smsc9420_phy_adjust_link, 0, PHY_INTERFACE_MODE_MII); 1182 1183 if (IS_ERR(phydev)) { 1184 pr_err("%s: Could not attach to PHY\n", dev->name); 1185 return PTR_ERR(phydev); 1186 } 1187 1188 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1189 dev->name, phydev->drv->name, dev_name(&phydev->dev), phydev->irq); 1190 1191 /* mask with MAC supported features */ 1192 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause | 1193 SUPPORTED_Asym_Pause); 1194 phydev->advertising = phydev->supported; 1195 1196 pd->phy_dev = phydev; 1197 pd->last_duplex = -1; 1198 pd->last_carrier = -1; 1199 1200 return 0; 1201 } 1202 1203 static int smsc9420_mii_init(struct net_device *dev) 1204 { 1205 struct smsc9420_pdata *pd = netdev_priv(dev); 1206 int err = -ENXIO, i; 1207 1208 pd->mii_bus = mdiobus_alloc(); 1209 if (!pd->mii_bus) { 1210 err = -ENOMEM; 1211 goto err_out_1; 1212 } 1213 pd->mii_bus->name = DRV_MDIONAME; 1214 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x", 1215 (pd->pdev->bus->number << 8) | pd->pdev->devfn); 1216 pd->mii_bus->priv = pd; 1217 pd->mii_bus->read = smsc9420_mii_read; 1218 pd->mii_bus->write = smsc9420_mii_write; 1219 pd->mii_bus->irq = pd->phy_irq; 1220 for (i = 0; i < PHY_MAX_ADDR; ++i) 1221 pd->mii_bus->irq[i] = PHY_POLL; 1222 1223 /* Mask all PHYs except ID 1 (internal) */ 1224 pd->mii_bus->phy_mask = ~(1 << 1); 1225 1226 if (mdiobus_register(pd->mii_bus)) { 1227 smsc_warn(PROBE, "Error registering mii bus"); 1228 goto err_out_free_bus_2; 1229 } 1230 1231 if (smsc9420_mii_probe(dev) < 0) { 1232 smsc_warn(PROBE, "Error probing mii bus"); 1233 goto err_out_unregister_bus_3; 1234 } 1235 1236 return 0; 1237 1238 err_out_unregister_bus_3: 1239 mdiobus_unregister(pd->mii_bus); 1240 err_out_free_bus_2: 1241 mdiobus_free(pd->mii_bus); 1242 err_out_1: 1243 return err; 1244 } 1245 1246 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd) 1247 { 1248 int i; 1249 1250 BUG_ON(!pd->tx_ring); 1251 1252 pd->tx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) * 1253 TX_RING_SIZE), GFP_KERNEL); 1254 if (!pd->tx_buffers) { 1255 smsc_warn(IFUP, "Failed to allocated tx_buffers"); 1256 return -ENOMEM; 1257 } 1258 1259 /* Initialize the TX Ring */ 1260 for (i = 0; i < TX_RING_SIZE; i++) { 1261 pd->tx_buffers[i].skb = NULL; 1262 pd->tx_buffers[i].mapping = 0; 1263 pd->tx_ring[i].status = 0; 1264 pd->tx_ring[i].length = 0; 1265 pd->tx_ring[i].buffer1 = 0; 1266 pd->tx_ring[i].buffer2 = 0; 1267 } 1268 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_; 1269 wmb(); 1270 1271 pd->tx_ring_head = 0; 1272 pd->tx_ring_tail = 0; 1273 1274 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr); 1275 smsc9420_pci_flush_write(pd); 1276 1277 return 0; 1278 } 1279 1280 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd) 1281 { 1282 int i; 1283 1284 BUG_ON(!pd->rx_ring); 1285 1286 pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) * 1287 RX_RING_SIZE), GFP_KERNEL); 1288 if (pd->rx_buffers == NULL) { 1289 smsc_warn(IFUP, "Failed to allocated rx_buffers"); 1290 goto out; 1291 } 1292 1293 /* initialize the rx ring */ 1294 for (i = 0; i < RX_RING_SIZE; i++) { 1295 pd->rx_ring[i].status = 0; 1296 pd->rx_ring[i].length = PKT_BUF_SZ; 1297 pd->rx_ring[i].buffer2 = 0; 1298 pd->rx_buffers[i].skb = NULL; 1299 pd->rx_buffers[i].mapping = 0; 1300 } 1301 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_); 1302 1303 /* now allocate the entire ring of skbs */ 1304 for (i = 0; i < RX_RING_SIZE; i++) { 1305 if (smsc9420_alloc_rx_buffer(pd, i)) { 1306 smsc_warn(IFUP, "failed to allocate rx skb %d", i); 1307 goto out_free_rx_skbs; 1308 } 1309 } 1310 1311 pd->rx_ring_head = 0; 1312 pd->rx_ring_tail = 0; 1313 1314 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q); 1315 smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1)); 1316 1317 if (pd->rx_csum) { 1318 /* Enable RX COE */ 1319 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN; 1320 smsc9420_reg_write(pd, COE_CR, coe); 1321 smsc_dbg(IFUP, "COE_CR = 0x%08x", coe); 1322 } 1323 1324 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr); 1325 smsc9420_pci_flush_write(pd); 1326 1327 return 0; 1328 1329 out_free_rx_skbs: 1330 smsc9420_free_rx_ring(pd); 1331 out: 1332 return -ENOMEM; 1333 } 1334 1335 static int smsc9420_open(struct net_device *dev) 1336 { 1337 struct smsc9420_pdata *pd; 1338 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl; 1339 unsigned long flags; 1340 int result = 0, timeout; 1341 1342 BUG_ON(!dev); 1343 pd = netdev_priv(dev); 1344 BUG_ON(!pd); 1345 1346 if (!is_valid_ether_addr(dev->dev_addr)) { 1347 smsc_warn(IFUP, "dev_addr is not a valid MAC address"); 1348 result = -EADDRNOTAVAIL; 1349 goto out_0; 1350 } 1351 1352 netif_carrier_off(dev); 1353 1354 /* disable, mask and acknowledge all interrupts */ 1355 spin_lock_irqsave(&pd->int_lock, flags); 1356 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 1357 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1358 smsc9420_reg_write(pd, INT_CTL, 0); 1359 spin_unlock_irqrestore(&pd->int_lock, flags); 1360 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0); 1361 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF); 1362 smsc9420_pci_flush_write(pd); 1363 1364 if (request_irq(dev->irq, smsc9420_isr, IRQF_SHARED | IRQF_DISABLED, 1365 DRV_NAME, pd)) { 1366 smsc_warn(IFUP, "Unable to use IRQ = %d", dev->irq); 1367 result = -ENODEV; 1368 goto out_0; 1369 } 1370 1371 smsc9420_dmac_soft_reset(pd); 1372 1373 /* make sure MAC_CR is sane */ 1374 smsc9420_reg_write(pd, MAC_CR, 0); 1375 1376 smsc9420_set_mac_address(dev); 1377 1378 /* Configure GPIO pins to drive LEDs */ 1379 smsc9420_reg_write(pd, GPIO_CFG, 1380 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_)); 1381 1382 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16; 1383 1384 #ifdef __BIG_ENDIAN 1385 bus_mode |= BUS_MODE_DBO_; 1386 #endif 1387 1388 smsc9420_reg_write(pd, BUS_MODE, bus_mode); 1389 1390 smsc9420_pci_flush_write(pd); 1391 1392 /* set bus master bridge arbitration priority for Rx and TX DMA */ 1393 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1); 1394 1395 smsc9420_reg_write(pd, DMAC_CONTROL, 1396 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_)); 1397 1398 smsc9420_pci_flush_write(pd); 1399 1400 /* test the IRQ connection to the ISR */ 1401 smsc_dbg(IFUP, "Testing ISR using IRQ %d", dev->irq); 1402 pd->software_irq_signal = false; 1403 1404 spin_lock_irqsave(&pd->int_lock, flags); 1405 /* configure interrupt deassertion timer and enable interrupts */ 1406 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_; 1407 int_cfg &= ~(INT_CFG_INT_DEAS_MASK); 1408 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK); 1409 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1410 1411 /* unmask software interrupt */ 1412 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_; 1413 smsc9420_reg_write(pd, INT_CTL, int_ctl); 1414 spin_unlock_irqrestore(&pd->int_lock, flags); 1415 smsc9420_pci_flush_write(pd); 1416 1417 timeout = 1000; 1418 while (timeout--) { 1419 if (pd->software_irq_signal) 1420 break; 1421 msleep(1); 1422 } 1423 1424 /* disable interrupts */ 1425 spin_lock_irqsave(&pd->int_lock, flags); 1426 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 1427 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1428 spin_unlock_irqrestore(&pd->int_lock, flags); 1429 1430 if (!pd->software_irq_signal) { 1431 smsc_warn(IFUP, "ISR failed signaling test"); 1432 result = -ENODEV; 1433 goto out_free_irq_1; 1434 } 1435 1436 smsc_dbg(IFUP, "ISR passed test using IRQ %d", dev->irq); 1437 1438 result = smsc9420_alloc_tx_ring(pd); 1439 if (result) { 1440 smsc_warn(IFUP, "Failed to Initialize tx dma ring"); 1441 result = -ENOMEM; 1442 goto out_free_irq_1; 1443 } 1444 1445 result = smsc9420_alloc_rx_ring(pd); 1446 if (result) { 1447 smsc_warn(IFUP, "Failed to Initialize rx dma ring"); 1448 result = -ENOMEM; 1449 goto out_free_tx_ring_2; 1450 } 1451 1452 result = smsc9420_mii_init(dev); 1453 if (result) { 1454 smsc_warn(IFUP, "Failed to initialize Phy"); 1455 result = -ENODEV; 1456 goto out_free_rx_ring_3; 1457 } 1458 1459 /* Bring the PHY up */ 1460 phy_start(pd->phy_dev); 1461 1462 napi_enable(&pd->napi); 1463 1464 /* start tx and rx */ 1465 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_; 1466 smsc9420_reg_write(pd, MAC_CR, mac_cr); 1467 1468 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); 1469 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_; 1470 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); 1471 smsc9420_pci_flush_write(pd); 1472 1473 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 1474 dma_intr_ena |= 1475 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_); 1476 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 1477 smsc9420_pci_flush_write(pd); 1478 1479 netif_wake_queue(dev); 1480 1481 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1); 1482 1483 /* enable interrupts */ 1484 spin_lock_irqsave(&pd->int_lock, flags); 1485 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_; 1486 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1487 spin_unlock_irqrestore(&pd->int_lock, flags); 1488 1489 return 0; 1490 1491 out_free_rx_ring_3: 1492 smsc9420_free_rx_ring(pd); 1493 out_free_tx_ring_2: 1494 smsc9420_free_tx_ring(pd); 1495 out_free_irq_1: 1496 free_irq(dev->irq, pd); 1497 out_0: 1498 return result; 1499 } 1500 1501 #ifdef CONFIG_PM 1502 1503 static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state) 1504 { 1505 struct net_device *dev = pci_get_drvdata(pdev); 1506 struct smsc9420_pdata *pd = netdev_priv(dev); 1507 u32 int_cfg; 1508 ulong flags; 1509 1510 /* disable interrupts */ 1511 spin_lock_irqsave(&pd->int_lock, flags); 1512 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 1513 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1514 spin_unlock_irqrestore(&pd->int_lock, flags); 1515 1516 if (netif_running(dev)) { 1517 netif_tx_disable(dev); 1518 smsc9420_stop_tx(pd); 1519 smsc9420_free_tx_ring(pd); 1520 1521 napi_disable(&pd->napi); 1522 smsc9420_stop_rx(pd); 1523 smsc9420_free_rx_ring(pd); 1524 1525 free_irq(dev->irq, pd); 1526 1527 netif_device_detach(dev); 1528 } 1529 1530 pci_save_state(pdev); 1531 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); 1532 pci_disable_device(pdev); 1533 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1534 1535 return 0; 1536 } 1537 1538 static int smsc9420_resume(struct pci_dev *pdev) 1539 { 1540 struct net_device *dev = pci_get_drvdata(pdev); 1541 struct smsc9420_pdata *pd = netdev_priv(dev); 1542 int err; 1543 1544 pci_set_power_state(pdev, PCI_D0); 1545 pci_restore_state(pdev); 1546 1547 err = pci_enable_device(pdev); 1548 if (err) 1549 return err; 1550 1551 pci_set_master(pdev); 1552 1553 err = pci_enable_wake(pdev, 0, 0); 1554 if (err) 1555 smsc_warn(IFUP, "pci_enable_wake failed: %d", err); 1556 1557 if (netif_running(dev)) { 1558 err = smsc9420_open(dev); 1559 netif_device_attach(dev); 1560 } 1561 return err; 1562 } 1563 1564 #endif /* CONFIG_PM */ 1565 1566 static const struct net_device_ops smsc9420_netdev_ops = { 1567 .ndo_open = smsc9420_open, 1568 .ndo_stop = smsc9420_stop, 1569 .ndo_start_xmit = smsc9420_hard_start_xmit, 1570 .ndo_get_stats = smsc9420_get_stats, 1571 .ndo_set_rx_mode = smsc9420_set_multicast_list, 1572 .ndo_do_ioctl = smsc9420_do_ioctl, 1573 .ndo_validate_addr = eth_validate_addr, 1574 .ndo_set_mac_address = eth_mac_addr, 1575 #ifdef CONFIG_NET_POLL_CONTROLLER 1576 .ndo_poll_controller = smsc9420_poll_controller, 1577 #endif /* CONFIG_NET_POLL_CONTROLLER */ 1578 }; 1579 1580 static int __devinit 1581 smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1582 { 1583 struct net_device *dev; 1584 struct smsc9420_pdata *pd; 1585 void __iomem *virt_addr; 1586 int result = 0; 1587 u32 id_rev; 1588 1589 printk(KERN_INFO DRV_DESCRIPTION " version " DRV_VERSION "\n"); 1590 1591 /* First do the PCI initialisation */ 1592 result = pci_enable_device(pdev); 1593 if (unlikely(result)) { 1594 printk(KERN_ERR "Cannot enable smsc9420\n"); 1595 goto out_0; 1596 } 1597 1598 pci_set_master(pdev); 1599 1600 dev = alloc_etherdev(sizeof(*pd)); 1601 if (!dev) { 1602 printk(KERN_ERR "ether device alloc failed\n"); 1603 goto out_disable_pci_device_1; 1604 } 1605 1606 SET_NETDEV_DEV(dev, &pdev->dev); 1607 1608 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) { 1609 printk(KERN_ERR "Cannot find PCI device base address\n"); 1610 goto out_free_netdev_2; 1611 } 1612 1613 if ((pci_request_regions(pdev, DRV_NAME))) { 1614 printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n"); 1615 goto out_free_netdev_2; 1616 } 1617 1618 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 1619 printk(KERN_ERR "No usable DMA configuration, aborting.\n"); 1620 goto out_free_regions_3; 1621 } 1622 1623 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR), 1624 pci_resource_len(pdev, SMSC_BAR)); 1625 if (!virt_addr) { 1626 printk(KERN_ERR "Cannot map device registers, aborting.\n"); 1627 goto out_free_regions_3; 1628 } 1629 1630 /* registers are double mapped with 0 offset for LE and 0x200 for BE */ 1631 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET; 1632 1633 dev->base_addr = (ulong)virt_addr; 1634 1635 pd = netdev_priv(dev); 1636 1637 /* pci descriptors are created in the PCI consistent area */ 1638 pd->rx_ring = pci_alloc_consistent(pdev, 1639 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE + 1640 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE, 1641 &pd->rx_dma_addr); 1642 1643 if (!pd->rx_ring) 1644 goto out_free_io_4; 1645 1646 /* descriptors are aligned due to the nature of pci_alloc_consistent */ 1647 pd->tx_ring = (struct smsc9420_dma_desc *) 1648 (pd->rx_ring + RX_RING_SIZE); 1649 pd->tx_dma_addr = pd->rx_dma_addr + 1650 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE; 1651 1652 pd->pdev = pdev; 1653 pd->dev = dev; 1654 pd->base_addr = virt_addr; 1655 pd->msg_enable = smsc_debug; 1656 pd->rx_csum = true; 1657 1658 smsc_dbg(PROBE, "lan_base=0x%08lx", (ulong)virt_addr); 1659 1660 id_rev = smsc9420_reg_read(pd, ID_REV); 1661 switch (id_rev & 0xFFFF0000) { 1662 case 0x94200000: 1663 smsc_info(PROBE, "LAN9420 identified, ID_REV=0x%08X", id_rev); 1664 break; 1665 default: 1666 smsc_warn(PROBE, "LAN9420 NOT identified"); 1667 smsc_warn(PROBE, "ID_REV=0x%08X", id_rev); 1668 goto out_free_dmadesc_5; 1669 } 1670 1671 smsc9420_dmac_soft_reset(pd); 1672 smsc9420_eeprom_reload(pd); 1673 smsc9420_check_mac_address(dev); 1674 1675 dev->netdev_ops = &smsc9420_netdev_ops; 1676 dev->ethtool_ops = &smsc9420_ethtool_ops; 1677 dev->irq = pdev->irq; 1678 1679 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT); 1680 1681 result = register_netdev(dev); 1682 if (result) { 1683 smsc_warn(PROBE, "error %i registering device", result); 1684 goto out_free_dmadesc_5; 1685 } 1686 1687 pci_set_drvdata(pdev, dev); 1688 1689 spin_lock_init(&pd->int_lock); 1690 spin_lock_init(&pd->phy_lock); 1691 1692 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr); 1693 1694 return 0; 1695 1696 out_free_dmadesc_5: 1697 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) * 1698 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr); 1699 out_free_io_4: 1700 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET); 1701 out_free_regions_3: 1702 pci_release_regions(pdev); 1703 out_free_netdev_2: 1704 free_netdev(dev); 1705 out_disable_pci_device_1: 1706 pci_disable_device(pdev); 1707 out_0: 1708 return -ENODEV; 1709 } 1710 1711 static void __devexit smsc9420_remove(struct pci_dev *pdev) 1712 { 1713 struct net_device *dev; 1714 struct smsc9420_pdata *pd; 1715 1716 dev = pci_get_drvdata(pdev); 1717 if (!dev) 1718 return; 1719 1720 pci_set_drvdata(pdev, NULL); 1721 1722 pd = netdev_priv(dev); 1723 unregister_netdev(dev); 1724 1725 /* tx_buffers and rx_buffers are freed in stop */ 1726 BUG_ON(pd->tx_buffers); 1727 BUG_ON(pd->rx_buffers); 1728 1729 BUG_ON(!pd->tx_ring); 1730 BUG_ON(!pd->rx_ring); 1731 1732 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) * 1733 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr); 1734 1735 iounmap(pd->base_addr - LAN9420_CPSR_ENDIAN_OFFSET); 1736 pci_release_regions(pdev); 1737 free_netdev(dev); 1738 pci_disable_device(pdev); 1739 } 1740 1741 static struct pci_driver smsc9420_driver = { 1742 .name = DRV_NAME, 1743 .id_table = smsc9420_id_table, 1744 .probe = smsc9420_probe, 1745 .remove = __devexit_p(smsc9420_remove), 1746 #ifdef CONFIG_PM 1747 .suspend = smsc9420_suspend, 1748 .resume = smsc9420_resume, 1749 #endif /* CONFIG_PM */ 1750 }; 1751 1752 static int __init smsc9420_init_module(void) 1753 { 1754 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT); 1755 1756 return pci_register_driver(&smsc9420_driver); 1757 } 1758 1759 static void __exit smsc9420_exit_module(void) 1760 { 1761 pci_unregister_driver(&smsc9420_driver); 1762 } 1763 1764 module_init(smsc9420_init_module); 1765 module_exit(smsc9420_exit_module); 1766