1 /* 2 * smc91x.c 3 * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices. 4 * 5 * Copyright (C) 1996 by Erik Stahlman 6 * Copyright (C) 2001 Standard Microsystems Corporation 7 * Developed by Simple Network Magic Corporation 8 * Copyright (C) 2003 Monta Vista Software, Inc. 9 * Unified SMC91x driver by Nicolas Pitre 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, see <http://www.gnu.org/licenses/>. 23 * 24 * Arguments: 25 * io = for the base address 26 * irq = for the IRQ 27 * nowait = 0 for normal wait states, 1 eliminates additional wait states 28 * 29 * original author: 30 * Erik Stahlman <erik@vt.edu> 31 * 32 * hardware multicast code: 33 * Peter Cammaert <pc@denkart.be> 34 * 35 * contributors: 36 * Daris A Nevil <dnevil@snmc.com> 37 * Nicolas Pitre <nico@fluxnic.net> 38 * Russell King <rmk@arm.linux.org.uk> 39 * 40 * History: 41 * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet 42 * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ" 43 * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111 44 * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111 45 * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111 46 * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support 47 * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races, 48 * more bus abstraction, big cleanup, etc. 49 * 29/09/03 Russell King - add driver model support 50 * - ethtool support 51 * - convert to use generic MII interface 52 * - add link up/down notification 53 * - don't try to handle full negotiation in 54 * smc_phy_configure 55 * - clean up (and fix stack overrun) in PHY 56 * MII read/write functions 57 * 22/09/04 Nicolas Pitre big update (see commit log for details) 58 */ 59 static const char version[] = 60 "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>"; 61 62 /* Debugging level */ 63 #ifndef SMC_DEBUG 64 #define SMC_DEBUG 0 65 #endif 66 67 68 #include <linux/module.h> 69 #include <linux/kernel.h> 70 #include <linux/sched.h> 71 #include <linux/delay.h> 72 #include <linux/interrupt.h> 73 #include <linux/irq.h> 74 #include <linux/errno.h> 75 #include <linux/ioport.h> 76 #include <linux/crc32.h> 77 #include <linux/platform_device.h> 78 #include <linux/spinlock.h> 79 #include <linux/ethtool.h> 80 #include <linux/mii.h> 81 #include <linux/workqueue.h> 82 #include <linux/of.h> 83 #include <linux/of_device.h> 84 #include <linux/of_gpio.h> 85 86 #include <linux/netdevice.h> 87 #include <linux/etherdevice.h> 88 #include <linux/skbuff.h> 89 90 #include <asm/io.h> 91 92 #include "smc91x.h" 93 94 #if defined(CONFIG_ASSABET_NEPONSET) 95 #include <mach/assabet.h> 96 #include <mach/neponset.h> 97 #endif 98 99 #ifndef SMC_NOWAIT 100 # define SMC_NOWAIT 0 101 #endif 102 static int nowait = SMC_NOWAIT; 103 module_param(nowait, int, 0400); 104 MODULE_PARM_DESC(nowait, "set to 1 for no wait state"); 105 106 /* 107 * Transmit timeout, default 5 seconds. 108 */ 109 static int watchdog = 1000; 110 module_param(watchdog, int, 0400); 111 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); 112 113 MODULE_LICENSE("GPL"); 114 MODULE_ALIAS("platform:smc91x"); 115 116 /* 117 * The internal workings of the driver. If you are changing anything 118 * here with the SMC stuff, you should have the datasheet and know 119 * what you are doing. 120 */ 121 #define CARDNAME "smc91x" 122 123 /* 124 * Use power-down feature of the chip 125 */ 126 #define POWER_DOWN 1 127 128 /* 129 * Wait time for memory to be free. This probably shouldn't be 130 * tuned that much, as waiting for this means nothing else happens 131 * in the system 132 */ 133 #define MEMORY_WAIT_TIME 16 134 135 /* 136 * The maximum number of processing loops allowed for each call to the 137 * IRQ handler. 138 */ 139 #define MAX_IRQ_LOOPS 8 140 141 /* 142 * This selects whether TX packets are sent one by one to the SMC91x internal 143 * memory and throttled until transmission completes. This may prevent 144 * RX overruns a litle by keeping much of the memory free for RX packets 145 * but to the expense of reduced TX throughput and increased IRQ overhead. 146 * Note this is not a cure for a too slow data bus or too high IRQ latency. 147 */ 148 #define THROTTLE_TX_PKTS 0 149 150 /* 151 * The MII clock high/low times. 2x this number gives the MII clock period 152 * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!) 153 */ 154 #define MII_DELAY 1 155 156 #define DBG(n, dev, fmt, ...) \ 157 do { \ 158 if (SMC_DEBUG >= (n)) \ 159 netdev_dbg(dev, fmt, ##__VA_ARGS__); \ 160 } while (0) 161 162 #define PRINTK(dev, fmt, ...) \ 163 do { \ 164 if (SMC_DEBUG > 0) \ 165 netdev_info(dev, fmt, ##__VA_ARGS__); \ 166 else \ 167 netdev_dbg(dev, fmt, ##__VA_ARGS__); \ 168 } while (0) 169 170 #if SMC_DEBUG > 3 171 static void PRINT_PKT(u_char *buf, int length) 172 { 173 int i; 174 int remainder; 175 int lines; 176 177 lines = length / 16; 178 remainder = length % 16; 179 180 for (i = 0; i < lines ; i ++) { 181 int cur; 182 printk(KERN_DEBUG); 183 for (cur = 0; cur < 8; cur++) { 184 u_char a, b; 185 a = *buf++; 186 b = *buf++; 187 pr_cont("%02x%02x ", a, b); 188 } 189 pr_cont("\n"); 190 } 191 printk(KERN_DEBUG); 192 for (i = 0; i < remainder/2 ; i++) { 193 u_char a, b; 194 a = *buf++; 195 b = *buf++; 196 pr_cont("%02x%02x ", a, b); 197 } 198 pr_cont("\n"); 199 } 200 #else 201 static inline void PRINT_PKT(u_char *buf, int length) { } 202 #endif 203 204 205 /* this enables an interrupt in the interrupt mask register */ 206 #define SMC_ENABLE_INT(lp, x) do { \ 207 unsigned char mask; \ 208 unsigned long smc_enable_flags; \ 209 spin_lock_irqsave(&lp->lock, smc_enable_flags); \ 210 mask = SMC_GET_INT_MASK(lp); \ 211 mask |= (x); \ 212 SMC_SET_INT_MASK(lp, mask); \ 213 spin_unlock_irqrestore(&lp->lock, smc_enable_flags); \ 214 } while (0) 215 216 /* this disables an interrupt from the interrupt mask register */ 217 #define SMC_DISABLE_INT(lp, x) do { \ 218 unsigned char mask; \ 219 unsigned long smc_disable_flags; \ 220 spin_lock_irqsave(&lp->lock, smc_disable_flags); \ 221 mask = SMC_GET_INT_MASK(lp); \ 222 mask &= ~(x); \ 223 SMC_SET_INT_MASK(lp, mask); \ 224 spin_unlock_irqrestore(&lp->lock, smc_disable_flags); \ 225 } while (0) 226 227 /* 228 * Wait while MMU is busy. This is usually in the order of a few nanosecs 229 * if at all, but let's avoid deadlocking the system if the hardware 230 * decides to go south. 231 */ 232 #define SMC_WAIT_MMU_BUSY(lp) do { \ 233 if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \ 234 unsigned long timeout = jiffies + 2; \ 235 while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \ 236 if (time_after(jiffies, timeout)) { \ 237 netdev_dbg(dev, "timeout %s line %d\n", \ 238 __FILE__, __LINE__); \ 239 break; \ 240 } \ 241 cpu_relax(); \ 242 } \ 243 } \ 244 } while (0) 245 246 247 /* 248 * this does a soft reset on the device 249 */ 250 static void smc_reset(struct net_device *dev) 251 { 252 struct smc_local *lp = netdev_priv(dev); 253 void __iomem *ioaddr = lp->base; 254 unsigned int ctl, cfg; 255 struct sk_buff *pending_skb; 256 257 DBG(2, dev, "%s\n", __func__); 258 259 /* Disable all interrupts, block TX tasklet */ 260 spin_lock_irq(&lp->lock); 261 SMC_SELECT_BANK(lp, 2); 262 SMC_SET_INT_MASK(lp, 0); 263 pending_skb = lp->pending_tx_skb; 264 lp->pending_tx_skb = NULL; 265 spin_unlock_irq(&lp->lock); 266 267 /* free any pending tx skb */ 268 if (pending_skb) { 269 dev_kfree_skb(pending_skb); 270 dev->stats.tx_errors++; 271 dev->stats.tx_aborted_errors++; 272 } 273 274 /* 275 * This resets the registers mostly to defaults, but doesn't 276 * affect EEPROM. That seems unnecessary 277 */ 278 SMC_SELECT_BANK(lp, 0); 279 SMC_SET_RCR(lp, RCR_SOFTRST); 280 281 /* 282 * Setup the Configuration Register 283 * This is necessary because the CONFIG_REG is not affected 284 * by a soft reset 285 */ 286 SMC_SELECT_BANK(lp, 1); 287 288 cfg = CONFIG_DEFAULT; 289 290 /* 291 * Setup for fast accesses if requested. If the card/system 292 * can't handle it then there will be no recovery except for 293 * a hard reset or power cycle 294 */ 295 if (lp->cfg.flags & SMC91X_NOWAIT) 296 cfg |= CONFIG_NO_WAIT; 297 298 /* 299 * Release from possible power-down state 300 * Configuration register is not affected by Soft Reset 301 */ 302 cfg |= CONFIG_EPH_POWER_EN; 303 304 SMC_SET_CONFIG(lp, cfg); 305 306 /* this should pause enough for the chip to be happy */ 307 /* 308 * elaborate? What does the chip _need_? --jgarzik 309 * 310 * This seems to be undocumented, but something the original 311 * driver(s) have always done. Suspect undocumented timing 312 * info/determined empirically. --rmk 313 */ 314 udelay(1); 315 316 /* Disable transmit and receive functionality */ 317 SMC_SELECT_BANK(lp, 0); 318 SMC_SET_RCR(lp, RCR_CLEAR); 319 SMC_SET_TCR(lp, TCR_CLEAR); 320 321 SMC_SELECT_BANK(lp, 1); 322 ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE; 323 324 /* 325 * Set the control register to automatically release successfully 326 * transmitted packets, to make the best use out of our limited 327 * memory 328 */ 329 if(!THROTTLE_TX_PKTS) 330 ctl |= CTL_AUTO_RELEASE; 331 else 332 ctl &= ~CTL_AUTO_RELEASE; 333 SMC_SET_CTL(lp, ctl); 334 335 /* Reset the MMU */ 336 SMC_SELECT_BANK(lp, 2); 337 SMC_SET_MMU_CMD(lp, MC_RESET); 338 SMC_WAIT_MMU_BUSY(lp); 339 } 340 341 /* 342 * Enable Interrupts, Receive, and Transmit 343 */ 344 static void smc_enable(struct net_device *dev) 345 { 346 struct smc_local *lp = netdev_priv(dev); 347 void __iomem *ioaddr = lp->base; 348 int mask; 349 350 DBG(2, dev, "%s\n", __func__); 351 352 /* see the header file for options in TCR/RCR DEFAULT */ 353 SMC_SELECT_BANK(lp, 0); 354 SMC_SET_TCR(lp, lp->tcr_cur_mode); 355 SMC_SET_RCR(lp, lp->rcr_cur_mode); 356 357 SMC_SELECT_BANK(lp, 1); 358 SMC_SET_MAC_ADDR(lp, dev->dev_addr); 359 360 /* now, enable interrupts */ 361 mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT; 362 if (lp->version >= (CHIP_91100 << 4)) 363 mask |= IM_MDINT; 364 SMC_SELECT_BANK(lp, 2); 365 SMC_SET_INT_MASK(lp, mask); 366 367 /* 368 * From this point the register bank must _NOT_ be switched away 369 * to something else than bank 2 without proper locking against 370 * races with any tasklet or interrupt handlers until smc_shutdown() 371 * or smc_reset() is called. 372 */ 373 } 374 375 /* 376 * this puts the device in an inactive state 377 */ 378 static void smc_shutdown(struct net_device *dev) 379 { 380 struct smc_local *lp = netdev_priv(dev); 381 void __iomem *ioaddr = lp->base; 382 struct sk_buff *pending_skb; 383 384 DBG(2, dev, "%s: %s\n", CARDNAME, __func__); 385 386 /* no more interrupts for me */ 387 spin_lock_irq(&lp->lock); 388 SMC_SELECT_BANK(lp, 2); 389 SMC_SET_INT_MASK(lp, 0); 390 pending_skb = lp->pending_tx_skb; 391 lp->pending_tx_skb = NULL; 392 spin_unlock_irq(&lp->lock); 393 if (pending_skb) 394 dev_kfree_skb(pending_skb); 395 396 /* and tell the card to stay away from that nasty outside world */ 397 SMC_SELECT_BANK(lp, 0); 398 SMC_SET_RCR(lp, RCR_CLEAR); 399 SMC_SET_TCR(lp, TCR_CLEAR); 400 401 #ifdef POWER_DOWN 402 /* finally, shut the chip down */ 403 SMC_SELECT_BANK(lp, 1); 404 SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN); 405 #endif 406 } 407 408 /* 409 * This is the procedure to handle the receipt of a packet. 410 */ 411 static inline void smc_rcv(struct net_device *dev) 412 { 413 struct smc_local *lp = netdev_priv(dev); 414 void __iomem *ioaddr = lp->base; 415 unsigned int packet_number, status, packet_len; 416 417 DBG(3, dev, "%s\n", __func__); 418 419 packet_number = SMC_GET_RXFIFO(lp); 420 if (unlikely(packet_number & RXFIFO_REMPTY)) { 421 PRINTK(dev, "smc_rcv with nothing on FIFO.\n"); 422 return; 423 } 424 425 /* read from start of packet */ 426 SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC); 427 428 /* First two words are status and packet length */ 429 SMC_GET_PKT_HDR(lp, status, packet_len); 430 packet_len &= 0x07ff; /* mask off top bits */ 431 DBG(2, dev, "RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n", 432 packet_number, status, packet_len, packet_len); 433 434 back: 435 if (unlikely(packet_len < 6 || status & RS_ERRORS)) { 436 if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) { 437 /* accept VLAN packets */ 438 status &= ~RS_TOOLONG; 439 goto back; 440 } 441 if (packet_len < 6) { 442 /* bloody hardware */ 443 netdev_err(dev, "fubar (rxlen %u status %x\n", 444 packet_len, status); 445 status |= RS_TOOSHORT; 446 } 447 SMC_WAIT_MMU_BUSY(lp); 448 SMC_SET_MMU_CMD(lp, MC_RELEASE); 449 dev->stats.rx_errors++; 450 if (status & RS_ALGNERR) 451 dev->stats.rx_frame_errors++; 452 if (status & (RS_TOOSHORT | RS_TOOLONG)) 453 dev->stats.rx_length_errors++; 454 if (status & RS_BADCRC) 455 dev->stats.rx_crc_errors++; 456 } else { 457 struct sk_buff *skb; 458 unsigned char *data; 459 unsigned int data_len; 460 461 /* set multicast stats */ 462 if (status & RS_MULTICAST) 463 dev->stats.multicast++; 464 465 /* 466 * Actual payload is packet_len - 6 (or 5 if odd byte). 467 * We want skb_reserve(2) and the final ctrl word 468 * (2 bytes, possibly containing the payload odd byte). 469 * Furthermore, we add 2 bytes to allow rounding up to 470 * multiple of 4 bytes on 32 bit buses. 471 * Hence packet_len - 6 + 2 + 2 + 2. 472 */ 473 skb = netdev_alloc_skb(dev, packet_len); 474 if (unlikely(skb == NULL)) { 475 SMC_WAIT_MMU_BUSY(lp); 476 SMC_SET_MMU_CMD(lp, MC_RELEASE); 477 dev->stats.rx_dropped++; 478 return; 479 } 480 481 /* Align IP header to 32 bits */ 482 skb_reserve(skb, 2); 483 484 /* BUG: the LAN91C111 rev A never sets this bit. Force it. */ 485 if (lp->version == 0x90) 486 status |= RS_ODDFRAME; 487 488 /* 489 * If odd length: packet_len - 5, 490 * otherwise packet_len - 6. 491 * With the trailing ctrl byte it's packet_len - 4. 492 */ 493 data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6); 494 data = skb_put(skb, data_len); 495 SMC_PULL_DATA(lp, data, packet_len - 4); 496 497 SMC_WAIT_MMU_BUSY(lp); 498 SMC_SET_MMU_CMD(lp, MC_RELEASE); 499 500 PRINT_PKT(data, packet_len - 4); 501 502 skb->protocol = eth_type_trans(skb, dev); 503 netif_rx(skb); 504 dev->stats.rx_packets++; 505 dev->stats.rx_bytes += data_len; 506 } 507 } 508 509 #ifdef CONFIG_SMP 510 /* 511 * On SMP we have the following problem: 512 * 513 * A = smc_hardware_send_pkt() 514 * B = smc_hard_start_xmit() 515 * C = smc_interrupt() 516 * 517 * A and B can never be executed simultaneously. However, at least on UP, 518 * it is possible (and even desirable) for C to interrupt execution of 519 * A or B in order to have better RX reliability and avoid overruns. 520 * C, just like A and B, must have exclusive access to the chip and 521 * each of them must lock against any other concurrent access. 522 * Unfortunately this is not possible to have C suspend execution of A or 523 * B taking place on another CPU. On UP this is no an issue since A and B 524 * are run from softirq context and C from hard IRQ context, and there is 525 * no other CPU where concurrent access can happen. 526 * If ever there is a way to force at least B and C to always be executed 527 * on the same CPU then we could use read/write locks to protect against 528 * any other concurrent access and C would always interrupt B. But life 529 * isn't that easy in a SMP world... 530 */ 531 #define smc_special_trylock(lock, flags) \ 532 ({ \ 533 int __ret; \ 534 local_irq_save(flags); \ 535 __ret = spin_trylock(lock); \ 536 if (!__ret) \ 537 local_irq_restore(flags); \ 538 __ret; \ 539 }) 540 #define smc_special_lock(lock, flags) spin_lock_irqsave(lock, flags) 541 #define smc_special_unlock(lock, flags) spin_unlock_irqrestore(lock, flags) 542 #else 543 #define smc_special_trylock(lock, flags) ((void)flags, true) 544 #define smc_special_lock(lock, flags) do { flags = 0; } while (0) 545 #define smc_special_unlock(lock, flags) do { flags = 0; } while (0) 546 #endif 547 548 /* 549 * This is called to actually send a packet to the chip. 550 */ 551 static void smc_hardware_send_pkt(unsigned long data) 552 { 553 struct net_device *dev = (struct net_device *)data; 554 struct smc_local *lp = netdev_priv(dev); 555 void __iomem *ioaddr = lp->base; 556 struct sk_buff *skb; 557 unsigned int packet_no, len; 558 unsigned char *buf; 559 unsigned long flags; 560 561 DBG(3, dev, "%s\n", __func__); 562 563 if (!smc_special_trylock(&lp->lock, flags)) { 564 netif_stop_queue(dev); 565 tasklet_schedule(&lp->tx_task); 566 return; 567 } 568 569 skb = lp->pending_tx_skb; 570 if (unlikely(!skb)) { 571 smc_special_unlock(&lp->lock, flags); 572 return; 573 } 574 lp->pending_tx_skb = NULL; 575 576 packet_no = SMC_GET_AR(lp); 577 if (unlikely(packet_no & AR_FAILED)) { 578 netdev_err(dev, "Memory allocation failed.\n"); 579 dev->stats.tx_errors++; 580 dev->stats.tx_fifo_errors++; 581 smc_special_unlock(&lp->lock, flags); 582 goto done; 583 } 584 585 /* point to the beginning of the packet */ 586 SMC_SET_PN(lp, packet_no); 587 SMC_SET_PTR(lp, PTR_AUTOINC); 588 589 buf = skb->data; 590 len = skb->len; 591 DBG(2, dev, "TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n", 592 packet_no, len, len, buf); 593 PRINT_PKT(buf, len); 594 595 /* 596 * Send the packet length (+6 for status words, length, and ctl. 597 * The card will pad to 64 bytes with zeroes if packet is too small. 598 */ 599 SMC_PUT_PKT_HDR(lp, 0, len + 6); 600 601 /* send the actual data */ 602 SMC_PUSH_DATA(lp, buf, len & ~1); 603 604 /* Send final ctl word with the last byte if there is one */ 605 SMC_outw(lp, ((len & 1) ? (0x2000 | buf[len - 1]) : 0), ioaddr, 606 DATA_REG(lp)); 607 608 /* 609 * If THROTTLE_TX_PKTS is set, we stop the queue here. This will 610 * have the effect of having at most one packet queued for TX 611 * in the chip's memory at all time. 612 * 613 * If THROTTLE_TX_PKTS is not set then the queue is stopped only 614 * when memory allocation (MC_ALLOC) does not succeed right away. 615 */ 616 if (THROTTLE_TX_PKTS) 617 netif_stop_queue(dev); 618 619 /* queue the packet for TX */ 620 SMC_SET_MMU_CMD(lp, MC_ENQUEUE); 621 smc_special_unlock(&lp->lock, flags); 622 623 netif_trans_update(dev); 624 dev->stats.tx_packets++; 625 dev->stats.tx_bytes += len; 626 627 SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT); 628 629 done: if (!THROTTLE_TX_PKTS) 630 netif_wake_queue(dev); 631 632 dev_consume_skb_any(skb); 633 } 634 635 /* 636 * Since I am not sure if I will have enough room in the chip's ram 637 * to store the packet, I call this routine which either sends it 638 * now, or set the card to generates an interrupt when ready 639 * for the packet. 640 */ 641 static netdev_tx_t 642 smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) 643 { 644 struct smc_local *lp = netdev_priv(dev); 645 void __iomem *ioaddr = lp->base; 646 unsigned int numPages, poll_count, status; 647 unsigned long flags; 648 649 DBG(3, dev, "%s\n", __func__); 650 651 BUG_ON(lp->pending_tx_skb != NULL); 652 653 /* 654 * The MMU wants the number of pages to be the number of 256 bytes 655 * 'pages', minus 1 (since a packet can't ever have 0 pages :)) 656 * 657 * The 91C111 ignores the size bits, but earlier models don't. 658 * 659 * Pkt size for allocating is data length +6 (for additional status 660 * words, length and ctl) 661 * 662 * If odd size then last byte is included in ctl word. 663 */ 664 numPages = ((skb->len & ~1) + (6 - 1)) >> 8; 665 if (unlikely(numPages > 7)) { 666 netdev_warn(dev, "Far too big packet error.\n"); 667 dev->stats.tx_errors++; 668 dev->stats.tx_dropped++; 669 dev_kfree_skb_any(skb); 670 return NETDEV_TX_OK; 671 } 672 673 smc_special_lock(&lp->lock, flags); 674 675 /* now, try to allocate the memory */ 676 SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages); 677 678 /* 679 * Poll the chip for a short amount of time in case the 680 * allocation succeeds quickly. 681 */ 682 poll_count = MEMORY_WAIT_TIME; 683 do { 684 status = SMC_GET_INT(lp); 685 if (status & IM_ALLOC_INT) { 686 SMC_ACK_INT(lp, IM_ALLOC_INT); 687 break; 688 } 689 } while (--poll_count); 690 691 smc_special_unlock(&lp->lock, flags); 692 693 lp->pending_tx_skb = skb; 694 if (!poll_count) { 695 /* oh well, wait until the chip finds memory later */ 696 netif_stop_queue(dev); 697 DBG(2, dev, "TX memory allocation deferred.\n"); 698 SMC_ENABLE_INT(lp, IM_ALLOC_INT); 699 } else { 700 /* 701 * Allocation succeeded: push packet to the chip's own memory 702 * immediately. 703 */ 704 smc_hardware_send_pkt((unsigned long)dev); 705 } 706 707 return NETDEV_TX_OK; 708 } 709 710 /* 711 * This handles a TX interrupt, which is only called when: 712 * - a TX error occurred, or 713 * - CTL_AUTO_RELEASE is not set and TX of a packet completed. 714 */ 715 static void smc_tx(struct net_device *dev) 716 { 717 struct smc_local *lp = netdev_priv(dev); 718 void __iomem *ioaddr = lp->base; 719 unsigned int saved_packet, packet_no, tx_status, pkt_len; 720 721 DBG(3, dev, "%s\n", __func__); 722 723 /* If the TX FIFO is empty then nothing to do */ 724 packet_no = SMC_GET_TXFIFO(lp); 725 if (unlikely(packet_no & TXFIFO_TEMPTY)) { 726 PRINTK(dev, "smc_tx with nothing on FIFO.\n"); 727 return; 728 } 729 730 /* select packet to read from */ 731 saved_packet = SMC_GET_PN(lp); 732 SMC_SET_PN(lp, packet_no); 733 734 /* read the first word (status word) from this packet */ 735 SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ); 736 SMC_GET_PKT_HDR(lp, tx_status, pkt_len); 737 DBG(2, dev, "TX STATUS 0x%04x PNR 0x%02x\n", 738 tx_status, packet_no); 739 740 if (!(tx_status & ES_TX_SUC)) 741 dev->stats.tx_errors++; 742 743 if (tx_status & ES_LOSTCARR) 744 dev->stats.tx_carrier_errors++; 745 746 if (tx_status & (ES_LATCOL | ES_16COL)) { 747 PRINTK(dev, "%s occurred on last xmit\n", 748 (tx_status & ES_LATCOL) ? 749 "late collision" : "too many collisions"); 750 dev->stats.tx_window_errors++; 751 if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) { 752 netdev_info(dev, "unexpectedly large number of bad collisions. Please check duplex setting.\n"); 753 } 754 } 755 756 /* kill the packet */ 757 SMC_WAIT_MMU_BUSY(lp); 758 SMC_SET_MMU_CMD(lp, MC_FREEPKT); 759 760 /* Don't restore Packet Number Reg until busy bit is cleared */ 761 SMC_WAIT_MMU_BUSY(lp); 762 SMC_SET_PN(lp, saved_packet); 763 764 /* re-enable transmit */ 765 SMC_SELECT_BANK(lp, 0); 766 SMC_SET_TCR(lp, lp->tcr_cur_mode); 767 SMC_SELECT_BANK(lp, 2); 768 } 769 770 771 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ 772 773 static void smc_mii_out(struct net_device *dev, unsigned int val, int bits) 774 { 775 struct smc_local *lp = netdev_priv(dev); 776 void __iomem *ioaddr = lp->base; 777 unsigned int mii_reg, mask; 778 779 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); 780 mii_reg |= MII_MDOE; 781 782 for (mask = 1 << (bits - 1); mask; mask >>= 1) { 783 if (val & mask) 784 mii_reg |= MII_MDO; 785 else 786 mii_reg &= ~MII_MDO; 787 788 SMC_SET_MII(lp, mii_reg); 789 udelay(MII_DELAY); 790 SMC_SET_MII(lp, mii_reg | MII_MCLK); 791 udelay(MII_DELAY); 792 } 793 } 794 795 static unsigned int smc_mii_in(struct net_device *dev, int bits) 796 { 797 struct smc_local *lp = netdev_priv(dev); 798 void __iomem *ioaddr = lp->base; 799 unsigned int mii_reg, mask, val; 800 801 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); 802 SMC_SET_MII(lp, mii_reg); 803 804 for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) { 805 if (SMC_GET_MII(lp) & MII_MDI) 806 val |= mask; 807 808 SMC_SET_MII(lp, mii_reg); 809 udelay(MII_DELAY); 810 SMC_SET_MII(lp, mii_reg | MII_MCLK); 811 udelay(MII_DELAY); 812 } 813 814 return val; 815 } 816 817 /* 818 * Reads a register from the MII Management serial interface 819 */ 820 static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg) 821 { 822 struct smc_local *lp = netdev_priv(dev); 823 void __iomem *ioaddr = lp->base; 824 unsigned int phydata; 825 826 SMC_SELECT_BANK(lp, 3); 827 828 /* Idle - 32 ones */ 829 smc_mii_out(dev, 0xffffffff, 32); 830 831 /* Start code (01) + read (10) + phyaddr + phyreg */ 832 smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14); 833 834 /* Turnaround (2bits) + phydata */ 835 phydata = smc_mii_in(dev, 18); 836 837 /* Return to idle state */ 838 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); 839 840 DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", 841 __func__, phyaddr, phyreg, phydata); 842 843 SMC_SELECT_BANK(lp, 2); 844 return phydata; 845 } 846 847 /* 848 * Writes a register to the MII Management serial interface 849 */ 850 static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg, 851 int phydata) 852 { 853 struct smc_local *lp = netdev_priv(dev); 854 void __iomem *ioaddr = lp->base; 855 856 SMC_SELECT_BANK(lp, 3); 857 858 /* Idle - 32 ones */ 859 smc_mii_out(dev, 0xffffffff, 32); 860 861 /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */ 862 smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32); 863 864 /* Return to idle state */ 865 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); 866 867 DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", 868 __func__, phyaddr, phyreg, phydata); 869 870 SMC_SELECT_BANK(lp, 2); 871 } 872 873 /* 874 * Finds and reports the PHY address 875 */ 876 static void smc_phy_detect(struct net_device *dev) 877 { 878 struct smc_local *lp = netdev_priv(dev); 879 int phyaddr; 880 881 DBG(2, dev, "%s\n", __func__); 882 883 lp->phy_type = 0; 884 885 /* 886 * Scan all 32 PHY addresses if necessary, starting at 887 * PHY#1 to PHY#31, and then PHY#0 last. 888 */ 889 for (phyaddr = 1; phyaddr < 33; ++phyaddr) { 890 unsigned int id1, id2; 891 892 /* Read the PHY identifiers */ 893 id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1); 894 id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2); 895 896 DBG(3, dev, "phy_id1=0x%x, phy_id2=0x%x\n", 897 id1, id2); 898 899 /* Make sure it is a valid identifier */ 900 if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 && 901 id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) { 902 /* Save the PHY's address */ 903 lp->mii.phy_id = phyaddr & 31; 904 lp->phy_type = id1 << 16 | id2; 905 break; 906 } 907 } 908 } 909 910 /* 911 * Sets the PHY to a configuration as determined by the user 912 */ 913 static int smc_phy_fixed(struct net_device *dev) 914 { 915 struct smc_local *lp = netdev_priv(dev); 916 void __iomem *ioaddr = lp->base; 917 int phyaddr = lp->mii.phy_id; 918 int bmcr, cfg1; 919 920 DBG(3, dev, "%s\n", __func__); 921 922 /* Enter Link Disable state */ 923 cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); 924 cfg1 |= PHY_CFG1_LNKDIS; 925 smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); 926 927 /* 928 * Set our fixed capabilities 929 * Disable auto-negotiation 930 */ 931 bmcr = 0; 932 933 if (lp->ctl_rfduplx) 934 bmcr |= BMCR_FULLDPLX; 935 936 if (lp->ctl_rspeed == 100) 937 bmcr |= BMCR_SPEED100; 938 939 /* Write our capabilities to the phy control register */ 940 smc_phy_write(dev, phyaddr, MII_BMCR, bmcr); 941 942 /* Re-Configure the Receive/Phy Control register */ 943 SMC_SELECT_BANK(lp, 0); 944 SMC_SET_RPC(lp, lp->rpc_cur_mode); 945 SMC_SELECT_BANK(lp, 2); 946 947 return 1; 948 } 949 950 /** 951 * smc_phy_reset - reset the phy 952 * @dev: net device 953 * @phy: phy address 954 * 955 * Issue a software reset for the specified PHY and 956 * wait up to 100ms for the reset to complete. We should 957 * not access the PHY for 50ms after issuing the reset. 958 * 959 * The time to wait appears to be dependent on the PHY. 960 * 961 * Must be called with lp->lock locked. 962 */ 963 static int smc_phy_reset(struct net_device *dev, int phy) 964 { 965 struct smc_local *lp = netdev_priv(dev); 966 unsigned int bmcr; 967 int timeout; 968 969 smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET); 970 971 for (timeout = 2; timeout; timeout--) { 972 spin_unlock_irq(&lp->lock); 973 msleep(50); 974 spin_lock_irq(&lp->lock); 975 976 bmcr = smc_phy_read(dev, phy, MII_BMCR); 977 if (!(bmcr & BMCR_RESET)) 978 break; 979 } 980 981 return bmcr & BMCR_RESET; 982 } 983 984 /** 985 * smc_phy_powerdown - powerdown phy 986 * @dev: net device 987 * 988 * Power down the specified PHY 989 */ 990 static void smc_phy_powerdown(struct net_device *dev) 991 { 992 struct smc_local *lp = netdev_priv(dev); 993 unsigned int bmcr; 994 int phy = lp->mii.phy_id; 995 996 if (lp->phy_type == 0) 997 return; 998 999 /* We need to ensure that no calls to smc_phy_configure are 1000 pending. 1001 */ 1002 cancel_work_sync(&lp->phy_configure); 1003 1004 bmcr = smc_phy_read(dev, phy, MII_BMCR); 1005 smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN); 1006 } 1007 1008 /** 1009 * smc_phy_check_media - check the media status and adjust TCR 1010 * @dev: net device 1011 * @init: set true for initialisation 1012 * 1013 * Select duplex mode depending on negotiation state. This 1014 * also updates our carrier state. 1015 */ 1016 static void smc_phy_check_media(struct net_device *dev, int init) 1017 { 1018 struct smc_local *lp = netdev_priv(dev); 1019 void __iomem *ioaddr = lp->base; 1020 1021 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { 1022 /* duplex state has changed */ 1023 if (lp->mii.full_duplex) { 1024 lp->tcr_cur_mode |= TCR_SWFDUP; 1025 } else { 1026 lp->tcr_cur_mode &= ~TCR_SWFDUP; 1027 } 1028 1029 SMC_SELECT_BANK(lp, 0); 1030 SMC_SET_TCR(lp, lp->tcr_cur_mode); 1031 } 1032 } 1033 1034 /* 1035 * Configures the specified PHY through the MII management interface 1036 * using Autonegotiation. 1037 * Calls smc_phy_fixed() if the user has requested a certain config. 1038 * If RPC ANEG bit is set, the media selection is dependent purely on 1039 * the selection by the MII (either in the MII BMCR reg or the result 1040 * of autonegotiation.) If the RPC ANEG bit is cleared, the selection 1041 * is controlled by the RPC SPEED and RPC DPLX bits. 1042 */ 1043 static void smc_phy_configure(struct work_struct *work) 1044 { 1045 struct smc_local *lp = 1046 container_of(work, struct smc_local, phy_configure); 1047 struct net_device *dev = lp->dev; 1048 void __iomem *ioaddr = lp->base; 1049 int phyaddr = lp->mii.phy_id; 1050 int my_phy_caps; /* My PHY capabilities */ 1051 int my_ad_caps; /* My Advertised capabilities */ 1052 int status; 1053 1054 DBG(3, dev, "smc_program_phy()\n"); 1055 1056 spin_lock_irq(&lp->lock); 1057 1058 /* 1059 * We should not be called if phy_type is zero. 1060 */ 1061 if (lp->phy_type == 0) 1062 goto smc_phy_configure_exit; 1063 1064 if (smc_phy_reset(dev, phyaddr)) { 1065 netdev_info(dev, "PHY reset timed out\n"); 1066 goto smc_phy_configure_exit; 1067 } 1068 1069 /* 1070 * Enable PHY Interrupts (for register 18) 1071 * Interrupts listed here are disabled 1072 */ 1073 smc_phy_write(dev, phyaddr, PHY_MASK_REG, 1074 PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD | 1075 PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB | 1076 PHY_INT_SPDDET | PHY_INT_DPLXDET); 1077 1078 /* Configure the Receive/Phy Control register */ 1079 SMC_SELECT_BANK(lp, 0); 1080 SMC_SET_RPC(lp, lp->rpc_cur_mode); 1081 1082 /* If the user requested no auto neg, then go set his request */ 1083 if (lp->mii.force_media) { 1084 smc_phy_fixed(dev); 1085 goto smc_phy_configure_exit; 1086 } 1087 1088 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */ 1089 my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR); 1090 1091 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) { 1092 netdev_info(dev, "Auto negotiation NOT supported\n"); 1093 smc_phy_fixed(dev); 1094 goto smc_phy_configure_exit; 1095 } 1096 1097 my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */ 1098 1099 if (my_phy_caps & BMSR_100BASE4) 1100 my_ad_caps |= ADVERTISE_100BASE4; 1101 if (my_phy_caps & BMSR_100FULL) 1102 my_ad_caps |= ADVERTISE_100FULL; 1103 if (my_phy_caps & BMSR_100HALF) 1104 my_ad_caps |= ADVERTISE_100HALF; 1105 if (my_phy_caps & BMSR_10FULL) 1106 my_ad_caps |= ADVERTISE_10FULL; 1107 if (my_phy_caps & BMSR_10HALF) 1108 my_ad_caps |= ADVERTISE_10HALF; 1109 1110 /* Disable capabilities not selected by our user */ 1111 if (lp->ctl_rspeed != 100) 1112 my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF); 1113 1114 if (!lp->ctl_rfduplx) 1115 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL); 1116 1117 /* Update our Auto-Neg Advertisement Register */ 1118 smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps); 1119 lp->mii.advertising = my_ad_caps; 1120 1121 /* 1122 * Read the register back. Without this, it appears that when 1123 * auto-negotiation is restarted, sometimes it isn't ready and 1124 * the link does not come up. 1125 */ 1126 status = smc_phy_read(dev, phyaddr, MII_ADVERTISE); 1127 1128 DBG(2, dev, "phy caps=%x\n", my_phy_caps); 1129 DBG(2, dev, "phy advertised caps=%x\n", my_ad_caps); 1130 1131 /* Restart auto-negotiation process in order to advertise my caps */ 1132 smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); 1133 1134 smc_phy_check_media(dev, 1); 1135 1136 smc_phy_configure_exit: 1137 SMC_SELECT_BANK(lp, 2); 1138 spin_unlock_irq(&lp->lock); 1139 } 1140 1141 /* 1142 * smc_phy_interrupt 1143 * 1144 * Purpose: Handle interrupts relating to PHY register 18. This is 1145 * called from the "hard" interrupt handler under our private spinlock. 1146 */ 1147 static void smc_phy_interrupt(struct net_device *dev) 1148 { 1149 struct smc_local *lp = netdev_priv(dev); 1150 int phyaddr = lp->mii.phy_id; 1151 int phy18; 1152 1153 DBG(2, dev, "%s\n", __func__); 1154 1155 if (lp->phy_type == 0) 1156 return; 1157 1158 for(;;) { 1159 smc_phy_check_media(dev, 0); 1160 1161 /* Read PHY Register 18, Status Output */ 1162 phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG); 1163 if ((phy18 & PHY_INT_INT) == 0) 1164 break; 1165 } 1166 } 1167 1168 /*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/ 1169 1170 static void smc_10bt_check_media(struct net_device *dev, int init) 1171 { 1172 struct smc_local *lp = netdev_priv(dev); 1173 void __iomem *ioaddr = lp->base; 1174 unsigned int old_carrier, new_carrier; 1175 1176 old_carrier = netif_carrier_ok(dev) ? 1 : 0; 1177 1178 SMC_SELECT_BANK(lp, 0); 1179 new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0; 1180 SMC_SELECT_BANK(lp, 2); 1181 1182 if (init || (old_carrier != new_carrier)) { 1183 if (!new_carrier) { 1184 netif_carrier_off(dev); 1185 } else { 1186 netif_carrier_on(dev); 1187 } 1188 if (netif_msg_link(lp)) 1189 netdev_info(dev, "link %s\n", 1190 new_carrier ? "up" : "down"); 1191 } 1192 } 1193 1194 static void smc_eph_interrupt(struct net_device *dev) 1195 { 1196 struct smc_local *lp = netdev_priv(dev); 1197 void __iomem *ioaddr = lp->base; 1198 unsigned int ctl; 1199 1200 smc_10bt_check_media(dev, 0); 1201 1202 SMC_SELECT_BANK(lp, 1); 1203 ctl = SMC_GET_CTL(lp); 1204 SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE); 1205 SMC_SET_CTL(lp, ctl); 1206 SMC_SELECT_BANK(lp, 2); 1207 } 1208 1209 /* 1210 * This is the main routine of the driver, to handle the device when 1211 * it needs some attention. 1212 */ 1213 static irqreturn_t smc_interrupt(int irq, void *dev_id) 1214 { 1215 struct net_device *dev = dev_id; 1216 struct smc_local *lp = netdev_priv(dev); 1217 void __iomem *ioaddr = lp->base; 1218 int status, mask, timeout, card_stats; 1219 int saved_pointer; 1220 1221 DBG(3, dev, "%s\n", __func__); 1222 1223 spin_lock(&lp->lock); 1224 1225 /* A preamble may be used when there is a potential race 1226 * between the interruptible transmit functions and this 1227 * ISR. */ 1228 SMC_INTERRUPT_PREAMBLE; 1229 1230 saved_pointer = SMC_GET_PTR(lp); 1231 mask = SMC_GET_INT_MASK(lp); 1232 SMC_SET_INT_MASK(lp, 0); 1233 1234 /* set a timeout value, so I don't stay here forever */ 1235 timeout = MAX_IRQ_LOOPS; 1236 1237 do { 1238 status = SMC_GET_INT(lp); 1239 1240 DBG(2, dev, "INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n", 1241 status, mask, 1242 ({ int meminfo; SMC_SELECT_BANK(lp, 0); 1243 meminfo = SMC_GET_MIR(lp); 1244 SMC_SELECT_BANK(lp, 2); meminfo; }), 1245 SMC_GET_FIFO(lp)); 1246 1247 status &= mask; 1248 if (!status) 1249 break; 1250 1251 if (status & IM_TX_INT) { 1252 /* do this before RX as it will free memory quickly */ 1253 DBG(3, dev, "TX int\n"); 1254 smc_tx(dev); 1255 SMC_ACK_INT(lp, IM_TX_INT); 1256 if (THROTTLE_TX_PKTS) 1257 netif_wake_queue(dev); 1258 } else if (status & IM_RCV_INT) { 1259 DBG(3, dev, "RX irq\n"); 1260 smc_rcv(dev); 1261 } else if (status & IM_ALLOC_INT) { 1262 DBG(3, dev, "Allocation irq\n"); 1263 tasklet_hi_schedule(&lp->tx_task); 1264 mask &= ~IM_ALLOC_INT; 1265 } else if (status & IM_TX_EMPTY_INT) { 1266 DBG(3, dev, "TX empty\n"); 1267 mask &= ~IM_TX_EMPTY_INT; 1268 1269 /* update stats */ 1270 SMC_SELECT_BANK(lp, 0); 1271 card_stats = SMC_GET_COUNTER(lp); 1272 SMC_SELECT_BANK(lp, 2); 1273 1274 /* single collisions */ 1275 dev->stats.collisions += card_stats & 0xF; 1276 card_stats >>= 4; 1277 1278 /* multiple collisions */ 1279 dev->stats.collisions += card_stats & 0xF; 1280 } else if (status & IM_RX_OVRN_INT) { 1281 DBG(1, dev, "RX overrun (EPH_ST 0x%04x)\n", 1282 ({ int eph_st; SMC_SELECT_BANK(lp, 0); 1283 eph_st = SMC_GET_EPH_STATUS(lp); 1284 SMC_SELECT_BANK(lp, 2); eph_st; })); 1285 SMC_ACK_INT(lp, IM_RX_OVRN_INT); 1286 dev->stats.rx_errors++; 1287 dev->stats.rx_fifo_errors++; 1288 } else if (status & IM_EPH_INT) { 1289 smc_eph_interrupt(dev); 1290 } else if (status & IM_MDINT) { 1291 SMC_ACK_INT(lp, IM_MDINT); 1292 smc_phy_interrupt(dev); 1293 } else if (status & IM_ERCV_INT) { 1294 SMC_ACK_INT(lp, IM_ERCV_INT); 1295 PRINTK(dev, "UNSUPPORTED: ERCV INTERRUPT\n"); 1296 } 1297 } while (--timeout); 1298 1299 /* restore register states */ 1300 SMC_SET_PTR(lp, saved_pointer); 1301 SMC_SET_INT_MASK(lp, mask); 1302 spin_unlock(&lp->lock); 1303 1304 #ifndef CONFIG_NET_POLL_CONTROLLER 1305 if (timeout == MAX_IRQ_LOOPS) 1306 PRINTK(dev, "spurious interrupt (mask = 0x%02x)\n", 1307 mask); 1308 #endif 1309 DBG(3, dev, "Interrupt done (%d loops)\n", 1310 MAX_IRQ_LOOPS - timeout); 1311 1312 /* 1313 * We return IRQ_HANDLED unconditionally here even if there was 1314 * nothing to do. There is a possibility that a packet might 1315 * get enqueued into the chip right after TX_EMPTY_INT is raised 1316 * but just before the CPU acknowledges the IRQ. 1317 * Better take an unneeded IRQ in some occasions than complexifying 1318 * the code for all cases. 1319 */ 1320 return IRQ_HANDLED; 1321 } 1322 1323 #ifdef CONFIG_NET_POLL_CONTROLLER 1324 /* 1325 * Polling receive - used by netconsole and other diagnostic tools 1326 * to allow network i/o with interrupts disabled. 1327 */ 1328 static void smc_poll_controller(struct net_device *dev) 1329 { 1330 disable_irq(dev->irq); 1331 smc_interrupt(dev->irq, dev); 1332 enable_irq(dev->irq); 1333 } 1334 #endif 1335 1336 /* Our watchdog timed out. Called by the networking layer */ 1337 static void smc_timeout(struct net_device *dev) 1338 { 1339 struct smc_local *lp = netdev_priv(dev); 1340 void __iomem *ioaddr = lp->base; 1341 int status, mask, eph_st, meminfo, fifo; 1342 1343 DBG(2, dev, "%s\n", __func__); 1344 1345 spin_lock_irq(&lp->lock); 1346 status = SMC_GET_INT(lp); 1347 mask = SMC_GET_INT_MASK(lp); 1348 fifo = SMC_GET_FIFO(lp); 1349 SMC_SELECT_BANK(lp, 0); 1350 eph_st = SMC_GET_EPH_STATUS(lp); 1351 meminfo = SMC_GET_MIR(lp); 1352 SMC_SELECT_BANK(lp, 2); 1353 spin_unlock_irq(&lp->lock); 1354 PRINTK(dev, "TX timeout (INT 0x%02x INTMASK 0x%02x MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n", 1355 status, mask, meminfo, fifo, eph_st); 1356 1357 smc_reset(dev); 1358 smc_enable(dev); 1359 1360 /* 1361 * Reconfiguring the PHY doesn't seem like a bad idea here, but 1362 * smc_phy_configure() calls msleep() which calls schedule_timeout() 1363 * which calls schedule(). Hence we use a work queue. 1364 */ 1365 if (lp->phy_type != 0) 1366 schedule_work(&lp->phy_configure); 1367 1368 /* We can accept TX packets again */ 1369 netif_trans_update(dev); /* prevent tx timeout */ 1370 netif_wake_queue(dev); 1371 } 1372 1373 /* 1374 * This routine will, depending on the values passed to it, 1375 * either make it accept multicast packets, go into 1376 * promiscuous mode (for TCPDUMP and cousins) or accept 1377 * a select set of multicast packets 1378 */ 1379 static void smc_set_multicast_list(struct net_device *dev) 1380 { 1381 struct smc_local *lp = netdev_priv(dev); 1382 void __iomem *ioaddr = lp->base; 1383 unsigned char multicast_table[8]; 1384 int update_multicast = 0; 1385 1386 DBG(2, dev, "%s\n", __func__); 1387 1388 if (dev->flags & IFF_PROMISC) { 1389 DBG(2, dev, "RCR_PRMS\n"); 1390 lp->rcr_cur_mode |= RCR_PRMS; 1391 } 1392 1393 /* BUG? I never disable promiscuous mode if multicasting was turned on. 1394 Now, I turn off promiscuous mode, but I don't do anything to multicasting 1395 when promiscuous mode is turned on. 1396 */ 1397 1398 /* 1399 * Here, I am setting this to accept all multicast packets. 1400 * I don't need to zero the multicast table, because the flag is 1401 * checked before the table is 1402 */ 1403 else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) { 1404 DBG(2, dev, "RCR_ALMUL\n"); 1405 lp->rcr_cur_mode |= RCR_ALMUL; 1406 } 1407 1408 /* 1409 * This sets the internal hardware table to filter out unwanted 1410 * multicast packets before they take up memory. 1411 * 1412 * The SMC chip uses a hash table where the high 6 bits of the CRC of 1413 * address are the offset into the table. If that bit is 1, then the 1414 * multicast packet is accepted. Otherwise, it's dropped silently. 1415 * 1416 * To use the 6 bits as an offset into the table, the high 3 bits are 1417 * the number of the 8 bit register, while the low 3 bits are the bit 1418 * within that register. 1419 */ 1420 else if (!netdev_mc_empty(dev)) { 1421 struct netdev_hw_addr *ha; 1422 1423 /* table for flipping the order of 3 bits */ 1424 static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7}; 1425 1426 /* start with a table of all zeros: reject all */ 1427 memset(multicast_table, 0, sizeof(multicast_table)); 1428 1429 netdev_for_each_mc_addr(ha, dev) { 1430 int position; 1431 1432 /* only use the low order bits */ 1433 position = crc32_le(~0, ha->addr, 6) & 0x3f; 1434 1435 /* do some messy swapping to put the bit in the right spot */ 1436 multicast_table[invert3[position&7]] |= 1437 (1<<invert3[(position>>3)&7]); 1438 } 1439 1440 /* be sure I get rid of flags I might have set */ 1441 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); 1442 1443 /* now, the table can be loaded into the chipset */ 1444 update_multicast = 1; 1445 } else { 1446 DBG(2, dev, "~(RCR_PRMS|RCR_ALMUL)\n"); 1447 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); 1448 1449 /* 1450 * since I'm disabling all multicast entirely, I need to 1451 * clear the multicast list 1452 */ 1453 memset(multicast_table, 0, sizeof(multicast_table)); 1454 update_multicast = 1; 1455 } 1456 1457 spin_lock_irq(&lp->lock); 1458 SMC_SELECT_BANK(lp, 0); 1459 SMC_SET_RCR(lp, lp->rcr_cur_mode); 1460 if (update_multicast) { 1461 SMC_SELECT_BANK(lp, 3); 1462 SMC_SET_MCAST(lp, multicast_table); 1463 } 1464 SMC_SELECT_BANK(lp, 2); 1465 spin_unlock_irq(&lp->lock); 1466 } 1467 1468 1469 /* 1470 * Open and Initialize the board 1471 * 1472 * Set up everything, reset the card, etc.. 1473 */ 1474 static int 1475 smc_open(struct net_device *dev) 1476 { 1477 struct smc_local *lp = netdev_priv(dev); 1478 1479 DBG(2, dev, "%s\n", __func__); 1480 1481 /* Setup the default Register Modes */ 1482 lp->tcr_cur_mode = TCR_DEFAULT; 1483 lp->rcr_cur_mode = RCR_DEFAULT; 1484 lp->rpc_cur_mode = RPC_DEFAULT | 1485 lp->cfg.leda << RPC_LSXA_SHFT | 1486 lp->cfg.ledb << RPC_LSXB_SHFT; 1487 1488 /* 1489 * If we are not using a MII interface, we need to 1490 * monitor our own carrier signal to detect faults. 1491 */ 1492 if (lp->phy_type == 0) 1493 lp->tcr_cur_mode |= TCR_MON_CSN; 1494 1495 /* reset the hardware */ 1496 smc_reset(dev); 1497 smc_enable(dev); 1498 1499 /* Configure the PHY, initialize the link state */ 1500 if (lp->phy_type != 0) 1501 smc_phy_configure(&lp->phy_configure); 1502 else { 1503 spin_lock_irq(&lp->lock); 1504 smc_10bt_check_media(dev, 1); 1505 spin_unlock_irq(&lp->lock); 1506 } 1507 1508 netif_start_queue(dev); 1509 return 0; 1510 } 1511 1512 /* 1513 * smc_close 1514 * 1515 * this makes the board clean up everything that it can 1516 * and not talk to the outside world. Caused by 1517 * an 'ifconfig ethX down' 1518 */ 1519 static int smc_close(struct net_device *dev) 1520 { 1521 struct smc_local *lp = netdev_priv(dev); 1522 1523 DBG(2, dev, "%s\n", __func__); 1524 1525 netif_stop_queue(dev); 1526 netif_carrier_off(dev); 1527 1528 /* clear everything */ 1529 smc_shutdown(dev); 1530 tasklet_kill(&lp->tx_task); 1531 smc_phy_powerdown(dev); 1532 return 0; 1533 } 1534 1535 /* 1536 * Ethtool support 1537 */ 1538 static int 1539 smc_ethtool_get_link_ksettings(struct net_device *dev, 1540 struct ethtool_link_ksettings *cmd) 1541 { 1542 struct smc_local *lp = netdev_priv(dev); 1543 1544 if (lp->phy_type != 0) { 1545 spin_lock_irq(&lp->lock); 1546 mii_ethtool_get_link_ksettings(&lp->mii, cmd); 1547 spin_unlock_irq(&lp->lock); 1548 } else { 1549 u32 supported = SUPPORTED_10baseT_Half | 1550 SUPPORTED_10baseT_Full | 1551 SUPPORTED_TP | SUPPORTED_AUI; 1552 1553 if (lp->ctl_rspeed == 10) 1554 cmd->base.speed = SPEED_10; 1555 else if (lp->ctl_rspeed == 100) 1556 cmd->base.speed = SPEED_100; 1557 1558 cmd->base.autoneg = AUTONEG_DISABLE; 1559 cmd->base.port = 0; 1560 cmd->base.duplex = lp->tcr_cur_mode & TCR_SWFDUP ? 1561 DUPLEX_FULL : DUPLEX_HALF; 1562 1563 ethtool_convert_legacy_u32_to_link_mode( 1564 cmd->link_modes.supported, supported); 1565 } 1566 1567 return 0; 1568 } 1569 1570 static int 1571 smc_ethtool_set_link_ksettings(struct net_device *dev, 1572 const struct ethtool_link_ksettings *cmd) 1573 { 1574 struct smc_local *lp = netdev_priv(dev); 1575 int ret; 1576 1577 if (lp->phy_type != 0) { 1578 spin_lock_irq(&lp->lock); 1579 ret = mii_ethtool_set_link_ksettings(&lp->mii, cmd); 1580 spin_unlock_irq(&lp->lock); 1581 } else { 1582 if (cmd->base.autoneg != AUTONEG_DISABLE || 1583 cmd->base.speed != SPEED_10 || 1584 (cmd->base.duplex != DUPLEX_HALF && 1585 cmd->base.duplex != DUPLEX_FULL) || 1586 (cmd->base.port != PORT_TP && cmd->base.port != PORT_AUI)) 1587 return -EINVAL; 1588 1589 // lp->port = cmd->base.port; 1590 lp->ctl_rfduplx = cmd->base.duplex == DUPLEX_FULL; 1591 1592 // if (netif_running(dev)) 1593 // smc_set_port(dev); 1594 1595 ret = 0; 1596 } 1597 1598 return ret; 1599 } 1600 1601 static void 1602 smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1603 { 1604 strlcpy(info->driver, CARDNAME, sizeof(info->driver)); 1605 strlcpy(info->version, version, sizeof(info->version)); 1606 strlcpy(info->bus_info, dev_name(dev->dev.parent), 1607 sizeof(info->bus_info)); 1608 } 1609 1610 static int smc_ethtool_nwayreset(struct net_device *dev) 1611 { 1612 struct smc_local *lp = netdev_priv(dev); 1613 int ret = -EINVAL; 1614 1615 if (lp->phy_type != 0) { 1616 spin_lock_irq(&lp->lock); 1617 ret = mii_nway_restart(&lp->mii); 1618 spin_unlock_irq(&lp->lock); 1619 } 1620 1621 return ret; 1622 } 1623 1624 static u32 smc_ethtool_getmsglevel(struct net_device *dev) 1625 { 1626 struct smc_local *lp = netdev_priv(dev); 1627 return lp->msg_enable; 1628 } 1629 1630 static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level) 1631 { 1632 struct smc_local *lp = netdev_priv(dev); 1633 lp->msg_enable = level; 1634 } 1635 1636 static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word) 1637 { 1638 u16 ctl; 1639 struct smc_local *lp = netdev_priv(dev); 1640 void __iomem *ioaddr = lp->base; 1641 1642 spin_lock_irq(&lp->lock); 1643 /* load word into GP register */ 1644 SMC_SELECT_BANK(lp, 1); 1645 SMC_SET_GP(lp, word); 1646 /* set the address to put the data in EEPROM */ 1647 SMC_SELECT_BANK(lp, 2); 1648 SMC_SET_PTR(lp, addr); 1649 /* tell it to write */ 1650 SMC_SELECT_BANK(lp, 1); 1651 ctl = SMC_GET_CTL(lp); 1652 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE)); 1653 /* wait for it to finish */ 1654 do { 1655 udelay(1); 1656 } while (SMC_GET_CTL(lp) & CTL_STORE); 1657 /* clean up */ 1658 SMC_SET_CTL(lp, ctl); 1659 SMC_SELECT_BANK(lp, 2); 1660 spin_unlock_irq(&lp->lock); 1661 return 0; 1662 } 1663 1664 static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word) 1665 { 1666 u16 ctl; 1667 struct smc_local *lp = netdev_priv(dev); 1668 void __iomem *ioaddr = lp->base; 1669 1670 spin_lock_irq(&lp->lock); 1671 /* set the EEPROM address to get the data from */ 1672 SMC_SELECT_BANK(lp, 2); 1673 SMC_SET_PTR(lp, addr | PTR_READ); 1674 /* tell it to load */ 1675 SMC_SELECT_BANK(lp, 1); 1676 SMC_SET_GP(lp, 0xffff); /* init to known */ 1677 ctl = SMC_GET_CTL(lp); 1678 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD)); 1679 /* wait for it to finish */ 1680 do { 1681 udelay(1); 1682 } while (SMC_GET_CTL(lp) & CTL_RELOAD); 1683 /* read word from GP register */ 1684 *word = SMC_GET_GP(lp); 1685 /* clean up */ 1686 SMC_SET_CTL(lp, ctl); 1687 SMC_SELECT_BANK(lp, 2); 1688 spin_unlock_irq(&lp->lock); 1689 return 0; 1690 } 1691 1692 static int smc_ethtool_geteeprom_len(struct net_device *dev) 1693 { 1694 return 0x23 * 2; 1695 } 1696 1697 static int smc_ethtool_geteeprom(struct net_device *dev, 1698 struct ethtool_eeprom *eeprom, u8 *data) 1699 { 1700 int i; 1701 int imax; 1702 1703 DBG(1, dev, "Reading %d bytes at %d(0x%x)\n", 1704 eeprom->len, eeprom->offset, eeprom->offset); 1705 imax = smc_ethtool_geteeprom_len(dev); 1706 for (i = 0; i < eeprom->len; i += 2) { 1707 int ret; 1708 u16 wbuf; 1709 int offset = i + eeprom->offset; 1710 if (offset > imax) 1711 break; 1712 ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf); 1713 if (ret != 0) 1714 return ret; 1715 DBG(2, dev, "Read 0x%x from 0x%x\n", wbuf, offset >> 1); 1716 data[i] = (wbuf >> 8) & 0xff; 1717 data[i+1] = wbuf & 0xff; 1718 } 1719 return 0; 1720 } 1721 1722 static int smc_ethtool_seteeprom(struct net_device *dev, 1723 struct ethtool_eeprom *eeprom, u8 *data) 1724 { 1725 int i; 1726 int imax; 1727 1728 DBG(1, dev, "Writing %d bytes to %d(0x%x)\n", 1729 eeprom->len, eeprom->offset, eeprom->offset); 1730 imax = smc_ethtool_geteeprom_len(dev); 1731 for (i = 0; i < eeprom->len; i += 2) { 1732 int ret; 1733 u16 wbuf; 1734 int offset = i + eeprom->offset; 1735 if (offset > imax) 1736 break; 1737 wbuf = (data[i] << 8) | data[i + 1]; 1738 DBG(2, dev, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1); 1739 ret = smc_write_eeprom_word(dev, offset >> 1, wbuf); 1740 if (ret != 0) 1741 return ret; 1742 } 1743 return 0; 1744 } 1745 1746 1747 static const struct ethtool_ops smc_ethtool_ops = { 1748 .get_drvinfo = smc_ethtool_getdrvinfo, 1749 1750 .get_msglevel = smc_ethtool_getmsglevel, 1751 .set_msglevel = smc_ethtool_setmsglevel, 1752 .nway_reset = smc_ethtool_nwayreset, 1753 .get_link = ethtool_op_get_link, 1754 .get_eeprom_len = smc_ethtool_geteeprom_len, 1755 .get_eeprom = smc_ethtool_geteeprom, 1756 .set_eeprom = smc_ethtool_seteeprom, 1757 .get_link_ksettings = smc_ethtool_get_link_ksettings, 1758 .set_link_ksettings = smc_ethtool_set_link_ksettings, 1759 }; 1760 1761 static const struct net_device_ops smc_netdev_ops = { 1762 .ndo_open = smc_open, 1763 .ndo_stop = smc_close, 1764 .ndo_start_xmit = smc_hard_start_xmit, 1765 .ndo_tx_timeout = smc_timeout, 1766 .ndo_set_rx_mode = smc_set_multicast_list, 1767 .ndo_validate_addr = eth_validate_addr, 1768 .ndo_set_mac_address = eth_mac_addr, 1769 #ifdef CONFIG_NET_POLL_CONTROLLER 1770 .ndo_poll_controller = smc_poll_controller, 1771 #endif 1772 }; 1773 1774 /* 1775 * smc_findirq 1776 * 1777 * This routine has a simple purpose -- make the SMC chip generate an 1778 * interrupt, so an auto-detect routine can detect it, and find the IRQ, 1779 */ 1780 /* 1781 * does this still work? 1782 * 1783 * I just deleted auto_irq.c, since it was never built... 1784 * --jgarzik 1785 */ 1786 static int smc_findirq(struct smc_local *lp) 1787 { 1788 void __iomem *ioaddr = lp->base; 1789 int timeout = 20; 1790 unsigned long cookie; 1791 1792 DBG(2, lp->dev, "%s: %s\n", CARDNAME, __func__); 1793 1794 cookie = probe_irq_on(); 1795 1796 /* 1797 * What I try to do here is trigger an ALLOC_INT. This is done 1798 * by allocating a small chunk of memory, which will give an interrupt 1799 * when done. 1800 */ 1801 /* enable ALLOCation interrupts ONLY */ 1802 SMC_SELECT_BANK(lp, 2); 1803 SMC_SET_INT_MASK(lp, IM_ALLOC_INT); 1804 1805 /* 1806 * Allocate 512 bytes of memory. Note that the chip was just 1807 * reset so all the memory is available 1808 */ 1809 SMC_SET_MMU_CMD(lp, MC_ALLOC | 1); 1810 1811 /* 1812 * Wait until positive that the interrupt has been generated 1813 */ 1814 do { 1815 int int_status; 1816 udelay(10); 1817 int_status = SMC_GET_INT(lp); 1818 if (int_status & IM_ALLOC_INT) 1819 break; /* got the interrupt */ 1820 } while (--timeout); 1821 1822 /* 1823 * there is really nothing that I can do here if timeout fails, 1824 * as autoirq_report will return a 0 anyway, which is what I 1825 * want in this case. Plus, the clean up is needed in both 1826 * cases. 1827 */ 1828 1829 /* and disable all interrupts again */ 1830 SMC_SET_INT_MASK(lp, 0); 1831 1832 /* and return what I found */ 1833 return probe_irq_off(cookie); 1834 } 1835 1836 /* 1837 * Function: smc_probe(unsigned long ioaddr) 1838 * 1839 * Purpose: 1840 * Tests to see if a given ioaddr points to an SMC91x chip. 1841 * Returns a 0 on success 1842 * 1843 * Algorithm: 1844 * (1) see if the high byte of BANK_SELECT is 0x33 1845 * (2) compare the ioaddr with the base register's address 1846 * (3) see if I recognize the chip ID in the appropriate register 1847 * 1848 * Here I do typical initialization tasks. 1849 * 1850 * o Initialize the structure if needed 1851 * o print out my vanity message if not done so already 1852 * o print out what type of hardware is detected 1853 * o print out the ethernet address 1854 * o find the IRQ 1855 * o set up my private data 1856 * o configure the dev structure with my subroutines 1857 * o actually GRAB the irq. 1858 * o GRAB the region 1859 */ 1860 static int smc_probe(struct net_device *dev, void __iomem *ioaddr, 1861 unsigned long irq_flags) 1862 { 1863 struct smc_local *lp = netdev_priv(dev); 1864 int retval; 1865 unsigned int val, revision_register; 1866 const char *version_string; 1867 1868 DBG(2, dev, "%s: %s\n", CARDNAME, __func__); 1869 1870 /* First, see if the high byte is 0x33 */ 1871 val = SMC_CURRENT_BANK(lp); 1872 DBG(2, dev, "%s: bank signature probe returned 0x%04x\n", 1873 CARDNAME, val); 1874 if ((val & 0xFF00) != 0x3300) { 1875 if ((val & 0xFF) == 0x33) { 1876 netdev_warn(dev, 1877 "%s: Detected possible byte-swapped interface at IOADDR %p\n", 1878 CARDNAME, ioaddr); 1879 } 1880 retval = -ENODEV; 1881 goto err_out; 1882 } 1883 1884 /* 1885 * The above MIGHT indicate a device, but I need to write to 1886 * further test this. 1887 */ 1888 SMC_SELECT_BANK(lp, 0); 1889 val = SMC_CURRENT_BANK(lp); 1890 if ((val & 0xFF00) != 0x3300) { 1891 retval = -ENODEV; 1892 goto err_out; 1893 } 1894 1895 /* 1896 * well, we've already written once, so hopefully another 1897 * time won't hurt. This time, I need to switch the bank 1898 * register to bank 1, so I can access the base address 1899 * register 1900 */ 1901 SMC_SELECT_BANK(lp, 1); 1902 val = SMC_GET_BASE(lp); 1903 val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT; 1904 if (((unsigned long)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) { 1905 netdev_warn(dev, "%s: IOADDR %p doesn't match configuration (%x).\n", 1906 CARDNAME, ioaddr, val); 1907 } 1908 1909 /* 1910 * check if the revision register is something that I 1911 * recognize. These might need to be added to later, 1912 * as future revisions could be added. 1913 */ 1914 SMC_SELECT_BANK(lp, 3); 1915 revision_register = SMC_GET_REV(lp); 1916 DBG(2, dev, "%s: revision = 0x%04x\n", CARDNAME, revision_register); 1917 version_string = chip_ids[ (revision_register >> 4) & 0xF]; 1918 if (!version_string || (revision_register & 0xff00) != 0x3300) { 1919 /* I don't recognize this chip, so... */ 1920 netdev_warn(dev, "%s: IO %p: Unrecognized revision register 0x%04x, Contact author.\n", 1921 CARDNAME, ioaddr, revision_register); 1922 1923 retval = -ENODEV; 1924 goto err_out; 1925 } 1926 1927 /* At this point I'll assume that the chip is an SMC91x. */ 1928 pr_info_once("%s\n", version); 1929 1930 /* fill in some of the fields */ 1931 dev->base_addr = (unsigned long)ioaddr; 1932 lp->base = ioaddr; 1933 lp->version = revision_register & 0xff; 1934 spin_lock_init(&lp->lock); 1935 1936 /* Get the MAC address */ 1937 SMC_SELECT_BANK(lp, 1); 1938 SMC_GET_MAC_ADDR(lp, dev->dev_addr); 1939 1940 /* now, reset the chip, and put it into a known state */ 1941 smc_reset(dev); 1942 1943 /* 1944 * If dev->irq is 0, then the device has to be banged on to see 1945 * what the IRQ is. 1946 * 1947 * This banging doesn't always detect the IRQ, for unknown reasons. 1948 * a workaround is to reset the chip and try again. 1949 * 1950 * Interestingly, the DOS packet driver *SETS* the IRQ on the card to 1951 * be what is requested on the command line. I don't do that, mostly 1952 * because the card that I have uses a non-standard method of accessing 1953 * the IRQs, and because this _should_ work in most configurations. 1954 * 1955 * Specifying an IRQ is done with the assumption that the user knows 1956 * what (s)he is doing. No checking is done!!!! 1957 */ 1958 if (dev->irq < 1) { 1959 int trials; 1960 1961 trials = 3; 1962 while (trials--) { 1963 dev->irq = smc_findirq(lp); 1964 if (dev->irq) 1965 break; 1966 /* kick the card and try again */ 1967 smc_reset(dev); 1968 } 1969 } 1970 if (dev->irq == 0) { 1971 netdev_warn(dev, "Couldn't autodetect your IRQ. Use irq=xx.\n"); 1972 retval = -ENODEV; 1973 goto err_out; 1974 } 1975 dev->irq = irq_canonicalize(dev->irq); 1976 1977 dev->watchdog_timeo = msecs_to_jiffies(watchdog); 1978 dev->netdev_ops = &smc_netdev_ops; 1979 dev->ethtool_ops = &smc_ethtool_ops; 1980 1981 tasklet_init(&lp->tx_task, smc_hardware_send_pkt, (unsigned long)dev); 1982 INIT_WORK(&lp->phy_configure, smc_phy_configure); 1983 lp->dev = dev; 1984 lp->mii.phy_id_mask = 0x1f; 1985 lp->mii.reg_num_mask = 0x1f; 1986 lp->mii.force_media = 0; 1987 lp->mii.full_duplex = 0; 1988 lp->mii.dev = dev; 1989 lp->mii.mdio_read = smc_phy_read; 1990 lp->mii.mdio_write = smc_phy_write; 1991 1992 /* 1993 * Locate the phy, if any. 1994 */ 1995 if (lp->version >= (CHIP_91100 << 4)) 1996 smc_phy_detect(dev); 1997 1998 /* then shut everything down to save power */ 1999 smc_shutdown(dev); 2000 smc_phy_powerdown(dev); 2001 2002 /* Set default parameters */ 2003 lp->msg_enable = NETIF_MSG_LINK; 2004 lp->ctl_rfduplx = 0; 2005 lp->ctl_rspeed = 10; 2006 2007 if (lp->version >= (CHIP_91100 << 4)) { 2008 lp->ctl_rfduplx = 1; 2009 lp->ctl_rspeed = 100; 2010 } 2011 2012 /* Grab the IRQ */ 2013 retval = request_irq(dev->irq, smc_interrupt, irq_flags, dev->name, dev); 2014 if (retval) 2015 goto err_out; 2016 2017 #ifdef CONFIG_ARCH_PXA 2018 # ifdef SMC_USE_PXA_DMA 2019 lp->cfg.flags |= SMC91X_USE_DMA; 2020 # endif 2021 if (lp->cfg.flags & SMC91X_USE_DMA) { 2022 dma_cap_mask_t mask; 2023 2024 dma_cap_zero(mask); 2025 dma_cap_set(DMA_SLAVE, mask); 2026 lp->dma_chan = dma_request_channel(mask, NULL, NULL); 2027 } 2028 #endif 2029 2030 retval = register_netdev(dev); 2031 if (retval == 0) { 2032 /* now, print out the card info, in a short format.. */ 2033 netdev_info(dev, "%s (rev %d) at %p IRQ %d", 2034 version_string, revision_register & 0x0f, 2035 lp->base, dev->irq); 2036 2037 if (lp->dma_chan) 2038 pr_cont(" DMA %p", lp->dma_chan); 2039 2040 pr_cont("%s%s\n", 2041 lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "", 2042 THROTTLE_TX_PKTS ? " [throttle_tx]" : ""); 2043 2044 if (!is_valid_ether_addr(dev->dev_addr)) { 2045 netdev_warn(dev, "Invalid ethernet MAC address. Please set using ifconfig\n"); 2046 } else { 2047 /* Print the Ethernet address */ 2048 netdev_info(dev, "Ethernet addr: %pM\n", 2049 dev->dev_addr); 2050 } 2051 2052 if (lp->phy_type == 0) { 2053 PRINTK(dev, "No PHY found\n"); 2054 } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) { 2055 PRINTK(dev, "PHY LAN83C183 (LAN91C111 Internal)\n"); 2056 } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) { 2057 PRINTK(dev, "PHY LAN83C180\n"); 2058 } 2059 } 2060 2061 err_out: 2062 #ifdef CONFIG_ARCH_PXA 2063 if (retval && lp->dma_chan) 2064 dma_release_channel(lp->dma_chan); 2065 #endif 2066 return retval; 2067 } 2068 2069 static int smc_enable_device(struct platform_device *pdev) 2070 { 2071 struct net_device *ndev = platform_get_drvdata(pdev); 2072 struct smc_local *lp = netdev_priv(ndev); 2073 unsigned long flags; 2074 unsigned char ecor, ecsr; 2075 void __iomem *addr; 2076 struct resource * res; 2077 2078 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2079 if (!res) 2080 return 0; 2081 2082 /* 2083 * Map the attribute space. This is overkill, but clean. 2084 */ 2085 addr = ioremap(res->start, ATTRIB_SIZE); 2086 if (!addr) 2087 return -ENOMEM; 2088 2089 /* 2090 * Reset the device. We must disable IRQs around this 2091 * since a reset causes the IRQ line become active. 2092 */ 2093 local_irq_save(flags); 2094 ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; 2095 writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); 2096 readb(addr + (ECOR << SMC_IO_SHIFT)); 2097 2098 /* 2099 * Wait 100us for the chip to reset. 2100 */ 2101 udelay(100); 2102 2103 /* 2104 * The device will ignore all writes to the enable bit while 2105 * reset is asserted, even if the reset bit is cleared in the 2106 * same write. Must clear reset first, then enable the device. 2107 */ 2108 writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); 2109 writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); 2110 2111 /* 2112 * Set the appropriate byte/word mode. 2113 */ 2114 ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; 2115 if (!SMC_16BIT(lp)) 2116 ecsr |= ECSR_IOIS8; 2117 writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); 2118 local_irq_restore(flags); 2119 2120 iounmap(addr); 2121 2122 /* 2123 * Wait for the chip to wake up. We could poll the control 2124 * register in the main register space, but that isn't mapped 2125 * yet. We know this is going to take 750us. 2126 */ 2127 msleep(1); 2128 2129 return 0; 2130 } 2131 2132 static int smc_request_attrib(struct platform_device *pdev, 2133 struct net_device *ndev) 2134 { 2135 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2136 struct smc_local *lp __maybe_unused = netdev_priv(ndev); 2137 2138 if (!res) 2139 return 0; 2140 2141 if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME)) 2142 return -EBUSY; 2143 2144 return 0; 2145 } 2146 2147 static void smc_release_attrib(struct platform_device *pdev, 2148 struct net_device *ndev) 2149 { 2150 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2151 struct smc_local *lp __maybe_unused = netdev_priv(ndev); 2152 2153 if (res) 2154 release_mem_region(res->start, ATTRIB_SIZE); 2155 } 2156 2157 static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev) 2158 { 2159 if (SMC_CAN_USE_DATACS) { 2160 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); 2161 struct smc_local *lp = netdev_priv(ndev); 2162 2163 if (!res) 2164 return; 2165 2166 if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) { 2167 netdev_info(ndev, "%s: failed to request datacs memory region.\n", 2168 CARDNAME); 2169 return; 2170 } 2171 2172 lp->datacs = ioremap(res->start, SMC_DATA_EXTENT); 2173 } 2174 } 2175 2176 static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev) 2177 { 2178 if (SMC_CAN_USE_DATACS) { 2179 struct smc_local *lp = netdev_priv(ndev); 2180 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); 2181 2182 if (lp->datacs) 2183 iounmap(lp->datacs); 2184 2185 lp->datacs = NULL; 2186 2187 if (res) 2188 release_mem_region(res->start, SMC_DATA_EXTENT); 2189 } 2190 } 2191 2192 static const struct acpi_device_id smc91x_acpi_match[] = { 2193 { "LNRO0003", 0 }, 2194 { } 2195 }; 2196 MODULE_DEVICE_TABLE(acpi, smc91x_acpi_match); 2197 2198 #if IS_BUILTIN(CONFIG_OF) 2199 static const struct of_device_id smc91x_match[] = { 2200 { .compatible = "smsc,lan91c94", }, 2201 { .compatible = "smsc,lan91c111", }, 2202 {}, 2203 }; 2204 MODULE_DEVICE_TABLE(of, smc91x_match); 2205 2206 /** 2207 * of_try_set_control_gpio - configure a gpio if it exists 2208 */ 2209 static int try_toggle_control_gpio(struct device *dev, 2210 struct gpio_desc **desc, 2211 const char *name, int index, 2212 int value, unsigned int nsdelay) 2213 { 2214 struct gpio_desc *gpio = *desc; 2215 enum gpiod_flags flags = value ? GPIOD_OUT_LOW : GPIOD_OUT_HIGH; 2216 2217 gpio = devm_gpiod_get_index_optional(dev, name, index, flags); 2218 if (IS_ERR(gpio)) 2219 return PTR_ERR(gpio); 2220 2221 if (gpio) { 2222 if (nsdelay) 2223 usleep_range(nsdelay, 2 * nsdelay); 2224 gpiod_set_value_cansleep(gpio, value); 2225 } 2226 *desc = gpio; 2227 2228 return 0; 2229 } 2230 #endif 2231 2232 /* 2233 * smc_init(void) 2234 * Input parameters: 2235 * dev->base_addr == 0, try to find all possible locations 2236 * dev->base_addr > 0x1ff, this is the address to check 2237 * dev->base_addr == <anything else>, return failure code 2238 * 2239 * Output: 2240 * 0 --> there is a device 2241 * anything else, error 2242 */ 2243 static int smc_drv_probe(struct platform_device *pdev) 2244 { 2245 struct smc91x_platdata *pd = dev_get_platdata(&pdev->dev); 2246 const struct of_device_id *match = NULL; 2247 struct smc_local *lp; 2248 struct net_device *ndev; 2249 struct resource *res; 2250 unsigned int __iomem *addr; 2251 unsigned long irq_flags = SMC_IRQ_FLAGS; 2252 unsigned long irq_resflags; 2253 int ret; 2254 2255 ndev = alloc_etherdev(sizeof(struct smc_local)); 2256 if (!ndev) { 2257 ret = -ENOMEM; 2258 goto out; 2259 } 2260 SET_NETDEV_DEV(ndev, &pdev->dev); 2261 2262 /* get configuration from platform data, only allow use of 2263 * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set. 2264 */ 2265 2266 lp = netdev_priv(ndev); 2267 lp->cfg.flags = 0; 2268 2269 if (pd) { 2270 memcpy(&lp->cfg, pd, sizeof(lp->cfg)); 2271 lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags); 2272 2273 if (!SMC_8BIT(lp) && !SMC_16BIT(lp)) { 2274 dev_err(&pdev->dev, 2275 "at least one of 8-bit or 16-bit access support is required.\n"); 2276 ret = -ENXIO; 2277 goto out_free_netdev; 2278 } 2279 } 2280 2281 #if IS_BUILTIN(CONFIG_OF) 2282 match = of_match_device(of_match_ptr(smc91x_match), &pdev->dev); 2283 if (match) { 2284 u32 val; 2285 2286 /* Optional pwrdwn GPIO configured? */ 2287 ret = try_toggle_control_gpio(&pdev->dev, &lp->power_gpio, 2288 "power", 0, 0, 100); 2289 if (ret) 2290 return ret; 2291 2292 /* 2293 * Optional reset GPIO configured? Minimum 100 ns reset needed 2294 * according to LAN91C96 datasheet page 14. 2295 */ 2296 ret = try_toggle_control_gpio(&pdev->dev, &lp->reset_gpio, 2297 "reset", 0, 0, 100); 2298 if (ret) 2299 return ret; 2300 2301 /* 2302 * Need to wait for optional EEPROM to load, max 750 us according 2303 * to LAN91C96 datasheet page 55. 2304 */ 2305 if (lp->reset_gpio) 2306 usleep_range(750, 1000); 2307 2308 /* Combination of IO widths supported, default to 16-bit */ 2309 if (!device_property_read_u32(&pdev->dev, "reg-io-width", 2310 &val)) { 2311 if (val & 1) 2312 lp->cfg.flags |= SMC91X_USE_8BIT; 2313 if ((val == 0) || (val & 2)) 2314 lp->cfg.flags |= SMC91X_USE_16BIT; 2315 if (val & 4) 2316 lp->cfg.flags |= SMC91X_USE_32BIT; 2317 } else { 2318 lp->cfg.flags |= SMC91X_USE_16BIT; 2319 } 2320 if (!device_property_read_u32(&pdev->dev, "reg-shift", 2321 &val)) 2322 lp->io_shift = val; 2323 lp->cfg.pxa_u16_align4 = 2324 device_property_read_bool(&pdev->dev, "pxa-u16-align4"); 2325 } 2326 #endif 2327 2328 if (!pd && !match) { 2329 lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0; 2330 lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0; 2331 lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0; 2332 lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0; 2333 } 2334 2335 if (!lp->cfg.leda && !lp->cfg.ledb) { 2336 lp->cfg.leda = RPC_LSA_DEFAULT; 2337 lp->cfg.ledb = RPC_LSB_DEFAULT; 2338 } 2339 2340 ndev->dma = (unsigned char)-1; 2341 2342 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); 2343 if (!res) 2344 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2345 if (!res) { 2346 ret = -ENODEV; 2347 goto out_free_netdev; 2348 } 2349 2350 2351 if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) { 2352 ret = -EBUSY; 2353 goto out_free_netdev; 2354 } 2355 2356 ndev->irq = platform_get_irq(pdev, 0); 2357 if (ndev->irq < 0) { 2358 ret = ndev->irq; 2359 goto out_release_io; 2360 } 2361 /* 2362 * If this platform does not specify any special irqflags, or if 2363 * the resource supplies a trigger, override the irqflags with 2364 * the trigger flags from the resource. 2365 */ 2366 irq_resflags = irqd_get_trigger_type(irq_get_irq_data(ndev->irq)); 2367 if (irq_flags == -1 || irq_resflags & IRQF_TRIGGER_MASK) 2368 irq_flags = irq_resflags & IRQF_TRIGGER_MASK; 2369 2370 ret = smc_request_attrib(pdev, ndev); 2371 if (ret) 2372 goto out_release_io; 2373 #if defined(CONFIG_ASSABET_NEPONSET) 2374 if (machine_is_assabet() && machine_has_neponset()) 2375 neponset_ncr_set(NCR_ENET_OSC_EN); 2376 #endif 2377 platform_set_drvdata(pdev, ndev); 2378 ret = smc_enable_device(pdev); 2379 if (ret) 2380 goto out_release_attrib; 2381 2382 addr = ioremap(res->start, SMC_IO_EXTENT); 2383 if (!addr) { 2384 ret = -ENOMEM; 2385 goto out_release_attrib; 2386 } 2387 2388 #ifdef CONFIG_ARCH_PXA 2389 { 2390 struct smc_local *lp = netdev_priv(ndev); 2391 lp->device = &pdev->dev; 2392 lp->physaddr = res->start; 2393 2394 } 2395 #endif 2396 2397 ret = smc_probe(ndev, addr, irq_flags); 2398 if (ret != 0) 2399 goto out_iounmap; 2400 2401 smc_request_datacs(pdev, ndev); 2402 2403 return 0; 2404 2405 out_iounmap: 2406 iounmap(addr); 2407 out_release_attrib: 2408 smc_release_attrib(pdev, ndev); 2409 out_release_io: 2410 release_mem_region(res->start, SMC_IO_EXTENT); 2411 out_free_netdev: 2412 free_netdev(ndev); 2413 out: 2414 pr_info("%s: not found (%d).\n", CARDNAME, ret); 2415 2416 return ret; 2417 } 2418 2419 static int smc_drv_remove(struct platform_device *pdev) 2420 { 2421 struct net_device *ndev = platform_get_drvdata(pdev); 2422 struct smc_local *lp = netdev_priv(ndev); 2423 struct resource *res; 2424 2425 unregister_netdev(ndev); 2426 2427 free_irq(ndev->irq, ndev); 2428 2429 #ifdef CONFIG_ARCH_PXA 2430 if (lp->dma_chan) 2431 dma_release_channel(lp->dma_chan); 2432 #endif 2433 iounmap(lp->base); 2434 2435 smc_release_datacs(pdev,ndev); 2436 smc_release_attrib(pdev,ndev); 2437 2438 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); 2439 if (!res) 2440 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2441 release_mem_region(res->start, SMC_IO_EXTENT); 2442 2443 free_netdev(ndev); 2444 2445 return 0; 2446 } 2447 2448 static int smc_drv_suspend(struct device *dev) 2449 { 2450 struct net_device *ndev = dev_get_drvdata(dev); 2451 2452 if (ndev) { 2453 if (netif_running(ndev)) { 2454 netif_device_detach(ndev); 2455 smc_shutdown(ndev); 2456 smc_phy_powerdown(ndev); 2457 } 2458 } 2459 return 0; 2460 } 2461 2462 static int smc_drv_resume(struct device *dev) 2463 { 2464 struct platform_device *pdev = to_platform_device(dev); 2465 struct net_device *ndev = platform_get_drvdata(pdev); 2466 2467 if (ndev) { 2468 struct smc_local *lp = netdev_priv(ndev); 2469 smc_enable_device(pdev); 2470 if (netif_running(ndev)) { 2471 smc_reset(ndev); 2472 smc_enable(ndev); 2473 if (lp->phy_type != 0) 2474 smc_phy_configure(&lp->phy_configure); 2475 netif_device_attach(ndev); 2476 } 2477 } 2478 return 0; 2479 } 2480 2481 static const struct dev_pm_ops smc_drv_pm_ops = { 2482 .suspend = smc_drv_suspend, 2483 .resume = smc_drv_resume, 2484 }; 2485 2486 static struct platform_driver smc_driver = { 2487 .probe = smc_drv_probe, 2488 .remove = smc_drv_remove, 2489 .driver = { 2490 .name = CARDNAME, 2491 .pm = &smc_drv_pm_ops, 2492 .of_match_table = of_match_ptr(smc91x_match), 2493 .acpi_match_table = smc91x_acpi_match, 2494 }, 2495 }; 2496 2497 module_platform_driver(smc_driver); 2498