xref: /linux/drivers/net/ethernet/smsc/smc91x.c (revision 0d456bad36d42d16022be045c8a53ddbb59ee478)
1 /*
2  * smc91x.c
3  * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices.
4  *
5  * Copyright (C) 1996 by Erik Stahlman
6  * Copyright (C) 2001 Standard Microsystems Corporation
7  *	Developed by Simple Network Magic Corporation
8  * Copyright (C) 2003 Monta Vista Software, Inc.
9  *	Unified SMC91x driver by Nicolas Pitre
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
24  *
25  * Arguments:
26  * 	io	= for the base address
27  *	irq	= for the IRQ
28  *	nowait	= 0 for normal wait states, 1 eliminates additional wait states
29  *
30  * original author:
31  * 	Erik Stahlman <erik@vt.edu>
32  *
33  * hardware multicast code:
34  *    Peter Cammaert <pc@denkart.be>
35  *
36  * contributors:
37  * 	Daris A Nevil <dnevil@snmc.com>
38  *      Nicolas Pitre <nico@fluxnic.net>
39  *	Russell King <rmk@arm.linux.org.uk>
40  *
41  * History:
42  *   08/20/00  Arnaldo Melo       fix kfree(skb) in smc_hardware_send_packet
43  *   12/15/00  Christian Jullien  fix "Warning: kfree_skb on hard IRQ"
44  *   03/16/01  Daris A Nevil      modified smc9194.c for use with LAN91C111
45  *   08/22/01  Scott Anderson     merge changes from smc9194 to smc91111
46  *   08/21/01  Pramod B Bhardwaj  added support for RevB of LAN91C111
47  *   12/20/01  Jeff Sutherland    initial port to Xscale PXA with DMA support
48  *   04/07/03  Nicolas Pitre      unified SMC91x driver, killed irq races,
49  *                                more bus abstraction, big cleanup, etc.
50  *   29/09/03  Russell King       - add driver model support
51  *                                - ethtool support
52  *                                - convert to use generic MII interface
53  *                                - add link up/down notification
54  *                                - don't try to handle full negotiation in
55  *                                  smc_phy_configure
56  *                                - clean up (and fix stack overrun) in PHY
57  *                                  MII read/write functions
58  *   22/09/04  Nicolas Pitre      big update (see commit log for details)
59  */
60 static const char version[] =
61 	"smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>\n";
62 
63 /* Debugging level */
64 #ifndef SMC_DEBUG
65 #define SMC_DEBUG		0
66 #endif
67 
68 
69 #include <linux/init.h>
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/sched.h>
73 #include <linux/delay.h>
74 #include <linux/interrupt.h>
75 #include <linux/irq.h>
76 #include <linux/errno.h>
77 #include <linux/ioport.h>
78 #include <linux/crc32.h>
79 #include <linux/platform_device.h>
80 #include <linux/spinlock.h>
81 #include <linux/ethtool.h>
82 #include <linux/mii.h>
83 #include <linux/workqueue.h>
84 #include <linux/of.h>
85 
86 #include <linux/netdevice.h>
87 #include <linux/etherdevice.h>
88 #include <linux/skbuff.h>
89 
90 #include <asm/io.h>
91 
92 #include "smc91x.h"
93 
94 #ifndef SMC_NOWAIT
95 # define SMC_NOWAIT		0
96 #endif
97 static int nowait = SMC_NOWAIT;
98 module_param(nowait, int, 0400);
99 MODULE_PARM_DESC(nowait, "set to 1 for no wait state");
100 
101 /*
102  * Transmit timeout, default 5 seconds.
103  */
104 static int watchdog = 1000;
105 module_param(watchdog, int, 0400);
106 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
107 
108 MODULE_LICENSE("GPL");
109 MODULE_ALIAS("platform:smc91x");
110 
111 /*
112  * The internal workings of the driver.  If you are changing anything
113  * here with the SMC stuff, you should have the datasheet and know
114  * what you are doing.
115  */
116 #define CARDNAME "smc91x"
117 
118 /*
119  * Use power-down feature of the chip
120  */
121 #define POWER_DOWN		1
122 
123 /*
124  * Wait time for memory to be free.  This probably shouldn't be
125  * tuned that much, as waiting for this means nothing else happens
126  * in the system
127  */
128 #define MEMORY_WAIT_TIME	16
129 
130 /*
131  * The maximum number of processing loops allowed for each call to the
132  * IRQ handler.
133  */
134 #define MAX_IRQ_LOOPS		8
135 
136 /*
137  * This selects whether TX packets are sent one by one to the SMC91x internal
138  * memory and throttled until transmission completes.  This may prevent
139  * RX overruns a litle by keeping much of the memory free for RX packets
140  * but to the expense of reduced TX throughput and increased IRQ overhead.
141  * Note this is not a cure for a too slow data bus or too high IRQ latency.
142  */
143 #define THROTTLE_TX_PKTS	0
144 
145 /*
146  * The MII clock high/low times.  2x this number gives the MII clock period
147  * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!)
148  */
149 #define MII_DELAY		1
150 
151 #if SMC_DEBUG > 0
152 #define DBG(n, args...)					\
153 	do {						\
154 		if (SMC_DEBUG >= (n))			\
155 			printk(args);	\
156 	} while (0)
157 
158 #define PRINTK(args...)   printk(args)
159 #else
160 #define DBG(n, args...)   do { } while(0)
161 #define PRINTK(args...)   printk(KERN_DEBUG args)
162 #endif
163 
164 #if SMC_DEBUG > 3
165 static void PRINT_PKT(u_char *buf, int length)
166 {
167 	int i;
168 	int remainder;
169 	int lines;
170 
171 	lines = length / 16;
172 	remainder = length % 16;
173 
174 	for (i = 0; i < lines ; i ++) {
175 		int cur;
176 		for (cur = 0; cur < 8; cur++) {
177 			u_char a, b;
178 			a = *buf++;
179 			b = *buf++;
180 			printk("%02x%02x ", a, b);
181 		}
182 		printk("\n");
183 	}
184 	for (i = 0; i < remainder/2 ; i++) {
185 		u_char a, b;
186 		a = *buf++;
187 		b = *buf++;
188 		printk("%02x%02x ", a, b);
189 	}
190 	printk("\n");
191 }
192 #else
193 #define PRINT_PKT(x...)  do { } while(0)
194 #endif
195 
196 
197 /* this enables an interrupt in the interrupt mask register */
198 #define SMC_ENABLE_INT(lp, x) do {					\
199 	unsigned char mask;						\
200 	unsigned long smc_enable_flags;					\
201 	spin_lock_irqsave(&lp->lock, smc_enable_flags);			\
202 	mask = SMC_GET_INT_MASK(lp);					\
203 	mask |= (x);							\
204 	SMC_SET_INT_MASK(lp, mask);					\
205 	spin_unlock_irqrestore(&lp->lock, smc_enable_flags);		\
206 } while (0)
207 
208 /* this disables an interrupt from the interrupt mask register */
209 #define SMC_DISABLE_INT(lp, x) do {					\
210 	unsigned char mask;						\
211 	unsigned long smc_disable_flags;				\
212 	spin_lock_irqsave(&lp->lock, smc_disable_flags);		\
213 	mask = SMC_GET_INT_MASK(lp);					\
214 	mask &= ~(x);							\
215 	SMC_SET_INT_MASK(lp, mask);					\
216 	spin_unlock_irqrestore(&lp->lock, smc_disable_flags);		\
217 } while (0)
218 
219 /*
220  * Wait while MMU is busy.  This is usually in the order of a few nanosecs
221  * if at all, but let's avoid deadlocking the system if the hardware
222  * decides to go south.
223  */
224 #define SMC_WAIT_MMU_BUSY(lp) do {					\
225 	if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) {		\
226 		unsigned long timeout = jiffies + 2;			\
227 		while (SMC_GET_MMU_CMD(lp) & MC_BUSY) {		\
228 			if (time_after(jiffies, timeout)) {		\
229 				printk("%s: timeout %s line %d\n",	\
230 					dev->name, __FILE__, __LINE__);	\
231 				break;					\
232 			}						\
233 			cpu_relax();					\
234 		}							\
235 	}								\
236 } while (0)
237 
238 
239 /*
240  * this does a soft reset on the device
241  */
242 static void smc_reset(struct net_device *dev)
243 {
244 	struct smc_local *lp = netdev_priv(dev);
245 	void __iomem *ioaddr = lp->base;
246 	unsigned int ctl, cfg;
247 	struct sk_buff *pending_skb;
248 
249 	DBG(2, "%s: %s\n", dev->name, __func__);
250 
251 	/* Disable all interrupts, block TX tasklet */
252 	spin_lock_irq(&lp->lock);
253 	SMC_SELECT_BANK(lp, 2);
254 	SMC_SET_INT_MASK(lp, 0);
255 	pending_skb = lp->pending_tx_skb;
256 	lp->pending_tx_skb = NULL;
257 	spin_unlock_irq(&lp->lock);
258 
259 	/* free any pending tx skb */
260 	if (pending_skb) {
261 		dev_kfree_skb(pending_skb);
262 		dev->stats.tx_errors++;
263 		dev->stats.tx_aborted_errors++;
264 	}
265 
266 	/*
267 	 * This resets the registers mostly to defaults, but doesn't
268 	 * affect EEPROM.  That seems unnecessary
269 	 */
270 	SMC_SELECT_BANK(lp, 0);
271 	SMC_SET_RCR(lp, RCR_SOFTRST);
272 
273 	/*
274 	 * Setup the Configuration Register
275 	 * This is necessary because the CONFIG_REG is not affected
276 	 * by a soft reset
277 	 */
278 	SMC_SELECT_BANK(lp, 1);
279 
280 	cfg = CONFIG_DEFAULT;
281 
282 	/*
283 	 * Setup for fast accesses if requested.  If the card/system
284 	 * can't handle it then there will be no recovery except for
285 	 * a hard reset or power cycle
286 	 */
287 	if (lp->cfg.flags & SMC91X_NOWAIT)
288 		cfg |= CONFIG_NO_WAIT;
289 
290 	/*
291 	 * Release from possible power-down state
292 	 * Configuration register is not affected by Soft Reset
293 	 */
294 	cfg |= CONFIG_EPH_POWER_EN;
295 
296 	SMC_SET_CONFIG(lp, cfg);
297 
298 	/* this should pause enough for the chip to be happy */
299 	/*
300 	 * elaborate?  What does the chip _need_? --jgarzik
301 	 *
302 	 * This seems to be undocumented, but something the original
303 	 * driver(s) have always done.  Suspect undocumented timing
304 	 * info/determined empirically. --rmk
305 	 */
306 	udelay(1);
307 
308 	/* Disable transmit and receive functionality */
309 	SMC_SELECT_BANK(lp, 0);
310 	SMC_SET_RCR(lp, RCR_CLEAR);
311 	SMC_SET_TCR(lp, TCR_CLEAR);
312 
313 	SMC_SELECT_BANK(lp, 1);
314 	ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE;
315 
316 	/*
317 	 * Set the control register to automatically release successfully
318 	 * transmitted packets, to make the best use out of our limited
319 	 * memory
320 	 */
321 	if(!THROTTLE_TX_PKTS)
322 		ctl |= CTL_AUTO_RELEASE;
323 	else
324 		ctl &= ~CTL_AUTO_RELEASE;
325 	SMC_SET_CTL(lp, ctl);
326 
327 	/* Reset the MMU */
328 	SMC_SELECT_BANK(lp, 2);
329 	SMC_SET_MMU_CMD(lp, MC_RESET);
330 	SMC_WAIT_MMU_BUSY(lp);
331 }
332 
333 /*
334  * Enable Interrupts, Receive, and Transmit
335  */
336 static void smc_enable(struct net_device *dev)
337 {
338 	struct smc_local *lp = netdev_priv(dev);
339 	void __iomem *ioaddr = lp->base;
340 	int mask;
341 
342 	DBG(2, "%s: %s\n", dev->name, __func__);
343 
344 	/* see the header file for options in TCR/RCR DEFAULT */
345 	SMC_SELECT_BANK(lp, 0);
346 	SMC_SET_TCR(lp, lp->tcr_cur_mode);
347 	SMC_SET_RCR(lp, lp->rcr_cur_mode);
348 
349 	SMC_SELECT_BANK(lp, 1);
350 	SMC_SET_MAC_ADDR(lp, dev->dev_addr);
351 
352 	/* now, enable interrupts */
353 	mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT;
354 	if (lp->version >= (CHIP_91100 << 4))
355 		mask |= IM_MDINT;
356 	SMC_SELECT_BANK(lp, 2);
357 	SMC_SET_INT_MASK(lp, mask);
358 
359 	/*
360 	 * From this point the register bank must _NOT_ be switched away
361 	 * to something else than bank 2 without proper locking against
362 	 * races with any tasklet or interrupt handlers until smc_shutdown()
363 	 * or smc_reset() is called.
364 	 */
365 }
366 
367 /*
368  * this puts the device in an inactive state
369  */
370 static void smc_shutdown(struct net_device *dev)
371 {
372 	struct smc_local *lp = netdev_priv(dev);
373 	void __iomem *ioaddr = lp->base;
374 	struct sk_buff *pending_skb;
375 
376 	DBG(2, "%s: %s\n", CARDNAME, __func__);
377 
378 	/* no more interrupts for me */
379 	spin_lock_irq(&lp->lock);
380 	SMC_SELECT_BANK(lp, 2);
381 	SMC_SET_INT_MASK(lp, 0);
382 	pending_skb = lp->pending_tx_skb;
383 	lp->pending_tx_skb = NULL;
384 	spin_unlock_irq(&lp->lock);
385 	if (pending_skb)
386 		dev_kfree_skb(pending_skb);
387 
388 	/* and tell the card to stay away from that nasty outside world */
389 	SMC_SELECT_BANK(lp, 0);
390 	SMC_SET_RCR(lp, RCR_CLEAR);
391 	SMC_SET_TCR(lp, TCR_CLEAR);
392 
393 #ifdef POWER_DOWN
394 	/* finally, shut the chip down */
395 	SMC_SELECT_BANK(lp, 1);
396 	SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN);
397 #endif
398 }
399 
400 /*
401  * This is the procedure to handle the receipt of a packet.
402  */
403 static inline void  smc_rcv(struct net_device *dev)
404 {
405 	struct smc_local *lp = netdev_priv(dev);
406 	void __iomem *ioaddr = lp->base;
407 	unsigned int packet_number, status, packet_len;
408 
409 	DBG(3, "%s: %s\n", dev->name, __func__);
410 
411 	packet_number = SMC_GET_RXFIFO(lp);
412 	if (unlikely(packet_number & RXFIFO_REMPTY)) {
413 		PRINTK("%s: smc_rcv with nothing on FIFO.\n", dev->name);
414 		return;
415 	}
416 
417 	/* read from start of packet */
418 	SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC);
419 
420 	/* First two words are status and packet length */
421 	SMC_GET_PKT_HDR(lp, status, packet_len);
422 	packet_len &= 0x07ff;  /* mask off top bits */
423 	DBG(2, "%s: RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n",
424 		dev->name, packet_number, status,
425 		packet_len, packet_len);
426 
427 	back:
428 	if (unlikely(packet_len < 6 || status & RS_ERRORS)) {
429 		if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) {
430 			/* accept VLAN packets */
431 			status &= ~RS_TOOLONG;
432 			goto back;
433 		}
434 		if (packet_len < 6) {
435 			/* bloody hardware */
436 			printk(KERN_ERR "%s: fubar (rxlen %u status %x\n",
437 					dev->name, packet_len, status);
438 			status |= RS_TOOSHORT;
439 		}
440 		SMC_WAIT_MMU_BUSY(lp);
441 		SMC_SET_MMU_CMD(lp, MC_RELEASE);
442 		dev->stats.rx_errors++;
443 		if (status & RS_ALGNERR)
444 			dev->stats.rx_frame_errors++;
445 		if (status & (RS_TOOSHORT | RS_TOOLONG))
446 			dev->stats.rx_length_errors++;
447 		if (status & RS_BADCRC)
448 			dev->stats.rx_crc_errors++;
449 	} else {
450 		struct sk_buff *skb;
451 		unsigned char *data;
452 		unsigned int data_len;
453 
454 		/* set multicast stats */
455 		if (status & RS_MULTICAST)
456 			dev->stats.multicast++;
457 
458 		/*
459 		 * Actual payload is packet_len - 6 (or 5 if odd byte).
460 		 * We want skb_reserve(2) and the final ctrl word
461 		 * (2 bytes, possibly containing the payload odd byte).
462 		 * Furthermore, we add 2 bytes to allow rounding up to
463 		 * multiple of 4 bytes on 32 bit buses.
464 		 * Hence packet_len - 6 + 2 + 2 + 2.
465 		 */
466 		skb = netdev_alloc_skb(dev, packet_len);
467 		if (unlikely(skb == NULL)) {
468 			printk(KERN_NOTICE "%s: Low memory, packet dropped.\n",
469 				dev->name);
470 			SMC_WAIT_MMU_BUSY(lp);
471 			SMC_SET_MMU_CMD(lp, MC_RELEASE);
472 			dev->stats.rx_dropped++;
473 			return;
474 		}
475 
476 		/* Align IP header to 32 bits */
477 		skb_reserve(skb, 2);
478 
479 		/* BUG: the LAN91C111 rev A never sets this bit. Force it. */
480 		if (lp->version == 0x90)
481 			status |= RS_ODDFRAME;
482 
483 		/*
484 		 * If odd length: packet_len - 5,
485 		 * otherwise packet_len - 6.
486 		 * With the trailing ctrl byte it's packet_len - 4.
487 		 */
488 		data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6);
489 		data = skb_put(skb, data_len);
490 		SMC_PULL_DATA(lp, data, packet_len - 4);
491 
492 		SMC_WAIT_MMU_BUSY(lp);
493 		SMC_SET_MMU_CMD(lp, MC_RELEASE);
494 
495 		PRINT_PKT(data, packet_len - 4);
496 
497 		skb->protocol = eth_type_trans(skb, dev);
498 		netif_rx(skb);
499 		dev->stats.rx_packets++;
500 		dev->stats.rx_bytes += data_len;
501 	}
502 }
503 
504 #ifdef CONFIG_SMP
505 /*
506  * On SMP we have the following problem:
507  *
508  * 	A = smc_hardware_send_pkt()
509  * 	B = smc_hard_start_xmit()
510  * 	C = smc_interrupt()
511  *
512  * A and B can never be executed simultaneously.  However, at least on UP,
513  * it is possible (and even desirable) for C to interrupt execution of
514  * A or B in order to have better RX reliability and avoid overruns.
515  * C, just like A and B, must have exclusive access to the chip and
516  * each of them must lock against any other concurrent access.
517  * Unfortunately this is not possible to have C suspend execution of A or
518  * B taking place on another CPU. On UP this is no an issue since A and B
519  * are run from softirq context and C from hard IRQ context, and there is
520  * no other CPU where concurrent access can happen.
521  * If ever there is a way to force at least B and C to always be executed
522  * on the same CPU then we could use read/write locks to protect against
523  * any other concurrent access and C would always interrupt B. But life
524  * isn't that easy in a SMP world...
525  */
526 #define smc_special_trylock(lock, flags)				\
527 ({									\
528 	int __ret;							\
529 	local_irq_save(flags);						\
530 	__ret = spin_trylock(lock);					\
531 	if (!__ret)							\
532 		local_irq_restore(flags);				\
533 	__ret;								\
534 })
535 #define smc_special_lock(lock, flags)		spin_lock_irqsave(lock, flags)
536 #define smc_special_unlock(lock, flags) 	spin_unlock_irqrestore(lock, flags)
537 #else
538 #define smc_special_trylock(lock, flags)	(flags == flags)
539 #define smc_special_lock(lock, flags)   	do { flags = 0; } while (0)
540 #define smc_special_unlock(lock, flags)	do { flags = 0; } while (0)
541 #endif
542 
543 /*
544  * This is called to actually send a packet to the chip.
545  */
546 static void smc_hardware_send_pkt(unsigned long data)
547 {
548 	struct net_device *dev = (struct net_device *)data;
549 	struct smc_local *lp = netdev_priv(dev);
550 	void __iomem *ioaddr = lp->base;
551 	struct sk_buff *skb;
552 	unsigned int packet_no, len;
553 	unsigned char *buf;
554 	unsigned long flags;
555 
556 	DBG(3, "%s: %s\n", dev->name, __func__);
557 
558 	if (!smc_special_trylock(&lp->lock, flags)) {
559 		netif_stop_queue(dev);
560 		tasklet_schedule(&lp->tx_task);
561 		return;
562 	}
563 
564 	skb = lp->pending_tx_skb;
565 	if (unlikely(!skb)) {
566 		smc_special_unlock(&lp->lock, flags);
567 		return;
568 	}
569 	lp->pending_tx_skb = NULL;
570 
571 	packet_no = SMC_GET_AR(lp);
572 	if (unlikely(packet_no & AR_FAILED)) {
573 		printk("%s: Memory allocation failed.\n", dev->name);
574 		dev->stats.tx_errors++;
575 		dev->stats.tx_fifo_errors++;
576 		smc_special_unlock(&lp->lock, flags);
577 		goto done;
578 	}
579 
580 	/* point to the beginning of the packet */
581 	SMC_SET_PN(lp, packet_no);
582 	SMC_SET_PTR(lp, PTR_AUTOINC);
583 
584 	buf = skb->data;
585 	len = skb->len;
586 	DBG(2, "%s: TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n",
587 		dev->name, packet_no, len, len, buf);
588 	PRINT_PKT(buf, len);
589 
590 	/*
591 	 * Send the packet length (+6 for status words, length, and ctl.
592 	 * The card will pad to 64 bytes with zeroes if packet is too small.
593 	 */
594 	SMC_PUT_PKT_HDR(lp, 0, len + 6);
595 
596 	/* send the actual data */
597 	SMC_PUSH_DATA(lp, buf, len & ~1);
598 
599 	/* Send final ctl word with the last byte if there is one */
600 	SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG(lp));
601 
602 	/*
603 	 * If THROTTLE_TX_PKTS is set, we stop the queue here. This will
604 	 * have the effect of having at most one packet queued for TX
605 	 * in the chip's memory at all time.
606 	 *
607 	 * If THROTTLE_TX_PKTS is not set then the queue is stopped only
608 	 * when memory allocation (MC_ALLOC) does not succeed right away.
609 	 */
610 	if (THROTTLE_TX_PKTS)
611 		netif_stop_queue(dev);
612 
613 	/* queue the packet for TX */
614 	SMC_SET_MMU_CMD(lp, MC_ENQUEUE);
615 	smc_special_unlock(&lp->lock, flags);
616 
617 	dev->trans_start = jiffies;
618 	dev->stats.tx_packets++;
619 	dev->stats.tx_bytes += len;
620 
621 	SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT);
622 
623 done:	if (!THROTTLE_TX_PKTS)
624 		netif_wake_queue(dev);
625 
626 	dev_kfree_skb(skb);
627 }
628 
629 /*
630  * Since I am not sure if I will have enough room in the chip's ram
631  * to store the packet, I call this routine which either sends it
632  * now, or set the card to generates an interrupt when ready
633  * for the packet.
634  */
635 static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
636 {
637 	struct smc_local *lp = netdev_priv(dev);
638 	void __iomem *ioaddr = lp->base;
639 	unsigned int numPages, poll_count, status;
640 	unsigned long flags;
641 
642 	DBG(3, "%s: %s\n", dev->name, __func__);
643 
644 	BUG_ON(lp->pending_tx_skb != NULL);
645 
646 	/*
647 	 * The MMU wants the number of pages to be the number of 256 bytes
648 	 * 'pages', minus 1 (since a packet can't ever have 0 pages :))
649 	 *
650 	 * The 91C111 ignores the size bits, but earlier models don't.
651 	 *
652 	 * Pkt size for allocating is data length +6 (for additional status
653 	 * words, length and ctl)
654 	 *
655 	 * If odd size then last byte is included in ctl word.
656 	 */
657 	numPages = ((skb->len & ~1) + (6 - 1)) >> 8;
658 	if (unlikely(numPages > 7)) {
659 		printk("%s: Far too big packet error.\n", dev->name);
660 		dev->stats.tx_errors++;
661 		dev->stats.tx_dropped++;
662 		dev_kfree_skb(skb);
663 		return NETDEV_TX_OK;
664 	}
665 
666 	smc_special_lock(&lp->lock, flags);
667 
668 	/* now, try to allocate the memory */
669 	SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages);
670 
671 	/*
672 	 * Poll the chip for a short amount of time in case the
673 	 * allocation succeeds quickly.
674 	 */
675 	poll_count = MEMORY_WAIT_TIME;
676 	do {
677 		status = SMC_GET_INT(lp);
678 		if (status & IM_ALLOC_INT) {
679 			SMC_ACK_INT(lp, IM_ALLOC_INT);
680   			break;
681 		}
682    	} while (--poll_count);
683 
684 	smc_special_unlock(&lp->lock, flags);
685 
686 	lp->pending_tx_skb = skb;
687    	if (!poll_count) {
688 		/* oh well, wait until the chip finds memory later */
689 		netif_stop_queue(dev);
690 		DBG(2, "%s: TX memory allocation deferred.\n", dev->name);
691 		SMC_ENABLE_INT(lp, IM_ALLOC_INT);
692    	} else {
693 		/*
694 		 * Allocation succeeded: push packet to the chip's own memory
695 		 * immediately.
696 		 */
697 		smc_hardware_send_pkt((unsigned long)dev);
698 	}
699 
700 	return NETDEV_TX_OK;
701 }
702 
703 /*
704  * This handles a TX interrupt, which is only called when:
705  * - a TX error occurred, or
706  * - CTL_AUTO_RELEASE is not set and TX of a packet completed.
707  */
708 static void smc_tx(struct net_device *dev)
709 {
710 	struct smc_local *lp = netdev_priv(dev);
711 	void __iomem *ioaddr = lp->base;
712 	unsigned int saved_packet, packet_no, tx_status, pkt_len;
713 
714 	DBG(3, "%s: %s\n", dev->name, __func__);
715 
716 	/* If the TX FIFO is empty then nothing to do */
717 	packet_no = SMC_GET_TXFIFO(lp);
718 	if (unlikely(packet_no & TXFIFO_TEMPTY)) {
719 		PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name);
720 		return;
721 	}
722 
723 	/* select packet to read from */
724 	saved_packet = SMC_GET_PN(lp);
725 	SMC_SET_PN(lp, packet_no);
726 
727 	/* read the first word (status word) from this packet */
728 	SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ);
729 	SMC_GET_PKT_HDR(lp, tx_status, pkt_len);
730 	DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n",
731 		dev->name, tx_status, packet_no);
732 
733 	if (!(tx_status & ES_TX_SUC))
734 		dev->stats.tx_errors++;
735 
736 	if (tx_status & ES_LOSTCARR)
737 		dev->stats.tx_carrier_errors++;
738 
739 	if (tx_status & (ES_LATCOL | ES_16COL)) {
740 		PRINTK("%s: %s occurred on last xmit\n", dev->name,
741 		       (tx_status & ES_LATCOL) ?
742 			"late collision" : "too many collisions");
743 		dev->stats.tx_window_errors++;
744 		if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) {
745 			printk(KERN_INFO "%s: unexpectedly large number of "
746 			       "bad collisions. Please check duplex "
747 			       "setting.\n", dev->name);
748 		}
749 	}
750 
751 	/* kill the packet */
752 	SMC_WAIT_MMU_BUSY(lp);
753 	SMC_SET_MMU_CMD(lp, MC_FREEPKT);
754 
755 	/* Don't restore Packet Number Reg until busy bit is cleared */
756 	SMC_WAIT_MMU_BUSY(lp);
757 	SMC_SET_PN(lp, saved_packet);
758 
759 	/* re-enable transmit */
760 	SMC_SELECT_BANK(lp, 0);
761 	SMC_SET_TCR(lp, lp->tcr_cur_mode);
762 	SMC_SELECT_BANK(lp, 2);
763 }
764 
765 
766 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
767 
768 static void smc_mii_out(struct net_device *dev, unsigned int val, int bits)
769 {
770 	struct smc_local *lp = netdev_priv(dev);
771 	void __iomem *ioaddr = lp->base;
772 	unsigned int mii_reg, mask;
773 
774 	mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
775 	mii_reg |= MII_MDOE;
776 
777 	for (mask = 1 << (bits - 1); mask; mask >>= 1) {
778 		if (val & mask)
779 			mii_reg |= MII_MDO;
780 		else
781 			mii_reg &= ~MII_MDO;
782 
783 		SMC_SET_MII(lp, mii_reg);
784 		udelay(MII_DELAY);
785 		SMC_SET_MII(lp, mii_reg | MII_MCLK);
786 		udelay(MII_DELAY);
787 	}
788 }
789 
790 static unsigned int smc_mii_in(struct net_device *dev, int bits)
791 {
792 	struct smc_local *lp = netdev_priv(dev);
793 	void __iomem *ioaddr = lp->base;
794 	unsigned int mii_reg, mask, val;
795 
796 	mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
797 	SMC_SET_MII(lp, mii_reg);
798 
799 	for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) {
800 		if (SMC_GET_MII(lp) & MII_MDI)
801 			val |= mask;
802 
803 		SMC_SET_MII(lp, mii_reg);
804 		udelay(MII_DELAY);
805 		SMC_SET_MII(lp, mii_reg | MII_MCLK);
806 		udelay(MII_DELAY);
807 	}
808 
809 	return val;
810 }
811 
812 /*
813  * Reads a register from the MII Management serial interface
814  */
815 static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg)
816 {
817 	struct smc_local *lp = netdev_priv(dev);
818 	void __iomem *ioaddr = lp->base;
819 	unsigned int phydata;
820 
821 	SMC_SELECT_BANK(lp, 3);
822 
823 	/* Idle - 32 ones */
824 	smc_mii_out(dev, 0xffffffff, 32);
825 
826 	/* Start code (01) + read (10) + phyaddr + phyreg */
827 	smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14);
828 
829 	/* Turnaround (2bits) + phydata */
830 	phydata = smc_mii_in(dev, 18);
831 
832 	/* Return to idle state */
833 	SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
834 
835 	DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
836 		__func__, phyaddr, phyreg, phydata);
837 
838 	SMC_SELECT_BANK(lp, 2);
839 	return phydata;
840 }
841 
842 /*
843  * Writes a register to the MII Management serial interface
844  */
845 static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg,
846 			  int phydata)
847 {
848 	struct smc_local *lp = netdev_priv(dev);
849 	void __iomem *ioaddr = lp->base;
850 
851 	SMC_SELECT_BANK(lp, 3);
852 
853 	/* Idle - 32 ones */
854 	smc_mii_out(dev, 0xffffffff, 32);
855 
856 	/* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */
857 	smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32);
858 
859 	/* Return to idle state */
860 	SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
861 
862 	DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
863 		__func__, phyaddr, phyreg, phydata);
864 
865 	SMC_SELECT_BANK(lp, 2);
866 }
867 
868 /*
869  * Finds and reports the PHY address
870  */
871 static void smc_phy_detect(struct net_device *dev)
872 {
873 	struct smc_local *lp = netdev_priv(dev);
874 	int phyaddr;
875 
876 	DBG(2, "%s: %s\n", dev->name, __func__);
877 
878 	lp->phy_type = 0;
879 
880 	/*
881 	 * Scan all 32 PHY addresses if necessary, starting at
882 	 * PHY#1 to PHY#31, and then PHY#0 last.
883 	 */
884 	for (phyaddr = 1; phyaddr < 33; ++phyaddr) {
885 		unsigned int id1, id2;
886 
887 		/* Read the PHY identifiers */
888 		id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1);
889 		id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2);
890 
891 		DBG(3, "%s: phy_id1=0x%x, phy_id2=0x%x\n",
892 			dev->name, id1, id2);
893 
894 		/* Make sure it is a valid identifier */
895 		if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 &&
896 		    id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) {
897 			/* Save the PHY's address */
898 			lp->mii.phy_id = phyaddr & 31;
899 			lp->phy_type = id1 << 16 | id2;
900 			break;
901 		}
902 	}
903 }
904 
905 /*
906  * Sets the PHY to a configuration as determined by the user
907  */
908 static int smc_phy_fixed(struct net_device *dev)
909 {
910 	struct smc_local *lp = netdev_priv(dev);
911 	void __iomem *ioaddr = lp->base;
912 	int phyaddr = lp->mii.phy_id;
913 	int bmcr, cfg1;
914 
915 	DBG(3, "%s: %s\n", dev->name, __func__);
916 
917 	/* Enter Link Disable state */
918 	cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG);
919 	cfg1 |= PHY_CFG1_LNKDIS;
920 	smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1);
921 
922 	/*
923 	 * Set our fixed capabilities
924 	 * Disable auto-negotiation
925 	 */
926 	bmcr = 0;
927 
928 	if (lp->ctl_rfduplx)
929 		bmcr |= BMCR_FULLDPLX;
930 
931 	if (lp->ctl_rspeed == 100)
932 		bmcr |= BMCR_SPEED100;
933 
934 	/* Write our capabilities to the phy control register */
935 	smc_phy_write(dev, phyaddr, MII_BMCR, bmcr);
936 
937 	/* Re-Configure the Receive/Phy Control register */
938 	SMC_SELECT_BANK(lp, 0);
939 	SMC_SET_RPC(lp, lp->rpc_cur_mode);
940 	SMC_SELECT_BANK(lp, 2);
941 
942 	return 1;
943 }
944 
945 /**
946  * smc_phy_reset - reset the phy
947  * @dev: net device
948  * @phy: phy address
949  *
950  * Issue a software reset for the specified PHY and
951  * wait up to 100ms for the reset to complete.  We should
952  * not access the PHY for 50ms after issuing the reset.
953  *
954  * The time to wait appears to be dependent on the PHY.
955  *
956  * Must be called with lp->lock locked.
957  */
958 static int smc_phy_reset(struct net_device *dev, int phy)
959 {
960 	struct smc_local *lp = netdev_priv(dev);
961 	unsigned int bmcr;
962 	int timeout;
963 
964 	smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET);
965 
966 	for (timeout = 2; timeout; timeout--) {
967 		spin_unlock_irq(&lp->lock);
968 		msleep(50);
969 		spin_lock_irq(&lp->lock);
970 
971 		bmcr = smc_phy_read(dev, phy, MII_BMCR);
972 		if (!(bmcr & BMCR_RESET))
973 			break;
974 	}
975 
976 	return bmcr & BMCR_RESET;
977 }
978 
979 /**
980  * smc_phy_powerdown - powerdown phy
981  * @dev: net device
982  *
983  * Power down the specified PHY
984  */
985 static void smc_phy_powerdown(struct net_device *dev)
986 {
987 	struct smc_local *lp = netdev_priv(dev);
988 	unsigned int bmcr;
989 	int phy = lp->mii.phy_id;
990 
991 	if (lp->phy_type == 0)
992 		return;
993 
994 	/* We need to ensure that no calls to smc_phy_configure are
995 	   pending.
996 	*/
997 	cancel_work_sync(&lp->phy_configure);
998 
999 	bmcr = smc_phy_read(dev, phy, MII_BMCR);
1000 	smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN);
1001 }
1002 
1003 /**
1004  * smc_phy_check_media - check the media status and adjust TCR
1005  * @dev: net device
1006  * @init: set true for initialisation
1007  *
1008  * Select duplex mode depending on negotiation state.  This
1009  * also updates our carrier state.
1010  */
1011 static void smc_phy_check_media(struct net_device *dev, int init)
1012 {
1013 	struct smc_local *lp = netdev_priv(dev);
1014 	void __iomem *ioaddr = lp->base;
1015 
1016 	if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
1017 		/* duplex state has changed */
1018 		if (lp->mii.full_duplex) {
1019 			lp->tcr_cur_mode |= TCR_SWFDUP;
1020 		} else {
1021 			lp->tcr_cur_mode &= ~TCR_SWFDUP;
1022 		}
1023 
1024 		SMC_SELECT_BANK(lp, 0);
1025 		SMC_SET_TCR(lp, lp->tcr_cur_mode);
1026 	}
1027 }
1028 
1029 /*
1030  * Configures the specified PHY through the MII management interface
1031  * using Autonegotiation.
1032  * Calls smc_phy_fixed() if the user has requested a certain config.
1033  * If RPC ANEG bit is set, the media selection is dependent purely on
1034  * the selection by the MII (either in the MII BMCR reg or the result
1035  * of autonegotiation.)  If the RPC ANEG bit is cleared, the selection
1036  * is controlled by the RPC SPEED and RPC DPLX bits.
1037  */
1038 static void smc_phy_configure(struct work_struct *work)
1039 {
1040 	struct smc_local *lp =
1041 		container_of(work, struct smc_local, phy_configure);
1042 	struct net_device *dev = lp->dev;
1043 	void __iomem *ioaddr = lp->base;
1044 	int phyaddr = lp->mii.phy_id;
1045 	int my_phy_caps; /* My PHY capabilities */
1046 	int my_ad_caps; /* My Advertised capabilities */
1047 	int status;
1048 
1049 	DBG(3, "%s:smc_program_phy()\n", dev->name);
1050 
1051 	spin_lock_irq(&lp->lock);
1052 
1053 	/*
1054 	 * We should not be called if phy_type is zero.
1055 	 */
1056 	if (lp->phy_type == 0)
1057 		goto smc_phy_configure_exit;
1058 
1059 	if (smc_phy_reset(dev, phyaddr)) {
1060 		printk("%s: PHY reset timed out\n", dev->name);
1061 		goto smc_phy_configure_exit;
1062 	}
1063 
1064 	/*
1065 	 * Enable PHY Interrupts (for register 18)
1066 	 * Interrupts listed here are disabled
1067 	 */
1068 	smc_phy_write(dev, phyaddr, PHY_MASK_REG,
1069 		PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
1070 		PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
1071 		PHY_INT_SPDDET | PHY_INT_DPLXDET);
1072 
1073 	/* Configure the Receive/Phy Control register */
1074 	SMC_SELECT_BANK(lp, 0);
1075 	SMC_SET_RPC(lp, lp->rpc_cur_mode);
1076 
1077 	/* If the user requested no auto neg, then go set his request */
1078 	if (lp->mii.force_media) {
1079 		smc_phy_fixed(dev);
1080 		goto smc_phy_configure_exit;
1081 	}
1082 
1083 	/* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
1084 	my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR);
1085 
1086 	if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
1087 		printk(KERN_INFO "Auto negotiation NOT supported\n");
1088 		smc_phy_fixed(dev);
1089 		goto smc_phy_configure_exit;
1090 	}
1091 
1092 	my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */
1093 
1094 	if (my_phy_caps & BMSR_100BASE4)
1095 		my_ad_caps |= ADVERTISE_100BASE4;
1096 	if (my_phy_caps & BMSR_100FULL)
1097 		my_ad_caps |= ADVERTISE_100FULL;
1098 	if (my_phy_caps & BMSR_100HALF)
1099 		my_ad_caps |= ADVERTISE_100HALF;
1100 	if (my_phy_caps & BMSR_10FULL)
1101 		my_ad_caps |= ADVERTISE_10FULL;
1102 	if (my_phy_caps & BMSR_10HALF)
1103 		my_ad_caps |= ADVERTISE_10HALF;
1104 
1105 	/* Disable capabilities not selected by our user */
1106 	if (lp->ctl_rspeed != 100)
1107 		my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
1108 
1109 	if (!lp->ctl_rfduplx)
1110 		my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
1111 
1112 	/* Update our Auto-Neg Advertisement Register */
1113 	smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps);
1114 	lp->mii.advertising = my_ad_caps;
1115 
1116 	/*
1117 	 * Read the register back.  Without this, it appears that when
1118 	 * auto-negotiation is restarted, sometimes it isn't ready and
1119 	 * the link does not come up.
1120 	 */
1121 	status = smc_phy_read(dev, phyaddr, MII_ADVERTISE);
1122 
1123 	DBG(2, "%s: phy caps=%x\n", dev->name, my_phy_caps);
1124 	DBG(2, "%s: phy advertised caps=%x\n", dev->name, my_ad_caps);
1125 
1126 	/* Restart auto-negotiation process in order to advertise my caps */
1127 	smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1128 
1129 	smc_phy_check_media(dev, 1);
1130 
1131 smc_phy_configure_exit:
1132 	SMC_SELECT_BANK(lp, 2);
1133 	spin_unlock_irq(&lp->lock);
1134 }
1135 
1136 /*
1137  * smc_phy_interrupt
1138  *
1139  * Purpose:  Handle interrupts relating to PHY register 18. This is
1140  *  called from the "hard" interrupt handler under our private spinlock.
1141  */
1142 static void smc_phy_interrupt(struct net_device *dev)
1143 {
1144 	struct smc_local *lp = netdev_priv(dev);
1145 	int phyaddr = lp->mii.phy_id;
1146 	int phy18;
1147 
1148 	DBG(2, "%s: %s\n", dev->name, __func__);
1149 
1150 	if (lp->phy_type == 0)
1151 		return;
1152 
1153 	for(;;) {
1154 		smc_phy_check_media(dev, 0);
1155 
1156 		/* Read PHY Register 18, Status Output */
1157 		phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG);
1158 		if ((phy18 & PHY_INT_INT) == 0)
1159 			break;
1160 	}
1161 }
1162 
1163 /*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
1164 
1165 static void smc_10bt_check_media(struct net_device *dev, int init)
1166 {
1167 	struct smc_local *lp = netdev_priv(dev);
1168 	void __iomem *ioaddr = lp->base;
1169 	unsigned int old_carrier, new_carrier;
1170 
1171 	old_carrier = netif_carrier_ok(dev) ? 1 : 0;
1172 
1173 	SMC_SELECT_BANK(lp, 0);
1174 	new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0;
1175 	SMC_SELECT_BANK(lp, 2);
1176 
1177 	if (init || (old_carrier != new_carrier)) {
1178 		if (!new_carrier) {
1179 			netif_carrier_off(dev);
1180 		} else {
1181 			netif_carrier_on(dev);
1182 		}
1183 		if (netif_msg_link(lp))
1184 			printk(KERN_INFO "%s: link %s\n", dev->name,
1185 			       new_carrier ? "up" : "down");
1186 	}
1187 }
1188 
1189 static void smc_eph_interrupt(struct net_device *dev)
1190 {
1191 	struct smc_local *lp = netdev_priv(dev);
1192 	void __iomem *ioaddr = lp->base;
1193 	unsigned int ctl;
1194 
1195 	smc_10bt_check_media(dev, 0);
1196 
1197 	SMC_SELECT_BANK(lp, 1);
1198 	ctl = SMC_GET_CTL(lp);
1199 	SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE);
1200 	SMC_SET_CTL(lp, ctl);
1201 	SMC_SELECT_BANK(lp, 2);
1202 }
1203 
1204 /*
1205  * This is the main routine of the driver, to handle the device when
1206  * it needs some attention.
1207  */
1208 static irqreturn_t smc_interrupt(int irq, void *dev_id)
1209 {
1210 	struct net_device *dev = dev_id;
1211 	struct smc_local *lp = netdev_priv(dev);
1212 	void __iomem *ioaddr = lp->base;
1213 	int status, mask, timeout, card_stats;
1214 	int saved_pointer;
1215 
1216 	DBG(3, "%s: %s\n", dev->name, __func__);
1217 
1218 	spin_lock(&lp->lock);
1219 
1220 	/* A preamble may be used when there is a potential race
1221 	 * between the interruptible transmit functions and this
1222 	 * ISR. */
1223 	SMC_INTERRUPT_PREAMBLE;
1224 
1225 	saved_pointer = SMC_GET_PTR(lp);
1226 	mask = SMC_GET_INT_MASK(lp);
1227 	SMC_SET_INT_MASK(lp, 0);
1228 
1229 	/* set a timeout value, so I don't stay here forever */
1230 	timeout = MAX_IRQ_LOOPS;
1231 
1232 	do {
1233 		status = SMC_GET_INT(lp);
1234 
1235 		DBG(2, "%s: INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n",
1236 			dev->name, status, mask,
1237 			({ int meminfo; SMC_SELECT_BANK(lp, 0);
1238 			   meminfo = SMC_GET_MIR(lp);
1239 			   SMC_SELECT_BANK(lp, 2); meminfo; }),
1240 			SMC_GET_FIFO(lp));
1241 
1242 		status &= mask;
1243 		if (!status)
1244 			break;
1245 
1246 		if (status & IM_TX_INT) {
1247 			/* do this before RX as it will free memory quickly */
1248 			DBG(3, "%s: TX int\n", dev->name);
1249 			smc_tx(dev);
1250 			SMC_ACK_INT(lp, IM_TX_INT);
1251 			if (THROTTLE_TX_PKTS)
1252 				netif_wake_queue(dev);
1253 		} else if (status & IM_RCV_INT) {
1254 			DBG(3, "%s: RX irq\n", dev->name);
1255 			smc_rcv(dev);
1256 		} else if (status & IM_ALLOC_INT) {
1257 			DBG(3, "%s: Allocation irq\n", dev->name);
1258 			tasklet_hi_schedule(&lp->tx_task);
1259 			mask &= ~IM_ALLOC_INT;
1260 		} else if (status & IM_TX_EMPTY_INT) {
1261 			DBG(3, "%s: TX empty\n", dev->name);
1262 			mask &= ~IM_TX_EMPTY_INT;
1263 
1264 			/* update stats */
1265 			SMC_SELECT_BANK(lp, 0);
1266 			card_stats = SMC_GET_COUNTER(lp);
1267 			SMC_SELECT_BANK(lp, 2);
1268 
1269 			/* single collisions */
1270 			dev->stats.collisions += card_stats & 0xF;
1271 			card_stats >>= 4;
1272 
1273 			/* multiple collisions */
1274 			dev->stats.collisions += card_stats & 0xF;
1275 		} else if (status & IM_RX_OVRN_INT) {
1276 			DBG(1, "%s: RX overrun (EPH_ST 0x%04x)\n", dev->name,
1277 			       ({ int eph_st; SMC_SELECT_BANK(lp, 0);
1278 				  eph_st = SMC_GET_EPH_STATUS(lp);
1279 				  SMC_SELECT_BANK(lp, 2); eph_st; }));
1280 			SMC_ACK_INT(lp, IM_RX_OVRN_INT);
1281 			dev->stats.rx_errors++;
1282 			dev->stats.rx_fifo_errors++;
1283 		} else if (status & IM_EPH_INT) {
1284 			smc_eph_interrupt(dev);
1285 		} else if (status & IM_MDINT) {
1286 			SMC_ACK_INT(lp, IM_MDINT);
1287 			smc_phy_interrupt(dev);
1288 		} else if (status & IM_ERCV_INT) {
1289 			SMC_ACK_INT(lp, IM_ERCV_INT);
1290 			PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT\n", dev->name);
1291 		}
1292 	} while (--timeout);
1293 
1294 	/* restore register states */
1295 	SMC_SET_PTR(lp, saved_pointer);
1296 	SMC_SET_INT_MASK(lp, mask);
1297 	spin_unlock(&lp->lock);
1298 
1299 #ifndef CONFIG_NET_POLL_CONTROLLER
1300 	if (timeout == MAX_IRQ_LOOPS)
1301 		PRINTK("%s: spurious interrupt (mask = 0x%02x)\n",
1302 		       dev->name, mask);
1303 #endif
1304 	DBG(3, "%s: Interrupt done (%d loops)\n",
1305 	       dev->name, MAX_IRQ_LOOPS - timeout);
1306 
1307 	/*
1308 	 * We return IRQ_HANDLED unconditionally here even if there was
1309 	 * nothing to do.  There is a possibility that a packet might
1310 	 * get enqueued into the chip right after TX_EMPTY_INT is raised
1311 	 * but just before the CPU acknowledges the IRQ.
1312 	 * Better take an unneeded IRQ in some occasions than complexifying
1313 	 * the code for all cases.
1314 	 */
1315 	return IRQ_HANDLED;
1316 }
1317 
1318 #ifdef CONFIG_NET_POLL_CONTROLLER
1319 /*
1320  * Polling receive - used by netconsole and other diagnostic tools
1321  * to allow network i/o with interrupts disabled.
1322  */
1323 static void smc_poll_controller(struct net_device *dev)
1324 {
1325 	disable_irq(dev->irq);
1326 	smc_interrupt(dev->irq, dev);
1327 	enable_irq(dev->irq);
1328 }
1329 #endif
1330 
1331 /* Our watchdog timed out. Called by the networking layer */
1332 static void smc_timeout(struct net_device *dev)
1333 {
1334 	struct smc_local *lp = netdev_priv(dev);
1335 	void __iomem *ioaddr = lp->base;
1336 	int status, mask, eph_st, meminfo, fifo;
1337 
1338 	DBG(2, "%s: %s\n", dev->name, __func__);
1339 
1340 	spin_lock_irq(&lp->lock);
1341 	status = SMC_GET_INT(lp);
1342 	mask = SMC_GET_INT_MASK(lp);
1343 	fifo = SMC_GET_FIFO(lp);
1344 	SMC_SELECT_BANK(lp, 0);
1345 	eph_st = SMC_GET_EPH_STATUS(lp);
1346 	meminfo = SMC_GET_MIR(lp);
1347 	SMC_SELECT_BANK(lp, 2);
1348 	spin_unlock_irq(&lp->lock);
1349 	PRINTK( "%s: TX timeout (INT 0x%02x INTMASK 0x%02x "
1350 		"MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n",
1351 		dev->name, status, mask, meminfo, fifo, eph_st );
1352 
1353 	smc_reset(dev);
1354 	smc_enable(dev);
1355 
1356 	/*
1357 	 * Reconfiguring the PHY doesn't seem like a bad idea here, but
1358 	 * smc_phy_configure() calls msleep() which calls schedule_timeout()
1359 	 * which calls schedule().  Hence we use a work queue.
1360 	 */
1361 	if (lp->phy_type != 0)
1362 		schedule_work(&lp->phy_configure);
1363 
1364 	/* We can accept TX packets again */
1365 	dev->trans_start = jiffies; /* prevent tx timeout */
1366 	netif_wake_queue(dev);
1367 }
1368 
1369 /*
1370  * This routine will, depending on the values passed to it,
1371  * either make it accept multicast packets, go into
1372  * promiscuous mode (for TCPDUMP and cousins) or accept
1373  * a select set of multicast packets
1374  */
1375 static void smc_set_multicast_list(struct net_device *dev)
1376 {
1377 	struct smc_local *lp = netdev_priv(dev);
1378 	void __iomem *ioaddr = lp->base;
1379 	unsigned char multicast_table[8];
1380 	int update_multicast = 0;
1381 
1382 	DBG(2, "%s: %s\n", dev->name, __func__);
1383 
1384 	if (dev->flags & IFF_PROMISC) {
1385 		DBG(2, "%s: RCR_PRMS\n", dev->name);
1386 		lp->rcr_cur_mode |= RCR_PRMS;
1387 	}
1388 
1389 /* BUG?  I never disable promiscuous mode if multicasting was turned on.
1390    Now, I turn off promiscuous mode, but I don't do anything to multicasting
1391    when promiscuous mode is turned on.
1392 */
1393 
1394 	/*
1395 	 * Here, I am setting this to accept all multicast packets.
1396 	 * I don't need to zero the multicast table, because the flag is
1397 	 * checked before the table is
1398 	 */
1399 	else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) {
1400 		DBG(2, "%s: RCR_ALMUL\n", dev->name);
1401 		lp->rcr_cur_mode |= RCR_ALMUL;
1402 	}
1403 
1404 	/*
1405 	 * This sets the internal hardware table to filter out unwanted
1406 	 * multicast packets before they take up memory.
1407 	 *
1408 	 * The SMC chip uses a hash table where the high 6 bits of the CRC of
1409 	 * address are the offset into the table.  If that bit is 1, then the
1410 	 * multicast packet is accepted.  Otherwise, it's dropped silently.
1411 	 *
1412 	 * To use the 6 bits as an offset into the table, the high 3 bits are
1413 	 * the number of the 8 bit register, while the low 3 bits are the bit
1414 	 * within that register.
1415 	 */
1416 	else if (!netdev_mc_empty(dev)) {
1417 		struct netdev_hw_addr *ha;
1418 
1419 		/* table for flipping the order of 3 bits */
1420 		static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7};
1421 
1422 		/* start with a table of all zeros: reject all */
1423 		memset(multicast_table, 0, sizeof(multicast_table));
1424 
1425 		netdev_for_each_mc_addr(ha, dev) {
1426 			int position;
1427 
1428 			/* only use the low order bits */
1429 			position = crc32_le(~0, ha->addr, 6) & 0x3f;
1430 
1431 			/* do some messy swapping to put the bit in the right spot */
1432 			multicast_table[invert3[position&7]] |=
1433 				(1<<invert3[(position>>3)&7]);
1434 		}
1435 
1436 		/* be sure I get rid of flags I might have set */
1437 		lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
1438 
1439 		/* now, the table can be loaded into the chipset */
1440 		update_multicast = 1;
1441 	} else  {
1442 		DBG(2, "%s: ~(RCR_PRMS|RCR_ALMUL)\n", dev->name);
1443 		lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
1444 
1445 		/*
1446 		 * since I'm disabling all multicast entirely, I need to
1447 		 * clear the multicast list
1448 		 */
1449 		memset(multicast_table, 0, sizeof(multicast_table));
1450 		update_multicast = 1;
1451 	}
1452 
1453 	spin_lock_irq(&lp->lock);
1454 	SMC_SELECT_BANK(lp, 0);
1455 	SMC_SET_RCR(lp, lp->rcr_cur_mode);
1456 	if (update_multicast) {
1457 		SMC_SELECT_BANK(lp, 3);
1458 		SMC_SET_MCAST(lp, multicast_table);
1459 	}
1460 	SMC_SELECT_BANK(lp, 2);
1461 	spin_unlock_irq(&lp->lock);
1462 }
1463 
1464 
1465 /*
1466  * Open and Initialize the board
1467  *
1468  * Set up everything, reset the card, etc..
1469  */
1470 static int
1471 smc_open(struct net_device *dev)
1472 {
1473 	struct smc_local *lp = netdev_priv(dev);
1474 
1475 	DBG(2, "%s: %s\n", dev->name, __func__);
1476 
1477 	/* Setup the default Register Modes */
1478 	lp->tcr_cur_mode = TCR_DEFAULT;
1479 	lp->rcr_cur_mode = RCR_DEFAULT;
1480 	lp->rpc_cur_mode = RPC_DEFAULT |
1481 				lp->cfg.leda << RPC_LSXA_SHFT |
1482 				lp->cfg.ledb << RPC_LSXB_SHFT;
1483 
1484 	/*
1485 	 * If we are not using a MII interface, we need to
1486 	 * monitor our own carrier signal to detect faults.
1487 	 */
1488 	if (lp->phy_type == 0)
1489 		lp->tcr_cur_mode |= TCR_MON_CSN;
1490 
1491 	/* reset the hardware */
1492 	smc_reset(dev);
1493 	smc_enable(dev);
1494 
1495 	/* Configure the PHY, initialize the link state */
1496 	if (lp->phy_type != 0)
1497 		smc_phy_configure(&lp->phy_configure);
1498 	else {
1499 		spin_lock_irq(&lp->lock);
1500 		smc_10bt_check_media(dev, 1);
1501 		spin_unlock_irq(&lp->lock);
1502 	}
1503 
1504 	netif_start_queue(dev);
1505 	return 0;
1506 }
1507 
1508 /*
1509  * smc_close
1510  *
1511  * this makes the board clean up everything that it can
1512  * and not talk to the outside world.   Caused by
1513  * an 'ifconfig ethX down'
1514  */
1515 static int smc_close(struct net_device *dev)
1516 {
1517 	struct smc_local *lp = netdev_priv(dev);
1518 
1519 	DBG(2, "%s: %s\n", dev->name, __func__);
1520 
1521 	netif_stop_queue(dev);
1522 	netif_carrier_off(dev);
1523 
1524 	/* clear everything */
1525 	smc_shutdown(dev);
1526 	tasklet_kill(&lp->tx_task);
1527 	smc_phy_powerdown(dev);
1528 	return 0;
1529 }
1530 
1531 /*
1532  * Ethtool support
1533  */
1534 static int
1535 smc_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1536 {
1537 	struct smc_local *lp = netdev_priv(dev);
1538 	int ret;
1539 
1540 	cmd->maxtxpkt = 1;
1541 	cmd->maxrxpkt = 1;
1542 
1543 	if (lp->phy_type != 0) {
1544 		spin_lock_irq(&lp->lock);
1545 		ret = mii_ethtool_gset(&lp->mii, cmd);
1546 		spin_unlock_irq(&lp->lock);
1547 	} else {
1548 		cmd->supported = SUPPORTED_10baseT_Half |
1549 				 SUPPORTED_10baseT_Full |
1550 				 SUPPORTED_TP | SUPPORTED_AUI;
1551 
1552 		if (lp->ctl_rspeed == 10)
1553 			ethtool_cmd_speed_set(cmd, SPEED_10);
1554 		else if (lp->ctl_rspeed == 100)
1555 			ethtool_cmd_speed_set(cmd, SPEED_100);
1556 
1557 		cmd->autoneg = AUTONEG_DISABLE;
1558 		cmd->transceiver = XCVR_INTERNAL;
1559 		cmd->port = 0;
1560 		cmd->duplex = lp->tcr_cur_mode & TCR_SWFDUP ? DUPLEX_FULL : DUPLEX_HALF;
1561 
1562 		ret = 0;
1563 	}
1564 
1565 	return ret;
1566 }
1567 
1568 static int
1569 smc_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1570 {
1571 	struct smc_local *lp = netdev_priv(dev);
1572 	int ret;
1573 
1574 	if (lp->phy_type != 0) {
1575 		spin_lock_irq(&lp->lock);
1576 		ret = mii_ethtool_sset(&lp->mii, cmd);
1577 		spin_unlock_irq(&lp->lock);
1578 	} else {
1579 		if (cmd->autoneg != AUTONEG_DISABLE ||
1580 		    cmd->speed != SPEED_10 ||
1581 		    (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) ||
1582 		    (cmd->port != PORT_TP && cmd->port != PORT_AUI))
1583 			return -EINVAL;
1584 
1585 //		lp->port = cmd->port;
1586 		lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL;
1587 
1588 //		if (netif_running(dev))
1589 //			smc_set_port(dev);
1590 
1591 		ret = 0;
1592 	}
1593 
1594 	return ret;
1595 }
1596 
1597 static void
1598 smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1599 {
1600 	strncpy(info->driver, CARDNAME, sizeof(info->driver));
1601 	strncpy(info->version, version, sizeof(info->version));
1602 	strncpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
1603 }
1604 
1605 static int smc_ethtool_nwayreset(struct net_device *dev)
1606 {
1607 	struct smc_local *lp = netdev_priv(dev);
1608 	int ret = -EINVAL;
1609 
1610 	if (lp->phy_type != 0) {
1611 		spin_lock_irq(&lp->lock);
1612 		ret = mii_nway_restart(&lp->mii);
1613 		spin_unlock_irq(&lp->lock);
1614 	}
1615 
1616 	return ret;
1617 }
1618 
1619 static u32 smc_ethtool_getmsglevel(struct net_device *dev)
1620 {
1621 	struct smc_local *lp = netdev_priv(dev);
1622 	return lp->msg_enable;
1623 }
1624 
1625 static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level)
1626 {
1627 	struct smc_local *lp = netdev_priv(dev);
1628 	lp->msg_enable = level;
1629 }
1630 
1631 static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word)
1632 {
1633 	u16 ctl;
1634 	struct smc_local *lp = netdev_priv(dev);
1635 	void __iomem *ioaddr = lp->base;
1636 
1637 	spin_lock_irq(&lp->lock);
1638 	/* load word into GP register */
1639 	SMC_SELECT_BANK(lp, 1);
1640 	SMC_SET_GP(lp, word);
1641 	/* set the address to put the data in EEPROM */
1642 	SMC_SELECT_BANK(lp, 2);
1643 	SMC_SET_PTR(lp, addr);
1644 	/* tell it to write */
1645 	SMC_SELECT_BANK(lp, 1);
1646 	ctl = SMC_GET_CTL(lp);
1647 	SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE));
1648 	/* wait for it to finish */
1649 	do {
1650 		udelay(1);
1651 	} while (SMC_GET_CTL(lp) & CTL_STORE);
1652 	/* clean up */
1653 	SMC_SET_CTL(lp, ctl);
1654 	SMC_SELECT_BANK(lp, 2);
1655 	spin_unlock_irq(&lp->lock);
1656 	return 0;
1657 }
1658 
1659 static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word)
1660 {
1661 	u16 ctl;
1662 	struct smc_local *lp = netdev_priv(dev);
1663 	void __iomem *ioaddr = lp->base;
1664 
1665 	spin_lock_irq(&lp->lock);
1666 	/* set the EEPROM address to get the data from */
1667 	SMC_SELECT_BANK(lp, 2);
1668 	SMC_SET_PTR(lp, addr | PTR_READ);
1669 	/* tell it to load */
1670 	SMC_SELECT_BANK(lp, 1);
1671 	SMC_SET_GP(lp, 0xffff);	/* init to known */
1672 	ctl = SMC_GET_CTL(lp);
1673 	SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD));
1674 	/* wait for it to finish */
1675 	do {
1676 		udelay(1);
1677 	} while (SMC_GET_CTL(lp) & CTL_RELOAD);
1678 	/* read word from GP register */
1679 	*word = SMC_GET_GP(lp);
1680 	/* clean up */
1681 	SMC_SET_CTL(lp, ctl);
1682 	SMC_SELECT_BANK(lp, 2);
1683 	spin_unlock_irq(&lp->lock);
1684 	return 0;
1685 }
1686 
1687 static int smc_ethtool_geteeprom_len(struct net_device *dev)
1688 {
1689 	return 0x23 * 2;
1690 }
1691 
1692 static int smc_ethtool_geteeprom(struct net_device *dev,
1693 		struct ethtool_eeprom *eeprom, u8 *data)
1694 {
1695 	int i;
1696 	int imax;
1697 
1698 	DBG(1, "Reading %d bytes at %d(0x%x)\n",
1699 		eeprom->len, eeprom->offset, eeprom->offset);
1700 	imax = smc_ethtool_geteeprom_len(dev);
1701 	for (i = 0; i < eeprom->len; i += 2) {
1702 		int ret;
1703 		u16 wbuf;
1704 		int offset = i + eeprom->offset;
1705 		if (offset > imax)
1706 			break;
1707 		ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf);
1708 		if (ret != 0)
1709 			return ret;
1710 		DBG(2, "Read 0x%x from 0x%x\n", wbuf, offset >> 1);
1711 		data[i] = (wbuf >> 8) & 0xff;
1712 		data[i+1] = wbuf & 0xff;
1713 	}
1714 	return 0;
1715 }
1716 
1717 static int smc_ethtool_seteeprom(struct net_device *dev,
1718 		struct ethtool_eeprom *eeprom, u8 *data)
1719 {
1720 	int i;
1721 	int imax;
1722 
1723 	DBG(1, "Writing %d bytes to %d(0x%x)\n",
1724 			eeprom->len, eeprom->offset, eeprom->offset);
1725 	imax = smc_ethtool_geteeprom_len(dev);
1726 	for (i = 0; i < eeprom->len; i += 2) {
1727 		int ret;
1728 		u16 wbuf;
1729 		int offset = i + eeprom->offset;
1730 		if (offset > imax)
1731 			break;
1732 		wbuf = (data[i] << 8) | data[i + 1];
1733 		DBG(2, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1);
1734 		ret = smc_write_eeprom_word(dev, offset >> 1, wbuf);
1735 		if (ret != 0)
1736 			return ret;
1737 	}
1738 	return 0;
1739 }
1740 
1741 
1742 static const struct ethtool_ops smc_ethtool_ops = {
1743 	.get_settings	= smc_ethtool_getsettings,
1744 	.set_settings	= smc_ethtool_setsettings,
1745 	.get_drvinfo	= smc_ethtool_getdrvinfo,
1746 
1747 	.get_msglevel	= smc_ethtool_getmsglevel,
1748 	.set_msglevel	= smc_ethtool_setmsglevel,
1749 	.nway_reset	= smc_ethtool_nwayreset,
1750 	.get_link	= ethtool_op_get_link,
1751 	.get_eeprom_len = smc_ethtool_geteeprom_len,
1752 	.get_eeprom	= smc_ethtool_geteeprom,
1753 	.set_eeprom	= smc_ethtool_seteeprom,
1754 };
1755 
1756 static const struct net_device_ops smc_netdev_ops = {
1757 	.ndo_open		= smc_open,
1758 	.ndo_stop		= smc_close,
1759 	.ndo_start_xmit		= smc_hard_start_xmit,
1760 	.ndo_tx_timeout		= smc_timeout,
1761 	.ndo_set_rx_mode	= smc_set_multicast_list,
1762 	.ndo_change_mtu		= eth_change_mtu,
1763 	.ndo_validate_addr	= eth_validate_addr,
1764 	.ndo_set_mac_address 	= eth_mac_addr,
1765 #ifdef CONFIG_NET_POLL_CONTROLLER
1766 	.ndo_poll_controller	= smc_poll_controller,
1767 #endif
1768 };
1769 
1770 /*
1771  * smc_findirq
1772  *
1773  * This routine has a simple purpose -- make the SMC chip generate an
1774  * interrupt, so an auto-detect routine can detect it, and find the IRQ,
1775  */
1776 /*
1777  * does this still work?
1778  *
1779  * I just deleted auto_irq.c, since it was never built...
1780  *   --jgarzik
1781  */
1782 static int smc_findirq(struct smc_local *lp)
1783 {
1784 	void __iomem *ioaddr = lp->base;
1785 	int timeout = 20;
1786 	unsigned long cookie;
1787 
1788 	DBG(2, "%s: %s\n", CARDNAME, __func__);
1789 
1790 	cookie = probe_irq_on();
1791 
1792 	/*
1793 	 * What I try to do here is trigger an ALLOC_INT. This is done
1794 	 * by allocating a small chunk of memory, which will give an interrupt
1795 	 * when done.
1796 	 */
1797 	/* enable ALLOCation interrupts ONLY */
1798 	SMC_SELECT_BANK(lp, 2);
1799 	SMC_SET_INT_MASK(lp, IM_ALLOC_INT);
1800 
1801 	/*
1802  	 * Allocate 512 bytes of memory.  Note that the chip was just
1803 	 * reset so all the memory is available
1804 	 */
1805 	SMC_SET_MMU_CMD(lp, MC_ALLOC | 1);
1806 
1807 	/*
1808 	 * Wait until positive that the interrupt has been generated
1809 	 */
1810 	do {
1811 		int int_status;
1812 		udelay(10);
1813 		int_status = SMC_GET_INT(lp);
1814 		if (int_status & IM_ALLOC_INT)
1815 			break;		/* got the interrupt */
1816 	} while (--timeout);
1817 
1818 	/*
1819 	 * there is really nothing that I can do here if timeout fails,
1820 	 * as autoirq_report will return a 0 anyway, which is what I
1821 	 * want in this case.   Plus, the clean up is needed in both
1822 	 * cases.
1823 	 */
1824 
1825 	/* and disable all interrupts again */
1826 	SMC_SET_INT_MASK(lp, 0);
1827 
1828 	/* and return what I found */
1829 	return probe_irq_off(cookie);
1830 }
1831 
1832 /*
1833  * Function: smc_probe(unsigned long ioaddr)
1834  *
1835  * Purpose:
1836  *	Tests to see if a given ioaddr points to an SMC91x chip.
1837  *	Returns a 0 on success
1838  *
1839  * Algorithm:
1840  *	(1) see if the high byte of BANK_SELECT is 0x33
1841  * 	(2) compare the ioaddr with the base register's address
1842  *	(3) see if I recognize the chip ID in the appropriate register
1843  *
1844  * Here I do typical initialization tasks.
1845  *
1846  * o  Initialize the structure if needed
1847  * o  print out my vanity message if not done so already
1848  * o  print out what type of hardware is detected
1849  * o  print out the ethernet address
1850  * o  find the IRQ
1851  * o  set up my private data
1852  * o  configure the dev structure with my subroutines
1853  * o  actually GRAB the irq.
1854  * o  GRAB the region
1855  */
1856 static int smc_probe(struct net_device *dev, void __iomem *ioaddr,
1857 		     unsigned long irq_flags)
1858 {
1859 	struct smc_local *lp = netdev_priv(dev);
1860 	static int version_printed = 0;
1861 	int retval;
1862 	unsigned int val, revision_register;
1863 	const char *version_string;
1864 
1865 	DBG(2, "%s: %s\n", CARDNAME, __func__);
1866 
1867 	/* First, see if the high byte is 0x33 */
1868 	val = SMC_CURRENT_BANK(lp);
1869 	DBG(2, "%s: bank signature probe returned 0x%04x\n", CARDNAME, val);
1870 	if ((val & 0xFF00) != 0x3300) {
1871 		if ((val & 0xFF) == 0x33) {
1872 			printk(KERN_WARNING
1873 				"%s: Detected possible byte-swapped interface"
1874 				" at IOADDR %p\n", CARDNAME, ioaddr);
1875 		}
1876 		retval = -ENODEV;
1877 		goto err_out;
1878 	}
1879 
1880 	/*
1881 	 * The above MIGHT indicate a device, but I need to write to
1882 	 * further test this.
1883 	 */
1884 	SMC_SELECT_BANK(lp, 0);
1885 	val = SMC_CURRENT_BANK(lp);
1886 	if ((val & 0xFF00) != 0x3300) {
1887 		retval = -ENODEV;
1888 		goto err_out;
1889 	}
1890 
1891 	/*
1892 	 * well, we've already written once, so hopefully another
1893 	 * time won't hurt.  This time, I need to switch the bank
1894 	 * register to bank 1, so I can access the base address
1895 	 * register
1896 	 */
1897 	SMC_SELECT_BANK(lp, 1);
1898 	val = SMC_GET_BASE(lp);
1899 	val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT;
1900 	if (((unsigned int)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) {
1901 		printk("%s: IOADDR %p doesn't match configuration (%x).\n",
1902 			CARDNAME, ioaddr, val);
1903 	}
1904 
1905 	/*
1906 	 * check if the revision register is something that I
1907 	 * recognize.  These might need to be added to later,
1908 	 * as future revisions could be added.
1909 	 */
1910 	SMC_SELECT_BANK(lp, 3);
1911 	revision_register = SMC_GET_REV(lp);
1912 	DBG(2, "%s: revision = 0x%04x\n", CARDNAME, revision_register);
1913 	version_string = chip_ids[ (revision_register >> 4) & 0xF];
1914 	if (!version_string || (revision_register & 0xff00) != 0x3300) {
1915 		/* I don't recognize this chip, so... */
1916 		printk("%s: IO %p: Unrecognized revision register 0x%04x"
1917 			", Contact author.\n", CARDNAME,
1918 			ioaddr, revision_register);
1919 
1920 		retval = -ENODEV;
1921 		goto err_out;
1922 	}
1923 
1924 	/* At this point I'll assume that the chip is an SMC91x. */
1925 	if (version_printed++ == 0)
1926 		printk("%s", version);
1927 
1928 	/* fill in some of the fields */
1929 	dev->base_addr = (unsigned long)ioaddr;
1930 	lp->base = ioaddr;
1931 	lp->version = revision_register & 0xff;
1932 	spin_lock_init(&lp->lock);
1933 
1934 	/* Get the MAC address */
1935 	SMC_SELECT_BANK(lp, 1);
1936 	SMC_GET_MAC_ADDR(lp, dev->dev_addr);
1937 
1938 	/* now, reset the chip, and put it into a known state */
1939 	smc_reset(dev);
1940 
1941 	/*
1942 	 * If dev->irq is 0, then the device has to be banged on to see
1943 	 * what the IRQ is.
1944  	 *
1945 	 * This banging doesn't always detect the IRQ, for unknown reasons.
1946 	 * a workaround is to reset the chip and try again.
1947 	 *
1948 	 * Interestingly, the DOS packet driver *SETS* the IRQ on the card to
1949 	 * be what is requested on the command line.   I don't do that, mostly
1950 	 * because the card that I have uses a non-standard method of accessing
1951 	 * the IRQs, and because this _should_ work in most configurations.
1952 	 *
1953 	 * Specifying an IRQ is done with the assumption that the user knows
1954 	 * what (s)he is doing.  No checking is done!!!!
1955 	 */
1956 	if (dev->irq < 1) {
1957 		int trials;
1958 
1959 		trials = 3;
1960 		while (trials--) {
1961 			dev->irq = smc_findirq(lp);
1962 			if (dev->irq)
1963 				break;
1964 			/* kick the card and try again */
1965 			smc_reset(dev);
1966 		}
1967 	}
1968 	if (dev->irq == 0) {
1969 		printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n",
1970 			dev->name);
1971 		retval = -ENODEV;
1972 		goto err_out;
1973 	}
1974 	dev->irq = irq_canonicalize(dev->irq);
1975 
1976 	/* Fill in the fields of the device structure with ethernet values. */
1977 	ether_setup(dev);
1978 
1979 	dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1980 	dev->netdev_ops = &smc_netdev_ops;
1981 	dev->ethtool_ops = &smc_ethtool_ops;
1982 
1983 	tasklet_init(&lp->tx_task, smc_hardware_send_pkt, (unsigned long)dev);
1984 	INIT_WORK(&lp->phy_configure, smc_phy_configure);
1985 	lp->dev = dev;
1986 	lp->mii.phy_id_mask = 0x1f;
1987 	lp->mii.reg_num_mask = 0x1f;
1988 	lp->mii.force_media = 0;
1989 	lp->mii.full_duplex = 0;
1990 	lp->mii.dev = dev;
1991 	lp->mii.mdio_read = smc_phy_read;
1992 	lp->mii.mdio_write = smc_phy_write;
1993 
1994 	/*
1995 	 * Locate the phy, if any.
1996 	 */
1997 	if (lp->version >= (CHIP_91100 << 4))
1998 		smc_phy_detect(dev);
1999 
2000 	/* then shut everything down to save power */
2001 	smc_shutdown(dev);
2002 	smc_phy_powerdown(dev);
2003 
2004 	/* Set default parameters */
2005 	lp->msg_enable = NETIF_MSG_LINK;
2006 	lp->ctl_rfduplx = 0;
2007 	lp->ctl_rspeed = 10;
2008 
2009 	if (lp->version >= (CHIP_91100 << 4)) {
2010 		lp->ctl_rfduplx = 1;
2011 		lp->ctl_rspeed = 100;
2012 	}
2013 
2014 	/* Grab the IRQ */
2015 	retval = request_irq(dev->irq, smc_interrupt, irq_flags, dev->name, dev);
2016       	if (retval)
2017       		goto err_out;
2018 
2019 #ifdef CONFIG_ARCH_PXA
2020 #  ifdef SMC_USE_PXA_DMA
2021 	lp->cfg.flags |= SMC91X_USE_DMA;
2022 #  endif
2023 	if (lp->cfg.flags & SMC91X_USE_DMA) {
2024 		int dma = pxa_request_dma(dev->name, DMA_PRIO_LOW,
2025 					  smc_pxa_dma_irq, NULL);
2026 		if (dma >= 0)
2027 			dev->dma = dma;
2028 	}
2029 #endif
2030 
2031 	retval = register_netdev(dev);
2032 	if (retval == 0) {
2033 		/* now, print out the card info, in a short format.. */
2034 		printk("%s: %s (rev %d) at %p IRQ %d",
2035 			dev->name, version_string, revision_register & 0x0f,
2036 			lp->base, dev->irq);
2037 
2038 		if (dev->dma != (unsigned char)-1)
2039 			printk(" DMA %d", dev->dma);
2040 
2041 		printk("%s%s\n",
2042 			lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "",
2043 			THROTTLE_TX_PKTS ? " [throttle_tx]" : "");
2044 
2045 		if (!is_valid_ether_addr(dev->dev_addr)) {
2046 			printk("%s: Invalid ethernet MAC address.  Please "
2047 			       "set using ifconfig\n", dev->name);
2048 		} else {
2049 			/* Print the Ethernet address */
2050 			printk("%s: Ethernet addr: %pM\n",
2051 			       dev->name, dev->dev_addr);
2052 		}
2053 
2054 		if (lp->phy_type == 0) {
2055 			PRINTK("%s: No PHY found\n", dev->name);
2056 		} else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) {
2057 			PRINTK("%s: PHY LAN83C183 (LAN91C111 Internal)\n", dev->name);
2058 		} else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) {
2059 			PRINTK("%s: PHY LAN83C180\n", dev->name);
2060 		}
2061 	}
2062 
2063 err_out:
2064 #ifdef CONFIG_ARCH_PXA
2065 	if (retval && dev->dma != (unsigned char)-1)
2066 		pxa_free_dma(dev->dma);
2067 #endif
2068 	return retval;
2069 }
2070 
2071 static int smc_enable_device(struct platform_device *pdev)
2072 {
2073 	struct net_device *ndev = platform_get_drvdata(pdev);
2074 	struct smc_local *lp = netdev_priv(ndev);
2075 	unsigned long flags;
2076 	unsigned char ecor, ecsr;
2077 	void __iomem *addr;
2078 	struct resource * res;
2079 
2080 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2081 	if (!res)
2082 		return 0;
2083 
2084 	/*
2085 	 * Map the attribute space.  This is overkill, but clean.
2086 	 */
2087 	addr = ioremap(res->start, ATTRIB_SIZE);
2088 	if (!addr)
2089 		return -ENOMEM;
2090 
2091 	/*
2092 	 * Reset the device.  We must disable IRQs around this
2093 	 * since a reset causes the IRQ line become active.
2094 	 */
2095 	local_irq_save(flags);
2096 	ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
2097 	writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
2098 	readb(addr + (ECOR << SMC_IO_SHIFT));
2099 
2100 	/*
2101 	 * Wait 100us for the chip to reset.
2102 	 */
2103 	udelay(100);
2104 
2105 	/*
2106 	 * The device will ignore all writes to the enable bit while
2107 	 * reset is asserted, even if the reset bit is cleared in the
2108 	 * same write.  Must clear reset first, then enable the device.
2109 	 */
2110 	writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
2111 	writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
2112 
2113 	/*
2114 	 * Set the appropriate byte/word mode.
2115 	 */
2116 	ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
2117 	if (!SMC_16BIT(lp))
2118 		ecsr |= ECSR_IOIS8;
2119 	writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
2120 	local_irq_restore(flags);
2121 
2122 	iounmap(addr);
2123 
2124 	/*
2125 	 * Wait for the chip to wake up.  We could poll the control
2126 	 * register in the main register space, but that isn't mapped
2127 	 * yet.  We know this is going to take 750us.
2128 	 */
2129 	msleep(1);
2130 
2131 	return 0;
2132 }
2133 
2134 static int smc_request_attrib(struct platform_device *pdev,
2135 			      struct net_device *ndev)
2136 {
2137 	struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2138 	struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2139 
2140 	if (!res)
2141 		return 0;
2142 
2143 	if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME))
2144 		return -EBUSY;
2145 
2146 	return 0;
2147 }
2148 
2149 static void smc_release_attrib(struct platform_device *pdev,
2150 			       struct net_device *ndev)
2151 {
2152 	struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2153 	struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2154 
2155 	if (res)
2156 		release_mem_region(res->start, ATTRIB_SIZE);
2157 }
2158 
2159 static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev)
2160 {
2161 	if (SMC_CAN_USE_DATACS) {
2162 		struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
2163 		struct smc_local *lp = netdev_priv(ndev);
2164 
2165 		if (!res)
2166 			return;
2167 
2168 		if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) {
2169 			printk(KERN_INFO "%s: failed to request datacs memory region.\n", CARDNAME);
2170 			return;
2171 		}
2172 
2173 		lp->datacs = ioremap(res->start, SMC_DATA_EXTENT);
2174 	}
2175 }
2176 
2177 static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev)
2178 {
2179 	if (SMC_CAN_USE_DATACS) {
2180 		struct smc_local *lp = netdev_priv(ndev);
2181 		struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
2182 
2183 		if (lp->datacs)
2184 			iounmap(lp->datacs);
2185 
2186 		lp->datacs = NULL;
2187 
2188 		if (res)
2189 			release_mem_region(res->start, SMC_DATA_EXTENT);
2190 	}
2191 }
2192 
2193 /*
2194  * smc_init(void)
2195  *   Input parameters:
2196  *	dev->base_addr == 0, try to find all possible locations
2197  *	dev->base_addr > 0x1ff, this is the address to check
2198  *	dev->base_addr == <anything else>, return failure code
2199  *
2200  *   Output:
2201  *	0 --> there is a device
2202  *	anything else, error
2203  */
2204 static int smc_drv_probe(struct platform_device *pdev)
2205 {
2206 	struct smc91x_platdata *pd = pdev->dev.platform_data;
2207 	struct smc_local *lp;
2208 	struct net_device *ndev;
2209 	struct resource *res, *ires;
2210 	unsigned int __iomem *addr;
2211 	unsigned long irq_flags = SMC_IRQ_FLAGS;
2212 	int ret;
2213 
2214 	ndev = alloc_etherdev(sizeof(struct smc_local));
2215 	if (!ndev) {
2216 		ret = -ENOMEM;
2217 		goto out;
2218 	}
2219 	SET_NETDEV_DEV(ndev, &pdev->dev);
2220 
2221 	/* get configuration from platform data, only allow use of
2222 	 * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set.
2223 	 */
2224 
2225 	lp = netdev_priv(ndev);
2226 
2227 	if (pd) {
2228 		memcpy(&lp->cfg, pd, sizeof(lp->cfg));
2229 		lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags);
2230 	} else {
2231 		lp->cfg.flags |= (SMC_CAN_USE_8BIT)  ? SMC91X_USE_8BIT  : 0;
2232 		lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0;
2233 		lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0;
2234 		lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0;
2235 	}
2236 
2237 	if (!lp->cfg.leda && !lp->cfg.ledb) {
2238 		lp->cfg.leda = RPC_LSA_DEFAULT;
2239 		lp->cfg.ledb = RPC_LSB_DEFAULT;
2240 	}
2241 
2242 	ndev->dma = (unsigned char)-1;
2243 
2244 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
2245 	if (!res)
2246 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2247 	if (!res) {
2248 		ret = -ENODEV;
2249 		goto out_free_netdev;
2250 	}
2251 
2252 
2253 	if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) {
2254 		ret = -EBUSY;
2255 		goto out_free_netdev;
2256 	}
2257 
2258 	ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2259 	if (!ires) {
2260 		ret = -ENODEV;
2261 		goto out_release_io;
2262 	}
2263 
2264 	ndev->irq = ires->start;
2265 
2266 	if (irq_flags == -1 || ires->flags & IRQF_TRIGGER_MASK)
2267 		irq_flags = ires->flags & IRQF_TRIGGER_MASK;
2268 
2269 	ret = smc_request_attrib(pdev, ndev);
2270 	if (ret)
2271 		goto out_release_io;
2272 #if defined(CONFIG_SA1100_ASSABET)
2273 	neponset_ncr_set(NCR_ENET_OSC_EN);
2274 #endif
2275 	platform_set_drvdata(pdev, ndev);
2276 	ret = smc_enable_device(pdev);
2277 	if (ret)
2278 		goto out_release_attrib;
2279 
2280 	addr = ioremap(res->start, SMC_IO_EXTENT);
2281 	if (!addr) {
2282 		ret = -ENOMEM;
2283 		goto out_release_attrib;
2284 	}
2285 
2286 #ifdef CONFIG_ARCH_PXA
2287 	{
2288 		struct smc_local *lp = netdev_priv(ndev);
2289 		lp->device = &pdev->dev;
2290 		lp->physaddr = res->start;
2291 	}
2292 #endif
2293 
2294 	ret = smc_probe(ndev, addr, irq_flags);
2295 	if (ret != 0)
2296 		goto out_iounmap;
2297 
2298 	smc_request_datacs(pdev, ndev);
2299 
2300 	return 0;
2301 
2302  out_iounmap:
2303 	platform_set_drvdata(pdev, NULL);
2304 	iounmap(addr);
2305  out_release_attrib:
2306 	smc_release_attrib(pdev, ndev);
2307  out_release_io:
2308 	release_mem_region(res->start, SMC_IO_EXTENT);
2309  out_free_netdev:
2310 	free_netdev(ndev);
2311  out:
2312 	printk("%s: not found (%d).\n", CARDNAME, ret);
2313 
2314 	return ret;
2315 }
2316 
2317 static int smc_drv_remove(struct platform_device *pdev)
2318 {
2319 	struct net_device *ndev = platform_get_drvdata(pdev);
2320 	struct smc_local *lp = netdev_priv(ndev);
2321 	struct resource *res;
2322 
2323 	platform_set_drvdata(pdev, NULL);
2324 
2325 	unregister_netdev(ndev);
2326 
2327 	free_irq(ndev->irq, ndev);
2328 
2329 #ifdef CONFIG_ARCH_PXA
2330 	if (ndev->dma != (unsigned char)-1)
2331 		pxa_free_dma(ndev->dma);
2332 #endif
2333 	iounmap(lp->base);
2334 
2335 	smc_release_datacs(pdev,ndev);
2336 	smc_release_attrib(pdev,ndev);
2337 
2338 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
2339 	if (!res)
2340 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2341 	release_mem_region(res->start, SMC_IO_EXTENT);
2342 
2343 	free_netdev(ndev);
2344 
2345 	return 0;
2346 }
2347 
2348 static int smc_drv_suspend(struct device *dev)
2349 {
2350 	struct platform_device *pdev = to_platform_device(dev);
2351 	struct net_device *ndev = platform_get_drvdata(pdev);
2352 
2353 	if (ndev) {
2354 		if (netif_running(ndev)) {
2355 			netif_device_detach(ndev);
2356 			smc_shutdown(ndev);
2357 			smc_phy_powerdown(ndev);
2358 		}
2359 	}
2360 	return 0;
2361 }
2362 
2363 static int smc_drv_resume(struct device *dev)
2364 {
2365 	struct platform_device *pdev = to_platform_device(dev);
2366 	struct net_device *ndev = platform_get_drvdata(pdev);
2367 
2368 	if (ndev) {
2369 		struct smc_local *lp = netdev_priv(ndev);
2370 		smc_enable_device(pdev);
2371 		if (netif_running(ndev)) {
2372 			smc_reset(ndev);
2373 			smc_enable(ndev);
2374 			if (lp->phy_type != 0)
2375 				smc_phy_configure(&lp->phy_configure);
2376 			netif_device_attach(ndev);
2377 		}
2378 	}
2379 	return 0;
2380 }
2381 
2382 #ifdef CONFIG_OF
2383 static const struct of_device_id smc91x_match[] = {
2384 	{ .compatible = "smsc,lan91c94", },
2385 	{ .compatible = "smsc,lan91c111", },
2386 	{},
2387 };
2388 MODULE_DEVICE_TABLE(of, smc91x_match);
2389 #else
2390 #define smc91x_match NULL
2391 #endif
2392 
2393 static struct dev_pm_ops smc_drv_pm_ops = {
2394 	.suspend	= smc_drv_suspend,
2395 	.resume		= smc_drv_resume,
2396 };
2397 
2398 static struct platform_driver smc_driver = {
2399 	.probe		= smc_drv_probe,
2400 	.remove		= smc_drv_remove,
2401 	.driver		= {
2402 		.name	= CARDNAME,
2403 		.owner	= THIS_MODULE,
2404 		.pm	= &smc_drv_pm_ops,
2405 		.of_match_table = smc91x_match,
2406 	},
2407 };
2408 
2409 module_platform_driver(smc_driver);
2410