1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for SGI's IOC3 based Ethernet cards as found in the PCI card. 3 * 4 * Copyright (C) 1999, 2000, 01, 03, 06 Ralf Baechle 5 * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc. 6 * 7 * References: 8 * o IOC3 ASIC specification 4.51, 1996-04-18 9 * o IEEE 802.3 specification, 2000 edition 10 * o DP38840A Specification, National Semiconductor, March 1997 11 * 12 * To do: 13 * 14 * o Use prefetching for large packets. What is a good lower limit for 15 * prefetching? 16 * o Use hardware checksums. 17 * o Which PHYs might possibly be attached to the IOC3 in real live, 18 * which workarounds are required for them? Do we ever have Lucent's? 19 * o For the 2.5 branch kill the mii-tool ioctls. 20 */ 21 22 #define IOC3_NAME "ioc3-eth" 23 #define IOC3_VERSION "2.6.3-4" 24 25 #include <linux/delay.h> 26 #include <linux/kernel.h> 27 #include <linux/mm.h> 28 #include <linux/errno.h> 29 #include <linux/module.h> 30 #include <linux/init.h> 31 #include <linux/crc16.h> 32 #include <linux/crc32.h> 33 #include <linux/mii.h> 34 #include <linux/in.h> 35 #include <linux/io.h> 36 #include <linux/ip.h> 37 #include <linux/tcp.h> 38 #include <linux/udp.h> 39 #include <linux/gfp.h> 40 #include <linux/netdevice.h> 41 #include <linux/etherdevice.h> 42 #include <linux/ethtool.h> 43 #include <linux/skbuff.h> 44 #include <linux/dma-mapping.h> 45 #include <linux/platform_device.h> 46 #include <linux/nvmem-consumer.h> 47 48 #include <net/ip.h> 49 50 #include <asm/sn/ioc3.h> 51 #include <asm/pci/bridge.h> 52 53 #define CRC16_INIT 0 54 #define CRC16_VALID 0xb001 55 56 /* Number of RX buffers. This is tunable in the range of 16 <= x < 512. 57 * The value must be a power of two. 58 */ 59 #define RX_BUFFS 64 60 #define RX_RING_ENTRIES 512 /* fixed in hardware */ 61 #define RX_RING_MASK (RX_RING_ENTRIES - 1) 62 #define RX_RING_SIZE (RX_RING_ENTRIES * sizeof(u64)) 63 64 /* 128 TX buffers (not tunable) */ 65 #define TX_RING_ENTRIES 128 66 #define TX_RING_MASK (TX_RING_ENTRIES - 1) 67 #define TX_RING_SIZE (TX_RING_ENTRIES * sizeof(struct ioc3_etxd)) 68 69 /* IOC3 does dma transfers in 128 byte blocks */ 70 #define IOC3_DMA_XFER_LEN 128UL 71 72 /* Every RX buffer starts with 8 byte descriptor data */ 73 #define RX_OFFSET (sizeof(struct ioc3_erxbuf) + NET_IP_ALIGN) 74 #define RX_BUF_SIZE (13 * IOC3_DMA_XFER_LEN) 75 76 #define ETCSR_FD ((21 << ETCSR_IPGR2_SHIFT) | (21 << ETCSR_IPGR1_SHIFT) | 21) 77 #define ETCSR_HD ((17 << ETCSR_IPGR2_SHIFT) | (11 << ETCSR_IPGR1_SHIFT) | 21) 78 79 /* Private per NIC data of the driver. */ 80 struct ioc3_private { 81 struct ioc3_ethregs *regs; 82 struct device *dma_dev; 83 u32 *ssram; 84 unsigned long *rxr; /* pointer to receiver ring */ 85 void *tx_ring; 86 struct ioc3_etxd *txr; 87 dma_addr_t rxr_dma; 88 dma_addr_t txr_dma; 89 struct sk_buff *rx_skbs[RX_RING_ENTRIES]; 90 struct sk_buff *tx_skbs[TX_RING_ENTRIES]; 91 int rx_ci; /* RX consumer index */ 92 int rx_pi; /* RX producer index */ 93 int tx_ci; /* TX consumer index */ 94 int tx_pi; /* TX producer index */ 95 int txqlen; 96 u32 emcr, ehar_h, ehar_l; 97 spinlock_t ioc3_lock; 98 struct mii_if_info mii; 99 100 /* Members used by autonegotiation */ 101 struct timer_list ioc3_timer; 102 }; 103 104 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 105 static void ioc3_set_multicast_list(struct net_device *dev); 106 static netdev_tx_t ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev); 107 static void ioc3_timeout(struct net_device *dev, unsigned int txqueue); 108 static inline unsigned int ioc3_hash(const unsigned char *addr); 109 static void ioc3_start(struct ioc3_private *ip); 110 static inline void ioc3_stop(struct ioc3_private *ip); 111 static void ioc3_init(struct net_device *dev); 112 static int ioc3_alloc_rx_bufs(struct net_device *dev); 113 static void ioc3_free_rx_bufs(struct ioc3_private *ip); 114 static inline void ioc3_clean_tx_ring(struct ioc3_private *ip); 115 116 static const struct ethtool_ops ioc3_ethtool_ops; 117 118 static inline unsigned long aligned_rx_skb_addr(unsigned long addr) 119 { 120 return (~addr + 1) & (IOC3_DMA_XFER_LEN - 1UL); 121 } 122 123 static inline int ioc3_alloc_skb(struct ioc3_private *ip, struct sk_buff **skb, 124 struct ioc3_erxbuf **rxb, dma_addr_t *rxb_dma) 125 { 126 struct sk_buff *new_skb; 127 dma_addr_t d; 128 int offset; 129 130 new_skb = alloc_skb(RX_BUF_SIZE + IOC3_DMA_XFER_LEN - 1, GFP_ATOMIC); 131 if (!new_skb) 132 return -ENOMEM; 133 134 /* ensure buffer is aligned to IOC3_DMA_XFER_LEN */ 135 offset = aligned_rx_skb_addr((unsigned long)new_skb->data); 136 if (offset) 137 skb_reserve(new_skb, offset); 138 139 d = dma_map_single(ip->dma_dev, new_skb->data, 140 RX_BUF_SIZE, DMA_FROM_DEVICE); 141 142 if (dma_mapping_error(ip->dma_dev, d)) { 143 dev_kfree_skb_any(new_skb); 144 return -ENOMEM; 145 } 146 *rxb_dma = d; 147 *rxb = (struct ioc3_erxbuf *)new_skb->data; 148 skb_reserve(new_skb, RX_OFFSET); 149 *skb = new_skb; 150 151 return 0; 152 } 153 154 #ifdef CONFIG_PCI_XTALK_BRIDGE 155 static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr) 156 { 157 return (addr & ~PCI64_ATTR_BAR) | attr; 158 } 159 160 #define ERBAR_VAL (ERBAR_BARRIER_BIT << ERBAR_RXBARR_SHIFT) 161 #else 162 static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr) 163 { 164 return addr; 165 } 166 167 #define ERBAR_VAL 0 168 #endif 169 170 static int ioc3eth_nvmem_match(struct device *dev, const void *data) 171 { 172 const char *name = dev_name(dev); 173 const char *prefix = data; 174 int prefix_len; 175 176 prefix_len = strlen(prefix); 177 if (strlen(name) < (prefix_len + 3)) 178 return 0; 179 180 if (memcmp(prefix, name, prefix_len) != 0) 181 return 0; 182 183 /* found nvmem device which is attached to our ioc3 184 * now check for one wire family code 09, 89 and 91 185 */ 186 if (memcmp(name + prefix_len, "09-", 3) == 0) 187 return 1; 188 if (memcmp(name + prefix_len, "89-", 3) == 0) 189 return 1; 190 if (memcmp(name + prefix_len, "91-", 3) == 0) 191 return 1; 192 193 return 0; 194 } 195 196 static int ioc3eth_get_mac_addr(struct resource *res, u8 mac_addr[6]) 197 { 198 struct nvmem_device *nvmem; 199 char prefix[24]; 200 u8 prom[16]; 201 int ret; 202 int i; 203 204 snprintf(prefix, sizeof(prefix), "ioc3-%012llx-", 205 res->start & ~0xffff); 206 207 nvmem = nvmem_device_find(prefix, ioc3eth_nvmem_match); 208 if (IS_ERR(nvmem)) 209 return PTR_ERR(nvmem); 210 211 ret = nvmem_device_read(nvmem, 0, 16, prom); 212 nvmem_device_put(nvmem); 213 if (ret < 0) 214 return ret; 215 216 /* check, if content is valid */ 217 if (prom[0] != 0x0a || 218 crc16(CRC16_INIT, prom, 13) != CRC16_VALID) 219 return -EINVAL; 220 221 for (i = 0; i < 6; i++) 222 mac_addr[i] = prom[10 - i]; 223 224 return 0; 225 } 226 227 static void __ioc3_set_mac_address(struct net_device *dev) 228 { 229 struct ioc3_private *ip = netdev_priv(dev); 230 231 writel((dev->dev_addr[5] << 8) | 232 dev->dev_addr[4], 233 &ip->regs->emar_h); 234 writel((dev->dev_addr[3] << 24) | 235 (dev->dev_addr[2] << 16) | 236 (dev->dev_addr[1] << 8) | 237 dev->dev_addr[0], 238 &ip->regs->emar_l); 239 } 240 241 static int ioc3_set_mac_address(struct net_device *dev, void *addr) 242 { 243 struct ioc3_private *ip = netdev_priv(dev); 244 struct sockaddr *sa = addr; 245 246 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len); 247 248 spin_lock_irq(&ip->ioc3_lock); 249 __ioc3_set_mac_address(dev); 250 spin_unlock_irq(&ip->ioc3_lock); 251 252 return 0; 253 } 254 255 /* Caller must hold the ioc3_lock ever for MII readers. This is also 256 * used to protect the transmitter side but it's low contention. 257 */ 258 static int ioc3_mdio_read(struct net_device *dev, int phy, int reg) 259 { 260 struct ioc3_private *ip = netdev_priv(dev); 261 struct ioc3_ethregs *regs = ip->regs; 262 263 while (readl(®s->micr) & MICR_BUSY) 264 ; 265 writel((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG, 266 ®s->micr); 267 while (readl(®s->micr) & MICR_BUSY) 268 ; 269 270 return readl(®s->midr_r) & MIDR_DATA_MASK; 271 } 272 273 static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data) 274 { 275 struct ioc3_private *ip = netdev_priv(dev); 276 struct ioc3_ethregs *regs = ip->regs; 277 278 while (readl(®s->micr) & MICR_BUSY) 279 ; 280 writel(data, ®s->midr_w); 281 writel((phy << MICR_PHYADDR_SHIFT) | reg, ®s->micr); 282 while (readl(®s->micr) & MICR_BUSY) 283 ; 284 } 285 286 static int ioc3_mii_init(struct ioc3_private *ip); 287 288 static struct net_device_stats *ioc3_get_stats(struct net_device *dev) 289 { 290 struct ioc3_private *ip = netdev_priv(dev); 291 struct ioc3_ethregs *regs = ip->regs; 292 293 dev->stats.collisions += readl(®s->etcdc) & ETCDC_COLLCNT_MASK; 294 return &dev->stats; 295 } 296 297 static void ioc3_tcpudp_checksum(struct sk_buff *skb, u32 hwsum, int len) 298 { 299 struct ethhdr *eh = eth_hdr(skb); 300 unsigned int proto; 301 unsigned char *cp; 302 struct iphdr *ih; 303 u32 csum, ehsum; 304 u16 *ew; 305 306 /* Did hardware handle the checksum at all? The cases we can handle 307 * are: 308 * 309 * - TCP and UDP checksums of IPv4 only. 310 * - IPv6 would be doable but we keep that for later ... 311 * - Only unfragmented packets. Did somebody already tell you 312 * fragmentation is evil? 313 * - don't care about packet size. Worst case when processing a 314 * malformed packet we'll try to access the packet at ip header + 315 * 64 bytes which is still inside the skb. Even in the unlikely 316 * case where the checksum is right the higher layers will still 317 * drop the packet as appropriate. 318 */ 319 if (eh->h_proto != htons(ETH_P_IP)) 320 return; 321 322 ih = (struct iphdr *)((char *)eh + ETH_HLEN); 323 if (ip_is_fragment(ih)) 324 return; 325 326 proto = ih->protocol; 327 if (proto != IPPROTO_TCP && proto != IPPROTO_UDP) 328 return; 329 330 /* Same as tx - compute csum of pseudo header */ 331 csum = hwsum + 332 (ih->tot_len - (ih->ihl << 2)) + 333 htons((u16)ih->protocol) + 334 (ih->saddr >> 16) + (ih->saddr & 0xffff) + 335 (ih->daddr >> 16) + (ih->daddr & 0xffff); 336 337 /* Sum up ethernet dest addr, src addr and protocol */ 338 ew = (u16 *)eh; 339 ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6]; 340 341 ehsum = (ehsum & 0xffff) + (ehsum >> 16); 342 ehsum = (ehsum & 0xffff) + (ehsum >> 16); 343 344 csum += 0xffff ^ ehsum; 345 346 /* In the next step we also subtract the 1's complement 347 * checksum of the trailing ethernet CRC. 348 */ 349 cp = (char *)eh + len; /* points at trailing CRC */ 350 if (len & 1) { 351 csum += 0xffff ^ (u16)((cp[1] << 8) | cp[0]); 352 csum += 0xffff ^ (u16)((cp[3] << 8) | cp[2]); 353 } else { 354 csum += 0xffff ^ (u16)((cp[0] << 8) | cp[1]); 355 csum += 0xffff ^ (u16)((cp[2] << 8) | cp[3]); 356 } 357 358 csum = (csum & 0xffff) + (csum >> 16); 359 csum = (csum & 0xffff) + (csum >> 16); 360 361 if (csum == 0xffff) 362 skb->ip_summed = CHECKSUM_UNNECESSARY; 363 } 364 365 static inline void ioc3_rx(struct net_device *dev) 366 { 367 struct ioc3_private *ip = netdev_priv(dev); 368 struct sk_buff *skb, *new_skb; 369 int rx_entry, n_entry, len; 370 struct ioc3_erxbuf *rxb; 371 unsigned long *rxr; 372 dma_addr_t d; 373 u32 w0, err; 374 375 rxr = ip->rxr; /* Ring base */ 376 rx_entry = ip->rx_ci; /* RX consume index */ 377 n_entry = ip->rx_pi; 378 379 skb = ip->rx_skbs[rx_entry]; 380 rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET); 381 w0 = be32_to_cpu(rxb->w0); 382 383 while (w0 & ERXBUF_V) { 384 err = be32_to_cpu(rxb->err); /* It's valid ... */ 385 if (err & ERXBUF_GOODPKT) { 386 len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4; 387 skb_put(skb, len); 388 skb->protocol = eth_type_trans(skb, dev); 389 390 if (ioc3_alloc_skb(ip, &new_skb, &rxb, &d)) { 391 /* Ouch, drop packet and just recycle packet 392 * to keep the ring filled. 393 */ 394 dev->stats.rx_dropped++; 395 new_skb = skb; 396 d = rxr[rx_entry]; 397 goto next; 398 } 399 400 if (likely(dev->features & NETIF_F_RXCSUM)) 401 ioc3_tcpudp_checksum(skb, 402 w0 & ERXBUF_IPCKSUM_MASK, 403 len); 404 405 dma_unmap_single(ip->dma_dev, rxr[rx_entry], 406 RX_BUF_SIZE, DMA_FROM_DEVICE); 407 408 netif_rx(skb); 409 410 ip->rx_skbs[rx_entry] = NULL; /* Poison */ 411 412 dev->stats.rx_packets++; /* Statistics */ 413 dev->stats.rx_bytes += len; 414 } else { 415 /* The frame is invalid and the skb never 416 * reached the network layer so we can just 417 * recycle it. 418 */ 419 new_skb = skb; 420 d = rxr[rx_entry]; 421 dev->stats.rx_errors++; 422 } 423 if (err & ERXBUF_CRCERR) /* Statistics */ 424 dev->stats.rx_crc_errors++; 425 if (err & ERXBUF_FRAMERR) 426 dev->stats.rx_frame_errors++; 427 428 next: 429 ip->rx_skbs[n_entry] = new_skb; 430 rxr[n_entry] = cpu_to_be64(ioc3_map(d, PCI64_ATTR_BAR)); 431 rxb->w0 = 0; /* Clear valid flag */ 432 n_entry = (n_entry + 1) & RX_RING_MASK; /* Update erpir */ 433 434 /* Now go on to the next ring entry. */ 435 rx_entry = (rx_entry + 1) & RX_RING_MASK; 436 skb = ip->rx_skbs[rx_entry]; 437 rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET); 438 w0 = be32_to_cpu(rxb->w0); 439 } 440 writel((n_entry << 3) | ERPIR_ARM, &ip->regs->erpir); 441 ip->rx_pi = n_entry; 442 ip->rx_ci = rx_entry; 443 } 444 445 static inline void ioc3_tx(struct net_device *dev) 446 { 447 struct ioc3_private *ip = netdev_priv(dev); 448 struct ioc3_ethregs *regs = ip->regs; 449 unsigned long packets, bytes; 450 int tx_entry, o_entry; 451 struct sk_buff *skb; 452 u32 etcir; 453 454 spin_lock(&ip->ioc3_lock); 455 etcir = readl(®s->etcir); 456 457 tx_entry = (etcir >> 7) & TX_RING_MASK; 458 o_entry = ip->tx_ci; 459 packets = 0; 460 bytes = 0; 461 462 while (o_entry != tx_entry) { 463 packets++; 464 skb = ip->tx_skbs[o_entry]; 465 bytes += skb->len; 466 dev_consume_skb_irq(skb); 467 ip->tx_skbs[o_entry] = NULL; 468 469 o_entry = (o_entry + 1) & TX_RING_MASK; /* Next */ 470 471 etcir = readl(®s->etcir); /* More pkts sent? */ 472 tx_entry = (etcir >> 7) & TX_RING_MASK; 473 } 474 475 dev->stats.tx_packets += packets; 476 dev->stats.tx_bytes += bytes; 477 ip->txqlen -= packets; 478 479 if (netif_queue_stopped(dev) && ip->txqlen < TX_RING_ENTRIES) 480 netif_wake_queue(dev); 481 482 ip->tx_ci = o_entry; 483 spin_unlock(&ip->ioc3_lock); 484 } 485 486 /* Deal with fatal IOC3 errors. This condition might be caused by a hard or 487 * software problems, so we should try to recover 488 * more gracefully if this ever happens. In theory we might be flooded 489 * with such error interrupts if something really goes wrong, so we might 490 * also consider to take the interface down. 491 */ 492 static void ioc3_error(struct net_device *dev, u32 eisr) 493 { 494 struct ioc3_private *ip = netdev_priv(dev); 495 496 spin_lock(&ip->ioc3_lock); 497 498 if (eisr & EISR_RXOFLO) 499 net_err_ratelimited("%s: RX overflow.\n", dev->name); 500 if (eisr & EISR_RXBUFOFLO) 501 net_err_ratelimited("%s: RX buffer overflow.\n", dev->name); 502 if (eisr & EISR_RXMEMERR) 503 net_err_ratelimited("%s: RX PCI error.\n", dev->name); 504 if (eisr & EISR_RXPARERR) 505 net_err_ratelimited("%s: RX SSRAM parity error.\n", dev->name); 506 if (eisr & EISR_TXBUFUFLO) 507 net_err_ratelimited("%s: TX buffer underflow.\n", dev->name); 508 if (eisr & EISR_TXMEMERR) 509 net_err_ratelimited("%s: TX PCI error.\n", dev->name); 510 511 ioc3_stop(ip); 512 ioc3_free_rx_bufs(ip); 513 ioc3_clean_tx_ring(ip); 514 515 ioc3_init(dev); 516 if (ioc3_alloc_rx_bufs(dev)) { 517 netdev_err(dev, "%s: rx buffer allocation failed\n", __func__); 518 spin_unlock(&ip->ioc3_lock); 519 return; 520 } 521 ioc3_start(ip); 522 ioc3_mii_init(ip); 523 524 netif_wake_queue(dev); 525 526 spin_unlock(&ip->ioc3_lock); 527 } 528 529 /* The interrupt handler does all of the Rx thread work and cleans up 530 * after the Tx thread. 531 */ 532 static irqreturn_t ioc3_interrupt(int irq, void *dev_id) 533 { 534 struct ioc3_private *ip = netdev_priv(dev_id); 535 struct ioc3_ethregs *regs = ip->regs; 536 u32 eisr; 537 538 eisr = readl(®s->eisr); 539 writel(eisr, ®s->eisr); 540 readl(®s->eisr); /* Flush */ 541 542 if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR | 543 EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR)) 544 ioc3_error(dev_id, eisr); 545 if (eisr & EISR_RXTIMERINT) 546 ioc3_rx(dev_id); 547 if (eisr & EISR_TXEXPLICIT) 548 ioc3_tx(dev_id); 549 550 return IRQ_HANDLED; 551 } 552 553 static inline void ioc3_setup_duplex(struct ioc3_private *ip) 554 { 555 struct ioc3_ethregs *regs = ip->regs; 556 557 spin_lock_irq(&ip->ioc3_lock); 558 559 if (ip->mii.full_duplex) { 560 writel(ETCSR_FD, ®s->etcsr); 561 ip->emcr |= EMCR_DUPLEX; 562 } else { 563 writel(ETCSR_HD, ®s->etcsr); 564 ip->emcr &= ~EMCR_DUPLEX; 565 } 566 writel(ip->emcr, ®s->emcr); 567 568 spin_unlock_irq(&ip->ioc3_lock); 569 } 570 571 static void ioc3_timer(struct timer_list *t) 572 { 573 struct ioc3_private *ip = from_timer(ip, t, ioc3_timer); 574 575 /* Print the link status if it has changed */ 576 mii_check_media(&ip->mii, 1, 0); 577 ioc3_setup_duplex(ip); 578 579 ip->ioc3_timer.expires = jiffies + ((12 * HZ) / 10); /* 1.2s */ 580 add_timer(&ip->ioc3_timer); 581 } 582 583 /* Try to find a PHY. There is no apparent relation between the MII addresses 584 * in the SGI documentation and what we find in reality, so we simply probe 585 * for the PHY. It seems IOC3 PHYs usually live on address 31. One of my 586 * onboard IOC3s has the special oddity that probing doesn't seem to find it 587 * yet the interface seems to work fine, so if probing fails we for now will 588 * simply default to PHY 31 instead of bailing out. 589 */ 590 static int ioc3_mii_init(struct ioc3_private *ip) 591 { 592 int ioc3_phy_workaround = 1; 593 int i, found = 0, res = 0; 594 u16 word; 595 596 for (i = 0; i < 32; i++) { 597 word = ioc3_mdio_read(ip->mii.dev, i, MII_PHYSID1); 598 599 if (word != 0xffff && word != 0x0000) { 600 found = 1; 601 break; /* Found a PHY */ 602 } 603 } 604 605 if (!found) { 606 if (ioc3_phy_workaround) { 607 i = 31; 608 } else { 609 ip->mii.phy_id = -1; 610 res = -ENODEV; 611 goto out; 612 } 613 } 614 615 ip->mii.phy_id = i; 616 617 out: 618 return res; 619 } 620 621 static void ioc3_mii_start(struct ioc3_private *ip) 622 { 623 ip->ioc3_timer.expires = jiffies + (12 * HZ) / 10; /* 1.2 sec. */ 624 add_timer(&ip->ioc3_timer); 625 } 626 627 static inline void ioc3_tx_unmap(struct ioc3_private *ip, int entry) 628 { 629 struct ioc3_etxd *desc; 630 u32 cmd, bufcnt, len; 631 632 desc = &ip->txr[entry]; 633 cmd = be32_to_cpu(desc->cmd); 634 bufcnt = be32_to_cpu(desc->bufcnt); 635 if (cmd & ETXD_B1V) { 636 len = (bufcnt & ETXD_B1CNT_MASK) >> ETXD_B1CNT_SHIFT; 637 dma_unmap_single(ip->dma_dev, be64_to_cpu(desc->p1), 638 len, DMA_TO_DEVICE); 639 } 640 if (cmd & ETXD_B2V) { 641 len = (bufcnt & ETXD_B2CNT_MASK) >> ETXD_B2CNT_SHIFT; 642 dma_unmap_single(ip->dma_dev, be64_to_cpu(desc->p2), 643 len, DMA_TO_DEVICE); 644 } 645 } 646 647 static inline void ioc3_clean_tx_ring(struct ioc3_private *ip) 648 { 649 struct sk_buff *skb; 650 int i; 651 652 for (i = 0; i < TX_RING_ENTRIES; i++) { 653 skb = ip->tx_skbs[i]; 654 if (skb) { 655 ioc3_tx_unmap(ip, i); 656 ip->tx_skbs[i] = NULL; 657 dev_kfree_skb_any(skb); 658 } 659 ip->txr[i].cmd = 0; 660 } 661 ip->tx_pi = 0; 662 ip->tx_ci = 0; 663 } 664 665 static void ioc3_free_rx_bufs(struct ioc3_private *ip) 666 { 667 int rx_entry, n_entry; 668 struct sk_buff *skb; 669 670 n_entry = ip->rx_ci; 671 rx_entry = ip->rx_pi; 672 673 while (n_entry != rx_entry) { 674 skb = ip->rx_skbs[n_entry]; 675 if (skb) { 676 dma_unmap_single(ip->dma_dev, 677 be64_to_cpu(ip->rxr[n_entry]), 678 RX_BUF_SIZE, DMA_FROM_DEVICE); 679 dev_kfree_skb_any(skb); 680 } 681 n_entry = (n_entry + 1) & RX_RING_MASK; 682 } 683 } 684 685 static int ioc3_alloc_rx_bufs(struct net_device *dev) 686 { 687 struct ioc3_private *ip = netdev_priv(dev); 688 struct ioc3_erxbuf *rxb; 689 dma_addr_t d; 690 int i; 691 692 /* Now the rx buffers. The RX ring may be larger but 693 * we only allocate 16 buffers for now. Need to tune 694 * this for performance and memory later. 695 */ 696 for (i = 0; i < RX_BUFFS; i++) { 697 if (ioc3_alloc_skb(ip, &ip->rx_skbs[i], &rxb, &d)) 698 return -ENOMEM; 699 700 rxb->w0 = 0; /* Clear valid flag */ 701 ip->rxr[i] = cpu_to_be64(ioc3_map(d, PCI64_ATTR_BAR)); 702 } 703 ip->rx_ci = 0; 704 ip->rx_pi = RX_BUFFS; 705 706 return 0; 707 } 708 709 static inline void ioc3_ssram_disc(struct ioc3_private *ip) 710 { 711 struct ioc3_ethregs *regs = ip->regs; 712 u32 *ssram0 = &ip->ssram[0x0000]; 713 u32 *ssram1 = &ip->ssram[0x4000]; 714 u32 pattern = 0x5555; 715 716 /* Assume the larger size SSRAM and enable parity checking */ 717 writel(readl(®s->emcr) | (EMCR_BUFSIZ | EMCR_RAMPAR), ®s->emcr); 718 readl(®s->emcr); /* Flush */ 719 720 writel(pattern, ssram0); 721 writel(~pattern & IOC3_SSRAM_DM, ssram1); 722 723 if ((readl(ssram0) & IOC3_SSRAM_DM) != pattern || 724 (readl(ssram1) & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) { 725 /* set ssram size to 64 KB */ 726 ip->emcr |= EMCR_RAMPAR; 727 writel(readl(®s->emcr) & ~EMCR_BUFSIZ, ®s->emcr); 728 } else { 729 ip->emcr |= EMCR_BUFSIZ | EMCR_RAMPAR; 730 } 731 } 732 733 static void ioc3_init(struct net_device *dev) 734 { 735 struct ioc3_private *ip = netdev_priv(dev); 736 struct ioc3_ethregs *regs = ip->regs; 737 738 del_timer_sync(&ip->ioc3_timer); /* Kill if running */ 739 740 writel(EMCR_RST, ®s->emcr); /* Reset */ 741 readl(®s->emcr); /* Flush WB */ 742 udelay(4); /* Give it time ... */ 743 writel(0, ®s->emcr); 744 readl(®s->emcr); 745 746 /* Misc registers */ 747 writel(ERBAR_VAL, ®s->erbar); 748 readl(®s->etcdc); /* Clear on read */ 749 writel(15, ®s->ercsr); /* RX low watermark */ 750 writel(0, ®s->ertr); /* Interrupt immediately */ 751 __ioc3_set_mac_address(dev); 752 writel(ip->ehar_h, ®s->ehar_h); 753 writel(ip->ehar_l, ®s->ehar_l); 754 writel(42, ®s->ersr); /* XXX should be random */ 755 } 756 757 static void ioc3_start(struct ioc3_private *ip) 758 { 759 struct ioc3_ethregs *regs = ip->regs; 760 unsigned long ring; 761 762 /* Now the rx ring base, consume & produce registers. */ 763 ring = ioc3_map(ip->rxr_dma, PCI64_ATTR_PREC); 764 writel(ring >> 32, ®s->erbr_h); 765 writel(ring & 0xffffffff, ®s->erbr_l); 766 writel(ip->rx_ci << 3, ®s->ercir); 767 writel((ip->rx_pi << 3) | ERPIR_ARM, ®s->erpir); 768 769 ring = ioc3_map(ip->txr_dma, PCI64_ATTR_PREC); 770 771 ip->txqlen = 0; /* nothing queued */ 772 773 /* Now the tx ring base, consume & produce registers. */ 774 writel(ring >> 32, ®s->etbr_h); 775 writel(ring & 0xffffffff, ®s->etbr_l); 776 writel(ip->tx_pi << 7, ®s->etpir); 777 writel(ip->tx_ci << 7, ®s->etcir); 778 readl(®s->etcir); /* Flush */ 779 780 ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN | 781 EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN; 782 writel(ip->emcr, ®s->emcr); 783 writel(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO | 784 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO | 785 EISR_TXEXPLICIT | EISR_TXMEMERR, ®s->eier); 786 readl(®s->eier); 787 } 788 789 static inline void ioc3_stop(struct ioc3_private *ip) 790 { 791 struct ioc3_ethregs *regs = ip->regs; 792 793 writel(0, ®s->emcr); /* Shutup */ 794 writel(0, ®s->eier); /* Disable interrupts */ 795 readl(®s->eier); /* Flush */ 796 } 797 798 static int ioc3_open(struct net_device *dev) 799 { 800 struct ioc3_private *ip = netdev_priv(dev); 801 802 ip->ehar_h = 0; 803 ip->ehar_l = 0; 804 805 ioc3_init(dev); 806 if (ioc3_alloc_rx_bufs(dev)) { 807 netdev_err(dev, "%s: rx buffer allocation failed\n", __func__); 808 return -ENOMEM; 809 } 810 ioc3_start(ip); 811 ioc3_mii_start(ip); 812 813 netif_start_queue(dev); 814 return 0; 815 } 816 817 static int ioc3_close(struct net_device *dev) 818 { 819 struct ioc3_private *ip = netdev_priv(dev); 820 821 del_timer_sync(&ip->ioc3_timer); 822 823 netif_stop_queue(dev); 824 825 ioc3_stop(ip); 826 free_irq(dev->irq, dev); 827 828 ioc3_free_rx_bufs(ip); 829 ioc3_clean_tx_ring(ip); 830 831 return 0; 832 } 833 834 static const struct net_device_ops ioc3_netdev_ops = { 835 .ndo_open = ioc3_open, 836 .ndo_stop = ioc3_close, 837 .ndo_start_xmit = ioc3_start_xmit, 838 .ndo_tx_timeout = ioc3_timeout, 839 .ndo_get_stats = ioc3_get_stats, 840 .ndo_set_rx_mode = ioc3_set_multicast_list, 841 .ndo_do_ioctl = ioc3_ioctl, 842 .ndo_validate_addr = eth_validate_addr, 843 .ndo_set_mac_address = ioc3_set_mac_address, 844 }; 845 846 static int ioc3eth_probe(struct platform_device *pdev) 847 { 848 u32 sw_physid1, sw_physid2, vendor, model, rev; 849 struct ioc3_private *ip; 850 struct net_device *dev; 851 struct resource *regs; 852 u8 mac_addr[6]; 853 int err; 854 855 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 856 /* get mac addr from one wire prom */ 857 if (ioc3eth_get_mac_addr(regs, mac_addr)) 858 return -EPROBE_DEFER; /* not available yet */ 859 860 dev = alloc_etherdev(sizeof(struct ioc3_private)); 861 if (!dev) 862 return -ENOMEM; 863 864 SET_NETDEV_DEV(dev, &pdev->dev); 865 866 ip = netdev_priv(dev); 867 ip->dma_dev = pdev->dev.parent; 868 ip->regs = devm_platform_ioremap_resource(pdev, 0); 869 if (!ip->regs) { 870 err = -ENOMEM; 871 goto out_free; 872 } 873 874 ip->ssram = devm_platform_ioremap_resource(pdev, 1); 875 if (!ip->ssram) { 876 err = -ENOMEM; 877 goto out_free; 878 } 879 880 dev->irq = platform_get_irq(pdev, 0); 881 if (dev->irq < 0) { 882 err = dev->irq; 883 goto out_free; 884 } 885 886 if (devm_request_irq(&pdev->dev, dev->irq, ioc3_interrupt, 887 IRQF_SHARED, "ioc3-eth", dev)) { 888 dev_err(&pdev->dev, "Can't get irq %d\n", dev->irq); 889 err = -ENODEV; 890 goto out_free; 891 } 892 893 spin_lock_init(&ip->ioc3_lock); 894 timer_setup(&ip->ioc3_timer, ioc3_timer, 0); 895 896 ioc3_stop(ip); 897 898 /* Allocate rx ring. 4kb = 512 entries, must be 4kb aligned */ 899 ip->rxr = dma_alloc_coherent(ip->dma_dev, RX_RING_SIZE, &ip->rxr_dma, 900 GFP_KERNEL); 901 if (!ip->rxr) { 902 pr_err("ioc3-eth: rx ring allocation failed\n"); 903 err = -ENOMEM; 904 goto out_stop; 905 } 906 907 /* Allocate tx rings. 16kb = 128 bufs, must be 16kb aligned */ 908 ip->tx_ring = dma_alloc_coherent(ip->dma_dev, TX_RING_SIZE + SZ_16K - 1, 909 &ip->txr_dma, GFP_KERNEL); 910 if (!ip->tx_ring) { 911 pr_err("ioc3-eth: tx ring allocation failed\n"); 912 err = -ENOMEM; 913 goto out_stop; 914 } 915 /* Align TX ring */ 916 ip->txr = PTR_ALIGN(ip->tx_ring, SZ_16K); 917 ip->txr_dma = ALIGN(ip->txr_dma, SZ_16K); 918 919 ioc3_init(dev); 920 921 ip->mii.phy_id_mask = 0x1f; 922 ip->mii.reg_num_mask = 0x1f; 923 ip->mii.dev = dev; 924 ip->mii.mdio_read = ioc3_mdio_read; 925 ip->mii.mdio_write = ioc3_mdio_write; 926 927 ioc3_mii_init(ip); 928 929 if (ip->mii.phy_id == -1) { 930 netdev_err(dev, "Didn't find a PHY, goodbye.\n"); 931 err = -ENODEV; 932 goto out_stop; 933 } 934 935 ioc3_mii_start(ip); 936 ioc3_ssram_disc(ip); 937 memcpy(dev->dev_addr, mac_addr, ETH_ALEN); 938 939 /* The IOC3-specific entries in the device structure. */ 940 dev->watchdog_timeo = 5 * HZ; 941 dev->netdev_ops = &ioc3_netdev_ops; 942 dev->ethtool_ops = &ioc3_ethtool_ops; 943 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM; 944 dev->features = NETIF_F_IP_CSUM | NETIF_F_HIGHDMA; 945 946 sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1); 947 sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2); 948 949 err = register_netdev(dev); 950 if (err) 951 goto out_stop; 952 953 mii_check_media(&ip->mii, 1, 1); 954 ioc3_setup_duplex(ip); 955 956 vendor = (sw_physid1 << 12) | (sw_physid2 >> 4); 957 model = (sw_physid2 >> 4) & 0x3f; 958 rev = sw_physid2 & 0xf; 959 netdev_info(dev, "Using PHY %d, vendor 0x%x, model %d, rev %d.\n", 960 ip->mii.phy_id, vendor, model, rev); 961 netdev_info(dev, "IOC3 SSRAM has %d kbyte.\n", 962 ip->emcr & EMCR_BUFSIZ ? 128 : 64); 963 964 return 0; 965 966 out_stop: 967 del_timer_sync(&ip->ioc3_timer); 968 if (ip->rxr) 969 dma_free_coherent(ip->dma_dev, RX_RING_SIZE, ip->rxr, 970 ip->rxr_dma); 971 if (ip->tx_ring) 972 dma_free_coherent(ip->dma_dev, TX_RING_SIZE, ip->tx_ring, 973 ip->txr_dma); 974 out_free: 975 free_netdev(dev); 976 return err; 977 } 978 979 static int ioc3eth_remove(struct platform_device *pdev) 980 { 981 struct net_device *dev = platform_get_drvdata(pdev); 982 struct ioc3_private *ip = netdev_priv(dev); 983 984 dma_free_coherent(ip->dma_dev, RX_RING_SIZE, ip->rxr, ip->rxr_dma); 985 dma_free_coherent(ip->dma_dev, TX_RING_SIZE, ip->tx_ring, ip->txr_dma); 986 987 unregister_netdev(dev); 988 del_timer_sync(&ip->ioc3_timer); 989 free_netdev(dev); 990 991 return 0; 992 } 993 994 995 static netdev_tx_t ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev) 996 { 997 struct ioc3_private *ip = netdev_priv(dev); 998 struct ioc3_etxd *desc; 999 unsigned long data; 1000 unsigned int len; 1001 int produce; 1002 u32 w0 = 0; 1003 1004 /* IOC3 has a fairly simple minded checksumming hardware which simply 1005 * adds up the 1's complement checksum for the entire packet and 1006 * inserts it at an offset which can be specified in the descriptor 1007 * into the transmit packet. This means we have to compensate for the 1008 * MAC header which should not be summed and the TCP/UDP pseudo headers 1009 * manually. 1010 */ 1011 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1012 const struct iphdr *ih = ip_hdr(skb); 1013 const int proto = ntohs(ih->protocol); 1014 unsigned int csoff; 1015 u32 csum, ehsum; 1016 u16 *eh; 1017 1018 /* The MAC header. skb->mac seem the logic approach 1019 * to find the MAC header - except it's a NULL pointer ... 1020 */ 1021 eh = (u16 *)skb->data; 1022 1023 /* Sum up dest addr, src addr and protocol */ 1024 ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6]; 1025 1026 /* Skip IP header; it's sum is always zero and was 1027 * already filled in by ip_output.c 1028 */ 1029 csum = csum_tcpudp_nofold(ih->saddr, ih->daddr, 1030 ih->tot_len - (ih->ihl << 2), 1031 proto, csum_fold(ehsum)); 1032 1033 csum = (csum & 0xffff) + (csum >> 16); /* Fold again */ 1034 csum = (csum & 0xffff) + (csum >> 16); 1035 1036 csoff = ETH_HLEN + (ih->ihl << 2); 1037 if (proto == IPPROTO_UDP) { 1038 csoff += offsetof(struct udphdr, check); 1039 udp_hdr(skb)->check = csum; 1040 } 1041 if (proto == IPPROTO_TCP) { 1042 csoff += offsetof(struct tcphdr, check); 1043 tcp_hdr(skb)->check = csum; 1044 } 1045 1046 w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT); 1047 } 1048 1049 spin_lock_irq(&ip->ioc3_lock); 1050 1051 data = (unsigned long)skb->data; 1052 len = skb->len; 1053 1054 produce = ip->tx_pi; 1055 desc = &ip->txr[produce]; 1056 1057 if (len <= 104) { 1058 /* Short packet, let's copy it directly into the ring. */ 1059 skb_copy_from_linear_data(skb, desc->data, skb->len); 1060 if (len < ETH_ZLEN) { 1061 /* Very short packet, pad with zeros at the end. */ 1062 memset(desc->data + len, 0, ETH_ZLEN - len); 1063 len = ETH_ZLEN; 1064 } 1065 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0); 1066 desc->bufcnt = cpu_to_be32(len); 1067 } else if ((data ^ (data + len - 1)) & 0x4000) { 1068 unsigned long b2 = (data | 0x3fffUL) + 1UL; 1069 unsigned long s1 = b2 - data; 1070 unsigned long s2 = data + len - b2; 1071 dma_addr_t d1, d2; 1072 1073 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | 1074 ETXD_B1V | ETXD_B2V | w0); 1075 desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) | 1076 (s2 << ETXD_B2CNT_SHIFT)); 1077 d1 = dma_map_single(ip->dma_dev, skb->data, s1, DMA_TO_DEVICE); 1078 if (dma_mapping_error(ip->dma_dev, d1)) 1079 goto drop_packet; 1080 d2 = dma_map_single(ip->dma_dev, (void *)b2, s1, DMA_TO_DEVICE); 1081 if (dma_mapping_error(ip->dma_dev, d2)) { 1082 dma_unmap_single(ip->dma_dev, d1, len, DMA_TO_DEVICE); 1083 goto drop_packet; 1084 } 1085 desc->p1 = cpu_to_be64(ioc3_map(d1, PCI64_ATTR_PREF)); 1086 desc->p2 = cpu_to_be64(ioc3_map(d2, PCI64_ATTR_PREF)); 1087 } else { 1088 dma_addr_t d; 1089 1090 /* Normal sized packet that doesn't cross a page boundary. */ 1091 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0); 1092 desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT); 1093 d = dma_map_single(ip->dma_dev, skb->data, len, DMA_TO_DEVICE); 1094 if (dma_mapping_error(ip->dma_dev, d)) 1095 goto drop_packet; 1096 desc->p1 = cpu_to_be64(ioc3_map(d, PCI64_ATTR_PREF)); 1097 } 1098 1099 mb(); /* make sure all descriptor changes are visible */ 1100 1101 ip->tx_skbs[produce] = skb; /* Remember skb */ 1102 produce = (produce + 1) & TX_RING_MASK; 1103 ip->tx_pi = produce; 1104 writel(produce << 7, &ip->regs->etpir); /* Fire ... */ 1105 1106 ip->txqlen++; 1107 1108 if (ip->txqlen >= (TX_RING_ENTRIES - 1)) 1109 netif_stop_queue(dev); 1110 1111 spin_unlock_irq(&ip->ioc3_lock); 1112 1113 return NETDEV_TX_OK; 1114 1115 drop_packet: 1116 dev_kfree_skb_any(skb); 1117 dev->stats.tx_dropped++; 1118 1119 spin_unlock_irq(&ip->ioc3_lock); 1120 1121 return NETDEV_TX_OK; 1122 } 1123 1124 static void ioc3_timeout(struct net_device *dev, unsigned int txqueue) 1125 { 1126 struct ioc3_private *ip = netdev_priv(dev); 1127 1128 netdev_err(dev, "transmit timed out, resetting\n"); 1129 1130 spin_lock_irq(&ip->ioc3_lock); 1131 1132 ioc3_stop(ip); 1133 ioc3_free_rx_bufs(ip); 1134 ioc3_clean_tx_ring(ip); 1135 1136 ioc3_init(dev); 1137 if (ioc3_alloc_rx_bufs(dev)) { 1138 netdev_err(dev, "%s: rx buffer allocation failed\n", __func__); 1139 spin_unlock_irq(&ip->ioc3_lock); 1140 return; 1141 } 1142 ioc3_start(ip); 1143 ioc3_mii_init(ip); 1144 ioc3_mii_start(ip); 1145 1146 spin_unlock_irq(&ip->ioc3_lock); 1147 1148 netif_wake_queue(dev); 1149 } 1150 1151 /* Given a multicast ethernet address, this routine calculates the 1152 * address's bit index in the logical address filter mask 1153 */ 1154 static inline unsigned int ioc3_hash(const unsigned char *addr) 1155 { 1156 unsigned int temp = 0; 1157 int bits; 1158 u32 crc; 1159 1160 crc = ether_crc_le(ETH_ALEN, addr); 1161 1162 crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */ 1163 for (bits = 6; --bits >= 0; ) { 1164 temp <<= 1; 1165 temp |= (crc & 0x1); 1166 crc >>= 1; 1167 } 1168 1169 return temp; 1170 } 1171 1172 static void ioc3_get_drvinfo(struct net_device *dev, 1173 struct ethtool_drvinfo *info) 1174 { 1175 strlcpy(info->driver, IOC3_NAME, sizeof(info->driver)); 1176 strlcpy(info->version, IOC3_VERSION, sizeof(info->version)); 1177 strlcpy(info->bus_info, pci_name(to_pci_dev(dev->dev.parent)), 1178 sizeof(info->bus_info)); 1179 } 1180 1181 static int ioc3_get_link_ksettings(struct net_device *dev, 1182 struct ethtool_link_ksettings *cmd) 1183 { 1184 struct ioc3_private *ip = netdev_priv(dev); 1185 1186 spin_lock_irq(&ip->ioc3_lock); 1187 mii_ethtool_get_link_ksettings(&ip->mii, cmd); 1188 spin_unlock_irq(&ip->ioc3_lock); 1189 1190 return 0; 1191 } 1192 1193 static int ioc3_set_link_ksettings(struct net_device *dev, 1194 const struct ethtool_link_ksettings *cmd) 1195 { 1196 struct ioc3_private *ip = netdev_priv(dev); 1197 int rc; 1198 1199 spin_lock_irq(&ip->ioc3_lock); 1200 rc = mii_ethtool_set_link_ksettings(&ip->mii, cmd); 1201 spin_unlock_irq(&ip->ioc3_lock); 1202 1203 return rc; 1204 } 1205 1206 static int ioc3_nway_reset(struct net_device *dev) 1207 { 1208 struct ioc3_private *ip = netdev_priv(dev); 1209 int rc; 1210 1211 spin_lock_irq(&ip->ioc3_lock); 1212 rc = mii_nway_restart(&ip->mii); 1213 spin_unlock_irq(&ip->ioc3_lock); 1214 1215 return rc; 1216 } 1217 1218 static u32 ioc3_get_link(struct net_device *dev) 1219 { 1220 struct ioc3_private *ip = netdev_priv(dev); 1221 int rc; 1222 1223 spin_lock_irq(&ip->ioc3_lock); 1224 rc = mii_link_ok(&ip->mii); 1225 spin_unlock_irq(&ip->ioc3_lock); 1226 1227 return rc; 1228 } 1229 1230 static const struct ethtool_ops ioc3_ethtool_ops = { 1231 .get_drvinfo = ioc3_get_drvinfo, 1232 .nway_reset = ioc3_nway_reset, 1233 .get_link = ioc3_get_link, 1234 .get_link_ksettings = ioc3_get_link_ksettings, 1235 .set_link_ksettings = ioc3_set_link_ksettings, 1236 }; 1237 1238 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1239 { 1240 struct ioc3_private *ip = netdev_priv(dev); 1241 int rc; 1242 1243 spin_lock_irq(&ip->ioc3_lock); 1244 rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL); 1245 spin_unlock_irq(&ip->ioc3_lock); 1246 1247 return rc; 1248 } 1249 1250 static void ioc3_set_multicast_list(struct net_device *dev) 1251 { 1252 struct ioc3_private *ip = netdev_priv(dev); 1253 struct ioc3_ethregs *regs = ip->regs; 1254 struct netdev_hw_addr *ha; 1255 u64 ehar = 0; 1256 1257 spin_lock_irq(&ip->ioc3_lock); 1258 1259 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ 1260 ip->emcr |= EMCR_PROMISC; 1261 writel(ip->emcr, ®s->emcr); 1262 readl(®s->emcr); 1263 } else { 1264 ip->emcr &= ~EMCR_PROMISC; 1265 writel(ip->emcr, ®s->emcr); /* Clear promiscuous. */ 1266 readl(®s->emcr); 1267 1268 if ((dev->flags & IFF_ALLMULTI) || 1269 (netdev_mc_count(dev) > 64)) { 1270 /* Too many for hashing to make sense or we want all 1271 * multicast packets anyway, so skip computing all the 1272 * hashes and just accept all packets. 1273 */ 1274 ip->ehar_h = 0xffffffff; 1275 ip->ehar_l = 0xffffffff; 1276 } else { 1277 netdev_for_each_mc_addr(ha, dev) { 1278 ehar |= (1UL << ioc3_hash(ha->addr)); 1279 } 1280 ip->ehar_h = ehar >> 32; 1281 ip->ehar_l = ehar & 0xffffffff; 1282 } 1283 writel(ip->ehar_h, ®s->ehar_h); 1284 writel(ip->ehar_l, ®s->ehar_l); 1285 } 1286 1287 spin_unlock_irq(&ip->ioc3_lock); 1288 } 1289 1290 static struct platform_driver ioc3eth_driver = { 1291 .probe = ioc3eth_probe, 1292 .remove = ioc3eth_remove, 1293 .driver = { 1294 .name = "ioc3-eth", 1295 } 1296 }; 1297 1298 module_platform_driver(ioc3eth_driver); 1299 1300 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); 1301 MODULE_DESCRIPTION("SGI IOC3 Ethernet driver"); 1302 MODULE_LICENSE("GPL"); 1303