1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2018 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include "net_driver.h" 12 #include "efx.h" 13 #include "nic_common.h" 14 #include "tx_common.h" 15 16 static unsigned int efx_tx_cb_page_count(struct efx_tx_queue *tx_queue) 17 { 18 return DIV_ROUND_UP(tx_queue->ptr_mask + 1, 19 PAGE_SIZE >> EFX_TX_CB_ORDER); 20 } 21 22 int efx_probe_tx_queue(struct efx_tx_queue *tx_queue) 23 { 24 struct efx_nic *efx = tx_queue->efx; 25 unsigned int entries; 26 int rc; 27 28 /* Create the smallest power-of-two aligned ring */ 29 entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE); 30 EFX_WARN_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE); 31 tx_queue->ptr_mask = entries - 1; 32 33 netif_dbg(efx, probe, efx->net_dev, 34 "creating TX queue %d size %#x mask %#x\n", 35 tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask); 36 37 /* Allocate software ring */ 38 tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer), 39 GFP_KERNEL); 40 if (!tx_queue->buffer) 41 return -ENOMEM; 42 43 tx_queue->cb_page = kcalloc(efx_tx_cb_page_count(tx_queue), 44 sizeof(tx_queue->cb_page[0]), GFP_KERNEL); 45 if (!tx_queue->cb_page) { 46 rc = -ENOMEM; 47 goto fail1; 48 } 49 50 /* Allocate hardware ring, determine TXQ type */ 51 rc = efx_nic_probe_tx(tx_queue); 52 if (rc) 53 goto fail2; 54 55 tx_queue->channel->tx_queue_by_type[tx_queue->type] = tx_queue; 56 return 0; 57 58 fail2: 59 kfree(tx_queue->cb_page); 60 tx_queue->cb_page = NULL; 61 fail1: 62 kfree(tx_queue->buffer); 63 tx_queue->buffer = NULL; 64 return rc; 65 } 66 67 void efx_init_tx_queue(struct efx_tx_queue *tx_queue) 68 { 69 struct efx_nic *efx = tx_queue->efx; 70 71 netif_dbg(efx, drv, efx->net_dev, 72 "initialising TX queue %d\n", tx_queue->queue); 73 74 tx_queue->insert_count = 0; 75 tx_queue->notify_count = 0; 76 tx_queue->write_count = 0; 77 tx_queue->packet_write_count = 0; 78 tx_queue->old_write_count = 0; 79 tx_queue->read_count = 0; 80 tx_queue->old_read_count = 0; 81 tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID; 82 tx_queue->xmit_pending = false; 83 tx_queue->timestamping = (efx_ptp_use_mac_tx_timestamps(efx) && 84 tx_queue->channel == efx_ptp_channel(efx)); 85 tx_queue->completed_timestamp_major = 0; 86 tx_queue->completed_timestamp_minor = 0; 87 88 tx_queue->xdp_tx = efx_channel_is_xdp_tx(tx_queue->channel); 89 tx_queue->tso_version = 0; 90 91 /* Set up TX descriptor ring */ 92 efx_nic_init_tx(tx_queue); 93 94 tx_queue->initialised = true; 95 } 96 97 void efx_fini_tx_queue(struct efx_tx_queue *tx_queue) 98 { 99 struct efx_tx_buffer *buffer; 100 101 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, 102 "shutting down TX queue %d\n", tx_queue->queue); 103 104 tx_queue->initialised = false; 105 106 if (!tx_queue->buffer) 107 return; 108 109 /* Free any buffers left in the ring */ 110 while (tx_queue->read_count != tx_queue->write_count) { 111 unsigned int pkts_compl = 0, bytes_compl = 0; 112 113 buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask]; 114 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl); 115 116 ++tx_queue->read_count; 117 } 118 tx_queue->xmit_pending = false; 119 netdev_tx_reset_queue(tx_queue->core_txq); 120 } 121 122 void efx_remove_tx_queue(struct efx_tx_queue *tx_queue) 123 { 124 int i; 125 126 if (!tx_queue->buffer) 127 return; 128 129 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, 130 "destroying TX queue %d\n", tx_queue->queue); 131 efx_nic_remove_tx(tx_queue); 132 133 if (tx_queue->cb_page) { 134 for (i = 0; i < efx_tx_cb_page_count(tx_queue); i++) 135 efx_nic_free_buffer(tx_queue->efx, 136 &tx_queue->cb_page[i]); 137 kfree(tx_queue->cb_page); 138 tx_queue->cb_page = NULL; 139 } 140 141 kfree(tx_queue->buffer); 142 tx_queue->buffer = NULL; 143 tx_queue->channel->tx_queue_by_type[tx_queue->type] = NULL; 144 } 145 146 void efx_dequeue_buffer(struct efx_tx_queue *tx_queue, 147 struct efx_tx_buffer *buffer, 148 unsigned int *pkts_compl, 149 unsigned int *bytes_compl) 150 { 151 if (buffer->unmap_len) { 152 struct device *dma_dev = &tx_queue->efx->pci_dev->dev; 153 dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset; 154 155 if (buffer->flags & EFX_TX_BUF_MAP_SINGLE) 156 dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len, 157 DMA_TO_DEVICE); 158 else 159 dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len, 160 DMA_TO_DEVICE); 161 buffer->unmap_len = 0; 162 } 163 164 if (buffer->flags & EFX_TX_BUF_SKB) { 165 struct sk_buff *skb = (struct sk_buff *)buffer->skb; 166 167 EFX_WARN_ON_PARANOID(!pkts_compl || !bytes_compl); 168 (*pkts_compl)++; 169 (*bytes_compl) += skb->len; 170 if (tx_queue->timestamping && 171 (tx_queue->completed_timestamp_major || 172 tx_queue->completed_timestamp_minor)) { 173 struct skb_shared_hwtstamps hwtstamp; 174 175 hwtstamp.hwtstamp = 176 efx_ptp_nic_to_kernel_time(tx_queue); 177 skb_tstamp_tx(skb, &hwtstamp); 178 179 tx_queue->completed_timestamp_major = 0; 180 tx_queue->completed_timestamp_minor = 0; 181 } 182 dev_consume_skb_any((struct sk_buff *)buffer->skb); 183 netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev, 184 "TX queue %d transmission id %x complete\n", 185 tx_queue->queue, tx_queue->read_count); 186 } else if (buffer->flags & EFX_TX_BUF_XDP) { 187 xdp_return_frame_rx_napi(buffer->xdpf); 188 } 189 190 buffer->len = 0; 191 buffer->flags = 0; 192 } 193 194 /* Remove packets from the TX queue 195 * 196 * This removes packets from the TX queue, up to and including the 197 * specified index. 198 */ 199 static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue, 200 unsigned int index, 201 unsigned int *pkts_compl, 202 unsigned int *bytes_compl) 203 { 204 struct efx_nic *efx = tx_queue->efx; 205 unsigned int stop_index, read_ptr; 206 207 stop_index = (index + 1) & tx_queue->ptr_mask; 208 read_ptr = tx_queue->read_count & tx_queue->ptr_mask; 209 210 while (read_ptr != stop_index) { 211 struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr]; 212 213 if (!efx_tx_buffer_in_use(buffer)) { 214 netif_err(efx, tx_err, efx->net_dev, 215 "TX queue %d spurious TX completion id %d\n", 216 tx_queue->queue, read_ptr); 217 efx_schedule_reset(efx, RESET_TYPE_TX_SKIP); 218 return; 219 } 220 221 efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl); 222 223 ++tx_queue->read_count; 224 read_ptr = tx_queue->read_count & tx_queue->ptr_mask; 225 } 226 } 227 228 void efx_xmit_done_check_empty(struct efx_tx_queue *tx_queue) 229 { 230 if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) { 231 tx_queue->old_write_count = READ_ONCE(tx_queue->write_count); 232 if (tx_queue->read_count == tx_queue->old_write_count) { 233 /* Ensure that read_count is flushed. */ 234 smp_mb(); 235 tx_queue->empty_read_count = 236 tx_queue->read_count | EFX_EMPTY_COUNT_VALID; 237 } 238 } 239 } 240 241 void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index) 242 { 243 unsigned int fill_level, pkts_compl = 0, bytes_compl = 0; 244 struct efx_nic *efx = tx_queue->efx; 245 246 EFX_WARN_ON_ONCE_PARANOID(index > tx_queue->ptr_mask); 247 248 efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl); 249 tx_queue->pkts_compl += pkts_compl; 250 tx_queue->bytes_compl += bytes_compl; 251 252 if (pkts_compl > 1) 253 ++tx_queue->merge_events; 254 255 /* See if we need to restart the netif queue. This memory 256 * barrier ensures that we write read_count (inside 257 * efx_dequeue_buffers()) before reading the queue status. 258 */ 259 smp_mb(); 260 if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) && 261 likely(efx->port_enabled) && 262 likely(netif_device_present(efx->net_dev))) { 263 fill_level = efx_channel_tx_fill_level(tx_queue->channel); 264 if (fill_level <= efx->txq_wake_thresh) 265 netif_tx_wake_queue(tx_queue->core_txq); 266 } 267 268 efx_xmit_done_check_empty(tx_queue); 269 } 270 271 /* Remove buffers put into a tx_queue for the current packet. 272 * None of the buffers must have an skb attached. 273 */ 274 void efx_enqueue_unwind(struct efx_tx_queue *tx_queue, 275 unsigned int insert_count) 276 { 277 struct efx_tx_buffer *buffer; 278 unsigned int bytes_compl = 0; 279 unsigned int pkts_compl = 0; 280 281 /* Work backwards until we hit the original insert pointer value */ 282 while (tx_queue->insert_count != insert_count) { 283 --tx_queue->insert_count; 284 buffer = __efx_tx_queue_get_insert_buffer(tx_queue); 285 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl); 286 } 287 } 288 289 struct efx_tx_buffer *efx_tx_map_chunk(struct efx_tx_queue *tx_queue, 290 dma_addr_t dma_addr, size_t len) 291 { 292 const struct efx_nic_type *nic_type = tx_queue->efx->type; 293 struct efx_tx_buffer *buffer; 294 unsigned int dma_len; 295 296 /* Map the fragment taking account of NIC-dependent DMA limits. */ 297 do { 298 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 299 300 if (nic_type->tx_limit_len) 301 dma_len = nic_type->tx_limit_len(tx_queue, dma_addr, len); 302 else 303 dma_len = len; 304 305 buffer->len = dma_len; 306 buffer->dma_addr = dma_addr; 307 buffer->flags = EFX_TX_BUF_CONT; 308 len -= dma_len; 309 dma_addr += dma_len; 310 ++tx_queue->insert_count; 311 } while (len); 312 313 return buffer; 314 } 315 316 int efx_tx_tso_header_length(struct sk_buff *skb) 317 { 318 size_t header_len; 319 320 if (skb->encapsulation) 321 header_len = skb_inner_transport_header(skb) - 322 skb->data + 323 (inner_tcp_hdr(skb)->doff << 2u); 324 else 325 header_len = skb_transport_header(skb) - skb->data + 326 (tcp_hdr(skb)->doff << 2u); 327 return header_len; 328 } 329 330 /* Map all data from an SKB for DMA and create descriptors on the queue. */ 331 int efx_tx_map_data(struct efx_tx_queue *tx_queue, struct sk_buff *skb, 332 unsigned int segment_count) 333 { 334 struct efx_nic *efx = tx_queue->efx; 335 struct device *dma_dev = &efx->pci_dev->dev; 336 unsigned int frag_index, nr_frags; 337 dma_addr_t dma_addr, unmap_addr; 338 unsigned short dma_flags; 339 size_t len, unmap_len; 340 341 nr_frags = skb_shinfo(skb)->nr_frags; 342 frag_index = 0; 343 344 /* Map header data. */ 345 len = skb_headlen(skb); 346 dma_addr = dma_map_single(dma_dev, skb->data, len, DMA_TO_DEVICE); 347 dma_flags = EFX_TX_BUF_MAP_SINGLE; 348 unmap_len = len; 349 unmap_addr = dma_addr; 350 351 if (unlikely(dma_mapping_error(dma_dev, dma_addr))) 352 return -EIO; 353 354 if (segment_count) { 355 /* For TSO we need to put the header in to a separate 356 * descriptor. Map this separately if necessary. 357 */ 358 size_t header_len = efx_tx_tso_header_length(skb); 359 360 if (header_len != len) { 361 tx_queue->tso_long_headers++; 362 efx_tx_map_chunk(tx_queue, dma_addr, header_len); 363 len -= header_len; 364 dma_addr += header_len; 365 } 366 } 367 368 /* Add descriptors for each fragment. */ 369 do { 370 struct efx_tx_buffer *buffer; 371 skb_frag_t *fragment; 372 373 buffer = efx_tx_map_chunk(tx_queue, dma_addr, len); 374 375 /* The final descriptor for a fragment is responsible for 376 * unmapping the whole fragment. 377 */ 378 buffer->flags = EFX_TX_BUF_CONT | dma_flags; 379 buffer->unmap_len = unmap_len; 380 buffer->dma_offset = buffer->dma_addr - unmap_addr; 381 382 if (frag_index >= nr_frags) { 383 /* Store SKB details with the final buffer for 384 * the completion. 385 */ 386 buffer->skb = skb; 387 buffer->flags = EFX_TX_BUF_SKB | dma_flags; 388 return 0; 389 } 390 391 /* Move on to the next fragment. */ 392 fragment = &skb_shinfo(skb)->frags[frag_index++]; 393 len = skb_frag_size(fragment); 394 dma_addr = skb_frag_dma_map(dma_dev, fragment, 0, len, 395 DMA_TO_DEVICE); 396 dma_flags = 0; 397 unmap_len = len; 398 unmap_addr = dma_addr; 399 400 if (unlikely(dma_mapping_error(dma_dev, dma_addr))) 401 return -EIO; 402 } while (1); 403 } 404 405 unsigned int efx_tx_max_skb_descs(struct efx_nic *efx) 406 { 407 /* Header and payload descriptor for each output segment, plus 408 * one for every input fragment boundary within a segment 409 */ 410 unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS; 411 412 /* Possibly one more per segment for option descriptors */ 413 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) 414 max_descs += EFX_TSO_MAX_SEGS; 415 416 /* Possibly more for PCIe page boundaries within input fragments */ 417 if (PAGE_SIZE > EFX_PAGE_SIZE) 418 max_descs += max_t(unsigned int, MAX_SKB_FRAGS, 419 DIV_ROUND_UP(GSO_MAX_SIZE, EFX_PAGE_SIZE)); 420 421 return max_descs; 422 } 423 424 /* 425 * Fallback to software TSO. 426 * 427 * This is used if we are unable to send a GSO packet through hardware TSO. 428 * This should only ever happen due to per-queue restrictions - unsupported 429 * packets should first be filtered by the feature flags. 430 * 431 * Returns 0 on success, error code otherwise. 432 */ 433 int efx_tx_tso_fallback(struct efx_tx_queue *tx_queue, struct sk_buff *skb) 434 { 435 struct sk_buff *segments, *next; 436 437 segments = skb_gso_segment(skb, 0); 438 if (IS_ERR(segments)) 439 return PTR_ERR(segments); 440 441 dev_consume_skb_any(skb); 442 443 skb_list_walk_safe(segments, skb, next) { 444 skb_mark_not_on_list(skb); 445 efx_enqueue_skb(tx_queue, skb); 446 } 447 448 return 0; 449 } 450