1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/tcp.h> 13 #include <linux/ip.h> 14 #include <linux/in.h> 15 #include <linux/ipv6.h> 16 #include <linux/slab.h> 17 #include <net/ipv6.h> 18 #include <linux/if_ether.h> 19 #include <linux/highmem.h> 20 #include <linux/cache.h> 21 #include "net_driver.h" 22 #include "efx.h" 23 #include "io.h" 24 #include "nic.h" 25 #include "workarounds.h" 26 #include "ef10_regs.h" 27 28 #ifdef EFX_USE_PIO 29 30 #define EFX_PIOBUF_SIZE_MAX ER_DZ_TX_PIOBUF_SIZE 31 #define EFX_PIOBUF_SIZE_DEF ALIGN(256, L1_CACHE_BYTES) 32 unsigned int efx_piobuf_size __read_mostly = EFX_PIOBUF_SIZE_DEF; 33 34 #endif /* EFX_USE_PIO */ 35 36 static inline unsigned int 37 efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue) 38 { 39 return tx_queue->insert_count & tx_queue->ptr_mask; 40 } 41 42 static inline struct efx_tx_buffer * 43 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue) 44 { 45 return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)]; 46 } 47 48 static inline struct efx_tx_buffer * 49 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue) 50 { 51 struct efx_tx_buffer *buffer = 52 __efx_tx_queue_get_insert_buffer(tx_queue); 53 54 EFX_BUG_ON_PARANOID(buffer->len); 55 EFX_BUG_ON_PARANOID(buffer->flags); 56 EFX_BUG_ON_PARANOID(buffer->unmap_len); 57 58 return buffer; 59 } 60 61 static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue, 62 struct efx_tx_buffer *buffer, 63 unsigned int *pkts_compl, 64 unsigned int *bytes_compl) 65 { 66 if (buffer->unmap_len) { 67 struct device *dma_dev = &tx_queue->efx->pci_dev->dev; 68 dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset; 69 if (buffer->flags & EFX_TX_BUF_MAP_SINGLE) 70 dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len, 71 DMA_TO_DEVICE); 72 else 73 dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len, 74 DMA_TO_DEVICE); 75 buffer->unmap_len = 0; 76 } 77 78 if (buffer->flags & EFX_TX_BUF_SKB) { 79 (*pkts_compl)++; 80 (*bytes_compl) += buffer->skb->len; 81 dev_consume_skb_any((struct sk_buff *)buffer->skb); 82 netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev, 83 "TX queue %d transmission id %x complete\n", 84 tx_queue->queue, tx_queue->read_count); 85 } else if (buffer->flags & EFX_TX_BUF_HEAP) { 86 kfree(buffer->heap_buf); 87 } 88 89 buffer->len = 0; 90 buffer->flags = 0; 91 } 92 93 static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, 94 struct sk_buff *skb); 95 96 static inline unsigned 97 efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr) 98 { 99 /* Depending on the NIC revision, we can use descriptor 100 * lengths up to 8K or 8K-1. However, since PCI Express 101 * devices must split read requests at 4K boundaries, there is 102 * little benefit from using descriptors that cross those 103 * boundaries and we keep things simple by not doing so. 104 */ 105 unsigned len = (~dma_addr & (EFX_PAGE_SIZE - 1)) + 1; 106 107 /* Work around hardware bug for unaligned buffers. */ 108 if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf)) 109 len = min_t(unsigned, len, 512 - (dma_addr & 0xf)); 110 111 return len; 112 } 113 114 unsigned int efx_tx_max_skb_descs(struct efx_nic *efx) 115 { 116 /* Header and payload descriptor for each output segment, plus 117 * one for every input fragment boundary within a segment 118 */ 119 unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS; 120 121 /* Possibly one more per segment for the alignment workaround, 122 * or for option descriptors 123 */ 124 if (EFX_WORKAROUND_5391(efx) || efx_nic_rev(efx) >= EFX_REV_HUNT_A0) 125 max_descs += EFX_TSO_MAX_SEGS; 126 127 /* Possibly more for PCIe page boundaries within input fragments */ 128 if (PAGE_SIZE > EFX_PAGE_SIZE) 129 max_descs += max_t(unsigned int, MAX_SKB_FRAGS, 130 DIV_ROUND_UP(GSO_MAX_SIZE, EFX_PAGE_SIZE)); 131 132 return max_descs; 133 } 134 135 static void efx_tx_maybe_stop_queue(struct efx_tx_queue *txq1) 136 { 137 /* We need to consider both queues that the net core sees as one */ 138 struct efx_tx_queue *txq2 = efx_tx_queue_partner(txq1); 139 struct efx_nic *efx = txq1->efx; 140 unsigned int fill_level; 141 142 fill_level = max(txq1->insert_count - txq1->old_read_count, 143 txq2->insert_count - txq2->old_read_count); 144 if (likely(fill_level < efx->txq_stop_thresh)) 145 return; 146 147 /* We used the stale old_read_count above, which gives us a 148 * pessimistic estimate of the fill level (which may even 149 * validly be >= efx->txq_entries). Now try again using 150 * read_count (more likely to be a cache miss). 151 * 152 * If we read read_count and then conditionally stop the 153 * queue, it is possible for the completion path to race with 154 * us and complete all outstanding descriptors in the middle, 155 * after which there will be no more completions to wake it. 156 * Therefore we stop the queue first, then read read_count 157 * (with a memory barrier to ensure the ordering), then 158 * restart the queue if the fill level turns out to be low 159 * enough. 160 */ 161 netif_tx_stop_queue(txq1->core_txq); 162 smp_mb(); 163 txq1->old_read_count = ACCESS_ONCE(txq1->read_count); 164 txq2->old_read_count = ACCESS_ONCE(txq2->read_count); 165 166 fill_level = max(txq1->insert_count - txq1->old_read_count, 167 txq2->insert_count - txq2->old_read_count); 168 EFX_BUG_ON_PARANOID(fill_level >= efx->txq_entries); 169 if (likely(fill_level < efx->txq_stop_thresh)) { 170 smp_mb(); 171 if (likely(!efx->loopback_selftest)) 172 netif_tx_start_queue(txq1->core_txq); 173 } 174 } 175 176 #ifdef EFX_USE_PIO 177 178 struct efx_short_copy_buffer { 179 int used; 180 u8 buf[L1_CACHE_BYTES]; 181 }; 182 183 /* Copy to PIO, respecting that writes to PIO buffers must be dword aligned. 184 * Advances piobuf pointer. Leaves additional data in the copy buffer. 185 */ 186 static void efx_memcpy_toio_aligned(struct efx_nic *efx, u8 __iomem **piobuf, 187 u8 *data, int len, 188 struct efx_short_copy_buffer *copy_buf) 189 { 190 int block_len = len & ~(sizeof(copy_buf->buf) - 1); 191 192 __iowrite64_copy(*piobuf, data, block_len >> 3); 193 *piobuf += block_len; 194 len -= block_len; 195 196 if (len) { 197 data += block_len; 198 BUG_ON(copy_buf->used); 199 BUG_ON(len > sizeof(copy_buf->buf)); 200 memcpy(copy_buf->buf, data, len); 201 copy_buf->used = len; 202 } 203 } 204 205 /* Copy to PIO, respecting dword alignment, popping data from copy buffer first. 206 * Advances piobuf pointer. Leaves additional data in the copy buffer. 207 */ 208 static void efx_memcpy_toio_aligned_cb(struct efx_nic *efx, u8 __iomem **piobuf, 209 u8 *data, int len, 210 struct efx_short_copy_buffer *copy_buf) 211 { 212 if (copy_buf->used) { 213 /* if the copy buffer is partially full, fill it up and write */ 214 int copy_to_buf = 215 min_t(int, sizeof(copy_buf->buf) - copy_buf->used, len); 216 217 memcpy(copy_buf->buf + copy_buf->used, data, copy_to_buf); 218 copy_buf->used += copy_to_buf; 219 220 /* if we didn't fill it up then we're done for now */ 221 if (copy_buf->used < sizeof(copy_buf->buf)) 222 return; 223 224 __iowrite64_copy(*piobuf, copy_buf->buf, 225 sizeof(copy_buf->buf) >> 3); 226 *piobuf += sizeof(copy_buf->buf); 227 data += copy_to_buf; 228 len -= copy_to_buf; 229 copy_buf->used = 0; 230 } 231 232 efx_memcpy_toio_aligned(efx, piobuf, data, len, copy_buf); 233 } 234 235 static void efx_flush_copy_buffer(struct efx_nic *efx, u8 __iomem *piobuf, 236 struct efx_short_copy_buffer *copy_buf) 237 { 238 /* if there's anything in it, write the whole buffer, including junk */ 239 if (copy_buf->used) 240 __iowrite64_copy(piobuf, copy_buf->buf, 241 sizeof(copy_buf->buf) >> 3); 242 } 243 244 /* Traverse skb structure and copy fragments in to PIO buffer. 245 * Advances piobuf pointer. 246 */ 247 static void efx_skb_copy_bits_to_pio(struct efx_nic *efx, struct sk_buff *skb, 248 u8 __iomem **piobuf, 249 struct efx_short_copy_buffer *copy_buf) 250 { 251 int i; 252 253 efx_memcpy_toio_aligned(efx, piobuf, skb->data, skb_headlen(skb), 254 copy_buf); 255 256 for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) { 257 skb_frag_t *f = &skb_shinfo(skb)->frags[i]; 258 u8 *vaddr; 259 260 vaddr = kmap_atomic(skb_frag_page(f)); 261 262 efx_memcpy_toio_aligned_cb(efx, piobuf, vaddr + f->page_offset, 263 skb_frag_size(f), copy_buf); 264 kunmap_atomic(vaddr); 265 } 266 267 EFX_BUG_ON_PARANOID(skb_shinfo(skb)->frag_list); 268 } 269 270 static struct efx_tx_buffer * 271 efx_enqueue_skb_pio(struct efx_tx_queue *tx_queue, struct sk_buff *skb) 272 { 273 struct efx_tx_buffer *buffer = 274 efx_tx_queue_get_insert_buffer(tx_queue); 275 u8 __iomem *piobuf = tx_queue->piobuf; 276 277 /* Copy to PIO buffer. Ensure the writes are padded to the end 278 * of a cache line, as this is required for write-combining to be 279 * effective on at least x86. 280 */ 281 282 if (skb_shinfo(skb)->nr_frags) { 283 /* The size of the copy buffer will ensure all writes 284 * are the size of a cache line. 285 */ 286 struct efx_short_copy_buffer copy_buf; 287 288 copy_buf.used = 0; 289 290 efx_skb_copy_bits_to_pio(tx_queue->efx, skb, 291 &piobuf, ©_buf); 292 efx_flush_copy_buffer(tx_queue->efx, piobuf, ©_buf); 293 } else { 294 /* Pad the write to the size of a cache line. 295 * We can do this because we know the skb_shared_info sruct is 296 * after the source, and the destination buffer is big enough. 297 */ 298 BUILD_BUG_ON(L1_CACHE_BYTES > 299 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); 300 __iowrite64_copy(tx_queue->piobuf, skb->data, 301 ALIGN(skb->len, L1_CACHE_BYTES) >> 3); 302 } 303 304 EFX_POPULATE_QWORD_5(buffer->option, 305 ESF_DZ_TX_DESC_IS_OPT, 1, 306 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_PIO, 307 ESF_DZ_TX_PIO_CONT, 0, 308 ESF_DZ_TX_PIO_BYTE_CNT, skb->len, 309 ESF_DZ_TX_PIO_BUF_ADDR, 310 tx_queue->piobuf_offset); 311 ++tx_queue->pio_packets; 312 ++tx_queue->insert_count; 313 return buffer; 314 } 315 #endif /* EFX_USE_PIO */ 316 317 /* 318 * Add a socket buffer to a TX queue 319 * 320 * This maps all fragments of a socket buffer for DMA and adds them to 321 * the TX queue. The queue's insert pointer will be incremented by 322 * the number of fragments in the socket buffer. 323 * 324 * If any DMA mapping fails, any mapped fragments will be unmapped, 325 * the queue's insert pointer will be restored to its original value. 326 * 327 * This function is split out from efx_hard_start_xmit to allow the 328 * loopback test to direct packets via specific TX queues. 329 * 330 * Returns NETDEV_TX_OK. 331 * You must hold netif_tx_lock() to call this function. 332 */ 333 netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb) 334 { 335 struct efx_nic *efx = tx_queue->efx; 336 struct device *dma_dev = &efx->pci_dev->dev; 337 struct efx_tx_buffer *buffer; 338 unsigned int old_insert_count = tx_queue->insert_count; 339 skb_frag_t *fragment; 340 unsigned int len, unmap_len = 0; 341 dma_addr_t dma_addr, unmap_addr = 0; 342 unsigned int dma_len; 343 unsigned short dma_flags; 344 int i = 0; 345 346 if (skb_shinfo(skb)->gso_size) 347 return efx_enqueue_skb_tso(tx_queue, skb); 348 349 /* Get size of the initial fragment */ 350 len = skb_headlen(skb); 351 352 /* Pad if necessary */ 353 if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) { 354 EFX_BUG_ON_PARANOID(skb->data_len); 355 len = 32 + 1; 356 if (skb_pad(skb, len - skb->len)) 357 return NETDEV_TX_OK; 358 } 359 360 /* Consider using PIO for short packets */ 361 #ifdef EFX_USE_PIO 362 if (skb->len <= efx_piobuf_size && !skb->xmit_more && 363 efx_nic_may_tx_pio(tx_queue)) { 364 buffer = efx_enqueue_skb_pio(tx_queue, skb); 365 dma_flags = EFX_TX_BUF_OPTION; 366 goto finish_packet; 367 } 368 #endif 369 370 /* Map for DMA. Use dma_map_single rather than dma_map_page 371 * since this is more efficient on machines with sparse 372 * memory. 373 */ 374 dma_flags = EFX_TX_BUF_MAP_SINGLE; 375 dma_addr = dma_map_single(dma_dev, skb->data, len, PCI_DMA_TODEVICE); 376 377 /* Process all fragments */ 378 while (1) { 379 if (unlikely(dma_mapping_error(dma_dev, dma_addr))) 380 goto dma_err; 381 382 /* Store fields for marking in the per-fragment final 383 * descriptor */ 384 unmap_len = len; 385 unmap_addr = dma_addr; 386 387 /* Add to TX queue, splitting across DMA boundaries */ 388 do { 389 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 390 391 dma_len = efx_max_tx_len(efx, dma_addr); 392 if (likely(dma_len >= len)) 393 dma_len = len; 394 395 /* Fill out per descriptor fields */ 396 buffer->len = dma_len; 397 buffer->dma_addr = dma_addr; 398 buffer->flags = EFX_TX_BUF_CONT; 399 len -= dma_len; 400 dma_addr += dma_len; 401 ++tx_queue->insert_count; 402 } while (len); 403 404 /* Transfer ownership of the unmapping to the final buffer */ 405 buffer->flags = EFX_TX_BUF_CONT | dma_flags; 406 buffer->unmap_len = unmap_len; 407 buffer->dma_offset = buffer->dma_addr - unmap_addr; 408 unmap_len = 0; 409 410 /* Get address and size of next fragment */ 411 if (i >= skb_shinfo(skb)->nr_frags) 412 break; 413 fragment = &skb_shinfo(skb)->frags[i]; 414 len = skb_frag_size(fragment); 415 i++; 416 /* Map for DMA */ 417 dma_flags = 0; 418 dma_addr = skb_frag_dma_map(dma_dev, fragment, 0, len, 419 DMA_TO_DEVICE); 420 } 421 422 /* Transfer ownership of the skb to the final buffer */ 423 #ifdef EFX_USE_PIO 424 finish_packet: 425 #endif 426 buffer->skb = skb; 427 buffer->flags = EFX_TX_BUF_SKB | dma_flags; 428 429 netdev_tx_sent_queue(tx_queue->core_txq, skb->len); 430 431 efx_tx_maybe_stop_queue(tx_queue); 432 433 /* Pass off to hardware */ 434 if (!skb->xmit_more || netif_xmit_stopped(tx_queue->core_txq)) 435 efx_nic_push_buffers(tx_queue); 436 437 tx_queue->tx_packets++; 438 439 return NETDEV_TX_OK; 440 441 dma_err: 442 netif_err(efx, tx_err, efx->net_dev, 443 " TX queue %d could not map skb with %d bytes %d " 444 "fragments for DMA\n", tx_queue->queue, skb->len, 445 skb_shinfo(skb)->nr_frags + 1); 446 447 /* Mark the packet as transmitted, and free the SKB ourselves */ 448 dev_kfree_skb_any(skb); 449 450 /* Work backwards until we hit the original insert pointer value */ 451 while (tx_queue->insert_count != old_insert_count) { 452 unsigned int pkts_compl = 0, bytes_compl = 0; 453 --tx_queue->insert_count; 454 buffer = __efx_tx_queue_get_insert_buffer(tx_queue); 455 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl); 456 } 457 458 /* Free the fragment we were mid-way through pushing */ 459 if (unmap_len) { 460 if (dma_flags & EFX_TX_BUF_MAP_SINGLE) 461 dma_unmap_single(dma_dev, unmap_addr, unmap_len, 462 DMA_TO_DEVICE); 463 else 464 dma_unmap_page(dma_dev, unmap_addr, unmap_len, 465 DMA_TO_DEVICE); 466 } 467 468 return NETDEV_TX_OK; 469 } 470 471 /* Remove packets from the TX queue 472 * 473 * This removes packets from the TX queue, up to and including the 474 * specified index. 475 */ 476 static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue, 477 unsigned int index, 478 unsigned int *pkts_compl, 479 unsigned int *bytes_compl) 480 { 481 struct efx_nic *efx = tx_queue->efx; 482 unsigned int stop_index, read_ptr; 483 484 stop_index = (index + 1) & tx_queue->ptr_mask; 485 read_ptr = tx_queue->read_count & tx_queue->ptr_mask; 486 487 while (read_ptr != stop_index) { 488 struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr]; 489 490 if (!(buffer->flags & EFX_TX_BUF_OPTION) && 491 unlikely(buffer->len == 0)) { 492 netif_err(efx, tx_err, efx->net_dev, 493 "TX queue %d spurious TX completion id %x\n", 494 tx_queue->queue, read_ptr); 495 efx_schedule_reset(efx, RESET_TYPE_TX_SKIP); 496 return; 497 } 498 499 efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl); 500 501 ++tx_queue->read_count; 502 read_ptr = tx_queue->read_count & tx_queue->ptr_mask; 503 } 504 } 505 506 /* Initiate a packet transmission. We use one channel per CPU 507 * (sharing when we have more CPUs than channels). On Falcon, the TX 508 * completion events will be directed back to the CPU that transmitted 509 * the packet, which should be cache-efficient. 510 * 511 * Context: non-blocking. 512 * Note that returning anything other than NETDEV_TX_OK will cause the 513 * OS to free the skb. 514 */ 515 netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb, 516 struct net_device *net_dev) 517 { 518 struct efx_nic *efx = netdev_priv(net_dev); 519 struct efx_tx_queue *tx_queue; 520 unsigned index, type; 521 522 EFX_WARN_ON_PARANOID(!netif_device_present(net_dev)); 523 524 /* PTP "event" packet */ 525 if (unlikely(efx_xmit_with_hwtstamp(skb)) && 526 unlikely(efx_ptp_is_ptp_tx(efx, skb))) { 527 return efx_ptp_tx(efx, skb); 528 } 529 530 index = skb_get_queue_mapping(skb); 531 type = skb->ip_summed == CHECKSUM_PARTIAL ? EFX_TXQ_TYPE_OFFLOAD : 0; 532 if (index >= efx->n_tx_channels) { 533 index -= efx->n_tx_channels; 534 type |= EFX_TXQ_TYPE_HIGHPRI; 535 } 536 tx_queue = efx_get_tx_queue(efx, index, type); 537 538 return efx_enqueue_skb(tx_queue, skb); 539 } 540 541 void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue) 542 { 543 struct efx_nic *efx = tx_queue->efx; 544 545 /* Must be inverse of queue lookup in efx_hard_start_xmit() */ 546 tx_queue->core_txq = 547 netdev_get_tx_queue(efx->net_dev, 548 tx_queue->queue / EFX_TXQ_TYPES + 549 ((tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ? 550 efx->n_tx_channels : 0)); 551 } 552 553 int efx_setup_tc(struct net_device *net_dev, u8 num_tc) 554 { 555 struct efx_nic *efx = netdev_priv(net_dev); 556 struct efx_channel *channel; 557 struct efx_tx_queue *tx_queue; 558 unsigned tc; 559 int rc; 560 561 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0 || num_tc > EFX_MAX_TX_TC) 562 return -EINVAL; 563 564 if (num_tc == net_dev->num_tc) 565 return 0; 566 567 for (tc = 0; tc < num_tc; tc++) { 568 net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels; 569 net_dev->tc_to_txq[tc].count = efx->n_tx_channels; 570 } 571 572 if (num_tc > net_dev->num_tc) { 573 /* Initialise high-priority queues as necessary */ 574 efx_for_each_channel(channel, efx) { 575 efx_for_each_possible_channel_tx_queue(tx_queue, 576 channel) { 577 if (!(tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI)) 578 continue; 579 if (!tx_queue->buffer) { 580 rc = efx_probe_tx_queue(tx_queue); 581 if (rc) 582 return rc; 583 } 584 if (!tx_queue->initialised) 585 efx_init_tx_queue(tx_queue); 586 efx_init_tx_queue_core_txq(tx_queue); 587 } 588 } 589 } else { 590 /* Reduce number of classes before number of queues */ 591 net_dev->num_tc = num_tc; 592 } 593 594 rc = netif_set_real_num_tx_queues(net_dev, 595 max_t(int, num_tc, 1) * 596 efx->n_tx_channels); 597 if (rc) 598 return rc; 599 600 /* Do not destroy high-priority queues when they become 601 * unused. We would have to flush them first, and it is 602 * fairly difficult to flush a subset of TX queues. Leave 603 * it to efx_fini_channels(). 604 */ 605 606 net_dev->num_tc = num_tc; 607 return 0; 608 } 609 610 void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index) 611 { 612 unsigned fill_level; 613 struct efx_nic *efx = tx_queue->efx; 614 struct efx_tx_queue *txq2; 615 unsigned int pkts_compl = 0, bytes_compl = 0; 616 617 EFX_BUG_ON_PARANOID(index > tx_queue->ptr_mask); 618 619 efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl); 620 netdev_tx_completed_queue(tx_queue->core_txq, pkts_compl, bytes_compl); 621 622 if (pkts_compl > 1) 623 ++tx_queue->merge_events; 624 625 /* See if we need to restart the netif queue. This memory 626 * barrier ensures that we write read_count (inside 627 * efx_dequeue_buffers()) before reading the queue status. 628 */ 629 smp_mb(); 630 if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) && 631 likely(efx->port_enabled) && 632 likely(netif_device_present(efx->net_dev))) { 633 txq2 = efx_tx_queue_partner(tx_queue); 634 fill_level = max(tx_queue->insert_count - tx_queue->read_count, 635 txq2->insert_count - txq2->read_count); 636 if (fill_level <= efx->txq_wake_thresh) 637 netif_tx_wake_queue(tx_queue->core_txq); 638 } 639 640 /* Check whether the hardware queue is now empty */ 641 if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) { 642 tx_queue->old_write_count = ACCESS_ONCE(tx_queue->write_count); 643 if (tx_queue->read_count == tx_queue->old_write_count) { 644 smp_mb(); 645 tx_queue->empty_read_count = 646 tx_queue->read_count | EFX_EMPTY_COUNT_VALID; 647 } 648 } 649 } 650 651 /* Size of page-based TSO header buffers. Larger blocks must be 652 * allocated from the heap. 653 */ 654 #define TSOH_STD_SIZE 128 655 #define TSOH_PER_PAGE (PAGE_SIZE / TSOH_STD_SIZE) 656 657 /* At most half the descriptors in the queue at any time will refer to 658 * a TSO header buffer, since they must always be followed by a 659 * payload descriptor referring to an skb. 660 */ 661 static unsigned int efx_tsoh_page_count(struct efx_tx_queue *tx_queue) 662 { 663 return DIV_ROUND_UP(tx_queue->ptr_mask + 1, 2 * TSOH_PER_PAGE); 664 } 665 666 int efx_probe_tx_queue(struct efx_tx_queue *tx_queue) 667 { 668 struct efx_nic *efx = tx_queue->efx; 669 unsigned int entries; 670 int rc; 671 672 /* Create the smallest power-of-two aligned ring */ 673 entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE); 674 EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE); 675 tx_queue->ptr_mask = entries - 1; 676 677 netif_dbg(efx, probe, efx->net_dev, 678 "creating TX queue %d size %#x mask %#x\n", 679 tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask); 680 681 /* Allocate software ring */ 682 tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer), 683 GFP_KERNEL); 684 if (!tx_queue->buffer) 685 return -ENOMEM; 686 687 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) { 688 tx_queue->tsoh_page = 689 kcalloc(efx_tsoh_page_count(tx_queue), 690 sizeof(tx_queue->tsoh_page[0]), GFP_KERNEL); 691 if (!tx_queue->tsoh_page) { 692 rc = -ENOMEM; 693 goto fail1; 694 } 695 } 696 697 /* Allocate hardware ring */ 698 rc = efx_nic_probe_tx(tx_queue); 699 if (rc) 700 goto fail2; 701 702 return 0; 703 704 fail2: 705 kfree(tx_queue->tsoh_page); 706 tx_queue->tsoh_page = NULL; 707 fail1: 708 kfree(tx_queue->buffer); 709 tx_queue->buffer = NULL; 710 return rc; 711 } 712 713 void efx_init_tx_queue(struct efx_tx_queue *tx_queue) 714 { 715 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, 716 "initialising TX queue %d\n", tx_queue->queue); 717 718 tx_queue->insert_count = 0; 719 tx_queue->write_count = 0; 720 tx_queue->old_write_count = 0; 721 tx_queue->read_count = 0; 722 tx_queue->old_read_count = 0; 723 tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID; 724 725 /* Set up TX descriptor ring */ 726 efx_nic_init_tx(tx_queue); 727 728 tx_queue->initialised = true; 729 } 730 731 void efx_fini_tx_queue(struct efx_tx_queue *tx_queue) 732 { 733 struct efx_tx_buffer *buffer; 734 735 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, 736 "shutting down TX queue %d\n", tx_queue->queue); 737 738 if (!tx_queue->buffer) 739 return; 740 741 /* Free any buffers left in the ring */ 742 while (tx_queue->read_count != tx_queue->write_count) { 743 unsigned int pkts_compl = 0, bytes_compl = 0; 744 buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask]; 745 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl); 746 747 ++tx_queue->read_count; 748 } 749 netdev_tx_reset_queue(tx_queue->core_txq); 750 } 751 752 void efx_remove_tx_queue(struct efx_tx_queue *tx_queue) 753 { 754 int i; 755 756 if (!tx_queue->buffer) 757 return; 758 759 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, 760 "destroying TX queue %d\n", tx_queue->queue); 761 efx_nic_remove_tx(tx_queue); 762 763 if (tx_queue->tsoh_page) { 764 for (i = 0; i < efx_tsoh_page_count(tx_queue); i++) 765 efx_nic_free_buffer(tx_queue->efx, 766 &tx_queue->tsoh_page[i]); 767 kfree(tx_queue->tsoh_page); 768 tx_queue->tsoh_page = NULL; 769 } 770 771 kfree(tx_queue->buffer); 772 tx_queue->buffer = NULL; 773 } 774 775 776 /* Efx TCP segmentation acceleration. 777 * 778 * Why? Because by doing it here in the driver we can go significantly 779 * faster than the GSO. 780 * 781 * Requires TX checksum offload support. 782 */ 783 784 #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2)) 785 786 /** 787 * struct tso_state - TSO state for an SKB 788 * @out_len: Remaining length in current segment 789 * @seqnum: Current sequence number 790 * @ipv4_id: Current IPv4 ID, host endian 791 * @packet_space: Remaining space in current packet 792 * @dma_addr: DMA address of current position 793 * @in_len: Remaining length in current SKB fragment 794 * @unmap_len: Length of SKB fragment 795 * @unmap_addr: DMA address of SKB fragment 796 * @dma_flags: TX buffer flags for DMA mapping - %EFX_TX_BUF_MAP_SINGLE or 0 797 * @protocol: Network protocol (after any VLAN header) 798 * @ip_off: Offset of IP header 799 * @tcp_off: Offset of TCP header 800 * @header_len: Number of bytes of header 801 * @ip_base_len: IPv4 tot_len or IPv6 payload_len, before TCP payload 802 * @header_dma_addr: Header DMA address, when using option descriptors 803 * @header_unmap_len: Header DMA mapped length, or 0 if not using option 804 * descriptors 805 * 806 * The state used during segmentation. It is put into this data structure 807 * just to make it easy to pass into inline functions. 808 */ 809 struct tso_state { 810 /* Output position */ 811 unsigned out_len; 812 unsigned seqnum; 813 u16 ipv4_id; 814 unsigned packet_space; 815 816 /* Input position */ 817 dma_addr_t dma_addr; 818 unsigned in_len; 819 unsigned unmap_len; 820 dma_addr_t unmap_addr; 821 unsigned short dma_flags; 822 823 __be16 protocol; 824 unsigned int ip_off; 825 unsigned int tcp_off; 826 unsigned header_len; 827 unsigned int ip_base_len; 828 dma_addr_t header_dma_addr; 829 unsigned int header_unmap_len; 830 }; 831 832 833 /* 834 * Verify that our various assumptions about sk_buffs and the conditions 835 * under which TSO will be attempted hold true. Return the protocol number. 836 */ 837 static __be16 efx_tso_check_protocol(struct sk_buff *skb) 838 { 839 __be16 protocol = skb->protocol; 840 841 EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto != 842 protocol); 843 if (protocol == htons(ETH_P_8021Q)) { 844 struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data; 845 protocol = veh->h_vlan_encapsulated_proto; 846 } 847 848 if (protocol == htons(ETH_P_IP)) { 849 EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP); 850 } else { 851 EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IPV6)); 852 EFX_BUG_ON_PARANOID(ipv6_hdr(skb)->nexthdr != NEXTHDR_TCP); 853 } 854 EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data) 855 + (tcp_hdr(skb)->doff << 2u)) > 856 skb_headlen(skb)); 857 858 return protocol; 859 } 860 861 static u8 *efx_tsoh_get_buffer(struct efx_tx_queue *tx_queue, 862 struct efx_tx_buffer *buffer, unsigned int len) 863 { 864 u8 *result; 865 866 EFX_BUG_ON_PARANOID(buffer->len); 867 EFX_BUG_ON_PARANOID(buffer->flags); 868 EFX_BUG_ON_PARANOID(buffer->unmap_len); 869 870 if (likely(len <= TSOH_STD_SIZE - NET_IP_ALIGN)) { 871 unsigned index = 872 (tx_queue->insert_count & tx_queue->ptr_mask) / 2; 873 struct efx_buffer *page_buf = 874 &tx_queue->tsoh_page[index / TSOH_PER_PAGE]; 875 unsigned offset = 876 TSOH_STD_SIZE * (index % TSOH_PER_PAGE) + NET_IP_ALIGN; 877 878 if (unlikely(!page_buf->addr) && 879 efx_nic_alloc_buffer(tx_queue->efx, page_buf, PAGE_SIZE, 880 GFP_ATOMIC)) 881 return NULL; 882 883 result = (u8 *)page_buf->addr + offset; 884 buffer->dma_addr = page_buf->dma_addr + offset; 885 buffer->flags = EFX_TX_BUF_CONT; 886 } else { 887 tx_queue->tso_long_headers++; 888 889 buffer->heap_buf = kmalloc(NET_IP_ALIGN + len, GFP_ATOMIC); 890 if (unlikely(!buffer->heap_buf)) 891 return NULL; 892 result = (u8 *)buffer->heap_buf + NET_IP_ALIGN; 893 buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_HEAP; 894 } 895 896 buffer->len = len; 897 898 return result; 899 } 900 901 /** 902 * efx_tx_queue_insert - push descriptors onto the TX queue 903 * @tx_queue: Efx TX queue 904 * @dma_addr: DMA address of fragment 905 * @len: Length of fragment 906 * @final_buffer: The final buffer inserted into the queue 907 * 908 * Push descriptors onto the TX queue. 909 */ 910 static void efx_tx_queue_insert(struct efx_tx_queue *tx_queue, 911 dma_addr_t dma_addr, unsigned len, 912 struct efx_tx_buffer **final_buffer) 913 { 914 struct efx_tx_buffer *buffer; 915 struct efx_nic *efx = tx_queue->efx; 916 unsigned dma_len; 917 918 EFX_BUG_ON_PARANOID(len <= 0); 919 920 while (1) { 921 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 922 ++tx_queue->insert_count; 923 924 EFX_BUG_ON_PARANOID(tx_queue->insert_count - 925 tx_queue->read_count >= 926 efx->txq_entries); 927 928 buffer->dma_addr = dma_addr; 929 930 dma_len = efx_max_tx_len(efx, dma_addr); 931 932 /* If there is enough space to send then do so */ 933 if (dma_len >= len) 934 break; 935 936 buffer->len = dma_len; 937 buffer->flags = EFX_TX_BUF_CONT; 938 dma_addr += dma_len; 939 len -= dma_len; 940 } 941 942 EFX_BUG_ON_PARANOID(!len); 943 buffer->len = len; 944 *final_buffer = buffer; 945 } 946 947 948 /* 949 * Put a TSO header into the TX queue. 950 * 951 * This is special-cased because we know that it is small enough to fit in 952 * a single fragment, and we know it doesn't cross a page boundary. It 953 * also allows us to not worry about end-of-packet etc. 954 */ 955 static int efx_tso_put_header(struct efx_tx_queue *tx_queue, 956 struct efx_tx_buffer *buffer, u8 *header) 957 { 958 if (unlikely(buffer->flags & EFX_TX_BUF_HEAP)) { 959 buffer->dma_addr = dma_map_single(&tx_queue->efx->pci_dev->dev, 960 header, buffer->len, 961 DMA_TO_DEVICE); 962 if (unlikely(dma_mapping_error(&tx_queue->efx->pci_dev->dev, 963 buffer->dma_addr))) { 964 kfree(buffer->heap_buf); 965 buffer->len = 0; 966 buffer->flags = 0; 967 return -ENOMEM; 968 } 969 buffer->unmap_len = buffer->len; 970 buffer->dma_offset = 0; 971 buffer->flags |= EFX_TX_BUF_MAP_SINGLE; 972 } 973 974 ++tx_queue->insert_count; 975 return 0; 976 } 977 978 979 /* Remove buffers put into a tx_queue. None of the buffers must have 980 * an skb attached. 981 */ 982 static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue, 983 unsigned int insert_count) 984 { 985 struct efx_tx_buffer *buffer; 986 987 /* Work backwards until we hit the original insert pointer value */ 988 while (tx_queue->insert_count != insert_count) { 989 --tx_queue->insert_count; 990 buffer = __efx_tx_queue_get_insert_buffer(tx_queue); 991 efx_dequeue_buffer(tx_queue, buffer, NULL, NULL); 992 } 993 } 994 995 996 /* Parse the SKB header and initialise state. */ 997 static int tso_start(struct tso_state *st, struct efx_nic *efx, 998 const struct sk_buff *skb) 999 { 1000 bool use_opt_desc = efx_nic_rev(efx) >= EFX_REV_HUNT_A0; 1001 struct device *dma_dev = &efx->pci_dev->dev; 1002 unsigned int header_len, in_len; 1003 dma_addr_t dma_addr; 1004 1005 st->ip_off = skb_network_header(skb) - skb->data; 1006 st->tcp_off = skb_transport_header(skb) - skb->data; 1007 header_len = st->tcp_off + (tcp_hdr(skb)->doff << 2u); 1008 in_len = skb_headlen(skb) - header_len; 1009 st->header_len = header_len; 1010 st->in_len = in_len; 1011 if (st->protocol == htons(ETH_P_IP)) { 1012 st->ip_base_len = st->header_len - st->ip_off; 1013 st->ipv4_id = ntohs(ip_hdr(skb)->id); 1014 } else { 1015 st->ip_base_len = st->header_len - st->tcp_off; 1016 st->ipv4_id = 0; 1017 } 1018 st->seqnum = ntohl(tcp_hdr(skb)->seq); 1019 1020 EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg); 1021 EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn); 1022 EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst); 1023 1024 st->out_len = skb->len - header_len; 1025 1026 if (!use_opt_desc) { 1027 st->header_unmap_len = 0; 1028 1029 if (likely(in_len == 0)) { 1030 st->dma_flags = 0; 1031 st->unmap_len = 0; 1032 return 0; 1033 } 1034 1035 dma_addr = dma_map_single(dma_dev, skb->data + header_len, 1036 in_len, DMA_TO_DEVICE); 1037 st->dma_flags = EFX_TX_BUF_MAP_SINGLE; 1038 st->dma_addr = dma_addr; 1039 st->unmap_addr = dma_addr; 1040 st->unmap_len = in_len; 1041 } else { 1042 dma_addr = dma_map_single(dma_dev, skb->data, 1043 skb_headlen(skb), DMA_TO_DEVICE); 1044 st->header_dma_addr = dma_addr; 1045 st->header_unmap_len = skb_headlen(skb); 1046 st->dma_flags = 0; 1047 st->dma_addr = dma_addr + header_len; 1048 st->unmap_len = 0; 1049 } 1050 1051 return unlikely(dma_mapping_error(dma_dev, dma_addr)) ? -ENOMEM : 0; 1052 } 1053 1054 static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx, 1055 skb_frag_t *frag) 1056 { 1057 st->unmap_addr = skb_frag_dma_map(&efx->pci_dev->dev, frag, 0, 1058 skb_frag_size(frag), DMA_TO_DEVICE); 1059 if (likely(!dma_mapping_error(&efx->pci_dev->dev, st->unmap_addr))) { 1060 st->dma_flags = 0; 1061 st->unmap_len = skb_frag_size(frag); 1062 st->in_len = skb_frag_size(frag); 1063 st->dma_addr = st->unmap_addr; 1064 return 0; 1065 } 1066 return -ENOMEM; 1067 } 1068 1069 1070 /** 1071 * tso_fill_packet_with_fragment - form descriptors for the current fragment 1072 * @tx_queue: Efx TX queue 1073 * @skb: Socket buffer 1074 * @st: TSO state 1075 * 1076 * Form descriptors for the current fragment, until we reach the end 1077 * of fragment or end-of-packet. 1078 */ 1079 static void tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue, 1080 const struct sk_buff *skb, 1081 struct tso_state *st) 1082 { 1083 struct efx_tx_buffer *buffer; 1084 int n; 1085 1086 if (st->in_len == 0) 1087 return; 1088 if (st->packet_space == 0) 1089 return; 1090 1091 EFX_BUG_ON_PARANOID(st->in_len <= 0); 1092 EFX_BUG_ON_PARANOID(st->packet_space <= 0); 1093 1094 n = min(st->in_len, st->packet_space); 1095 1096 st->packet_space -= n; 1097 st->out_len -= n; 1098 st->in_len -= n; 1099 1100 efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer); 1101 1102 if (st->out_len == 0) { 1103 /* Transfer ownership of the skb */ 1104 buffer->skb = skb; 1105 buffer->flags = EFX_TX_BUF_SKB; 1106 } else if (st->packet_space != 0) { 1107 buffer->flags = EFX_TX_BUF_CONT; 1108 } 1109 1110 if (st->in_len == 0) { 1111 /* Transfer ownership of the DMA mapping */ 1112 buffer->unmap_len = st->unmap_len; 1113 buffer->dma_offset = buffer->unmap_len - buffer->len; 1114 buffer->flags |= st->dma_flags; 1115 st->unmap_len = 0; 1116 } 1117 1118 st->dma_addr += n; 1119 } 1120 1121 1122 /** 1123 * tso_start_new_packet - generate a new header and prepare for the new packet 1124 * @tx_queue: Efx TX queue 1125 * @skb: Socket buffer 1126 * @st: TSO state 1127 * 1128 * Generate a new header and prepare for the new packet. Return 0 on 1129 * success, or -%ENOMEM if failed to alloc header. 1130 */ 1131 static int tso_start_new_packet(struct efx_tx_queue *tx_queue, 1132 const struct sk_buff *skb, 1133 struct tso_state *st) 1134 { 1135 struct efx_tx_buffer *buffer = 1136 efx_tx_queue_get_insert_buffer(tx_queue); 1137 bool is_last = st->out_len <= skb_shinfo(skb)->gso_size; 1138 u8 tcp_flags_clear; 1139 1140 if (!is_last) { 1141 st->packet_space = skb_shinfo(skb)->gso_size; 1142 tcp_flags_clear = 0x09; /* mask out FIN and PSH */ 1143 } else { 1144 st->packet_space = st->out_len; 1145 tcp_flags_clear = 0x00; 1146 } 1147 1148 if (!st->header_unmap_len) { 1149 /* Allocate and insert a DMA-mapped header buffer. */ 1150 struct tcphdr *tsoh_th; 1151 unsigned ip_length; 1152 u8 *header; 1153 int rc; 1154 1155 header = efx_tsoh_get_buffer(tx_queue, buffer, st->header_len); 1156 if (!header) 1157 return -ENOMEM; 1158 1159 tsoh_th = (struct tcphdr *)(header + st->tcp_off); 1160 1161 /* Copy and update the headers. */ 1162 memcpy(header, skb->data, st->header_len); 1163 1164 tsoh_th->seq = htonl(st->seqnum); 1165 ((u8 *)tsoh_th)[13] &= ~tcp_flags_clear; 1166 1167 ip_length = st->ip_base_len + st->packet_space; 1168 1169 if (st->protocol == htons(ETH_P_IP)) { 1170 struct iphdr *tsoh_iph = 1171 (struct iphdr *)(header + st->ip_off); 1172 1173 tsoh_iph->tot_len = htons(ip_length); 1174 tsoh_iph->id = htons(st->ipv4_id); 1175 } else { 1176 struct ipv6hdr *tsoh_iph = 1177 (struct ipv6hdr *)(header + st->ip_off); 1178 1179 tsoh_iph->payload_len = htons(ip_length); 1180 } 1181 1182 rc = efx_tso_put_header(tx_queue, buffer, header); 1183 if (unlikely(rc)) 1184 return rc; 1185 } else { 1186 /* Send the original headers with a TSO option descriptor 1187 * in front 1188 */ 1189 u8 tcp_flags = ((u8 *)tcp_hdr(skb))[13] & ~tcp_flags_clear; 1190 1191 buffer->flags = EFX_TX_BUF_OPTION; 1192 buffer->len = 0; 1193 buffer->unmap_len = 0; 1194 EFX_POPULATE_QWORD_5(buffer->option, 1195 ESF_DZ_TX_DESC_IS_OPT, 1, 1196 ESF_DZ_TX_OPTION_TYPE, 1197 ESE_DZ_TX_OPTION_DESC_TSO, 1198 ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags, 1199 ESF_DZ_TX_TSO_IP_ID, st->ipv4_id, 1200 ESF_DZ_TX_TSO_TCP_SEQNO, st->seqnum); 1201 ++tx_queue->insert_count; 1202 1203 /* We mapped the headers in tso_start(). Unmap them 1204 * when the last segment is completed. 1205 */ 1206 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 1207 buffer->dma_addr = st->header_dma_addr; 1208 buffer->len = st->header_len; 1209 if (is_last) { 1210 buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_MAP_SINGLE; 1211 buffer->unmap_len = st->header_unmap_len; 1212 buffer->dma_offset = 0; 1213 /* Ensure we only unmap them once in case of a 1214 * later DMA mapping error and rollback 1215 */ 1216 st->header_unmap_len = 0; 1217 } else { 1218 buffer->flags = EFX_TX_BUF_CONT; 1219 buffer->unmap_len = 0; 1220 } 1221 ++tx_queue->insert_count; 1222 } 1223 1224 st->seqnum += skb_shinfo(skb)->gso_size; 1225 1226 /* Linux leaves suitable gaps in the IP ID space for us to fill. */ 1227 ++st->ipv4_id; 1228 1229 ++tx_queue->tso_packets; 1230 1231 ++tx_queue->tx_packets; 1232 1233 return 0; 1234 } 1235 1236 1237 /** 1238 * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer 1239 * @tx_queue: Efx TX queue 1240 * @skb: Socket buffer 1241 * 1242 * Context: You must hold netif_tx_lock() to call this function. 1243 * 1244 * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if 1245 * @skb was not enqueued. In all cases @skb is consumed. Return 1246 * %NETDEV_TX_OK. 1247 */ 1248 static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, 1249 struct sk_buff *skb) 1250 { 1251 struct efx_nic *efx = tx_queue->efx; 1252 unsigned int old_insert_count = tx_queue->insert_count; 1253 int frag_i, rc; 1254 struct tso_state state; 1255 1256 /* Find the packet protocol and sanity-check it */ 1257 state.protocol = efx_tso_check_protocol(skb); 1258 1259 rc = tso_start(&state, efx, skb); 1260 if (rc) 1261 goto mem_err; 1262 1263 if (likely(state.in_len == 0)) { 1264 /* Grab the first payload fragment. */ 1265 EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1); 1266 frag_i = 0; 1267 rc = tso_get_fragment(&state, efx, 1268 skb_shinfo(skb)->frags + frag_i); 1269 if (rc) 1270 goto mem_err; 1271 } else { 1272 /* Payload starts in the header area. */ 1273 frag_i = -1; 1274 } 1275 1276 if (tso_start_new_packet(tx_queue, skb, &state) < 0) 1277 goto mem_err; 1278 1279 while (1) { 1280 tso_fill_packet_with_fragment(tx_queue, skb, &state); 1281 1282 /* Move onto the next fragment? */ 1283 if (state.in_len == 0) { 1284 if (++frag_i >= skb_shinfo(skb)->nr_frags) 1285 /* End of payload reached. */ 1286 break; 1287 rc = tso_get_fragment(&state, efx, 1288 skb_shinfo(skb)->frags + frag_i); 1289 if (rc) 1290 goto mem_err; 1291 } 1292 1293 /* Start at new packet? */ 1294 if (state.packet_space == 0 && 1295 tso_start_new_packet(tx_queue, skb, &state) < 0) 1296 goto mem_err; 1297 } 1298 1299 netdev_tx_sent_queue(tx_queue->core_txq, skb->len); 1300 1301 efx_tx_maybe_stop_queue(tx_queue); 1302 1303 /* Pass off to hardware */ 1304 if (!skb->xmit_more || netif_xmit_stopped(tx_queue->core_txq)) 1305 efx_nic_push_buffers(tx_queue); 1306 1307 tx_queue->tso_bursts++; 1308 return NETDEV_TX_OK; 1309 1310 mem_err: 1311 netif_err(efx, tx_err, efx->net_dev, 1312 "Out of memory for TSO headers, or DMA mapping error\n"); 1313 dev_kfree_skb_any(skb); 1314 1315 /* Free the DMA mapping we were in the process of writing out */ 1316 if (state.unmap_len) { 1317 if (state.dma_flags & EFX_TX_BUF_MAP_SINGLE) 1318 dma_unmap_single(&efx->pci_dev->dev, state.unmap_addr, 1319 state.unmap_len, DMA_TO_DEVICE); 1320 else 1321 dma_unmap_page(&efx->pci_dev->dev, state.unmap_addr, 1322 state.unmap_len, DMA_TO_DEVICE); 1323 } 1324 1325 /* Free the header DMA mapping, if using option descriptors */ 1326 if (state.header_unmap_len) 1327 dma_unmap_single(&efx->pci_dev->dev, state.header_dma_addr, 1328 state.header_unmap_len, DMA_TO_DEVICE); 1329 1330 efx_enqueue_unwind(tx_queue, old_insert_count); 1331 return NETDEV_TX_OK; 1332 } 1333