1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2019 Solarflare Communications Inc. 5 * Copyright 2020-2022 Xilinx Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation, incorporated herein by reference. 10 */ 11 12 #ifndef EFX_TC_H 13 #define EFX_TC_H 14 #include <net/flow_offload.h> 15 #include <linux/rhashtable.h> 16 #include "net_driver.h" 17 #include "tc_counters.h" 18 19 #define IS_ALL_ONES(v) (!(typeof (v))~(v)) 20 21 #ifdef CONFIG_IPV6 22 static inline bool efx_ipv6_addr_all_ones(struct in6_addr *addr) 23 { 24 return !memchr_inv(addr, 0xff, sizeof(*addr)); 25 } 26 #endif 27 28 struct efx_tc_action_set { 29 u16 vlan_push:2; 30 u16 vlan_pop:2; 31 u16 decap:1; 32 u16 deliver:1; 33 __be16 vlan_tci[2]; /* TCIs for vlan_push */ 34 __be16 vlan_proto[2]; /* Ethertypes for vlan_push */ 35 struct efx_tc_counter_index *count; 36 u32 dest_mport; 37 u32 fw_id; /* index of this entry in firmware actions table */ 38 struct list_head list; 39 }; 40 41 struct efx_tc_match_fields { 42 /* L1 */ 43 u32 ingress_port; 44 u8 recirc_id; 45 /* L2 (inner when encap) */ 46 __be16 eth_proto; 47 __be16 vlan_tci[2], vlan_proto[2]; 48 u8 eth_saddr[ETH_ALEN], eth_daddr[ETH_ALEN]; 49 /* L3 (when IP) */ 50 u8 ip_proto, ip_tos, ip_ttl; 51 __be32 src_ip, dst_ip; 52 #ifdef CONFIG_IPV6 53 struct in6_addr src_ip6, dst_ip6; 54 #endif 55 bool ip_frag, ip_firstfrag; 56 /* L4 */ 57 __be16 l4_sport, l4_dport; /* Ports (UDP, TCP) */ 58 __be16 tcp_flags; 59 /* Encap. The following are *outer* fields. Note that there are no 60 * outer eth (L2) fields; this is because TC doesn't have them. 61 */ 62 __be32 enc_src_ip, enc_dst_ip; 63 struct in6_addr enc_src_ip6, enc_dst_ip6; 64 u8 enc_ip_tos, enc_ip_ttl; 65 __be16 enc_sport, enc_dport; 66 __be32 enc_keyid; /* e.g. VNI, VSID */ 67 }; 68 69 static inline bool efx_tc_match_is_encap(const struct efx_tc_match_fields *mask) 70 { 71 return mask->enc_src_ip || mask->enc_dst_ip || 72 !ipv6_addr_any(&mask->enc_src_ip6) || 73 !ipv6_addr_any(&mask->enc_dst_ip6) || mask->enc_ip_tos || 74 mask->enc_ip_ttl || mask->enc_sport || mask->enc_dport; 75 } 76 77 /** 78 * enum efx_tc_em_pseudo_type - &struct efx_tc_encap_match pseudo type 79 * 80 * These are used to classify "pseudo" encap matches, which don't refer 81 * to an entry in hardware but rather indicate that a section of the 82 * match space is in use by another Outer Rule. 83 * 84 * @EFX_TC_EM_DIRECT: real HW entry in Outer Rule table; not a pseudo. 85 * Hardware index in &struct efx_tc_encap_match.fw_id is valid. 86 * @EFX_TC_EM_PSEUDO_MASK: registered by an encap match which includes a 87 * match on an optional field (currently ip_tos and/or udp_sport), 88 * to prevent an overlapping encap match _without_ optional fields. 89 * The pseudo encap match may be referenced again by an encap match 90 * with different values for these fields, but all masks must match the 91 * first (stored in our child_* fields). 92 */ 93 enum efx_tc_em_pseudo_type { 94 EFX_TC_EM_DIRECT, 95 EFX_TC_EM_PSEUDO_MASK, 96 }; 97 98 struct efx_tc_encap_match { 99 __be32 src_ip, dst_ip; 100 struct in6_addr src_ip6, dst_ip6; 101 __be16 udp_dport; 102 __be16 udp_sport, udp_sport_mask; 103 u8 ip_tos, ip_tos_mask; 104 struct rhash_head linkage; 105 enum efx_encap_type tun_type; 106 u8 child_ip_tos_mask; 107 __be16 child_udp_sport_mask; 108 refcount_t ref; 109 enum efx_tc_em_pseudo_type type; 110 u32 fw_id; /* index of this entry in firmware encap match table */ 111 struct efx_tc_encap_match *pseudo; /* Referenced pseudo EM if needed */ 112 }; 113 114 struct efx_tc_match { 115 struct efx_tc_match_fields value; 116 struct efx_tc_match_fields mask; 117 struct efx_tc_encap_match *encap; 118 }; 119 120 struct efx_tc_action_set_list { 121 struct list_head list; 122 u32 fw_id; 123 }; 124 125 struct efx_tc_flow_rule { 126 unsigned long cookie; 127 struct rhash_head linkage; 128 struct efx_tc_match match; 129 struct efx_tc_action_set_list acts; 130 u32 fw_id; 131 }; 132 133 enum efx_tc_rule_prios { 134 EFX_TC_PRIO_TC, /* Rule inserted by TC */ 135 EFX_TC_PRIO_DFLT, /* Default switch rule; one of efx_tc_default_rules */ 136 EFX_TC_PRIO__NUM 137 }; 138 139 /** 140 * struct efx_tc_state - control plane data for TC offload 141 * 142 * @caps: MAE capabilities reported by MCDI 143 * @block_list: List of &struct efx_tc_block_binding 144 * @mutex: Used to serialise operations on TC hashtables 145 * @counter_ht: Hashtable of TC counters (FW IDs and counter values) 146 * @counter_id_ht: Hashtable mapping TC counter cookies to counters 147 * @encap_match_ht: Hashtable of TC encap matches 148 * @match_action_ht: Hashtable of TC match-action rules 149 * @reps_mport_id: MAE port allocated for representor RX 150 * @reps_filter_uc: VNIC filter for representor unicast RX (promisc) 151 * @reps_filter_mc: VNIC filter for representor multicast RX (allmulti) 152 * @reps_mport_vport_id: vport_id for representor RX filters 153 * @flush_counters: counters have been stopped, waiting for drain 154 * @flush_gen: final generation count per type array as reported by 155 * MC_CMD_MAE_COUNTERS_STREAM_STOP 156 * @seen_gen: most recent generation count per type as seen by efx_tc_rx() 157 * @flush_wq: wait queue used by efx_mae_stop_counters() to wait for 158 * MAE counters RXQ to finish draining 159 * @dflt: Match-action rules for default switching; at priority 160 * %EFX_TC_PRIO_DFLT. Named by *ingress* port 161 * @dflt.pf: rule for traffic ingressing from PF (egresses to wire) 162 * @dflt.wire: rule for traffic ingressing from wire (egresses to PF) 163 * @up: have TC datastructures been set up? 164 */ 165 struct efx_tc_state { 166 struct mae_caps *caps; 167 struct list_head block_list; 168 struct mutex mutex; 169 struct rhashtable counter_ht; 170 struct rhashtable counter_id_ht; 171 struct rhashtable encap_match_ht; 172 struct rhashtable match_action_ht; 173 u32 reps_mport_id, reps_mport_vport_id; 174 s32 reps_filter_uc, reps_filter_mc; 175 bool flush_counters; 176 u32 flush_gen[EFX_TC_COUNTER_TYPE_MAX]; 177 u32 seen_gen[EFX_TC_COUNTER_TYPE_MAX]; 178 wait_queue_head_t flush_wq; 179 struct { 180 struct efx_tc_flow_rule pf; 181 struct efx_tc_flow_rule wire; 182 } dflt; 183 bool up; 184 }; 185 186 struct efx_rep; 187 188 int efx_tc_configure_default_rule_rep(struct efx_rep *efv); 189 void efx_tc_deconfigure_default_rule(struct efx_nic *efx, 190 struct efx_tc_flow_rule *rule); 191 int efx_tc_flower(struct efx_nic *efx, struct net_device *net_dev, 192 struct flow_cls_offload *tc, struct efx_rep *efv); 193 194 int efx_tc_insert_rep_filters(struct efx_nic *efx); 195 void efx_tc_remove_rep_filters(struct efx_nic *efx); 196 197 int efx_init_tc(struct efx_nic *efx); 198 void efx_fini_tc(struct efx_nic *efx); 199 200 int efx_init_struct_tc(struct efx_nic *efx); 201 void efx_fini_struct_tc(struct efx_nic *efx); 202 203 #endif /* EFX_TC_H */ 204