1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2018 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #ifndef EFX_RX_COMMON_H 12 #define EFX_RX_COMMON_H 13 14 /* Preferred number of descriptors to fill at once */ 15 #define EFX_RX_PREFERRED_BATCH 8U 16 17 /* Each packet can consume up to ceil(max_frame_len / buffer_size) buffers */ 18 #define EFX_RX_MAX_FRAGS DIV_ROUND_UP(EFX_MAX_FRAME_LEN(EFX_MAX_MTU), \ 19 EFX_RX_USR_BUF_SIZE) 20 21 /* Number of RX buffers to recycle pages for. When creating the RX page recycle 22 * ring, this number is divided by the number of buffers per page to calculate 23 * the number of pages to store in the RX page recycle ring. 24 */ 25 #define EFX_RECYCLE_RING_SIZE_10G 256 26 27 static inline u8 *efx_rx_buf_va(struct efx_rx_buffer *buf) 28 { 29 return page_address(buf->page) + buf->page_offset; 30 } 31 32 static inline u32 efx_rx_buf_hash(struct efx_nic *efx, const u8 *eh) 33 { 34 #if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) 35 return __le32_to_cpup((const __le32 *)(eh + efx->rx_packet_hash_offset)); 36 #else 37 const u8 *data = eh + efx->rx_packet_hash_offset; 38 39 return (u32)data[0] | 40 (u32)data[1] << 8 | 41 (u32)data[2] << 16 | 42 (u32)data[3] << 24; 43 #endif 44 } 45 46 void efx_siena_rx_slow_fill(struct timer_list *t); 47 48 void efx_siena_recycle_rx_pages(struct efx_channel *channel, 49 struct efx_rx_buffer *rx_buf, 50 unsigned int n_frags); 51 void efx_siena_discard_rx_packet(struct efx_channel *channel, 52 struct efx_rx_buffer *rx_buf, 53 unsigned int n_frags); 54 55 int efx_siena_probe_rx_queue(struct efx_rx_queue *rx_queue); 56 void efx_siena_init_rx_queue(struct efx_rx_queue *rx_queue); 57 void efx_siena_fini_rx_queue(struct efx_rx_queue *rx_queue); 58 void efx_siena_remove_rx_queue(struct efx_rx_queue *rx_queue); 59 60 static inline void efx_sync_rx_buffer(struct efx_nic *efx, 61 struct efx_rx_buffer *rx_buf, 62 unsigned int len) 63 { 64 dma_sync_single_for_cpu(&efx->pci_dev->dev, rx_buf->dma_addr, len, 65 DMA_FROM_DEVICE); 66 } 67 68 void efx_siena_free_rx_buffers(struct efx_rx_queue *rx_queue, 69 struct efx_rx_buffer *rx_buf, 70 unsigned int num_bufs); 71 72 void efx_siena_rx_config_page_split(struct efx_nic *efx); 73 void efx_siena_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue, 74 bool atomic); 75 76 void 77 efx_siena_rx_packet_gro(struct efx_channel *channel, 78 struct efx_rx_buffer *rx_buf, 79 unsigned int n_frags, u8 *eh, __wsum csum); 80 81 void efx_siena_set_default_rx_indir_table(struct efx_nic *efx, 82 struct efx_rss_context *ctx); 83 84 bool efx_siena_filter_is_mc_recipient(const struct efx_filter_spec *spec); 85 bool efx_siena_filter_spec_equal(const struct efx_filter_spec *left, 86 const struct efx_filter_spec *right); 87 u32 efx_siena_filter_spec_hash(const struct efx_filter_spec *spec); 88 89 #ifdef CONFIG_RFS_ACCEL 90 bool efx_siena_rps_check_rule(struct efx_arfs_rule *rule, 91 unsigned int filter_idx, bool *force); 92 struct efx_arfs_rule *efx_siena_rps_hash_find(struct efx_nic *efx, 93 const struct efx_filter_spec *spec); 94 void efx_siena_rps_hash_del(struct efx_nic *efx, 95 const struct efx_filter_spec *spec); 96 97 int efx_siena_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb, 98 u16 rxq_index, u32 flow_id); 99 bool __efx_siena_filter_rfs_expire(struct efx_channel *channel, 100 unsigned int quota); 101 #endif 102 103 int efx_siena_probe_filters(struct efx_nic *efx); 104 void efx_siena_remove_filters(struct efx_nic *efx); 105 106 #endif 107