1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2005-2006 Fen Systems Ltd. 5 * Copyright 2006-2013 Solarflare Communications Inc. 6 * Copyright 2019-2020 Xilinx Inc. 7 */ 8 9 #ifndef EFX_NIC_COMMON_H 10 #define EFX_NIC_COMMON_H 11 12 #include "net_driver.h" 13 #include "efx_common.h" 14 #include "mcdi.h" 15 #include "ptp.h" 16 17 enum { 18 /* Revisions 0-3 were Falcon A0, A1, B0 and Siena respectively. 19 * They are not supported by this driver but these revision numbers 20 * form part of the ethtool API for register dumping. 21 */ 22 EFX_REV_HUNT_A0 = 4, 23 EFX_REV_EF100 = 5, 24 EFX_REV_X4 = 6, 25 }; 26 27 static inline int efx_nic_rev(struct efx_nic *efx) 28 { 29 return efx->type->revision; 30 } 31 32 /* Read the current event from the event queue */ 33 static inline efx_qword_t *efx_event(struct efx_channel *channel, 34 unsigned int index) 35 { 36 return ((efx_qword_t *)(channel->eventq.addr)) + 37 (index & channel->eventq_mask); 38 } 39 40 /* See if an event is present 41 * 42 * We check both the high and low dword of the event for all ones. We 43 * wrote all ones when we cleared the event, and no valid event can 44 * have all ones in either its high or low dwords. This approach is 45 * robust against reordering. 46 * 47 * Note that using a single 64-bit comparison is incorrect; even 48 * though the CPU read will be atomic, the DMA write may not be. 49 */ 50 static inline int efx_event_present(efx_qword_t *event) 51 { 52 return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | 53 EFX_DWORD_IS_ALL_ONES(event->dword[1])); 54 } 55 56 /* Returns a pointer to the specified transmit descriptor in the TX 57 * descriptor queue belonging to the specified channel. 58 */ 59 static inline efx_qword_t * 60 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index) 61 { 62 return ((efx_qword_t *)(tx_queue->txd.addr)) + index; 63 } 64 65 /* Report whether this TX queue would be empty for the given write_count. 66 * May return false negative. 67 */ 68 static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue, unsigned int write_count) 69 { 70 unsigned int empty_read_count = READ_ONCE(tx_queue->empty_read_count); 71 72 if (empty_read_count == 0) 73 return false; 74 75 return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0; 76 } 77 78 int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, struct sk_buff *skb, 79 bool *data_mapped); 80 81 /* Decide whether to push a TX descriptor to the NIC vs merely writing 82 * the doorbell. This can reduce latency when we are adding a single 83 * descriptor to an empty queue, but is otherwise pointless. 84 * We use the write_count used for the last doorbell push, to get the 85 * NIC's view of the tx queue. 86 */ 87 static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue, 88 unsigned int write_count) 89 { 90 bool was_empty = efx_nic_tx_is_empty(tx_queue, write_count); 91 92 tx_queue->empty_read_count = 0; 93 return was_empty && tx_queue->write_count - write_count == 1; 94 } 95 96 /* Returns a pointer to the specified descriptor in the RX descriptor queue */ 97 static inline efx_qword_t * 98 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 99 { 100 return ((efx_qword_t *)(rx_queue->rxd.addr)) + index; 101 } 102 103 /* Alignment of PCIe DMA boundaries (4KB) */ 104 #define EFX_PAGE_SIZE 4096 105 /* Size and alignment of buffer table entries (same) */ 106 #define EFX_BUF_SIZE EFX_PAGE_SIZE 107 108 /* NIC-generic software stats */ 109 enum { 110 GENERIC_STAT_rx_noskb_drops, 111 GENERIC_STAT_rx_nodesc_trunc, 112 GENERIC_STAT_COUNT 113 }; 114 115 #define EFX_GENERIC_SW_STAT(ext_name) \ 116 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } 117 118 /* TX data path */ 119 static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue) 120 { 121 return tx_queue->efx->type->tx_probe(tx_queue); 122 } 123 static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue) 124 { 125 tx_queue->efx->type->tx_init(tx_queue); 126 } 127 static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue) 128 { 129 if (tx_queue->efx->type->tx_remove) 130 tx_queue->efx->type->tx_remove(tx_queue); 131 } 132 static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue) 133 { 134 tx_queue->efx->type->tx_write(tx_queue); 135 } 136 137 /* RX data path */ 138 static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue) 139 { 140 return rx_queue->efx->type->rx_probe(rx_queue); 141 } 142 static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue) 143 { 144 rx_queue->efx->type->rx_init(rx_queue); 145 } 146 static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue) 147 { 148 rx_queue->efx->type->rx_remove(rx_queue); 149 } 150 static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue) 151 { 152 rx_queue->efx->type->rx_write(rx_queue); 153 } 154 static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue) 155 { 156 rx_queue->efx->type->rx_defer_refill(rx_queue); 157 } 158 159 /* Event data path */ 160 static inline int efx_nic_probe_eventq(struct efx_channel *channel) 161 { 162 return channel->efx->type->ev_probe(channel); 163 } 164 static inline int efx_nic_init_eventq(struct efx_channel *channel) 165 { 166 return channel->efx->type->ev_init(channel); 167 } 168 static inline void efx_nic_fini_eventq(struct efx_channel *channel) 169 { 170 channel->efx->type->ev_fini(channel); 171 } 172 static inline void efx_nic_remove_eventq(struct efx_channel *channel) 173 { 174 channel->efx->type->ev_remove(channel); 175 } 176 static inline int 177 efx_nic_process_eventq(struct efx_channel *channel, int quota) 178 { 179 return channel->efx->type->ev_process(channel, quota); 180 } 181 static inline void efx_nic_eventq_read_ack(struct efx_channel *channel) 182 { 183 channel->efx->type->ev_read_ack(channel); 184 } 185 186 void efx_nic_event_test_start(struct efx_channel *channel); 187 188 bool efx_nic_event_present(struct efx_channel *channel); 189 190 static inline void efx_sensor_event(struct efx_nic *efx, efx_qword_t *ev) 191 { 192 if (efx->type->sensor_event) 193 efx->type->sensor_event(efx, ev); 194 } 195 196 static inline unsigned int efx_rx_recycle_ring_size(const struct efx_nic *efx) 197 { 198 return efx->type->rx_recycle_ring_size(efx); 199 } 200 201 /* Some statistics are computed as A - B where A and B each increase 202 * linearly with some hardware counter(s) and the counters are read 203 * asynchronously. If the counters contributing to B are always read 204 * after those contributing to A, the computed value may be lower than 205 * the true value by some variable amount, and may decrease between 206 * subsequent computations. 207 * 208 * We should never allow statistics to decrease or to exceed the true 209 * value. Since the computed value will never be greater than the 210 * true value, we can achieve this by only storing the computed value 211 * when it increases. 212 */ 213 static inline void efx_update_diff_stat(u64 *stat, u64 diff) 214 { 215 if ((s64)(diff - *stat) > 0) 216 *stat = diff; 217 } 218 219 /* Interrupts */ 220 int efx_nic_init_interrupt(struct efx_nic *efx); 221 int efx_nic_irq_test_start(struct efx_nic *efx); 222 void efx_nic_fini_interrupt(struct efx_nic *efx); 223 224 static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel) 225 { 226 return READ_ONCE(channel->event_test_cpu); 227 } 228 static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx) 229 { 230 return READ_ONCE(efx->last_irq_cpu); 231 } 232 233 /* Global Resources */ 234 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, 235 unsigned int len, gfp_t gfp_flags); 236 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer); 237 238 size_t efx_nic_get_regs_len(struct efx_nic *efx); 239 void efx_nic_get_regs(struct efx_nic *efx, void *buf); 240 241 #define EFX_MC_STATS_GENERATION_INVALID ((__force __le64)(-1)) 242 243 size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count, 244 const unsigned long *mask, u8 **names); 245 int efx_nic_copy_stats(struct efx_nic *efx, __le64 *dest); 246 void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count, 247 const unsigned long *mask, u64 *stats, 248 const void *dma_buf, bool accumulate); 249 void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat); 250 static inline size_t efx_nic_update_stats_atomic(struct efx_nic *efx, u64 *full_stats, 251 struct rtnl_link_stats64 *core_stats) 252 { 253 if (efx->type->update_stats_atomic) 254 return efx->type->update_stats_atomic(efx, full_stats, core_stats); 255 return efx->type->update_stats(efx, full_stats, core_stats); 256 } 257 258 #define EFX_MAX_FLUSH_TIME 5000 259 260 #endif /* EFX_NIC_COMMON_H */ 261