1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 /* Common definitions for all Efx net driver code */ 12 13 #ifndef EFX_NET_DRIVER_H 14 #define EFX_NET_DRIVER_H 15 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ethtool.h> 19 #include <linux/if_vlan.h> 20 #include <linux/timer.h> 21 #include <linux/mdio.h> 22 #include <linux/list.h> 23 #include <linux/pci.h> 24 #include <linux/device.h> 25 #include <linux/highmem.h> 26 #include <linux/workqueue.h> 27 #include <linux/mutex.h> 28 #include <linux/rwsem.h> 29 #include <linux/vmalloc.h> 30 #include <linux/i2c.h> 31 #include <linux/mtd/mtd.h> 32 #include <net/busy_poll.h> 33 34 #include "enum.h" 35 #include "bitfield.h" 36 #include "filter.h" 37 38 /************************************************************************** 39 * 40 * Build definitions 41 * 42 **************************************************************************/ 43 44 #define EFX_DRIVER_VERSION "4.0" 45 46 #ifdef DEBUG 47 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) 48 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) 49 #else 50 #define EFX_BUG_ON_PARANOID(x) do {} while (0) 51 #define EFX_WARN_ON_PARANOID(x) do {} while (0) 52 #endif 53 54 /************************************************************************** 55 * 56 * Efx data structures 57 * 58 **************************************************************************/ 59 60 #define EFX_MAX_CHANNELS 32U 61 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS 62 #define EFX_EXTRA_CHANNEL_IOV 0 63 #define EFX_EXTRA_CHANNEL_PTP 1 64 #define EFX_MAX_EXTRA_CHANNELS 2U 65 66 /* Checksum generation is a per-queue option in hardware, so each 67 * queue visible to the networking core is backed by two hardware TX 68 * queues. */ 69 #define EFX_MAX_TX_TC 2 70 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) 71 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */ 72 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */ 73 #define EFX_TXQ_TYPES 4 74 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS) 75 76 /* Maximum possible MTU the driver supports */ 77 #define EFX_MAX_MTU (9 * 1024) 78 79 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page, 80 * and should be a multiple of the cache line size. 81 */ 82 #define EFX_RX_USR_BUF_SIZE (2048 - 256) 83 84 /* If possible, we should ensure cache line alignment at start and end 85 * of every buffer. Otherwise, we just need to ensure 4-byte 86 * alignment of the network header. 87 */ 88 #if NET_IP_ALIGN == 0 89 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES 90 #else 91 #define EFX_RX_BUF_ALIGNMENT 4 92 #endif 93 94 /* Forward declare Precision Time Protocol (PTP) support structure. */ 95 struct efx_ptp_data; 96 struct hwtstamp_config; 97 98 struct efx_self_tests; 99 100 /** 101 * struct efx_buffer - A general-purpose DMA buffer 102 * @addr: host base address of the buffer 103 * @dma_addr: DMA base address of the buffer 104 * @len: Buffer length, in bytes 105 * 106 * The NIC uses these buffers for its interrupt status registers and 107 * MAC stats dumps. 108 */ 109 struct efx_buffer { 110 void *addr; 111 dma_addr_t dma_addr; 112 unsigned int len; 113 }; 114 115 /** 116 * struct efx_special_buffer - DMA buffer entered into buffer table 117 * @buf: Standard &struct efx_buffer 118 * @index: Buffer index within controller;s buffer table 119 * @entries: Number of buffer table entries 120 * 121 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE. 122 * Event and descriptor rings are addressed via one or more buffer 123 * table entries (and so can be physically non-contiguous, although we 124 * currently do not take advantage of that). On Falcon and Siena we 125 * have to take care of allocating and initialising the entries 126 * ourselves. On later hardware this is managed by the firmware and 127 * @index and @entries are left as 0. 128 */ 129 struct efx_special_buffer { 130 struct efx_buffer buf; 131 unsigned int index; 132 unsigned int entries; 133 }; 134 135 /** 136 * struct efx_tx_buffer - buffer state for a TX descriptor 137 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be 138 * freed when descriptor completes 139 * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be 140 * freed when descriptor completes. 141 * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor. 142 * @dma_addr: DMA address of the fragment. 143 * @flags: Flags for allocation and DMA mapping type 144 * @len: Length of this fragment. 145 * This field is zero when the queue slot is empty. 146 * @unmap_len: Length of this fragment to unmap 147 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping. 148 * Only valid if @unmap_len != 0. 149 */ 150 struct efx_tx_buffer { 151 union { 152 const struct sk_buff *skb; 153 void *heap_buf; 154 }; 155 union { 156 efx_qword_t option; 157 dma_addr_t dma_addr; 158 }; 159 unsigned short flags; 160 unsigned short len; 161 unsigned short unmap_len; 162 unsigned short dma_offset; 163 }; 164 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */ 165 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */ 166 #define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */ 167 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */ 168 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */ 169 170 /** 171 * struct efx_tx_queue - An Efx TX queue 172 * 173 * This is a ring buffer of TX fragments. 174 * Since the TX completion path always executes on the same 175 * CPU and the xmit path can operate on different CPUs, 176 * performance is increased by ensuring that the completion 177 * path and the xmit path operate on different cache lines. 178 * This is particularly important if the xmit path is always 179 * executing on one CPU which is different from the completion 180 * path. There is also a cache line for members which are 181 * read but not written on the fast path. 182 * 183 * @efx: The associated Efx NIC 184 * @queue: DMA queue number 185 * @channel: The associated channel 186 * @core_txq: The networking core TX queue structure 187 * @buffer: The software buffer ring 188 * @tsoh_page: Array of pages of TSO header buffers 189 * @txd: The hardware descriptor ring 190 * @ptr_mask: The size of the ring minus 1. 191 * @piobuf: PIO buffer region for this TX queue (shared with its partner). 192 * Size of the region is efx_piobuf_size. 193 * @piobuf_offset: Buffer offset to be specified in PIO descriptors 194 * @initialised: Has hardware queue been initialised? 195 * @read_count: Current read pointer. 196 * This is the number of buffers that have been removed from both rings. 197 * @old_write_count: The value of @write_count when last checked. 198 * This is here for performance reasons. The xmit path will 199 * only get the up-to-date value of @write_count if this 200 * variable indicates that the queue is empty. This is to 201 * avoid cache-line ping-pong between the xmit path and the 202 * completion path. 203 * @merge_events: Number of TX merged completion events 204 * @insert_count: Current insert pointer 205 * This is the number of buffers that have been added to the 206 * software ring. 207 * @write_count: Current write pointer 208 * This is the number of buffers that have been added to the 209 * hardware ring. 210 * @old_read_count: The value of read_count when last checked. 211 * This is here for performance reasons. The xmit path will 212 * only get the up-to-date value of read_count if this 213 * variable indicates that the queue is full. This is to 214 * avoid cache-line ping-pong between the xmit path and the 215 * completion path. 216 * @tso_bursts: Number of times TSO xmit invoked by kernel 217 * @tso_long_headers: Number of packets with headers too long for standard 218 * blocks 219 * @tso_packets: Number of packets via the TSO xmit path 220 * @pushes: Number of times the TX push feature has been used 221 * @pio_packets: Number of times the TX PIO feature has been used 222 * @empty_read_count: If the completion path has seen the queue as empty 223 * and the transmission path has not yet checked this, the value of 224 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. 225 */ 226 struct efx_tx_queue { 227 /* Members which don't change on the fast path */ 228 struct efx_nic *efx ____cacheline_aligned_in_smp; 229 unsigned queue; 230 struct efx_channel *channel; 231 struct netdev_queue *core_txq; 232 struct efx_tx_buffer *buffer; 233 struct efx_buffer *tsoh_page; 234 struct efx_special_buffer txd; 235 unsigned int ptr_mask; 236 void __iomem *piobuf; 237 unsigned int piobuf_offset; 238 bool initialised; 239 240 /* Members used mainly on the completion path */ 241 unsigned int read_count ____cacheline_aligned_in_smp; 242 unsigned int old_write_count; 243 unsigned int merge_events; 244 unsigned int bytes_compl; 245 unsigned int pkts_compl; 246 247 /* Members used only on the xmit path */ 248 unsigned int insert_count ____cacheline_aligned_in_smp; 249 unsigned int write_count; 250 unsigned int old_read_count; 251 unsigned int tso_bursts; 252 unsigned int tso_long_headers; 253 unsigned int tso_packets; 254 unsigned int pushes; 255 unsigned int pio_packets; 256 /* Statistics to supplement MAC stats */ 257 unsigned long tx_packets; 258 259 /* Members shared between paths and sometimes updated */ 260 unsigned int empty_read_count ____cacheline_aligned_in_smp; 261 #define EFX_EMPTY_COUNT_VALID 0x80000000 262 atomic_t flush_outstanding; 263 }; 264 265 /** 266 * struct efx_rx_buffer - An Efx RX data buffer 267 * @dma_addr: DMA base address of the buffer 268 * @page: The associated page buffer. 269 * Will be %NULL if the buffer slot is currently free. 270 * @page_offset: If pending: offset in @page of DMA base address. 271 * If completed: offset in @page of Ethernet header. 272 * @len: If pending: length for DMA descriptor. 273 * If completed: received length, excluding hash prefix. 274 * @flags: Flags for buffer and packet state. These are only set on the 275 * first buffer of a scattered packet. 276 */ 277 struct efx_rx_buffer { 278 dma_addr_t dma_addr; 279 struct page *page; 280 u16 page_offset; 281 u16 len; 282 u16 flags; 283 }; 284 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001 285 #define EFX_RX_PKT_CSUMMED 0x0002 286 #define EFX_RX_PKT_DISCARD 0x0004 287 #define EFX_RX_PKT_TCP 0x0040 288 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */ 289 290 /** 291 * struct efx_rx_page_state - Page-based rx buffer state 292 * 293 * Inserted at the start of every page allocated for receive buffers. 294 * Used to facilitate sharing dma mappings between recycled rx buffers 295 * and those passed up to the kernel. 296 * 297 * @dma_addr: The dma address of this page. 298 */ 299 struct efx_rx_page_state { 300 dma_addr_t dma_addr; 301 302 unsigned int __pad[0] ____cacheline_aligned; 303 }; 304 305 /** 306 * struct efx_rx_queue - An Efx RX queue 307 * @efx: The associated Efx NIC 308 * @core_index: Index of network core RX queue. Will be >= 0 iff this 309 * is associated with a real RX queue. 310 * @buffer: The software buffer ring 311 * @rxd: The hardware descriptor ring 312 * @ptr_mask: The size of the ring minus 1. 313 * @refill_enabled: Enable refill whenever fill level is low 314 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as 315 * @rxq_flush_pending. 316 * @added_count: Number of buffers added to the receive queue. 317 * @notified_count: Number of buffers given to NIC (<= @added_count). 318 * @removed_count: Number of buffers removed from the receive queue. 319 * @scatter_n: Used by NIC specific receive code. 320 * @scatter_len: Used by NIC specific receive code. 321 * @page_ring: The ring to store DMA mapped pages for reuse. 322 * @page_add: Counter to calculate the write pointer for the recycle ring. 323 * @page_remove: Counter to calculate the read pointer for the recycle ring. 324 * @page_recycle_count: The number of pages that have been recycled. 325 * @page_recycle_failed: The number of pages that couldn't be recycled because 326 * the kernel still held a reference to them. 327 * @page_recycle_full: The number of pages that were released because the 328 * recycle ring was full. 329 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1. 330 * @max_fill: RX descriptor maximum fill level (<= ring size) 331 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill 332 * (<= @max_fill) 333 * @min_fill: RX descriptor minimum non-zero fill level. 334 * This records the minimum fill level observed when a ring 335 * refill was triggered. 336 * @recycle_count: RX buffer recycle counter. 337 * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). 338 */ 339 struct efx_rx_queue { 340 struct efx_nic *efx; 341 int core_index; 342 struct efx_rx_buffer *buffer; 343 struct efx_special_buffer rxd; 344 unsigned int ptr_mask; 345 bool refill_enabled; 346 bool flush_pending; 347 348 unsigned int added_count; 349 unsigned int notified_count; 350 unsigned int removed_count; 351 unsigned int scatter_n; 352 unsigned int scatter_len; 353 struct page **page_ring; 354 unsigned int page_add; 355 unsigned int page_remove; 356 unsigned int page_recycle_count; 357 unsigned int page_recycle_failed; 358 unsigned int page_recycle_full; 359 unsigned int page_ptr_mask; 360 unsigned int max_fill; 361 unsigned int fast_fill_trigger; 362 unsigned int min_fill; 363 unsigned int min_overfill; 364 unsigned int recycle_count; 365 struct timer_list slow_fill; 366 unsigned int slow_fill_count; 367 /* Statistics to supplement MAC stats */ 368 unsigned long rx_packets; 369 }; 370 371 enum efx_sync_events_state { 372 SYNC_EVENTS_DISABLED = 0, 373 SYNC_EVENTS_QUIESCENT, 374 SYNC_EVENTS_REQUESTED, 375 SYNC_EVENTS_VALID, 376 }; 377 378 /** 379 * struct efx_channel - An Efx channel 380 * 381 * A channel comprises an event queue, at least one TX queue, at least 382 * one RX queue, and an associated tasklet for processing the event 383 * queue. 384 * 385 * @efx: Associated Efx NIC 386 * @channel: Channel instance number 387 * @type: Channel type definition 388 * @eventq_init: Event queue initialised flag 389 * @enabled: Channel enabled indicator 390 * @irq: IRQ number (MSI and MSI-X only) 391 * @irq_moderation: IRQ moderation value (in hardware ticks) 392 * @napi_dev: Net device used with NAPI 393 * @napi_str: NAPI control structure 394 * @state: state for NAPI vs busy polling 395 * @state_lock: lock protecting @state 396 * @eventq: Event queue buffer 397 * @eventq_mask: Event queue pointer mask 398 * @eventq_read_ptr: Event queue read pointer 399 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel 400 * @irq_count: Number of IRQs since last adaptive moderation decision 401 * @irq_mod_score: IRQ moderation score 402 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors 403 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors 404 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors 405 * @n_rx_mcast_mismatch: Count of unmatched multicast frames 406 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors 407 * @n_rx_overlength: Count of RX_OVERLENGTH errors 408 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun 409 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to 410 * lack of descriptors 411 * @n_rx_merge_events: Number of RX merged completion events 412 * @n_rx_merge_packets: Number of RX packets completed by merged events 413 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by 414 * __efx_rx_packet(), or zero if there is none 415 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered 416 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0 417 * @rx_queue: RX queue for this channel 418 * @tx_queue: TX queues for this channel 419 * @sync_events_state: Current state of sync events on this channel 420 * @sync_timestamp_major: Major part of the last ptp sync event 421 * @sync_timestamp_minor: Minor part of the last ptp sync event 422 */ 423 struct efx_channel { 424 struct efx_nic *efx; 425 int channel; 426 const struct efx_channel_type *type; 427 bool eventq_init; 428 bool enabled; 429 int irq; 430 unsigned int irq_moderation; 431 struct net_device *napi_dev; 432 struct napi_struct napi_str; 433 #ifdef CONFIG_NET_RX_BUSY_POLL 434 unsigned int state; 435 spinlock_t state_lock; 436 #define EFX_CHANNEL_STATE_IDLE 0 437 #define EFX_CHANNEL_STATE_NAPI (1 << 0) /* NAPI owns this channel */ 438 #define EFX_CHANNEL_STATE_POLL (1 << 1) /* poll owns this channel */ 439 #define EFX_CHANNEL_STATE_DISABLED (1 << 2) /* channel is disabled */ 440 #define EFX_CHANNEL_STATE_NAPI_YIELD (1 << 3) /* NAPI yielded this channel */ 441 #define EFX_CHANNEL_STATE_POLL_YIELD (1 << 4) /* poll yielded this channel */ 442 #define EFX_CHANNEL_OWNED \ 443 (EFX_CHANNEL_STATE_NAPI | EFX_CHANNEL_STATE_POLL) 444 #define EFX_CHANNEL_LOCKED \ 445 (EFX_CHANNEL_OWNED | EFX_CHANNEL_STATE_DISABLED) 446 #define EFX_CHANNEL_USER_PEND \ 447 (EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_POLL_YIELD) 448 #endif /* CONFIG_NET_RX_BUSY_POLL */ 449 struct efx_special_buffer eventq; 450 unsigned int eventq_mask; 451 unsigned int eventq_read_ptr; 452 int event_test_cpu; 453 454 unsigned int irq_count; 455 unsigned int irq_mod_score; 456 #ifdef CONFIG_RFS_ACCEL 457 unsigned int rfs_filters_added; 458 #endif 459 460 unsigned n_rx_tobe_disc; 461 unsigned n_rx_ip_hdr_chksum_err; 462 unsigned n_rx_tcp_udp_chksum_err; 463 unsigned n_rx_mcast_mismatch; 464 unsigned n_rx_frm_trunc; 465 unsigned n_rx_overlength; 466 unsigned n_skbuff_leaks; 467 unsigned int n_rx_nodesc_trunc; 468 unsigned int n_rx_merge_events; 469 unsigned int n_rx_merge_packets; 470 471 unsigned int rx_pkt_n_frags; 472 unsigned int rx_pkt_index; 473 474 struct efx_rx_queue rx_queue; 475 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES]; 476 477 enum efx_sync_events_state sync_events_state; 478 u32 sync_timestamp_major; 479 u32 sync_timestamp_minor; 480 }; 481 482 #ifdef CONFIG_NET_RX_BUSY_POLL 483 static inline void efx_channel_init_lock(struct efx_channel *channel) 484 { 485 spin_lock_init(&channel->state_lock); 486 } 487 488 /* Called from the device poll routine to get ownership of a channel. */ 489 static inline bool efx_channel_lock_napi(struct efx_channel *channel) 490 { 491 bool rc = true; 492 493 spin_lock_bh(&channel->state_lock); 494 if (channel->state & EFX_CHANNEL_LOCKED) { 495 WARN_ON(channel->state & EFX_CHANNEL_STATE_NAPI); 496 channel->state |= EFX_CHANNEL_STATE_NAPI_YIELD; 497 rc = false; 498 } else { 499 /* we don't care if someone yielded */ 500 channel->state = EFX_CHANNEL_STATE_NAPI; 501 } 502 spin_unlock_bh(&channel->state_lock); 503 return rc; 504 } 505 506 static inline void efx_channel_unlock_napi(struct efx_channel *channel) 507 { 508 spin_lock_bh(&channel->state_lock); 509 WARN_ON(channel->state & 510 (EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_NAPI_YIELD)); 511 512 channel->state &= EFX_CHANNEL_STATE_DISABLED; 513 spin_unlock_bh(&channel->state_lock); 514 } 515 516 /* Called from efx_busy_poll(). */ 517 static inline bool efx_channel_lock_poll(struct efx_channel *channel) 518 { 519 bool rc = true; 520 521 spin_lock_bh(&channel->state_lock); 522 if ((channel->state & EFX_CHANNEL_LOCKED)) { 523 channel->state |= EFX_CHANNEL_STATE_POLL_YIELD; 524 rc = false; 525 } else { 526 /* preserve yield marks */ 527 channel->state |= EFX_CHANNEL_STATE_POLL; 528 } 529 spin_unlock_bh(&channel->state_lock); 530 return rc; 531 } 532 533 /* Returns true if NAPI tried to get the channel while it was locked. */ 534 static inline void efx_channel_unlock_poll(struct efx_channel *channel) 535 { 536 spin_lock_bh(&channel->state_lock); 537 WARN_ON(channel->state & EFX_CHANNEL_STATE_NAPI); 538 539 /* will reset state to idle, unless channel is disabled */ 540 channel->state &= EFX_CHANNEL_STATE_DISABLED; 541 spin_unlock_bh(&channel->state_lock); 542 } 543 544 /* True if a socket is polling, even if it did not get the lock. */ 545 static inline bool efx_channel_busy_polling(struct efx_channel *channel) 546 { 547 WARN_ON(!(channel->state & EFX_CHANNEL_OWNED)); 548 return channel->state & EFX_CHANNEL_USER_PEND; 549 } 550 551 static inline void efx_channel_enable(struct efx_channel *channel) 552 { 553 spin_lock_bh(&channel->state_lock); 554 channel->state = EFX_CHANNEL_STATE_IDLE; 555 spin_unlock_bh(&channel->state_lock); 556 } 557 558 /* False if the channel is currently owned. */ 559 static inline bool efx_channel_disable(struct efx_channel *channel) 560 { 561 bool rc = true; 562 563 spin_lock_bh(&channel->state_lock); 564 if (channel->state & EFX_CHANNEL_OWNED) 565 rc = false; 566 channel->state |= EFX_CHANNEL_STATE_DISABLED; 567 spin_unlock_bh(&channel->state_lock); 568 569 return rc; 570 } 571 572 #else /* CONFIG_NET_RX_BUSY_POLL */ 573 574 static inline void efx_channel_init_lock(struct efx_channel *channel) 575 { 576 } 577 578 static inline bool efx_channel_lock_napi(struct efx_channel *channel) 579 { 580 return true; 581 } 582 583 static inline void efx_channel_unlock_napi(struct efx_channel *channel) 584 { 585 } 586 587 static inline bool efx_channel_lock_poll(struct efx_channel *channel) 588 { 589 return false; 590 } 591 592 static inline void efx_channel_unlock_poll(struct efx_channel *channel) 593 { 594 } 595 596 static inline bool efx_channel_busy_polling(struct efx_channel *channel) 597 { 598 return false; 599 } 600 601 static inline void efx_channel_enable(struct efx_channel *channel) 602 { 603 } 604 605 static inline bool efx_channel_disable(struct efx_channel *channel) 606 { 607 return true; 608 } 609 #endif /* CONFIG_NET_RX_BUSY_POLL */ 610 611 /** 612 * struct efx_msi_context - Context for each MSI 613 * @efx: The associated NIC 614 * @index: Index of the channel/IRQ 615 * @name: Name of the channel/IRQ 616 * 617 * Unlike &struct efx_channel, this is never reallocated and is always 618 * safe for the IRQ handler to access. 619 */ 620 struct efx_msi_context { 621 struct efx_nic *efx; 622 unsigned int index; 623 char name[IFNAMSIZ + 6]; 624 }; 625 626 /** 627 * struct efx_channel_type - distinguishes traffic and extra channels 628 * @handle_no_channel: Handle failure to allocate an extra channel 629 * @pre_probe: Set up extra state prior to initialisation 630 * @post_remove: Tear down extra state after finalisation, if allocated. 631 * May be called on channels that have not been probed. 632 * @get_name: Generate the channel's name (used for its IRQ handler) 633 * @copy: Copy the channel state prior to reallocation. May be %NULL if 634 * reallocation is not supported. 635 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb() 636 * @keep_eventq: Flag for whether event queue should be kept initialised 637 * while the device is stopped 638 */ 639 struct efx_channel_type { 640 void (*handle_no_channel)(struct efx_nic *); 641 int (*pre_probe)(struct efx_channel *); 642 void (*post_remove)(struct efx_channel *); 643 void (*get_name)(struct efx_channel *, char *buf, size_t len); 644 struct efx_channel *(*copy)(const struct efx_channel *); 645 bool (*receive_skb)(struct efx_channel *, struct sk_buff *); 646 bool keep_eventq; 647 }; 648 649 enum efx_led_mode { 650 EFX_LED_OFF = 0, 651 EFX_LED_ON = 1, 652 EFX_LED_DEFAULT = 2 653 }; 654 655 #define STRING_TABLE_LOOKUP(val, member) \ 656 ((val) < member ## _max) ? member ## _names[val] : "(invalid)" 657 658 extern const char *const efx_loopback_mode_names[]; 659 extern const unsigned int efx_loopback_mode_max; 660 #define LOOPBACK_MODE(efx) \ 661 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) 662 663 extern const char *const efx_reset_type_names[]; 664 extern const unsigned int efx_reset_type_max; 665 #define RESET_TYPE(type) \ 666 STRING_TABLE_LOOKUP(type, efx_reset_type) 667 668 enum efx_int_mode { 669 /* Be careful if altering to correct macro below */ 670 EFX_INT_MODE_MSIX = 0, 671 EFX_INT_MODE_MSI = 1, 672 EFX_INT_MODE_LEGACY = 2, 673 EFX_INT_MODE_MAX /* Insert any new items before this */ 674 }; 675 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) 676 677 enum nic_state { 678 STATE_UNINIT = 0, /* device being probed/removed or is frozen */ 679 STATE_READY = 1, /* hardware ready and netdev registered */ 680 STATE_DISABLED = 2, /* device disabled due to hardware errors */ 681 STATE_RECOVERY = 3, /* device recovering from PCI error */ 682 }; 683 684 /* Forward declaration */ 685 struct efx_nic; 686 687 /* Pseudo bit-mask flow control field */ 688 #define EFX_FC_RX FLOW_CTRL_RX 689 #define EFX_FC_TX FLOW_CTRL_TX 690 #define EFX_FC_AUTO 4 691 692 /** 693 * struct efx_link_state - Current state of the link 694 * @up: Link is up 695 * @fd: Link is full-duplex 696 * @fc: Actual flow control flags 697 * @speed: Link speed (Mbps) 698 */ 699 struct efx_link_state { 700 bool up; 701 bool fd; 702 u8 fc; 703 unsigned int speed; 704 }; 705 706 static inline bool efx_link_state_equal(const struct efx_link_state *left, 707 const struct efx_link_state *right) 708 { 709 return left->up == right->up && left->fd == right->fd && 710 left->fc == right->fc && left->speed == right->speed; 711 } 712 713 /** 714 * struct efx_phy_operations - Efx PHY operations table 715 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, 716 * efx->loopback_modes. 717 * @init: Initialise PHY 718 * @fini: Shut down PHY 719 * @reconfigure: Reconfigure PHY (e.g. for new link parameters) 720 * @poll: Update @link_state and report whether it changed. 721 * Serialised by the mac_lock. 722 * @get_settings: Get ethtool settings. Serialised by the mac_lock. 723 * @set_settings: Set ethtool settings. Serialised by the mac_lock. 724 * @set_npage_adv: Set abilities advertised in (Extended) Next Page 725 * (only needed where AN bit is set in mmds) 726 * @test_alive: Test that PHY is 'alive' (online) 727 * @test_name: Get the name of a PHY-specific test/result 728 * @run_tests: Run tests and record results as appropriate (offline). 729 * Flags are the ethtool tests flags. 730 */ 731 struct efx_phy_operations { 732 int (*probe) (struct efx_nic *efx); 733 int (*init) (struct efx_nic *efx); 734 void (*fini) (struct efx_nic *efx); 735 void (*remove) (struct efx_nic *efx); 736 int (*reconfigure) (struct efx_nic *efx); 737 bool (*poll) (struct efx_nic *efx); 738 void (*get_settings) (struct efx_nic *efx, 739 struct ethtool_cmd *ecmd); 740 int (*set_settings) (struct efx_nic *efx, 741 struct ethtool_cmd *ecmd); 742 void (*set_npage_adv) (struct efx_nic *efx, u32); 743 int (*test_alive) (struct efx_nic *efx); 744 const char *(*test_name) (struct efx_nic *efx, unsigned int index); 745 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); 746 int (*get_module_eeprom) (struct efx_nic *efx, 747 struct ethtool_eeprom *ee, 748 u8 *data); 749 int (*get_module_info) (struct efx_nic *efx, 750 struct ethtool_modinfo *modinfo); 751 }; 752 753 /** 754 * enum efx_phy_mode - PHY operating mode flags 755 * @PHY_MODE_NORMAL: on and should pass traffic 756 * @PHY_MODE_TX_DISABLED: on with TX disabled 757 * @PHY_MODE_LOW_POWER: set to low power through MDIO 758 * @PHY_MODE_OFF: switched off through external control 759 * @PHY_MODE_SPECIAL: on but will not pass traffic 760 */ 761 enum efx_phy_mode { 762 PHY_MODE_NORMAL = 0, 763 PHY_MODE_TX_DISABLED = 1, 764 PHY_MODE_LOW_POWER = 2, 765 PHY_MODE_OFF = 4, 766 PHY_MODE_SPECIAL = 8, 767 }; 768 769 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) 770 { 771 return !!(mode & ~PHY_MODE_TX_DISABLED); 772 } 773 774 /** 775 * struct efx_hw_stat_desc - Description of a hardware statistic 776 * @name: Name of the statistic as visible through ethtool, or %NULL if 777 * it should not be exposed 778 * @dma_width: Width in bits (0 for non-DMA statistics) 779 * @offset: Offset within stats (ignored for non-DMA statistics) 780 */ 781 struct efx_hw_stat_desc { 782 const char *name; 783 u16 dma_width; 784 u16 offset; 785 }; 786 787 /* Number of bits used in a multicast filter hash address */ 788 #define EFX_MCAST_HASH_BITS 8 789 790 /* Number of (single-bit) entries in a multicast filter hash */ 791 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) 792 793 /* An Efx multicast filter hash */ 794 union efx_multicast_hash { 795 u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; 796 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; 797 }; 798 799 struct vfdi_status; 800 801 /** 802 * struct efx_nic - an Efx NIC 803 * @name: Device name (net device name or bus id before net device registered) 804 * @pci_dev: The PCI device 805 * @node: List node for maintaning primary/secondary function lists 806 * @primary: &struct efx_nic instance for the primary function of this 807 * controller. May be the same structure, and may be %NULL if no 808 * primary function is bound. Serialised by rtnl_lock. 809 * @secondary_list: List of &struct efx_nic instances for the secondary PCI 810 * functions of the controller, if this is for the primary function. 811 * Serialised by rtnl_lock. 812 * @type: Controller type attributes 813 * @legacy_irq: IRQ number 814 * @workqueue: Workqueue for port reconfigures and the HW monitor. 815 * Work items do not hold and must not acquire RTNL. 816 * @workqueue_name: Name of workqueue 817 * @reset_work: Scheduled reset workitem 818 * @membase_phys: Memory BAR value as physical address 819 * @membase: Memory BAR value 820 * @interrupt_mode: Interrupt mode 821 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds 822 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues 823 * @irq_rx_moderation: IRQ moderation time for RX event queues 824 * @msg_enable: Log message enable flags 825 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock. 826 * @reset_pending: Bitmask for pending resets 827 * @tx_queue: TX DMA queues 828 * @rx_queue: RX DMA queues 829 * @channel: Channels 830 * @msi_context: Context for each MSI 831 * @extra_channel_types: Types of extra (non-traffic) channels that 832 * should be allocated for this NIC 833 * @rxq_entries: Size of receive queues requested by user. 834 * @txq_entries: Size of transmit queues requested by user. 835 * @txq_stop_thresh: TX queue fill level at or above which we stop it. 836 * @txq_wake_thresh: TX queue fill level at or below which we wake it. 837 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches 838 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches 839 * @sram_lim_qw: Qword address limit of SRAM 840 * @next_buffer_table: First available buffer table id 841 * @n_channels: Number of channels in use 842 * @n_rx_channels: Number of channels used for RX (= number of RX queues) 843 * @n_tx_channels: Number of channels used for TX 844 * @rx_ip_align: RX DMA address offset to have IP header aligned in 845 * in accordance with NET_IP_ALIGN 846 * @rx_dma_len: Current maximum RX DMA length 847 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer 848 * @rx_buffer_truesize: Amortised allocation size of an RX buffer, 849 * for use in sk_buff::truesize 850 * @rx_prefix_size: Size of RX prefix before packet data 851 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data 852 * (valid only if @rx_prefix_size != 0; always negative) 853 * @rx_packet_len_offset: Offset of RX packet length from start of packet data 854 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative) 855 * @rx_packet_ts_offset: Offset of timestamp from start of packet data 856 * (valid only if channel->sync_timestamps_enabled; always negative) 857 * @rx_hash_key: Toeplitz hash key for RSS 858 * @rx_indir_table: Indirection table for RSS 859 * @rx_scatter: Scatter mode enabled for receives 860 * @int_error_count: Number of internal errors seen recently 861 * @int_error_expire: Time at which error count will be expired 862 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will 863 * acknowledge but do nothing else. 864 * @irq_status: Interrupt status buffer 865 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 866 * @irq_level: IRQ level/index for IRQs not triggered by an event queue 867 * @selftest_work: Work item for asynchronous self-test 868 * @mtd_list: List of MTDs attached to the NIC 869 * @nic_data: Hardware dependent state 870 * @mcdi: Management-Controller-to-Driver Interface state 871 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, 872 * efx_monitor() and efx_reconfigure_port() 873 * @port_enabled: Port enabled indicator. 874 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and 875 * efx_mac_work() with kernel interfaces. Safe to read under any 876 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must 877 * be held to modify it. 878 * @port_initialized: Port initialized? 879 * @net_dev: Operating system network device. Consider holding the rtnl lock 880 * @stats_buffer: DMA buffer for statistics 881 * @phy_type: PHY type 882 * @phy_op: PHY interface 883 * @phy_data: PHY private data (including PHY-specific stats) 884 * @mdio: PHY MDIO interface 885 * @mdio_bus: PHY MDIO bus ID (only used by Siena) 886 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 887 * @link_advertising: Autonegotiation advertising flags 888 * @link_state: Current state of the link 889 * @n_link_state_changes: Number of times the link has changed state 890 * @unicast_filter: Flag for Falcon-arch simple unicast filter. 891 * Protected by @mac_lock. 892 * @multicast_hash: Multicast hash table for Falcon-arch. 893 * Protected by @mac_lock. 894 * @wanted_fc: Wanted flow control flags 895 * @fc_disable: When non-zero flow control is disabled. Typically used to 896 * ensure that network back pressure doesn't delay dma queue flushes. 897 * Serialised by the rtnl lock. 898 * @mac_work: Work item for changing MAC promiscuity and multicast hash 899 * @loopback_mode: Loopback status 900 * @loopback_modes: Supported loopback mode bitmask 901 * @loopback_selftest: Offline self-test private state 902 * @filter_sem: Filter table rw_semaphore, for freeing the table 903 * @filter_lock: Filter table lock, for mere content changes 904 * @filter_state: Architecture-dependent filter table state 905 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS, 906 * indexed by filter ID 907 * @rps_expire_index: Next index to check for expiry in @rps_flow_id 908 * @active_queues: Count of RX and TX queues that haven't been flushed and drained. 909 * @rxq_flush_pending: Count of number of receive queues that need to be flushed. 910 * Decremented when the efx_flush_rx_queue() is called. 911 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet 912 * completed (either success or failure). Not used when MCDI is used to 913 * flush receive queues. 914 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. 915 * @vf_count: Number of VFs intended to be enabled. 916 * @vf_init_count: Number of VFs that have been fully initialised. 917 * @vi_scale: log2 number of vnics per VF. 918 * @ptp_data: PTP state data 919 * @vpd_sn: Serial number read from VPD 920 * @monitor_work: Hardware monitor workitem 921 * @biu_lock: BIU (bus interface unit) lock 922 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This 923 * field is used by efx_test_interrupts() to verify that an 924 * interrupt has occurred. 925 * @stats_lock: Statistics update lock. Must be held when calling 926 * efx_nic_type::{update,start,stop}_stats. 927 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb 928 * @mc_promisc: Whether in multicast promiscuous mode when last changed 929 * 930 * This is stored in the private area of the &struct net_device. 931 */ 932 struct efx_nic { 933 /* The following fields should be written very rarely */ 934 935 char name[IFNAMSIZ]; 936 struct list_head node; 937 struct efx_nic *primary; 938 struct list_head secondary_list; 939 struct pci_dev *pci_dev; 940 unsigned int port_num; 941 const struct efx_nic_type *type; 942 int legacy_irq; 943 bool eeh_disabled_legacy_irq; 944 struct workqueue_struct *workqueue; 945 char workqueue_name[16]; 946 struct work_struct reset_work; 947 resource_size_t membase_phys; 948 void __iomem *membase; 949 950 enum efx_int_mode interrupt_mode; 951 unsigned int timer_quantum_ns; 952 bool irq_rx_adaptive; 953 unsigned int irq_rx_moderation; 954 u32 msg_enable; 955 956 enum nic_state state; 957 unsigned long reset_pending; 958 959 struct efx_channel *channel[EFX_MAX_CHANNELS]; 960 struct efx_msi_context msi_context[EFX_MAX_CHANNELS]; 961 const struct efx_channel_type * 962 extra_channel_type[EFX_MAX_EXTRA_CHANNELS]; 963 964 unsigned rxq_entries; 965 unsigned txq_entries; 966 unsigned int txq_stop_thresh; 967 unsigned int txq_wake_thresh; 968 969 unsigned tx_dc_base; 970 unsigned rx_dc_base; 971 unsigned sram_lim_qw; 972 unsigned next_buffer_table; 973 974 unsigned int max_channels; 975 unsigned int max_tx_channels; 976 unsigned n_channels; 977 unsigned n_rx_channels; 978 unsigned rss_spread; 979 unsigned tx_channel_offset; 980 unsigned n_tx_channels; 981 unsigned int rx_ip_align; 982 unsigned int rx_dma_len; 983 unsigned int rx_buffer_order; 984 unsigned int rx_buffer_truesize; 985 unsigned int rx_page_buf_step; 986 unsigned int rx_bufs_per_page; 987 unsigned int rx_pages_per_batch; 988 unsigned int rx_prefix_size; 989 int rx_packet_hash_offset; 990 int rx_packet_len_offset; 991 int rx_packet_ts_offset; 992 u8 rx_hash_key[40]; 993 u32 rx_indir_table[128]; 994 bool rx_scatter; 995 996 unsigned int_error_count; 997 unsigned long int_error_expire; 998 999 bool irq_soft_enabled; 1000 struct efx_buffer irq_status; 1001 unsigned irq_zero_count; 1002 unsigned irq_level; 1003 struct delayed_work selftest_work; 1004 1005 #ifdef CONFIG_SFC_MTD 1006 struct list_head mtd_list; 1007 #endif 1008 1009 void *nic_data; 1010 struct efx_mcdi_data *mcdi; 1011 1012 struct mutex mac_lock; 1013 struct work_struct mac_work; 1014 bool port_enabled; 1015 1016 bool mc_bist_for_other_fn; 1017 bool port_initialized; 1018 struct net_device *net_dev; 1019 1020 struct efx_buffer stats_buffer; 1021 u64 rx_nodesc_drops_total; 1022 u64 rx_nodesc_drops_while_down; 1023 bool rx_nodesc_drops_prev_state; 1024 1025 unsigned int phy_type; 1026 const struct efx_phy_operations *phy_op; 1027 void *phy_data; 1028 struct mdio_if_info mdio; 1029 unsigned int mdio_bus; 1030 enum efx_phy_mode phy_mode; 1031 1032 u32 link_advertising; 1033 struct efx_link_state link_state; 1034 unsigned int n_link_state_changes; 1035 1036 bool unicast_filter; 1037 union efx_multicast_hash multicast_hash; 1038 u8 wanted_fc; 1039 unsigned fc_disable; 1040 1041 atomic_t rx_reset; 1042 enum efx_loopback_mode loopback_mode; 1043 u64 loopback_modes; 1044 1045 void *loopback_selftest; 1046 1047 struct rw_semaphore filter_sem; 1048 spinlock_t filter_lock; 1049 void *filter_state; 1050 #ifdef CONFIG_RFS_ACCEL 1051 u32 *rps_flow_id; 1052 unsigned int rps_expire_index; 1053 #endif 1054 1055 atomic_t active_queues; 1056 atomic_t rxq_flush_pending; 1057 atomic_t rxq_flush_outstanding; 1058 wait_queue_head_t flush_wq; 1059 1060 #ifdef CONFIG_SFC_SRIOV 1061 unsigned vf_count; 1062 unsigned vf_init_count; 1063 unsigned vi_scale; 1064 #endif 1065 1066 struct efx_ptp_data *ptp_data; 1067 1068 char *vpd_sn; 1069 1070 /* The following fields may be written more often */ 1071 1072 struct delayed_work monitor_work ____cacheline_aligned_in_smp; 1073 spinlock_t biu_lock; 1074 int last_irq_cpu; 1075 spinlock_t stats_lock; 1076 atomic_t n_rx_noskb_drops; 1077 bool mc_promisc; 1078 }; 1079 1080 static inline int efx_dev_registered(struct efx_nic *efx) 1081 { 1082 return efx->net_dev->reg_state == NETREG_REGISTERED; 1083 } 1084 1085 static inline unsigned int efx_port_num(struct efx_nic *efx) 1086 { 1087 return efx->port_num; 1088 } 1089 1090 struct efx_mtd_partition { 1091 struct list_head node; 1092 struct mtd_info mtd; 1093 const char *dev_type_name; 1094 const char *type_name; 1095 char name[IFNAMSIZ + 20]; 1096 }; 1097 1098 /** 1099 * struct efx_nic_type - Efx device type definition 1100 * @mem_bar: Get the memory BAR 1101 * @mem_map_size: Get memory BAR mapped size 1102 * @probe: Probe the controller 1103 * @remove: Free resources allocated by probe() 1104 * @init: Initialise the controller 1105 * @dimension_resources: Dimension controller resources (buffer table, 1106 * and VIs once the available interrupt resources are clear) 1107 * @fini: Shut down the controller 1108 * @monitor: Periodic function for polling link state and hardware monitor 1109 * @map_reset_reason: Map ethtool reset reason to a reset method 1110 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible 1111 * @reset: Reset the controller hardware and possibly the PHY. This will 1112 * be called while the controller is uninitialised. 1113 * @probe_port: Probe the MAC and PHY 1114 * @remove_port: Free resources allocated by probe_port() 1115 * @handle_global_event: Handle a "global" event (may be %NULL) 1116 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues) 1117 * @prepare_flush: Prepare the hardware for flushing the DMA queues 1118 * (for Falcon architecture) 1119 * @finish_flush: Clean up after flushing the DMA queues (for Falcon 1120 * architecture) 1121 * @prepare_flr: Prepare for an FLR 1122 * @finish_flr: Clean up after an FLR 1123 * @describe_stats: Describe statistics for ethtool 1124 * @update_stats: Update statistics not provided by event handling. 1125 * Either argument may be %NULL. 1126 * @start_stats: Start the regular fetching of statistics 1127 * @pull_stats: Pull stats from the NIC and wait until they arrive. 1128 * @stop_stats: Stop the regular fetching of statistics 1129 * @set_id_led: Set state of identifying LED or revert to automatic function 1130 * @push_irq_moderation: Apply interrupt moderation value 1131 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY 1132 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL) 1133 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings 1134 * to the hardware. Serialised by the mac_lock. 1135 * @check_mac_fault: Check MAC fault state. True if fault present. 1136 * @get_wol: Get WoL configuration from driver state 1137 * @set_wol: Push WoL configuration to the NIC 1138 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) 1139 * @test_chip: Test registers. May use efx_farch_test_registers(), and is 1140 * expected to reset the NIC. 1141 * @test_nvram: Test validity of NVRAM contents 1142 * @mcdi_request: Send an MCDI request with the given header and SDU. 1143 * The SDU length may be any value from 0 up to the protocol- 1144 * defined maximum, but its buffer will be padded to a multiple 1145 * of 4 bytes. 1146 * @mcdi_poll_response: Test whether an MCDI response is available. 1147 * @mcdi_read_response: Read the MCDI response PDU. The offset will 1148 * be a multiple of 4. The length may not be, but the buffer 1149 * will be padded so it is safe to round up. 1150 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so, 1151 * return an appropriate error code for aborting any current 1152 * request; otherwise return 0. 1153 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must 1154 * be separately enabled after this. 1155 * @irq_test_generate: Generate a test IRQ 1156 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event 1157 * queue must be separately disabled before this. 1158 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is 1159 * a pointer to the &struct efx_msi_context for the channel. 1160 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument 1161 * is a pointer to the &struct efx_nic. 1162 * @tx_probe: Allocate resources for TX queue 1163 * @tx_init: Initialise TX queue on the NIC 1164 * @tx_remove: Free resources for TX queue 1165 * @tx_write: Write TX descriptors and doorbell 1166 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC 1167 * @rx_probe: Allocate resources for RX queue 1168 * @rx_init: Initialise RX queue on the NIC 1169 * @rx_remove: Free resources for RX queue 1170 * @rx_write: Write RX descriptors and doorbell 1171 * @rx_defer_refill: Generate a refill reminder event 1172 * @ev_probe: Allocate resources for event queue 1173 * @ev_init: Initialise event queue on the NIC 1174 * @ev_fini: Deinitialise event queue on the NIC 1175 * @ev_remove: Free resources for event queue 1176 * @ev_process: Process events for a queue, up to the given NAPI quota 1177 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ 1178 * @ev_test_generate: Generate a test event 1179 * @filter_table_probe: Probe filter capabilities and set up filter software state 1180 * @filter_table_restore: Restore filters removed from hardware 1181 * @filter_table_remove: Remove filters from hardware and tear down software state 1182 * @filter_update_rx_scatter: Update filters after change to rx scatter setting 1183 * @filter_insert: add or replace a filter 1184 * @filter_remove_safe: remove a filter by ID, carefully 1185 * @filter_get_safe: retrieve a filter by ID, carefully 1186 * @filter_clear_rx: Remove all RX filters whose priority is less than or 1187 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO 1188 * @filter_count_rx_used: Get the number of filters in use at a given priority 1189 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1 1190 * @filter_get_rx_ids: Get list of RX filters at a given priority 1191 * @filter_rfs_insert: Add or replace a filter for RFS. This must be 1192 * atomic. The hardware change may be asynchronous but should 1193 * not be delayed for long. It may fail if this can't be done 1194 * atomically. 1195 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS. 1196 * This must check whether the specified table entry is used by RFS 1197 * and that rps_may_expire_flow() returns true for it. 1198 * @mtd_probe: Probe and add MTD partitions associated with this net device, 1199 * using efx_mtd_add() 1200 * @mtd_rename: Set an MTD partition name using the net device name 1201 * @mtd_read: Read from an MTD partition 1202 * @mtd_erase: Erase part of an MTD partition 1203 * @mtd_write: Write to an MTD partition 1204 * @mtd_sync: Wait for write-back to complete on MTD partition. This 1205 * also notifies the driver that a writer has finished using this 1206 * partition. 1207 * @ptp_write_host_time: Send host time to MC as part of sync protocol 1208 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX 1209 * timestamping, possibly only temporarily for the purposes of a reset. 1210 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags 1211 * and tx_type will already have been validated but this operation 1212 * must validate and update rx_filter. 1213 * @set_mac_address: Set the MAC address of the device 1214 * @revision: Hardware architecture revision 1215 * @txd_ptr_tbl_base: TX descriptor ring base address 1216 * @rxd_ptr_tbl_base: RX descriptor ring base address 1217 * @buf_tbl_base: Buffer table base address 1218 * @evq_ptr_tbl_base: Event queue pointer table base address 1219 * @evq_rptr_tbl_base: Event queue read-pointer table base address 1220 * @max_dma_mask: Maximum possible DMA mask 1221 * @rx_prefix_size: Size of RX prefix before packet data 1222 * @rx_hash_offset: Offset of RX flow hash within prefix 1223 * @rx_ts_offset: Offset of timestamp within prefix 1224 * @rx_buffer_padding: Size of padding at end of RX packet 1225 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers 1226 * @always_rx_scatter: NIC will always scatter packets to multiple buffers 1227 * @max_interrupt_mode: Highest capability interrupt mode supported 1228 * from &enum efx_init_mode. 1229 * @timer_period_max: Maximum period of interrupt timer (in ticks) 1230 * @offload_features: net_device feature flags for protocol offload 1231 * features implemented in hardware 1232 * @mcdi_max_ver: Maximum MCDI version supported 1233 * @hwtstamp_filters: Mask of hardware timestamp filter types supported 1234 */ 1235 struct efx_nic_type { 1236 bool is_vf; 1237 unsigned int mem_bar; 1238 unsigned int (*mem_map_size)(struct efx_nic *efx); 1239 int (*probe)(struct efx_nic *efx); 1240 void (*remove)(struct efx_nic *efx); 1241 int (*init)(struct efx_nic *efx); 1242 int (*dimension_resources)(struct efx_nic *efx); 1243 void (*fini)(struct efx_nic *efx); 1244 void (*monitor)(struct efx_nic *efx); 1245 enum reset_type (*map_reset_reason)(enum reset_type reason); 1246 int (*map_reset_flags)(u32 *flags); 1247 int (*reset)(struct efx_nic *efx, enum reset_type method); 1248 int (*probe_port)(struct efx_nic *efx); 1249 void (*remove_port)(struct efx_nic *efx); 1250 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); 1251 int (*fini_dmaq)(struct efx_nic *efx); 1252 void (*prepare_flush)(struct efx_nic *efx); 1253 void (*finish_flush)(struct efx_nic *efx); 1254 void (*prepare_flr)(struct efx_nic *efx); 1255 void (*finish_flr)(struct efx_nic *efx); 1256 size_t (*describe_stats)(struct efx_nic *efx, u8 *names); 1257 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats, 1258 struct rtnl_link_stats64 *core_stats); 1259 void (*start_stats)(struct efx_nic *efx); 1260 void (*pull_stats)(struct efx_nic *efx); 1261 void (*stop_stats)(struct efx_nic *efx); 1262 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); 1263 void (*push_irq_moderation)(struct efx_channel *channel); 1264 int (*reconfigure_port)(struct efx_nic *efx); 1265 void (*prepare_enable_fc_tx)(struct efx_nic *efx); 1266 int (*reconfigure_mac)(struct efx_nic *efx); 1267 bool (*check_mac_fault)(struct efx_nic *efx); 1268 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); 1269 int (*set_wol)(struct efx_nic *efx, u32 type); 1270 void (*resume_wol)(struct efx_nic *efx); 1271 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests); 1272 int (*test_nvram)(struct efx_nic *efx); 1273 void (*mcdi_request)(struct efx_nic *efx, 1274 const efx_dword_t *hdr, size_t hdr_len, 1275 const efx_dword_t *sdu, size_t sdu_len); 1276 bool (*mcdi_poll_response)(struct efx_nic *efx); 1277 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu, 1278 size_t pdu_offset, size_t pdu_len); 1279 int (*mcdi_poll_reboot)(struct efx_nic *efx); 1280 void (*irq_enable_master)(struct efx_nic *efx); 1281 void (*irq_test_generate)(struct efx_nic *efx); 1282 void (*irq_disable_non_ev)(struct efx_nic *efx); 1283 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id); 1284 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id); 1285 int (*tx_probe)(struct efx_tx_queue *tx_queue); 1286 void (*tx_init)(struct efx_tx_queue *tx_queue); 1287 void (*tx_remove)(struct efx_tx_queue *tx_queue); 1288 void (*tx_write)(struct efx_tx_queue *tx_queue); 1289 int (*rx_push_rss_config)(struct efx_nic *efx, bool user, 1290 const u32 *rx_indir_table); 1291 int (*rx_probe)(struct efx_rx_queue *rx_queue); 1292 void (*rx_init)(struct efx_rx_queue *rx_queue); 1293 void (*rx_remove)(struct efx_rx_queue *rx_queue); 1294 void (*rx_write)(struct efx_rx_queue *rx_queue); 1295 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue); 1296 int (*ev_probe)(struct efx_channel *channel); 1297 int (*ev_init)(struct efx_channel *channel); 1298 void (*ev_fini)(struct efx_channel *channel); 1299 void (*ev_remove)(struct efx_channel *channel); 1300 int (*ev_process)(struct efx_channel *channel, int quota); 1301 void (*ev_read_ack)(struct efx_channel *channel); 1302 void (*ev_test_generate)(struct efx_channel *channel); 1303 int (*filter_table_probe)(struct efx_nic *efx); 1304 void (*filter_table_restore)(struct efx_nic *efx); 1305 void (*filter_table_remove)(struct efx_nic *efx); 1306 void (*filter_update_rx_scatter)(struct efx_nic *efx); 1307 s32 (*filter_insert)(struct efx_nic *efx, 1308 struct efx_filter_spec *spec, bool replace); 1309 int (*filter_remove_safe)(struct efx_nic *efx, 1310 enum efx_filter_priority priority, 1311 u32 filter_id); 1312 int (*filter_get_safe)(struct efx_nic *efx, 1313 enum efx_filter_priority priority, 1314 u32 filter_id, struct efx_filter_spec *); 1315 int (*filter_clear_rx)(struct efx_nic *efx, 1316 enum efx_filter_priority priority); 1317 u32 (*filter_count_rx_used)(struct efx_nic *efx, 1318 enum efx_filter_priority priority); 1319 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx); 1320 s32 (*filter_get_rx_ids)(struct efx_nic *efx, 1321 enum efx_filter_priority priority, 1322 u32 *buf, u32 size); 1323 #ifdef CONFIG_RFS_ACCEL 1324 s32 (*filter_rfs_insert)(struct efx_nic *efx, 1325 struct efx_filter_spec *spec); 1326 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id, 1327 unsigned int index); 1328 #endif 1329 #ifdef CONFIG_SFC_MTD 1330 int (*mtd_probe)(struct efx_nic *efx); 1331 void (*mtd_rename)(struct efx_mtd_partition *part); 1332 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len, 1333 size_t *retlen, u8 *buffer); 1334 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len); 1335 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len, 1336 size_t *retlen, const u8 *buffer); 1337 int (*mtd_sync)(struct mtd_info *mtd); 1338 #endif 1339 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time); 1340 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp); 1341 int (*ptp_set_ts_config)(struct efx_nic *efx, 1342 struct hwtstamp_config *init); 1343 int (*sriov_configure)(struct efx_nic *efx, int num_vfs); 1344 int (*sriov_init)(struct efx_nic *efx); 1345 void (*sriov_fini)(struct efx_nic *efx); 1346 bool (*sriov_wanted)(struct efx_nic *efx); 1347 void (*sriov_reset)(struct efx_nic *efx); 1348 void (*sriov_flr)(struct efx_nic *efx, unsigned vf_i); 1349 int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, u8 *mac); 1350 int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan, 1351 u8 qos); 1352 int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i, 1353 bool spoofchk); 1354 int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i, 1355 struct ifla_vf_info *ivi); 1356 int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i, 1357 int link_state); 1358 int (*sriov_get_phys_port_id)(struct efx_nic *efx, 1359 struct netdev_phys_item_id *ppid); 1360 int (*vswitching_probe)(struct efx_nic *efx); 1361 int (*vswitching_restore)(struct efx_nic *efx); 1362 void (*vswitching_remove)(struct efx_nic *efx); 1363 int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr); 1364 int (*set_mac_address)(struct efx_nic *efx); 1365 1366 int revision; 1367 unsigned int txd_ptr_tbl_base; 1368 unsigned int rxd_ptr_tbl_base; 1369 unsigned int buf_tbl_base; 1370 unsigned int evq_ptr_tbl_base; 1371 unsigned int evq_rptr_tbl_base; 1372 u64 max_dma_mask; 1373 unsigned int rx_prefix_size; 1374 unsigned int rx_hash_offset; 1375 unsigned int rx_ts_offset; 1376 unsigned int rx_buffer_padding; 1377 bool can_rx_scatter; 1378 bool always_rx_scatter; 1379 unsigned int max_interrupt_mode; 1380 unsigned int timer_period_max; 1381 netdev_features_t offload_features; 1382 int mcdi_max_ver; 1383 unsigned int max_rx_ip_filters; 1384 u32 hwtstamp_filters; 1385 }; 1386 1387 /************************************************************************** 1388 * 1389 * Prototypes and inline functions 1390 * 1391 *************************************************************************/ 1392 1393 static inline struct efx_channel * 1394 efx_get_channel(struct efx_nic *efx, unsigned index) 1395 { 1396 EFX_BUG_ON_PARANOID(index >= efx->n_channels); 1397 return efx->channel[index]; 1398 } 1399 1400 /* Iterate over all used channels */ 1401 #define efx_for_each_channel(_channel, _efx) \ 1402 for (_channel = (_efx)->channel[0]; \ 1403 _channel; \ 1404 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ 1405 (_efx)->channel[_channel->channel + 1] : NULL) 1406 1407 /* Iterate over all used channels in reverse */ 1408 #define efx_for_each_channel_rev(_channel, _efx) \ 1409 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ 1410 _channel; \ 1411 _channel = _channel->channel ? \ 1412 (_efx)->channel[_channel->channel - 1] : NULL) 1413 1414 static inline struct efx_tx_queue * 1415 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) 1416 { 1417 EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || 1418 type >= EFX_TXQ_TYPES); 1419 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; 1420 } 1421 1422 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) 1423 { 1424 return channel->channel - channel->efx->tx_channel_offset < 1425 channel->efx->n_tx_channels; 1426 } 1427 1428 static inline struct efx_tx_queue * 1429 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) 1430 { 1431 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) || 1432 type >= EFX_TXQ_TYPES); 1433 return &channel->tx_queue[type]; 1434 } 1435 1436 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue) 1437 { 1438 return !(tx_queue->efx->net_dev->num_tc < 2 && 1439 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI); 1440 } 1441 1442 /* Iterate over all TX queues belonging to a channel */ 1443 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ 1444 if (!efx_channel_has_tx_queues(_channel)) \ 1445 ; \ 1446 else \ 1447 for (_tx_queue = (_channel)->tx_queue; \ 1448 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \ 1449 efx_tx_queue_used(_tx_queue); \ 1450 _tx_queue++) 1451 1452 /* Iterate over all possible TX queues belonging to a channel */ 1453 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ 1454 if (!efx_channel_has_tx_queues(_channel)) \ 1455 ; \ 1456 else \ 1457 for (_tx_queue = (_channel)->tx_queue; \ 1458 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ 1459 _tx_queue++) 1460 1461 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) 1462 { 1463 return channel->rx_queue.core_index >= 0; 1464 } 1465 1466 static inline struct efx_rx_queue * 1467 efx_channel_get_rx_queue(struct efx_channel *channel) 1468 { 1469 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel)); 1470 return &channel->rx_queue; 1471 } 1472 1473 /* Iterate over all RX queues belonging to a channel */ 1474 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ 1475 if (!efx_channel_has_rx_queue(_channel)) \ 1476 ; \ 1477 else \ 1478 for (_rx_queue = &(_channel)->rx_queue; \ 1479 _rx_queue; \ 1480 _rx_queue = NULL) 1481 1482 static inline struct efx_channel * 1483 efx_rx_queue_channel(struct efx_rx_queue *rx_queue) 1484 { 1485 return container_of(rx_queue, struct efx_channel, rx_queue); 1486 } 1487 1488 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) 1489 { 1490 return efx_rx_queue_channel(rx_queue)->channel; 1491 } 1492 1493 /* Returns a pointer to the specified receive buffer in the RX 1494 * descriptor queue. 1495 */ 1496 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, 1497 unsigned int index) 1498 { 1499 return &rx_queue->buffer[index]; 1500 } 1501 1502 /** 1503 * EFX_MAX_FRAME_LEN - calculate maximum frame length 1504 * 1505 * This calculates the maximum frame length that will be used for a 1506 * given MTU. The frame length will be equal to the MTU plus a 1507 * constant amount of header space and padding. This is the quantity 1508 * that the net driver will program into the MAC as the maximum frame 1509 * length. 1510 * 1511 * The 10G MAC requires 8-byte alignment on the frame 1512 * length, so we round up to the nearest 8. 1513 * 1514 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an 1515 * XGMII cycle). If the frame length reaches the maximum value in the 1516 * same cycle, the XMAC can miss the IPG altogether. We work around 1517 * this by adding a further 16 bytes. 1518 */ 1519 #define EFX_MAX_FRAME_LEN(mtu) \ 1520 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16) 1521 1522 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb) 1523 { 1524 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP; 1525 } 1526 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb) 1527 { 1528 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1529 } 1530 1531 #endif /* EFX_NET_DRIVER_H */ 1532