1 /**************************************************************************** 2 * Driver for Solarflare Solarstorm network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2011 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 /* Common definitions for all Efx net driver code */ 12 13 #ifndef EFX_NET_DRIVER_H 14 #define EFX_NET_DRIVER_H 15 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ethtool.h> 19 #include <linux/if_vlan.h> 20 #include <linux/timer.h> 21 #include <linux/mdio.h> 22 #include <linux/list.h> 23 #include <linux/pci.h> 24 #include <linux/device.h> 25 #include <linux/highmem.h> 26 #include <linux/workqueue.h> 27 #include <linux/mutex.h> 28 #include <linux/vmalloc.h> 29 #include <linux/i2c.h> 30 31 #include "enum.h" 32 #include "bitfield.h" 33 34 /************************************************************************** 35 * 36 * Build definitions 37 * 38 **************************************************************************/ 39 40 #define EFX_DRIVER_VERSION "3.2" 41 42 #ifdef DEBUG 43 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) 44 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) 45 #else 46 #define EFX_BUG_ON_PARANOID(x) do {} while (0) 47 #define EFX_WARN_ON_PARANOID(x) do {} while (0) 48 #endif 49 50 /************************************************************************** 51 * 52 * Efx data structures 53 * 54 **************************************************************************/ 55 56 #define EFX_MAX_CHANNELS 32U 57 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS 58 #define EFX_EXTRA_CHANNEL_IOV 0 59 #define EFX_EXTRA_CHANNEL_PTP 1 60 #define EFX_MAX_EXTRA_CHANNELS 2U 61 62 /* Checksum generation is a per-queue option in hardware, so each 63 * queue visible to the networking core is backed by two hardware TX 64 * queues. */ 65 #define EFX_MAX_TX_TC 2 66 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) 67 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */ 68 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */ 69 #define EFX_TXQ_TYPES 4 70 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS) 71 72 /* Forward declare Precision Time Protocol (PTP) support structure. */ 73 struct efx_ptp_data; 74 75 struct efx_self_tests; 76 77 /** 78 * struct efx_special_buffer - An Efx special buffer 79 * @addr: CPU base address of the buffer 80 * @dma_addr: DMA base address of the buffer 81 * @len: Buffer length, in bytes 82 * @index: Buffer index within controller;s buffer table 83 * @entries: Number of buffer table entries 84 * 85 * Special buffers are used for the event queues and the TX and RX 86 * descriptor queues for each channel. They are *not* used for the 87 * actual transmit and receive buffers. 88 */ 89 struct efx_special_buffer { 90 void *addr; 91 dma_addr_t dma_addr; 92 unsigned int len; 93 unsigned int index; 94 unsigned int entries; 95 }; 96 97 /** 98 * struct efx_tx_buffer - buffer state for a TX descriptor 99 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be 100 * freed when descriptor completes 101 * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be 102 * freed when descriptor completes. 103 * @dma_addr: DMA address of the fragment. 104 * @flags: Flags for allocation and DMA mapping type 105 * @len: Length of this fragment. 106 * This field is zero when the queue slot is empty. 107 * @unmap_len: Length of this fragment to unmap 108 */ 109 struct efx_tx_buffer { 110 union { 111 const struct sk_buff *skb; 112 void *heap_buf; 113 }; 114 dma_addr_t dma_addr; 115 unsigned short flags; 116 unsigned short len; 117 unsigned short unmap_len; 118 }; 119 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */ 120 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */ 121 #define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */ 122 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */ 123 124 /** 125 * struct efx_tx_queue - An Efx TX queue 126 * 127 * This is a ring buffer of TX fragments. 128 * Since the TX completion path always executes on the same 129 * CPU and the xmit path can operate on different CPUs, 130 * performance is increased by ensuring that the completion 131 * path and the xmit path operate on different cache lines. 132 * This is particularly important if the xmit path is always 133 * executing on one CPU which is different from the completion 134 * path. There is also a cache line for members which are 135 * read but not written on the fast path. 136 * 137 * @efx: The associated Efx NIC 138 * @queue: DMA queue number 139 * @channel: The associated channel 140 * @core_txq: The networking core TX queue structure 141 * @buffer: The software buffer ring 142 * @tsoh_page: Array of pages of TSO header buffers 143 * @txd: The hardware descriptor ring 144 * @ptr_mask: The size of the ring minus 1. 145 * @initialised: Has hardware queue been initialised? 146 * @read_count: Current read pointer. 147 * This is the number of buffers that have been removed from both rings. 148 * @old_write_count: The value of @write_count when last checked. 149 * This is here for performance reasons. The xmit path will 150 * only get the up-to-date value of @write_count if this 151 * variable indicates that the queue is empty. This is to 152 * avoid cache-line ping-pong between the xmit path and the 153 * completion path. 154 * @insert_count: Current insert pointer 155 * This is the number of buffers that have been added to the 156 * software ring. 157 * @write_count: Current write pointer 158 * This is the number of buffers that have been added to the 159 * hardware ring. 160 * @old_read_count: The value of read_count when last checked. 161 * This is here for performance reasons. The xmit path will 162 * only get the up-to-date value of read_count if this 163 * variable indicates that the queue is full. This is to 164 * avoid cache-line ping-pong between the xmit path and the 165 * completion path. 166 * @tso_bursts: Number of times TSO xmit invoked by kernel 167 * @tso_long_headers: Number of packets with headers too long for standard 168 * blocks 169 * @tso_packets: Number of packets via the TSO xmit path 170 * @pushes: Number of times the TX push feature has been used 171 * @empty_read_count: If the completion path has seen the queue as empty 172 * and the transmission path has not yet checked this, the value of 173 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. 174 */ 175 struct efx_tx_queue { 176 /* Members which don't change on the fast path */ 177 struct efx_nic *efx ____cacheline_aligned_in_smp; 178 unsigned queue; 179 struct efx_channel *channel; 180 struct netdev_queue *core_txq; 181 struct efx_tx_buffer *buffer; 182 struct efx_buffer *tsoh_page; 183 struct efx_special_buffer txd; 184 unsigned int ptr_mask; 185 bool initialised; 186 187 /* Members used mainly on the completion path */ 188 unsigned int read_count ____cacheline_aligned_in_smp; 189 unsigned int old_write_count; 190 191 /* Members used only on the xmit path */ 192 unsigned int insert_count ____cacheline_aligned_in_smp; 193 unsigned int write_count; 194 unsigned int old_read_count; 195 unsigned int tso_bursts; 196 unsigned int tso_long_headers; 197 unsigned int tso_packets; 198 unsigned int pushes; 199 200 /* Members shared between paths and sometimes updated */ 201 unsigned int empty_read_count ____cacheline_aligned_in_smp; 202 #define EFX_EMPTY_COUNT_VALID 0x80000000 203 atomic_t flush_outstanding; 204 }; 205 206 /** 207 * struct efx_rx_buffer - An Efx RX data buffer 208 * @dma_addr: DMA base address of the buffer 209 * @skb: The associated socket buffer. Valid iff !(@flags & %EFX_RX_BUF_PAGE). 210 * Will be %NULL if the buffer slot is currently free. 211 * @page: The associated page buffer. Valif iff @flags & %EFX_RX_BUF_PAGE. 212 * Will be %NULL if the buffer slot is currently free. 213 * @len: Buffer length, in bytes. 214 * @flags: Flags for buffer and packet state. 215 */ 216 struct efx_rx_buffer { 217 dma_addr_t dma_addr; 218 union { 219 struct sk_buff *skb; 220 struct page *page; 221 } u; 222 unsigned int len; 223 u16 flags; 224 }; 225 #define EFX_RX_BUF_PAGE 0x0001 226 #define EFX_RX_PKT_CSUMMED 0x0002 227 #define EFX_RX_PKT_DISCARD 0x0004 228 229 /** 230 * struct efx_rx_page_state - Page-based rx buffer state 231 * 232 * Inserted at the start of every page allocated for receive buffers. 233 * Used to facilitate sharing dma mappings between recycled rx buffers 234 * and those passed up to the kernel. 235 * 236 * @refcnt: Number of struct efx_rx_buffer's referencing this page. 237 * When refcnt falls to zero, the page is unmapped for dma 238 * @dma_addr: The dma address of this page. 239 */ 240 struct efx_rx_page_state { 241 unsigned refcnt; 242 dma_addr_t dma_addr; 243 244 unsigned int __pad[0] ____cacheline_aligned; 245 }; 246 247 /** 248 * struct efx_rx_queue - An Efx RX queue 249 * @efx: The associated Efx NIC 250 * @core_index: Index of network core RX queue. Will be >= 0 iff this 251 * is associated with a real RX queue. 252 * @buffer: The software buffer ring 253 * @rxd: The hardware descriptor ring 254 * @ptr_mask: The size of the ring minus 1. 255 * @enabled: Receive queue enabled indicator. 256 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as 257 * @rxq_flush_pending. 258 * @added_count: Number of buffers added to the receive queue. 259 * @notified_count: Number of buffers given to NIC (<= @added_count). 260 * @removed_count: Number of buffers removed from the receive queue. 261 * @max_fill: RX descriptor maximum fill level (<= ring size) 262 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill 263 * (<= @max_fill) 264 * @min_fill: RX descriptor minimum non-zero fill level. 265 * This records the minimum fill level observed when a ring 266 * refill was triggered. 267 * @alloc_page_count: RX allocation strategy counter. 268 * @alloc_skb_count: RX allocation strategy counter. 269 * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). 270 */ 271 struct efx_rx_queue { 272 struct efx_nic *efx; 273 int core_index; 274 struct efx_rx_buffer *buffer; 275 struct efx_special_buffer rxd; 276 unsigned int ptr_mask; 277 bool enabled; 278 bool flush_pending; 279 280 int added_count; 281 int notified_count; 282 int removed_count; 283 unsigned int max_fill; 284 unsigned int fast_fill_trigger; 285 unsigned int min_fill; 286 unsigned int min_overfill; 287 unsigned int alloc_page_count; 288 unsigned int alloc_skb_count; 289 struct timer_list slow_fill; 290 unsigned int slow_fill_count; 291 }; 292 293 /** 294 * struct efx_buffer - An Efx general-purpose buffer 295 * @addr: host base address of the buffer 296 * @dma_addr: DMA base address of the buffer 297 * @len: Buffer length, in bytes 298 * 299 * The NIC uses these buffers for its interrupt status registers and 300 * MAC stats dumps. 301 */ 302 struct efx_buffer { 303 void *addr; 304 dma_addr_t dma_addr; 305 unsigned int len; 306 }; 307 308 309 enum efx_rx_alloc_method { 310 RX_ALLOC_METHOD_AUTO = 0, 311 RX_ALLOC_METHOD_SKB = 1, 312 RX_ALLOC_METHOD_PAGE = 2, 313 }; 314 315 /** 316 * struct efx_channel - An Efx channel 317 * 318 * A channel comprises an event queue, at least one TX queue, at least 319 * one RX queue, and an associated tasklet for processing the event 320 * queue. 321 * 322 * @efx: Associated Efx NIC 323 * @channel: Channel instance number 324 * @type: Channel type definition 325 * @enabled: Channel enabled indicator 326 * @irq: IRQ number (MSI and MSI-X only) 327 * @irq_moderation: IRQ moderation value (in hardware ticks) 328 * @napi_dev: Net device used with NAPI 329 * @napi_str: NAPI control structure 330 * @work_pending: Is work pending via NAPI? 331 * @eventq: Event queue buffer 332 * @eventq_mask: Event queue pointer mask 333 * @eventq_read_ptr: Event queue read pointer 334 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel 335 * @irq_count: Number of IRQs since last adaptive moderation decision 336 * @irq_mod_score: IRQ moderation score 337 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors 338 * and diagnostic counters 339 * @rx_alloc_push_pages: RX allocation method currently in use for pushing 340 * descriptors 341 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors 342 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors 343 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors 344 * @n_rx_mcast_mismatch: Count of unmatched multicast frames 345 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors 346 * @n_rx_overlength: Count of RX_OVERLENGTH errors 347 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun 348 * @rx_queue: RX queue for this channel 349 * @tx_queue: TX queues for this channel 350 */ 351 struct efx_channel { 352 struct efx_nic *efx; 353 int channel; 354 const struct efx_channel_type *type; 355 bool enabled; 356 int irq; 357 unsigned int irq_moderation; 358 struct net_device *napi_dev; 359 struct napi_struct napi_str; 360 bool work_pending; 361 struct efx_special_buffer eventq; 362 unsigned int eventq_mask; 363 unsigned int eventq_read_ptr; 364 int event_test_cpu; 365 366 unsigned int irq_count; 367 unsigned int irq_mod_score; 368 #ifdef CONFIG_RFS_ACCEL 369 unsigned int rfs_filters_added; 370 #endif 371 372 int rx_alloc_level; 373 int rx_alloc_push_pages; 374 375 unsigned n_rx_tobe_disc; 376 unsigned n_rx_ip_hdr_chksum_err; 377 unsigned n_rx_tcp_udp_chksum_err; 378 unsigned n_rx_mcast_mismatch; 379 unsigned n_rx_frm_trunc; 380 unsigned n_rx_overlength; 381 unsigned n_skbuff_leaks; 382 383 /* Used to pipeline received packets in order to optimise memory 384 * access with prefetches. 385 */ 386 struct efx_rx_buffer *rx_pkt; 387 388 struct efx_rx_queue rx_queue; 389 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES]; 390 }; 391 392 /** 393 * struct efx_channel_type - distinguishes traffic and extra channels 394 * @handle_no_channel: Handle failure to allocate an extra channel 395 * @pre_probe: Set up extra state prior to initialisation 396 * @post_remove: Tear down extra state after finalisation, if allocated. 397 * May be called on channels that have not been probed. 398 * @get_name: Generate the channel's name (used for its IRQ handler) 399 * @copy: Copy the channel state prior to reallocation. May be %NULL if 400 * reallocation is not supported. 401 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb() 402 * @keep_eventq: Flag for whether event queue should be kept initialised 403 * while the device is stopped 404 */ 405 struct efx_channel_type { 406 void (*handle_no_channel)(struct efx_nic *); 407 int (*pre_probe)(struct efx_channel *); 408 void (*post_remove)(struct efx_channel *); 409 void (*get_name)(struct efx_channel *, char *buf, size_t len); 410 struct efx_channel *(*copy)(const struct efx_channel *); 411 void (*receive_skb)(struct efx_channel *, struct sk_buff *); 412 bool keep_eventq; 413 }; 414 415 enum efx_led_mode { 416 EFX_LED_OFF = 0, 417 EFX_LED_ON = 1, 418 EFX_LED_DEFAULT = 2 419 }; 420 421 #define STRING_TABLE_LOOKUP(val, member) \ 422 ((val) < member ## _max) ? member ## _names[val] : "(invalid)" 423 424 extern const char *const efx_loopback_mode_names[]; 425 extern const unsigned int efx_loopback_mode_max; 426 #define LOOPBACK_MODE(efx) \ 427 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) 428 429 extern const char *const efx_reset_type_names[]; 430 extern const unsigned int efx_reset_type_max; 431 #define RESET_TYPE(type) \ 432 STRING_TABLE_LOOKUP(type, efx_reset_type) 433 434 enum efx_int_mode { 435 /* Be careful if altering to correct macro below */ 436 EFX_INT_MODE_MSIX = 0, 437 EFX_INT_MODE_MSI = 1, 438 EFX_INT_MODE_LEGACY = 2, 439 EFX_INT_MODE_MAX /* Insert any new items before this */ 440 }; 441 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) 442 443 enum nic_state { 444 STATE_UNINIT = 0, /* device being probed/removed or is frozen */ 445 STATE_READY = 1, /* hardware ready and netdev registered */ 446 STATE_DISABLED = 2, /* device disabled due to hardware errors */ 447 }; 448 449 /* 450 * Alignment of page-allocated RX buffers 451 * 452 * Controls the number of bytes inserted at the start of an RX buffer. 453 * This is the equivalent of NET_IP_ALIGN [which controls the alignment 454 * of the skb->head for hardware DMA]. 455 */ 456 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 457 #define EFX_PAGE_IP_ALIGN 0 458 #else 459 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN 460 #endif 461 462 /* 463 * Alignment of the skb->head which wraps a page-allocated RX buffer 464 * 465 * The skb allocated to wrap an rx_buffer can have this alignment. Since 466 * the data is memcpy'd from the rx_buf, it does not need to be equal to 467 * EFX_PAGE_IP_ALIGN. 468 */ 469 #define EFX_PAGE_SKB_ALIGN 2 470 471 /* Forward declaration */ 472 struct efx_nic; 473 474 /* Pseudo bit-mask flow control field */ 475 #define EFX_FC_RX FLOW_CTRL_RX 476 #define EFX_FC_TX FLOW_CTRL_TX 477 #define EFX_FC_AUTO 4 478 479 /** 480 * struct efx_link_state - Current state of the link 481 * @up: Link is up 482 * @fd: Link is full-duplex 483 * @fc: Actual flow control flags 484 * @speed: Link speed (Mbps) 485 */ 486 struct efx_link_state { 487 bool up; 488 bool fd; 489 u8 fc; 490 unsigned int speed; 491 }; 492 493 static inline bool efx_link_state_equal(const struct efx_link_state *left, 494 const struct efx_link_state *right) 495 { 496 return left->up == right->up && left->fd == right->fd && 497 left->fc == right->fc && left->speed == right->speed; 498 } 499 500 /** 501 * struct efx_phy_operations - Efx PHY operations table 502 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, 503 * efx->loopback_modes. 504 * @init: Initialise PHY 505 * @fini: Shut down PHY 506 * @reconfigure: Reconfigure PHY (e.g. for new link parameters) 507 * @poll: Update @link_state and report whether it changed. 508 * Serialised by the mac_lock. 509 * @get_settings: Get ethtool settings. Serialised by the mac_lock. 510 * @set_settings: Set ethtool settings. Serialised by the mac_lock. 511 * @set_npage_adv: Set abilities advertised in (Extended) Next Page 512 * (only needed where AN bit is set in mmds) 513 * @test_alive: Test that PHY is 'alive' (online) 514 * @test_name: Get the name of a PHY-specific test/result 515 * @run_tests: Run tests and record results as appropriate (offline). 516 * Flags are the ethtool tests flags. 517 */ 518 struct efx_phy_operations { 519 int (*probe) (struct efx_nic *efx); 520 int (*init) (struct efx_nic *efx); 521 void (*fini) (struct efx_nic *efx); 522 void (*remove) (struct efx_nic *efx); 523 int (*reconfigure) (struct efx_nic *efx); 524 bool (*poll) (struct efx_nic *efx); 525 void (*get_settings) (struct efx_nic *efx, 526 struct ethtool_cmd *ecmd); 527 int (*set_settings) (struct efx_nic *efx, 528 struct ethtool_cmd *ecmd); 529 void (*set_npage_adv) (struct efx_nic *efx, u32); 530 int (*test_alive) (struct efx_nic *efx); 531 const char *(*test_name) (struct efx_nic *efx, unsigned int index); 532 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); 533 int (*get_module_eeprom) (struct efx_nic *efx, 534 struct ethtool_eeprom *ee, 535 u8 *data); 536 int (*get_module_info) (struct efx_nic *efx, 537 struct ethtool_modinfo *modinfo); 538 }; 539 540 /** 541 * enum efx_phy_mode - PHY operating mode flags 542 * @PHY_MODE_NORMAL: on and should pass traffic 543 * @PHY_MODE_TX_DISABLED: on with TX disabled 544 * @PHY_MODE_LOW_POWER: set to low power through MDIO 545 * @PHY_MODE_OFF: switched off through external control 546 * @PHY_MODE_SPECIAL: on but will not pass traffic 547 */ 548 enum efx_phy_mode { 549 PHY_MODE_NORMAL = 0, 550 PHY_MODE_TX_DISABLED = 1, 551 PHY_MODE_LOW_POWER = 2, 552 PHY_MODE_OFF = 4, 553 PHY_MODE_SPECIAL = 8, 554 }; 555 556 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) 557 { 558 return !!(mode & ~PHY_MODE_TX_DISABLED); 559 } 560 561 /* 562 * Efx extended statistics 563 * 564 * Not all statistics are provided by all supported MACs. The purpose 565 * is this structure is to contain the raw statistics provided by each 566 * MAC. 567 */ 568 struct efx_mac_stats { 569 u64 tx_bytes; 570 u64 tx_good_bytes; 571 u64 tx_bad_bytes; 572 u64 tx_packets; 573 u64 tx_bad; 574 u64 tx_pause; 575 u64 tx_control; 576 u64 tx_unicast; 577 u64 tx_multicast; 578 u64 tx_broadcast; 579 u64 tx_lt64; 580 u64 tx_64; 581 u64 tx_65_to_127; 582 u64 tx_128_to_255; 583 u64 tx_256_to_511; 584 u64 tx_512_to_1023; 585 u64 tx_1024_to_15xx; 586 u64 tx_15xx_to_jumbo; 587 u64 tx_gtjumbo; 588 u64 tx_collision; 589 u64 tx_single_collision; 590 u64 tx_multiple_collision; 591 u64 tx_excessive_collision; 592 u64 tx_deferred; 593 u64 tx_late_collision; 594 u64 tx_excessive_deferred; 595 u64 tx_non_tcpudp; 596 u64 tx_mac_src_error; 597 u64 tx_ip_src_error; 598 u64 rx_bytes; 599 u64 rx_good_bytes; 600 u64 rx_bad_bytes; 601 u64 rx_packets; 602 u64 rx_good; 603 u64 rx_bad; 604 u64 rx_pause; 605 u64 rx_control; 606 u64 rx_unicast; 607 u64 rx_multicast; 608 u64 rx_broadcast; 609 u64 rx_lt64; 610 u64 rx_64; 611 u64 rx_65_to_127; 612 u64 rx_128_to_255; 613 u64 rx_256_to_511; 614 u64 rx_512_to_1023; 615 u64 rx_1024_to_15xx; 616 u64 rx_15xx_to_jumbo; 617 u64 rx_gtjumbo; 618 u64 rx_bad_lt64; 619 u64 rx_bad_64_to_15xx; 620 u64 rx_bad_15xx_to_jumbo; 621 u64 rx_bad_gtjumbo; 622 u64 rx_overflow; 623 u64 rx_missed; 624 u64 rx_false_carrier; 625 u64 rx_symbol_error; 626 u64 rx_align_error; 627 u64 rx_length_error; 628 u64 rx_internal_error; 629 u64 rx_good_lt64; 630 }; 631 632 /* Number of bits used in a multicast filter hash address */ 633 #define EFX_MCAST_HASH_BITS 8 634 635 /* Number of (single-bit) entries in a multicast filter hash */ 636 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) 637 638 /* An Efx multicast filter hash */ 639 union efx_multicast_hash { 640 u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; 641 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; 642 }; 643 644 struct efx_filter_state; 645 struct efx_vf; 646 struct vfdi_status; 647 648 /** 649 * struct efx_nic - an Efx NIC 650 * @name: Device name (net device name or bus id before net device registered) 651 * @pci_dev: The PCI device 652 * @type: Controller type attributes 653 * @legacy_irq: IRQ number 654 * @legacy_irq_enabled: Are IRQs enabled on NIC (INT_EN_KER register)? 655 * @workqueue: Workqueue for port reconfigures and the HW monitor. 656 * Work items do not hold and must not acquire RTNL. 657 * @workqueue_name: Name of workqueue 658 * @reset_work: Scheduled reset workitem 659 * @membase_phys: Memory BAR value as physical address 660 * @membase: Memory BAR value 661 * @interrupt_mode: Interrupt mode 662 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds 663 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues 664 * @irq_rx_moderation: IRQ moderation time for RX event queues 665 * @msg_enable: Log message enable flags 666 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock. 667 * @reset_pending: Bitmask for pending resets 668 * @tx_queue: TX DMA queues 669 * @rx_queue: RX DMA queues 670 * @channel: Channels 671 * @channel_name: Names for channels and their IRQs 672 * @extra_channel_types: Types of extra (non-traffic) channels that 673 * should be allocated for this NIC 674 * @rxq_entries: Size of receive queues requested by user. 675 * @txq_entries: Size of transmit queues requested by user. 676 * @txq_stop_thresh: TX queue fill level at or above which we stop it. 677 * @txq_wake_thresh: TX queue fill level at or below which we wake it. 678 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches 679 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches 680 * @sram_lim_qw: Qword address limit of SRAM 681 * @next_buffer_table: First available buffer table id 682 * @n_channels: Number of channels in use 683 * @n_rx_channels: Number of channels used for RX (= number of RX queues) 684 * @n_tx_channels: Number of channels used for TX 685 * @rx_buffer_len: RX buffer length 686 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer 687 * @rx_hash_key: Toeplitz hash key for RSS 688 * @rx_indir_table: Indirection table for RSS 689 * @int_error_count: Number of internal errors seen recently 690 * @int_error_expire: Time at which error count will be expired 691 * @irq_status: Interrupt status buffer 692 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 693 * @irq_level: IRQ level/index for IRQs not triggered by an event queue 694 * @selftest_work: Work item for asynchronous self-test 695 * @mtd_list: List of MTDs attached to the NIC 696 * @nic_data: Hardware dependent state 697 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, 698 * efx_monitor() and efx_reconfigure_port() 699 * @port_enabled: Port enabled indicator. 700 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and 701 * efx_mac_work() with kernel interfaces. Safe to read under any 702 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must 703 * be held to modify it. 704 * @port_initialized: Port initialized? 705 * @net_dev: Operating system network device. Consider holding the rtnl lock 706 * @stats_buffer: DMA buffer for statistics 707 * @phy_type: PHY type 708 * @phy_op: PHY interface 709 * @phy_data: PHY private data (including PHY-specific stats) 710 * @mdio: PHY MDIO interface 711 * @mdio_bus: PHY MDIO bus ID (only used by Siena) 712 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 713 * @link_advertising: Autonegotiation advertising flags 714 * @link_state: Current state of the link 715 * @n_link_state_changes: Number of times the link has changed state 716 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock. 717 * @multicast_hash: Multicast hash table 718 * @wanted_fc: Wanted flow control flags 719 * @fc_disable: When non-zero flow control is disabled. Typically used to 720 * ensure that network back pressure doesn't delay dma queue flushes. 721 * Serialised by the rtnl lock. 722 * @mac_work: Work item for changing MAC promiscuity and multicast hash 723 * @loopback_mode: Loopback status 724 * @loopback_modes: Supported loopback mode bitmask 725 * @loopback_selftest: Offline self-test private state 726 * @drain_pending: Count of RX and TX queues that haven't been flushed and drained. 727 * @rxq_flush_pending: Count of number of receive queues that need to be flushed. 728 * Decremented when the efx_flush_rx_queue() is called. 729 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet 730 * completed (either success or failure). Not used when MCDI is used to 731 * flush receive queues. 732 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. 733 * @vf: Array of &struct efx_vf objects. 734 * @vf_count: Number of VFs intended to be enabled. 735 * @vf_init_count: Number of VFs that have been fully initialised. 736 * @vi_scale: log2 number of vnics per VF. 737 * @vf_buftbl_base: The zeroth buffer table index used to back VF queues. 738 * @vfdi_status: Common VFDI status page to be dmad to VF address space. 739 * @local_addr_list: List of local addresses. Protected by %local_lock. 740 * @local_page_list: List of DMA addressable pages used to broadcast 741 * %local_addr_list. Protected by %local_lock. 742 * @local_lock: Mutex protecting %local_addr_list and %local_page_list. 743 * @peer_work: Work item to broadcast peer addresses to VMs. 744 * @ptp_data: PTP state data 745 * @monitor_work: Hardware monitor workitem 746 * @biu_lock: BIU (bus interface unit) lock 747 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This 748 * field is used by efx_test_interrupts() to verify that an 749 * interrupt has occurred. 750 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count 751 * @mac_stats: MAC statistics. These include all statistics the MACs 752 * can provide. Generic code converts these into a standard 753 * &struct net_device_stats. 754 * @stats_lock: Statistics update lock. Serialises statistics fetches 755 * and access to @mac_stats. 756 * 757 * This is stored in the private area of the &struct net_device. 758 */ 759 struct efx_nic { 760 /* The following fields should be written very rarely */ 761 762 char name[IFNAMSIZ]; 763 struct pci_dev *pci_dev; 764 const struct efx_nic_type *type; 765 int legacy_irq; 766 bool legacy_irq_enabled; 767 struct workqueue_struct *workqueue; 768 char workqueue_name[16]; 769 struct work_struct reset_work; 770 resource_size_t membase_phys; 771 void __iomem *membase; 772 773 enum efx_int_mode interrupt_mode; 774 unsigned int timer_quantum_ns; 775 bool irq_rx_adaptive; 776 unsigned int irq_rx_moderation; 777 u32 msg_enable; 778 779 enum nic_state state; 780 unsigned long reset_pending; 781 782 struct efx_channel *channel[EFX_MAX_CHANNELS]; 783 char channel_name[EFX_MAX_CHANNELS][IFNAMSIZ + 6]; 784 const struct efx_channel_type * 785 extra_channel_type[EFX_MAX_EXTRA_CHANNELS]; 786 787 unsigned rxq_entries; 788 unsigned txq_entries; 789 unsigned int txq_stop_thresh; 790 unsigned int txq_wake_thresh; 791 792 unsigned tx_dc_base; 793 unsigned rx_dc_base; 794 unsigned sram_lim_qw; 795 unsigned next_buffer_table; 796 unsigned n_channels; 797 unsigned n_rx_channels; 798 unsigned rss_spread; 799 unsigned tx_channel_offset; 800 unsigned n_tx_channels; 801 unsigned int rx_buffer_len; 802 unsigned int rx_buffer_order; 803 u8 rx_hash_key[40]; 804 u32 rx_indir_table[128]; 805 806 unsigned int_error_count; 807 unsigned long int_error_expire; 808 809 struct efx_buffer irq_status; 810 unsigned irq_zero_count; 811 unsigned irq_level; 812 struct delayed_work selftest_work; 813 814 #ifdef CONFIG_SFC_MTD 815 struct list_head mtd_list; 816 #endif 817 818 void *nic_data; 819 820 struct mutex mac_lock; 821 struct work_struct mac_work; 822 bool port_enabled; 823 824 bool port_initialized; 825 struct net_device *net_dev; 826 827 struct efx_buffer stats_buffer; 828 829 unsigned int phy_type; 830 const struct efx_phy_operations *phy_op; 831 void *phy_data; 832 struct mdio_if_info mdio; 833 unsigned int mdio_bus; 834 enum efx_phy_mode phy_mode; 835 836 u32 link_advertising; 837 struct efx_link_state link_state; 838 unsigned int n_link_state_changes; 839 840 bool promiscuous; 841 union efx_multicast_hash multicast_hash; 842 u8 wanted_fc; 843 unsigned fc_disable; 844 845 atomic_t rx_reset; 846 enum efx_loopback_mode loopback_mode; 847 u64 loopback_modes; 848 849 void *loopback_selftest; 850 851 struct efx_filter_state *filter_state; 852 853 atomic_t drain_pending; 854 atomic_t rxq_flush_pending; 855 atomic_t rxq_flush_outstanding; 856 wait_queue_head_t flush_wq; 857 858 #ifdef CONFIG_SFC_SRIOV 859 struct efx_channel *vfdi_channel; 860 struct efx_vf *vf; 861 unsigned vf_count; 862 unsigned vf_init_count; 863 unsigned vi_scale; 864 unsigned vf_buftbl_base; 865 struct efx_buffer vfdi_status; 866 struct list_head local_addr_list; 867 struct list_head local_page_list; 868 struct mutex local_lock; 869 struct work_struct peer_work; 870 #endif 871 872 struct efx_ptp_data *ptp_data; 873 874 /* The following fields may be written more often */ 875 876 struct delayed_work monitor_work ____cacheline_aligned_in_smp; 877 spinlock_t biu_lock; 878 int last_irq_cpu; 879 unsigned n_rx_nodesc_drop_cnt; 880 struct efx_mac_stats mac_stats; 881 spinlock_t stats_lock; 882 }; 883 884 static inline int efx_dev_registered(struct efx_nic *efx) 885 { 886 return efx->net_dev->reg_state == NETREG_REGISTERED; 887 } 888 889 static inline unsigned int efx_port_num(struct efx_nic *efx) 890 { 891 return efx->net_dev->dev_id; 892 } 893 894 /** 895 * struct efx_nic_type - Efx device type definition 896 * @probe: Probe the controller 897 * @remove: Free resources allocated by probe() 898 * @init: Initialise the controller 899 * @dimension_resources: Dimension controller resources (buffer table, 900 * and VIs once the available interrupt resources are clear) 901 * @fini: Shut down the controller 902 * @monitor: Periodic function for polling link state and hardware monitor 903 * @map_reset_reason: Map ethtool reset reason to a reset method 904 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible 905 * @reset: Reset the controller hardware and possibly the PHY. This will 906 * be called while the controller is uninitialised. 907 * @probe_port: Probe the MAC and PHY 908 * @remove_port: Free resources allocated by probe_port() 909 * @handle_global_event: Handle a "global" event (may be %NULL) 910 * @prepare_flush: Prepare the hardware for flushing the DMA queues 911 * @finish_flush: Clean up after flushing the DMA queues 912 * @update_stats: Update statistics not provided by event handling 913 * @start_stats: Start the regular fetching of statistics 914 * @stop_stats: Stop the regular fetching of statistics 915 * @set_id_led: Set state of identifying LED or revert to automatic function 916 * @push_irq_moderation: Apply interrupt moderation value 917 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY 918 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings 919 * to the hardware. Serialised by the mac_lock. 920 * @check_mac_fault: Check MAC fault state. True if fault present. 921 * @get_wol: Get WoL configuration from driver state 922 * @set_wol: Push WoL configuration to the NIC 923 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) 924 * @test_chip: Test registers. Should use efx_nic_test_registers(), and is 925 * expected to reset the NIC. 926 * @test_nvram: Test validity of NVRAM contents 927 * @revision: Hardware architecture revision 928 * @mem_map_size: Memory BAR mapped size 929 * @txd_ptr_tbl_base: TX descriptor ring base address 930 * @rxd_ptr_tbl_base: RX descriptor ring base address 931 * @buf_tbl_base: Buffer table base address 932 * @evq_ptr_tbl_base: Event queue pointer table base address 933 * @evq_rptr_tbl_base: Event queue read-pointer table base address 934 * @max_dma_mask: Maximum possible DMA mask 935 * @rx_buffer_hash_size: Size of hash at start of RX buffer 936 * @rx_buffer_padding: Size of padding at end of RX buffer 937 * @max_interrupt_mode: Highest capability interrupt mode supported 938 * from &enum efx_init_mode. 939 * @phys_addr_channels: Number of channels with physically addressed 940 * descriptors 941 * @timer_period_max: Maximum period of interrupt timer (in ticks) 942 * @offload_features: net_device feature flags for protocol offload 943 * features implemented in hardware 944 */ 945 struct efx_nic_type { 946 int (*probe)(struct efx_nic *efx); 947 void (*remove)(struct efx_nic *efx); 948 int (*init)(struct efx_nic *efx); 949 void (*dimension_resources)(struct efx_nic *efx); 950 void (*fini)(struct efx_nic *efx); 951 void (*monitor)(struct efx_nic *efx); 952 enum reset_type (*map_reset_reason)(enum reset_type reason); 953 int (*map_reset_flags)(u32 *flags); 954 int (*reset)(struct efx_nic *efx, enum reset_type method); 955 int (*probe_port)(struct efx_nic *efx); 956 void (*remove_port)(struct efx_nic *efx); 957 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); 958 void (*prepare_flush)(struct efx_nic *efx); 959 void (*finish_flush)(struct efx_nic *efx); 960 void (*update_stats)(struct efx_nic *efx); 961 void (*start_stats)(struct efx_nic *efx); 962 void (*stop_stats)(struct efx_nic *efx); 963 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); 964 void (*push_irq_moderation)(struct efx_channel *channel); 965 int (*reconfigure_port)(struct efx_nic *efx); 966 int (*reconfigure_mac)(struct efx_nic *efx); 967 bool (*check_mac_fault)(struct efx_nic *efx); 968 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); 969 int (*set_wol)(struct efx_nic *efx, u32 type); 970 void (*resume_wol)(struct efx_nic *efx); 971 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests); 972 int (*test_nvram)(struct efx_nic *efx); 973 974 int revision; 975 unsigned int mem_map_size; 976 unsigned int txd_ptr_tbl_base; 977 unsigned int rxd_ptr_tbl_base; 978 unsigned int buf_tbl_base; 979 unsigned int evq_ptr_tbl_base; 980 unsigned int evq_rptr_tbl_base; 981 u64 max_dma_mask; 982 unsigned int rx_buffer_hash_size; 983 unsigned int rx_buffer_padding; 984 unsigned int max_interrupt_mode; 985 unsigned int phys_addr_channels; 986 unsigned int timer_period_max; 987 netdev_features_t offload_features; 988 }; 989 990 /************************************************************************** 991 * 992 * Prototypes and inline functions 993 * 994 *************************************************************************/ 995 996 static inline struct efx_channel * 997 efx_get_channel(struct efx_nic *efx, unsigned index) 998 { 999 EFX_BUG_ON_PARANOID(index >= efx->n_channels); 1000 return efx->channel[index]; 1001 } 1002 1003 /* Iterate over all used channels */ 1004 #define efx_for_each_channel(_channel, _efx) \ 1005 for (_channel = (_efx)->channel[0]; \ 1006 _channel; \ 1007 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ 1008 (_efx)->channel[_channel->channel + 1] : NULL) 1009 1010 /* Iterate over all used channels in reverse */ 1011 #define efx_for_each_channel_rev(_channel, _efx) \ 1012 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ 1013 _channel; \ 1014 _channel = _channel->channel ? \ 1015 (_efx)->channel[_channel->channel - 1] : NULL) 1016 1017 static inline struct efx_tx_queue * 1018 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) 1019 { 1020 EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || 1021 type >= EFX_TXQ_TYPES); 1022 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; 1023 } 1024 1025 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) 1026 { 1027 return channel->channel - channel->efx->tx_channel_offset < 1028 channel->efx->n_tx_channels; 1029 } 1030 1031 static inline struct efx_tx_queue * 1032 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) 1033 { 1034 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) || 1035 type >= EFX_TXQ_TYPES); 1036 return &channel->tx_queue[type]; 1037 } 1038 1039 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue) 1040 { 1041 return !(tx_queue->efx->net_dev->num_tc < 2 && 1042 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI); 1043 } 1044 1045 /* Iterate over all TX queues belonging to a channel */ 1046 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ 1047 if (!efx_channel_has_tx_queues(_channel)) \ 1048 ; \ 1049 else \ 1050 for (_tx_queue = (_channel)->tx_queue; \ 1051 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \ 1052 efx_tx_queue_used(_tx_queue); \ 1053 _tx_queue++) 1054 1055 /* Iterate over all possible TX queues belonging to a channel */ 1056 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ 1057 if (!efx_channel_has_tx_queues(_channel)) \ 1058 ; \ 1059 else \ 1060 for (_tx_queue = (_channel)->tx_queue; \ 1061 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ 1062 _tx_queue++) 1063 1064 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) 1065 { 1066 return channel->rx_queue.core_index >= 0; 1067 } 1068 1069 static inline struct efx_rx_queue * 1070 efx_channel_get_rx_queue(struct efx_channel *channel) 1071 { 1072 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel)); 1073 return &channel->rx_queue; 1074 } 1075 1076 /* Iterate over all RX queues belonging to a channel */ 1077 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ 1078 if (!efx_channel_has_rx_queue(_channel)) \ 1079 ; \ 1080 else \ 1081 for (_rx_queue = &(_channel)->rx_queue; \ 1082 _rx_queue; \ 1083 _rx_queue = NULL) 1084 1085 static inline struct efx_channel * 1086 efx_rx_queue_channel(struct efx_rx_queue *rx_queue) 1087 { 1088 return container_of(rx_queue, struct efx_channel, rx_queue); 1089 } 1090 1091 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) 1092 { 1093 return efx_rx_queue_channel(rx_queue)->channel; 1094 } 1095 1096 /* Returns a pointer to the specified receive buffer in the RX 1097 * descriptor queue. 1098 */ 1099 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, 1100 unsigned int index) 1101 { 1102 return &rx_queue->buffer[index]; 1103 } 1104 1105 1106 /** 1107 * EFX_MAX_FRAME_LEN - calculate maximum frame length 1108 * 1109 * This calculates the maximum frame length that will be used for a 1110 * given MTU. The frame length will be equal to the MTU plus a 1111 * constant amount of header space and padding. This is the quantity 1112 * that the net driver will program into the MAC as the maximum frame 1113 * length. 1114 * 1115 * The 10G MAC requires 8-byte alignment on the frame 1116 * length, so we round up to the nearest 8. 1117 * 1118 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an 1119 * XGMII cycle). If the frame length reaches the maximum value in the 1120 * same cycle, the XMAC can miss the IPG altogether. We work around 1121 * this by adding a further 16 bytes. 1122 */ 1123 #define EFX_MAX_FRAME_LEN(mtu) \ 1124 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16) 1125 1126 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb) 1127 { 1128 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP; 1129 } 1130 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb) 1131 { 1132 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1133 } 1134 1135 #endif /* EFX_NET_DRIVER_H */ 1136