1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2009-2013 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 11 #ifndef MCDI_PCOL_H 12 #define MCDI_PCOL_H 13 14 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 15 /* Power-on reset state */ 16 #define MC_FW_STATE_POR (1) 17 /* If this is set in MC_RESET_STATE_REG then it should be 18 * possible to jump into IMEM without loading code from flash. */ 19 #define MC_FW_WARM_BOOT_OK (2) 20 /* The MC main image has started to boot. */ 21 #define MC_FW_STATE_BOOTING (4) 22 /* The Scheduler has started. */ 23 #define MC_FW_STATE_SCHED (8) 24 /* If this is set in MC_RESET_STATE_REG then it should be 25 * possible to jump into IMEM without loading code from flash. 26 * Unlike a warm boot, assume DMEM has been reloaded, so that 27 * the MC persistent data must be reinitialised. */ 28 #define MC_FW_TEPID_BOOT_OK (16) 29 /* We have entered the main firmware via recovery mode. This 30 * means that MC persistent data must be reinitialised, but that 31 * we shouldn't touch PCIe config. */ 32 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) 33 /* BIST state has been initialized */ 34 #define MC_FW_BIST_INIT_OK (128) 35 36 /* Siena MC shared memmory offsets */ 37 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 38 #define MC_SMEM_P0_DOORBELL_OFST 0x000 39 #define MC_SMEM_P1_DOORBELL_OFST 0x004 40 /* The rest of these are firmware-defined */ 41 #define MC_SMEM_P0_PDU_OFST 0x008 42 #define MC_SMEM_P1_PDU_OFST 0x108 43 #define MC_SMEM_PDU_LEN 0x100 44 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 45 #define MC_SMEM_P0_STATUS_OFST 0x7f8 46 #define MC_SMEM_P1_STATUS_OFST 0x7fc 47 48 /* Values to be written to the per-port status dword in shared 49 * memory on reboot and assert */ 50 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 51 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 52 53 /* Check whether an mcfw version (in host order) belongs to a bootloader */ 54 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) 55 56 /* The current version of the MCDI protocol. 57 * 58 * Note that the ROM burnt into the card only talks V0, so at the very 59 * least every driver must support version 0 and MCDI_PCOL_VERSION 60 */ 61 #define MCDI_PCOL_VERSION 2 62 63 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 64 65 /* MCDI version 1 66 * 67 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 68 * structure, filled in by the client. 69 * 70 * 0 7 8 16 20 22 23 24 31 71 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 72 * | | | 73 * | | \--- Response 74 * | \------- Error 75 * \------------------------------ Resync (always set) 76 * 77 * The client writes it's request into MC shared memory, and rings the 78 * doorbell. Each request is completed by either by the MC writting 79 * back into shared memory, or by writting out an event. 80 * 81 * All MCDI commands support completion by shared memory response. Each 82 * request may also contain additional data (accounted for by HEADER.LEN), 83 * and some response's may also contain additional data (again, accounted 84 * for by HEADER.LEN). 85 * 86 * Some MCDI commands support completion by event, in which any associated 87 * response data is included in the event. 88 * 89 * The protocol requires one response to be delivered for every request, a 90 * request should not be sent unless the response for the previous request 91 * has been received (either by polling shared memory, or by receiving 92 * an event). 93 */ 94 95 /** Request/Response structure */ 96 #define MCDI_HEADER_OFST 0 97 #define MCDI_HEADER_CODE_LBN 0 98 #define MCDI_HEADER_CODE_WIDTH 7 99 #define MCDI_HEADER_RESYNC_LBN 7 100 #define MCDI_HEADER_RESYNC_WIDTH 1 101 #define MCDI_HEADER_DATALEN_LBN 8 102 #define MCDI_HEADER_DATALEN_WIDTH 8 103 #define MCDI_HEADER_SEQ_LBN 16 104 #define MCDI_HEADER_SEQ_WIDTH 4 105 #define MCDI_HEADER_RSVD_LBN 20 106 #define MCDI_HEADER_RSVD_WIDTH 1 107 #define MCDI_HEADER_NOT_EPOCH_LBN 21 108 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 109 #define MCDI_HEADER_ERROR_LBN 22 110 #define MCDI_HEADER_ERROR_WIDTH 1 111 #define MCDI_HEADER_RESPONSE_LBN 23 112 #define MCDI_HEADER_RESPONSE_WIDTH 1 113 #define MCDI_HEADER_XFLAGS_LBN 24 114 #define MCDI_HEADER_XFLAGS_WIDTH 8 115 /* Request response using event */ 116 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 117 118 /* Maximum number of payload bytes */ 119 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc 120 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 121 122 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 123 124 125 /* The MC can generate events for two reasons: 126 * - To complete a shared memory request if XFLAGS_EVREQ was set 127 * - As a notification (link state, i2c event), controlled 128 * via MC_CMD_LOG_CTRL 129 * 130 * Both events share a common structure: 131 * 132 * 0 32 33 36 44 52 60 133 * | Data | Cont | Level | Src | Code | Rsvd | 134 * | 135 * \ There is another event pending in this notification 136 * 137 * If Code==CMDDONE, then the fields are further interpreted as: 138 * 139 * - LEVEL==INFO Command succeeded 140 * - LEVEL==ERR Command failed 141 * 142 * 0 8 16 24 32 143 * | Seq | Datalen | Errno | Rsvd | 144 * 145 * These fields are taken directly out of the standard MCDI header, i.e., 146 * LEVEL==ERR, Datalen == 0 => Reboot 147 * 148 * Events can be squirted out of the UART (using LOG_CTRL) without a 149 * MCDI header. An event can be distinguished from a MCDI response by 150 * examining the first byte which is 0xc0. This corresponds to the 151 * non-existent MCDI command MC_CMD_DEBUG_LOG. 152 * 153 * 0 7 8 154 * | command | Resync | = 0xc0 155 * 156 * Since the event is written in big-endian byte order, this works 157 * providing bits 56-63 of the event are 0xc0. 158 * 159 * 56 60 63 160 * | Rsvd | Code | = 0xc0 161 * 162 * Which means for convenience the event code is 0xc for all MC 163 * generated events. 164 */ 165 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 166 167 168 /* Operation not permitted. */ 169 #define MC_CMD_ERR_EPERM 1 170 /* Non-existent command target */ 171 #define MC_CMD_ERR_ENOENT 2 172 /* assert() has killed the MC */ 173 #define MC_CMD_ERR_EINTR 4 174 /* I/O failure */ 175 #define MC_CMD_ERR_EIO 5 176 /* Already exists */ 177 #define MC_CMD_ERR_EEXIST 6 178 /* Try again */ 179 #define MC_CMD_ERR_EAGAIN 11 180 /* Out of memory */ 181 #define MC_CMD_ERR_ENOMEM 12 182 /* Caller does not hold required locks */ 183 #define MC_CMD_ERR_EACCES 13 184 /* Resource is currently unavailable (e.g. lock contention) */ 185 #define MC_CMD_ERR_EBUSY 16 186 /* No such device */ 187 #define MC_CMD_ERR_ENODEV 19 188 /* Invalid argument to target */ 189 #define MC_CMD_ERR_EINVAL 22 190 /* Broken pipe */ 191 #define MC_CMD_ERR_EPIPE 32 192 /* Read-only */ 193 #define MC_CMD_ERR_EROFS 30 194 /* Out of range */ 195 #define MC_CMD_ERR_ERANGE 34 196 /* Non-recursive resource is already acquired */ 197 #define MC_CMD_ERR_EDEADLK 35 198 /* Operation not implemented */ 199 #define MC_CMD_ERR_ENOSYS 38 200 /* Operation timed out */ 201 #define MC_CMD_ERR_ETIME 62 202 /* Link has been severed */ 203 #define MC_CMD_ERR_ENOLINK 67 204 /* Protocol error */ 205 #define MC_CMD_ERR_EPROTO 71 206 /* Operation not supported */ 207 #define MC_CMD_ERR_ENOTSUP 95 208 /* Address not available */ 209 #define MC_CMD_ERR_EADDRNOTAVAIL 99 210 /* Not connected */ 211 #define MC_CMD_ERR_ENOTCONN 107 212 /* Operation already in progress */ 213 #define MC_CMD_ERR_EALREADY 114 214 215 /* Resource allocation failed. */ 216 #define MC_CMD_ERR_ALLOC_FAIL 0x1000 217 /* V-adaptor not found. */ 218 #define MC_CMD_ERR_NO_VADAPTOR 0x1001 219 /* EVB port not found. */ 220 #define MC_CMD_ERR_NO_EVB_PORT 0x1002 221 /* V-switch not found. */ 222 #define MC_CMD_ERR_NO_VSWITCH 0x1003 223 /* Too many VLAN tags. */ 224 #define MC_CMD_ERR_VLAN_LIMIT 0x1004 225 /* Bad PCI function number. */ 226 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 227 /* Invalid VLAN mode. */ 228 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 229 /* Invalid v-switch type. */ 230 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 231 /* Invalid v-port type. */ 232 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 233 /* MAC address exists. */ 234 #define MC_CMD_ERR_MAC_EXIST 0x1009 235 /* Slave core not present */ 236 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 237 /* The datapath is disabled. */ 238 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b 239 /* The requesting client is not a function */ 240 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c 241 /* The requested operation might require the 242 command to be passed between MCs, and the 243 transport doesn't support that. Should 244 only ever been seen over the UART. */ 245 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d 246 /* VLAN tag(s) exists */ 247 #define MC_CMD_ERR_VLAN_EXIST 0x100e 248 /* No MAC address assigned to an EVB port */ 249 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f 250 /* Notifies the driver that the request has been relayed 251 * to an admin function for authorization. The driver should 252 * wait for a PROXY_RESPONSE event and then resend its request. 253 * This error code is followed by a 32-bit handle that 254 * helps matching it with the respective PROXY_RESPONSE event. */ 255 #define MC_CMD_ERR_PROXY_PENDING 0x1010 256 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 257 /* The request cannot be passed for authorization because 258 * another request from the same function is currently being 259 * authorized. The drvier should try again later. */ 260 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 261 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function 262 * that has enabled proxying or BLOCK_INDEX points to a function that 263 * doesn't await an authorization. */ 264 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 265 /* This code is currently only used internally in FW. Its meaning is that 266 * an operation failed due to lack of SR-IOV privilege. 267 * Normally it is translated to EPERM by send_cmd_err(), 268 * but it may also be used to trigger some special mechanism 269 * for handling such case, e.g. to relay the failed request 270 * to a designated admin function for authorization. */ 271 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013 272 /* Workaround 26807 could not be turned on/off because some functions 273 * have already installed filters. See the comment at 274 * MC_CMD_WORKAROUND_BUG26807. */ 275 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 276 277 #define MC_CMD_ERR_CODE_OFST 0 278 279 /* We define 8 "escape" commands to allow 280 for command number space extension */ 281 282 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 283 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 284 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 285 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 286 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 287 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 288 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 289 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 290 291 /* Vectors in the boot ROM */ 292 /* Point to the copycode entry point. */ 293 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) 294 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) 295 /* Points to the recovery mode entry point. */ 296 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) 297 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) 298 299 /* The command set exported by the boot ROM (MCDI v0) */ 300 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 301 (1 << MC_CMD_READ32) | \ 302 (1 << MC_CMD_WRITE32) | \ 303 (1 << MC_CMD_COPYCODE) | \ 304 (1 << MC_CMD_GET_VERSION), \ 305 0, 0, 0 } 306 307 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 308 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 309 310 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 311 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 312 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 313 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 314 315 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 316 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 317 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 318 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 319 320 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 321 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 322 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 323 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 324 325 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default 326 * stack ID (which must be in the range 1-255) along with an EVB port ID. 327 */ 328 #define EVB_STACK_ID(n) (((n) & 0xff) << 16) 329 330 331 /* Version 2 adds an optional argument to error returns: the errno value 332 * may be followed by the (0-based) number of the first argument that 333 * could not be processed. 334 */ 335 #define MC_CMD_ERR_ARG_OFST 4 336 337 /* No space */ 338 #define MC_CMD_ERR_ENOSPC 28 339 340 /* MCDI_EVENT structuredef */ 341 #define MCDI_EVENT_LEN 8 342 #define MCDI_EVENT_CONT_LBN 32 343 #define MCDI_EVENT_CONT_WIDTH 1 344 #define MCDI_EVENT_LEVEL_LBN 33 345 #define MCDI_EVENT_LEVEL_WIDTH 3 346 /* enum: Info. */ 347 #define MCDI_EVENT_LEVEL_INFO 0x0 348 /* enum: Warning. */ 349 #define MCDI_EVENT_LEVEL_WARN 0x1 350 /* enum: Error. */ 351 #define MCDI_EVENT_LEVEL_ERR 0x2 352 /* enum: Fatal. */ 353 #define MCDI_EVENT_LEVEL_FATAL 0x3 354 #define MCDI_EVENT_DATA_OFST 0 355 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 356 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 357 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 358 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 359 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 360 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 361 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 362 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 363 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 364 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 365 /* enum: 100Mbs */ 366 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 367 /* enum: 1Gbs */ 368 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 369 /* enum: 10Gbs */ 370 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 371 /* enum: 40Gbs */ 372 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 373 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 374 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 375 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 376 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 377 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 378 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 379 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 380 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 381 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 382 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 383 #define MCDI_EVENT_FWALERT_DATA_LBN 8 384 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 385 #define MCDI_EVENT_FWALERT_REASON_LBN 0 386 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 387 /* enum: SRAM Access. */ 388 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 389 #define MCDI_EVENT_FLR_VF_LBN 0 390 #define MCDI_EVENT_FLR_VF_WIDTH 8 391 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 392 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 393 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 394 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 395 /* enum: Descriptor loader reported failure */ 396 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 397 /* enum: Descriptor ring empty and no EOP seen for packet */ 398 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 399 /* enum: Overlength packet */ 400 #define MCDI_EVENT_TX_ERR_2BIG 0x3 401 /* enum: Malformed option descriptor */ 402 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 403 /* enum: Option descriptor part way through a packet */ 404 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 405 /* enum: DMA or PIO data access error */ 406 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 407 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 408 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 409 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 410 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 411 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 412 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 413 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 414 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 415 /* enum: PLL lost lock */ 416 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 417 /* enum: Filter overflow (PDMA) */ 418 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 419 /* enum: FIFO overflow (FPGA) */ 420 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 421 /* enum: Merge queue overflow */ 422 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 423 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 424 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 425 /* enum: AOE failed to load - no valid image? */ 426 #define MCDI_EVENT_AOE_NO_LOAD 0x1 427 /* enum: AOE FC reported an exception */ 428 #define MCDI_EVENT_AOE_FC_ASSERT 0x2 429 /* enum: AOE FC watchdogged */ 430 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 431 /* enum: AOE FC failed to start */ 432 #define MCDI_EVENT_AOE_FC_NO_START 0x4 433 /* enum: Generic AOE fault - likely to have been reported via other means too 434 * but intended for use by aoex driver. 435 */ 436 #define MCDI_EVENT_AOE_FAULT 0x5 437 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ 438 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 439 /* enum: AOE loaded successfully */ 440 #define MCDI_EVENT_AOE_LOAD 0x7 441 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ 442 #define MCDI_EVENT_AOE_DMA 0x8 443 /* enum: AOE byteblaster connected/disconnected (Connection status in 444 * AOE_ERR_DATA) 445 */ 446 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 447 /* enum: DDR ECC status update */ 448 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa 449 /* enum: PTP status update */ 450 #define MCDI_EVENT_AOE_PTP_STATUS 0xb 451 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 452 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 453 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 454 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 455 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 456 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 457 #define MCDI_EVENT_RX_ERR_INFO_LBN 16 458 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 459 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 460 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 461 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 462 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 463 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 464 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 465 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 466 #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 467 /* enum: MUM failed to load - no valid image? */ 468 #define MCDI_EVENT_MUM_NO_LOAD 0x1 469 /* enum: MUM f/w reported an exception */ 470 #define MCDI_EVENT_MUM_ASSERT 0x2 471 /* enum: MUM not kicking watchdog */ 472 #define MCDI_EVENT_MUM_WATCHDOG 0x3 473 #define MCDI_EVENT_MUM_ERR_DATA_LBN 8 474 #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 475 #define MCDI_EVENT_DATA_LBN 0 476 #define MCDI_EVENT_DATA_WIDTH 32 477 #define MCDI_EVENT_SRC_LBN 36 478 #define MCDI_EVENT_SRC_WIDTH 8 479 #define MCDI_EVENT_EV_CODE_LBN 60 480 #define MCDI_EVENT_EV_CODE_WIDTH 4 481 #define MCDI_EVENT_CODE_LBN 44 482 #define MCDI_EVENT_CODE_WIDTH 8 483 /* enum: Event generated by host software */ 484 #define MCDI_EVENT_SW_EVENT 0x0 485 /* enum: Bad assert. */ 486 #define MCDI_EVENT_CODE_BADSSERT 0x1 487 /* enum: PM Notice. */ 488 #define MCDI_EVENT_CODE_PMNOTICE 0x2 489 /* enum: Command done. */ 490 #define MCDI_EVENT_CODE_CMDDONE 0x3 491 /* enum: Link change. */ 492 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 493 /* enum: Sensor Event. */ 494 #define MCDI_EVENT_CODE_SENSOREVT 0x5 495 /* enum: Schedule error. */ 496 #define MCDI_EVENT_CODE_SCHEDERR 0x6 497 /* enum: Reboot. */ 498 #define MCDI_EVENT_CODE_REBOOT 0x7 499 /* enum: Mac stats DMA. */ 500 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 501 /* enum: Firmware alert. */ 502 #define MCDI_EVENT_CODE_FWALERT 0x9 503 /* enum: Function level reset. */ 504 #define MCDI_EVENT_CODE_FLR 0xa 505 /* enum: Transmit error */ 506 #define MCDI_EVENT_CODE_TX_ERR 0xb 507 /* enum: Tx flush has completed */ 508 #define MCDI_EVENT_CODE_TX_FLUSH 0xc 509 /* enum: PTP packet received timestamp */ 510 #define MCDI_EVENT_CODE_PTP_RX 0xd 511 /* enum: PTP NIC failure */ 512 #define MCDI_EVENT_CODE_PTP_FAULT 0xe 513 /* enum: PTP PPS event */ 514 #define MCDI_EVENT_CODE_PTP_PPS 0xf 515 /* enum: Rx flush has completed */ 516 #define MCDI_EVENT_CODE_RX_FLUSH 0x10 517 /* enum: Receive error */ 518 #define MCDI_EVENT_CODE_RX_ERR 0x11 519 /* enum: AOE fault */ 520 #define MCDI_EVENT_CODE_AOE 0x12 521 /* enum: Network port calibration failed (VCAL). */ 522 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 523 /* enum: HW PPS event */ 524 #define MCDI_EVENT_CODE_HW_PPS 0x14 525 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and 526 * a different format) 527 */ 528 #define MCDI_EVENT_CODE_MC_REBOOT 0x15 529 /* enum: the MC has detected a parity error */ 530 #define MCDI_EVENT_CODE_PAR_ERR 0x16 531 /* enum: the MC has detected a correctable error */ 532 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 533 /* enum: the MC has detected an uncorrectable error */ 534 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 535 /* enum: The MC has entered offline BIST mode */ 536 #define MCDI_EVENT_CODE_MC_BIST 0x19 537 /* enum: PTP tick event providing current NIC time */ 538 #define MCDI_EVENT_CODE_PTP_TIME 0x1a 539 /* enum: MUM fault */ 540 #define MCDI_EVENT_CODE_MUM 0x1b 541 /* enum: notify the designated PF of a new authorization request */ 542 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c 543 /* enum: notify a function that awaits an authorization that its request has 544 * been processed and it may now resend the command 545 */ 546 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d 547 /* enum: Artificial event generated by host and posted via MC for test 548 * purposes. 549 */ 550 #define MCDI_EVENT_CODE_TESTGEN 0xfa 551 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 552 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 553 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 554 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 555 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 556 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 557 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 558 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 559 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 560 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 561 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 562 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 563 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 564 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 565 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 566 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of 567 * timestamp 568 */ 569 #define MCDI_EVENT_PTP_SECONDS_OFST 0 570 #define MCDI_EVENT_PTP_SECONDS_LBN 0 571 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 572 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of 573 * timestamp 574 */ 575 #define MCDI_EVENT_PTP_MAJOR_OFST 0 576 #define MCDI_EVENT_PTP_MAJOR_LBN 0 577 #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 578 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field 579 * of timestamp 580 */ 581 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 582 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 583 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 584 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of 585 * timestamp 586 */ 587 #define MCDI_EVENT_PTP_MINOR_OFST 0 588 #define MCDI_EVENT_PTP_MINOR_LBN 0 589 #define MCDI_EVENT_PTP_MINOR_WIDTH 32 590 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet 591 */ 592 #define MCDI_EVENT_PTP_UUID_OFST 0 593 #define MCDI_EVENT_PTP_UUID_LBN 0 594 #define MCDI_EVENT_PTP_UUID_WIDTH 32 595 #define MCDI_EVENT_RX_ERR_DATA_OFST 0 596 #define MCDI_EVENT_RX_ERR_DATA_LBN 0 597 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 598 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 599 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 600 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 601 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 602 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 603 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 604 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 605 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 606 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 607 /* For CODE_PTP_TIME events, the major value of the PTP clock */ 608 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 609 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 610 #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 611 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ 612 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 613 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 614 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 615 * whether the NIC clock has ever been set 616 */ 617 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 618 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 619 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 620 * whether the NIC and System clocks are in sync 621 */ 622 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 623 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 624 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of 625 * the minor value of the PTP clock 626 */ 627 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 628 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 629 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 630 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 631 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 632 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 633 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 634 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 635 /* Zero means that the request has been completed or authorized, and the driver 636 * should resend it. A non-zero value means that the authorization has been 637 * denied, and gives the reason. Typically it will be EPERM. 638 */ 639 #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 640 #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 641 642 /* FCDI_EVENT structuredef */ 643 #define FCDI_EVENT_LEN 8 644 #define FCDI_EVENT_CONT_LBN 32 645 #define FCDI_EVENT_CONT_WIDTH 1 646 #define FCDI_EVENT_LEVEL_LBN 33 647 #define FCDI_EVENT_LEVEL_WIDTH 3 648 /* enum: Info. */ 649 #define FCDI_EVENT_LEVEL_INFO 0x0 650 /* enum: Warning. */ 651 #define FCDI_EVENT_LEVEL_WARN 0x1 652 /* enum: Error. */ 653 #define FCDI_EVENT_LEVEL_ERR 0x2 654 /* enum: Fatal. */ 655 #define FCDI_EVENT_LEVEL_FATAL 0x3 656 #define FCDI_EVENT_DATA_OFST 0 657 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 658 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 659 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 660 #define FCDI_EVENT_LINK_UP 0x1 /* enum */ 661 #define FCDI_EVENT_DATA_LBN 0 662 #define FCDI_EVENT_DATA_WIDTH 32 663 #define FCDI_EVENT_SRC_LBN 36 664 #define FCDI_EVENT_SRC_WIDTH 8 665 #define FCDI_EVENT_EV_CODE_LBN 60 666 #define FCDI_EVENT_EV_CODE_WIDTH 4 667 #define FCDI_EVENT_CODE_LBN 44 668 #define FCDI_EVENT_CODE_WIDTH 8 669 /* enum: The FC was rebooted. */ 670 #define FCDI_EVENT_CODE_REBOOT 0x1 671 /* enum: Bad assert. */ 672 #define FCDI_EVENT_CODE_ASSERT 0x2 673 /* enum: DDR3 test result. */ 674 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 675 /* enum: Link status. */ 676 #define FCDI_EVENT_CODE_LINK_STATE 0x4 677 /* enum: A timed read is ready to be serviced. */ 678 #define FCDI_EVENT_CODE_TIMED_READ 0x5 679 /* enum: One or more PPS IN events */ 680 #define FCDI_EVENT_CODE_PPS_IN 0x6 681 /* enum: Tick event from PTP clock */ 682 #define FCDI_EVENT_CODE_PTP_TICK 0x7 683 /* enum: ECC error counters */ 684 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 685 /* enum: Current status of PTP */ 686 #define FCDI_EVENT_CODE_PTP_STATUS 0x9 687 /* enum: Port id config to map MC-FC port idx */ 688 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa 689 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 690 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 691 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 692 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 693 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 694 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 695 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 696 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 697 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 698 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 699 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 700 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 701 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 702 #define FCDI_EVENT_PTP_STATE_OFST 0 703 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ 704 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ 705 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ 706 #define FCDI_EVENT_PTP_STATE_LBN 0 707 #define FCDI_EVENT_PTP_STATE_WIDTH 32 708 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 709 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 710 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 711 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 712 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 713 /* Index of MC port being referred to */ 714 #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 715 #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 716 /* FC Port index that matches the MC port index in SRC */ 717 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 718 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 719 #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 720 721 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events 722 * to the MC. Note that this structure | is overlayed over a normal FCDI event 723 * such that bits 32-63 containing | event code, level, source etc remain the 724 * same. In this case the data | field of the header is defined to be the 725 * number of timestamps 726 */ 727 #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 728 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 729 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) 730 /* Number of timestamps following */ 731 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 732 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 733 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 734 /* Seconds field of a timestamp record */ 735 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 736 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 737 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 738 /* Nanoseconds field of a timestamp record */ 739 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 740 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 741 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 742 /* Timestamp records comprising the event */ 743 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 744 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 745 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 746 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 747 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 748 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 749 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 750 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 751 752 /* MUM_EVENT structuredef */ 753 #define MUM_EVENT_LEN 8 754 #define MUM_EVENT_CONT_LBN 32 755 #define MUM_EVENT_CONT_WIDTH 1 756 #define MUM_EVENT_LEVEL_LBN 33 757 #define MUM_EVENT_LEVEL_WIDTH 3 758 /* enum: Info. */ 759 #define MUM_EVENT_LEVEL_INFO 0x0 760 /* enum: Warning. */ 761 #define MUM_EVENT_LEVEL_WARN 0x1 762 /* enum: Error. */ 763 #define MUM_EVENT_LEVEL_ERR 0x2 764 /* enum: Fatal. */ 765 #define MUM_EVENT_LEVEL_FATAL 0x3 766 #define MUM_EVENT_DATA_OFST 0 767 #define MUM_EVENT_SENSOR_ID_LBN 0 768 #define MUM_EVENT_SENSOR_ID_WIDTH 8 769 /* Enum values, see field(s): */ 770 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 771 #define MUM_EVENT_SENSOR_STATE_LBN 8 772 #define MUM_EVENT_SENSOR_STATE_WIDTH 8 773 #define MUM_EVENT_PORT_PHY_READY_LBN 0 774 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1 775 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 776 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 777 #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 778 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 779 #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 780 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 781 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 782 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 783 #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 784 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 785 #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 786 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 787 #define MUM_EVENT_DATA_LBN 0 788 #define MUM_EVENT_DATA_WIDTH 32 789 #define MUM_EVENT_SRC_LBN 36 790 #define MUM_EVENT_SRC_WIDTH 8 791 #define MUM_EVENT_EV_CODE_LBN 60 792 #define MUM_EVENT_EV_CODE_WIDTH 4 793 #define MUM_EVENT_CODE_LBN 44 794 #define MUM_EVENT_CODE_WIDTH 8 795 /* enum: The MUM was rebooted. */ 796 #define MUM_EVENT_CODE_REBOOT 0x1 797 /* enum: Bad assert. */ 798 #define MUM_EVENT_CODE_ASSERT 0x2 799 /* enum: Sensor failure. */ 800 #define MUM_EVENT_CODE_SENSOR 0x3 801 /* enum: Link fault has been asserted, or has cleared. */ 802 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 803 #define MUM_EVENT_SENSOR_DATA_OFST 0 804 #define MUM_EVENT_SENSOR_DATA_LBN 0 805 #define MUM_EVENT_SENSOR_DATA_WIDTH 32 806 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 807 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 808 #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 809 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 810 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 811 #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 812 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0 813 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0 814 #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 815 #define MUM_EVENT_PORT_PHY_TECH_OFST 0 816 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ 817 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ 818 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ 819 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ 820 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ 821 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ 822 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ 823 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ 824 #define MUM_EVENT_PORT_PHY_TECH_LBN 0 825 #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 826 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 827 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 828 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ 829 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ 830 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ 831 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ 832 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ 833 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 834 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 835 836 837 /***********************************/ 838 /* MC_CMD_READ32 839 * Read multiple 32byte words from MC memory. 840 */ 841 #define MC_CMD_READ32 0x1 842 843 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 844 845 /* MC_CMD_READ32_IN msgrequest */ 846 #define MC_CMD_READ32_IN_LEN 8 847 #define MC_CMD_READ32_IN_ADDR_OFST 0 848 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 849 850 /* MC_CMD_READ32_OUT msgresponse */ 851 #define MC_CMD_READ32_OUT_LENMIN 4 852 #define MC_CMD_READ32_OUT_LENMAX 252 853 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 854 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 855 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 856 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 857 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 858 859 860 /***********************************/ 861 /* MC_CMD_WRITE32 862 * Write multiple 32byte words to MC memory. 863 */ 864 #define MC_CMD_WRITE32 0x2 865 866 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 867 868 /* MC_CMD_WRITE32_IN msgrequest */ 869 #define MC_CMD_WRITE32_IN_LENMIN 8 870 #define MC_CMD_WRITE32_IN_LENMAX 252 871 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 872 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 873 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 874 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 875 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 876 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 877 878 /* MC_CMD_WRITE32_OUT msgresponse */ 879 #define MC_CMD_WRITE32_OUT_LEN 0 880 881 882 /***********************************/ 883 /* MC_CMD_COPYCODE 884 * Copy MC code between two locations and jump. 885 */ 886 #define MC_CMD_COPYCODE 0x3 887 888 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN 889 890 /* MC_CMD_COPYCODE_IN msgrequest */ 891 #define MC_CMD_COPYCODE_IN_LEN 16 892 /* Source address 893 * 894 * The main image should be entered via a copy of a single word from and to a 895 * magic address, which controls various aspects of the boot. The magic address 896 * is a bitfield, with each bit as documented below. 897 */ 898 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 899 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ 900 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 901 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and 902 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) 903 */ 904 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 905 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, 906 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see 907 * below) 908 */ 909 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 910 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 911 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 912 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 913 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 914 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 915 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 916 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 917 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 918 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 919 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 920 /* Destination address */ 921 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 922 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 923 /* Address of where to jump after copy. */ 924 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 925 /* enum: Control should return to the caller rather than jumping */ 926 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 927 928 /* MC_CMD_COPYCODE_OUT msgresponse */ 929 #define MC_CMD_COPYCODE_OUT_LEN 0 930 931 932 /***********************************/ 933 /* MC_CMD_SET_FUNC 934 * Select function for function-specific commands. 935 */ 936 #define MC_CMD_SET_FUNC 0x4 937 938 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 939 940 /* MC_CMD_SET_FUNC_IN msgrequest */ 941 #define MC_CMD_SET_FUNC_IN_LEN 4 942 /* Set function */ 943 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 944 945 /* MC_CMD_SET_FUNC_OUT msgresponse */ 946 #define MC_CMD_SET_FUNC_OUT_LEN 0 947 948 949 /***********************************/ 950 /* MC_CMD_GET_BOOT_STATUS 951 * Get the instruction address from which the MC booted. 952 */ 953 #define MC_CMD_GET_BOOT_STATUS 0x5 954 955 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 956 957 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 958 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 959 960 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 961 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 962 /* ?? */ 963 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 964 /* enum: indicates that the MC wasn't flash booted */ 965 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef 966 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 967 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 968 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 969 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 970 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 971 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 972 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 973 974 975 /***********************************/ 976 /* MC_CMD_GET_ASSERTS 977 * Get (and optionally clear) the current assertion status. Only 978 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other 979 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS 980 */ 981 #define MC_CMD_GET_ASSERTS 0x6 982 983 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 984 985 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 986 #define MC_CMD_GET_ASSERTS_IN_LEN 4 987 /* Set to clear assertion */ 988 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 989 990 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 991 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 992 /* Assertion status flag. */ 993 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 994 /* enum: No assertions have failed. */ 995 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 996 /* enum: A system-level assertion has failed. */ 997 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 998 /* enum: A thread-level assertion has failed. */ 999 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 1000 /* enum: The system was reset by the watchdog. */ 1001 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 1002 /* enum: An illegal address trap stopped the system (huntington and later) */ 1003 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 1004 /* Failing PC value */ 1005 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 1006 /* Saved GP regs */ 1007 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 1008 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 1009 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 1010 /* enum: A magic value hinting that the value in this register at the time of 1011 * the failure has likely been lost. 1012 */ 1013 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 1014 /* Failing thread address */ 1015 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 1016 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 1017 1018 1019 /***********************************/ 1020 /* MC_CMD_LOG_CTRL 1021 * Configure the output stream for log events such as link state changes, 1022 * sensor notifications and MCDI completions 1023 */ 1024 #define MC_CMD_LOG_CTRL 0x7 1025 1026 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1027 1028 /* MC_CMD_LOG_CTRL_IN msgrequest */ 1029 #define MC_CMD_LOG_CTRL_IN_LEN 8 1030 /* Log destination */ 1031 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 1032 /* enum: UART. */ 1033 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 1034 /* enum: Event queue. */ 1035 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 1036 /* Legacy argument. Must be zero. */ 1037 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 1038 1039 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 1040 #define MC_CMD_LOG_CTRL_OUT_LEN 0 1041 1042 1043 /***********************************/ 1044 /* MC_CMD_GET_VERSION 1045 * Get version information about the MC firmware. 1046 */ 1047 #define MC_CMD_GET_VERSION 0x8 1048 1049 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1050 1051 /* MC_CMD_GET_VERSION_IN msgrequest */ 1052 #define MC_CMD_GET_VERSION_IN_LEN 0 1053 1054 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ 1055 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 1056 /* placeholder, set to 0 */ 1057 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 1058 1059 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ 1060 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 1061 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 1062 /* enum: Reserved version number to indicate "any" version. */ 1063 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 1064 /* enum: Bootrom version value for Siena. */ 1065 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 1066 /* enum: Bootrom version value for Huntington. */ 1067 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 1068 1069 /* MC_CMD_GET_VERSION_OUT msgresponse */ 1070 #define MC_CMD_GET_VERSION_OUT_LEN 32 1071 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1072 /* Enum values, see field(s): */ 1073 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1074 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 1075 /* 128bit mask of functions supported by the current firmware */ 1076 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 1077 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 1078 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 1079 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 1080 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 1081 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 1082 1083 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 1084 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 1085 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1086 /* Enum values, see field(s): */ 1087 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1088 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 1089 /* 128bit mask of functions supported by the current firmware */ 1090 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 1091 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 1092 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 1093 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 1094 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 1095 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 1096 /* extra info */ 1097 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 1098 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 1099 1100 1101 /***********************************/ 1102 /* MC_CMD_PTP 1103 * Perform PTP operation 1104 */ 1105 #define MC_CMD_PTP 0xb 1106 1107 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1108 1109 /* MC_CMD_PTP_IN msgrequest */ 1110 #define MC_CMD_PTP_IN_LEN 1 1111 /* PTP operation code */ 1112 #define MC_CMD_PTP_IN_OP_OFST 0 1113 #define MC_CMD_PTP_IN_OP_LEN 1 1114 /* enum: Enable PTP packet timestamping operation. */ 1115 #define MC_CMD_PTP_OP_ENABLE 0x1 1116 /* enum: Disable PTP packet timestamping operation. */ 1117 #define MC_CMD_PTP_OP_DISABLE 0x2 1118 /* enum: Send a PTP packet. */ 1119 #define MC_CMD_PTP_OP_TRANSMIT 0x3 1120 /* enum: Read the current NIC time. */ 1121 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 1122 /* enum: Get the current PTP status. */ 1123 #define MC_CMD_PTP_OP_STATUS 0x5 1124 /* enum: Adjust the PTP NIC's time. */ 1125 #define MC_CMD_PTP_OP_ADJUST 0x6 1126 /* enum: Synchronize host and NIC time. */ 1127 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 1128 /* enum: Basic manufacturing tests. */ 1129 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 1130 /* enum: Packet based manufacturing tests. */ 1131 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 1132 /* enum: Reset some of the PTP related statistics */ 1133 #define MC_CMD_PTP_OP_RESET_STATS 0xa 1134 /* enum: Debug operations to MC. */ 1135 #define MC_CMD_PTP_OP_DEBUG 0xb 1136 /* enum: Read an FPGA register */ 1137 #define MC_CMD_PTP_OP_FPGAREAD 0xc 1138 /* enum: Write an FPGA register */ 1139 #define MC_CMD_PTP_OP_FPGAWRITE 0xd 1140 /* enum: Apply an offset to the NIC clock */ 1141 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe 1142 /* enum: Change Apply an offset to the NIC clock */ 1143 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf 1144 /* enum: Set the MC packet filter VLAN tags for received PTP packets */ 1145 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 1146 /* enum: Set the MC packet filter UUID for received PTP packets */ 1147 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 1148 /* enum: Set the MC packet filter Domain for received PTP packets */ 1149 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 1150 /* enum: Set the clock source */ 1151 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 1152 /* enum: Reset value of Timer Reg. */ 1153 #define MC_CMD_PTP_OP_RST_CLK 0x14 1154 /* enum: Enable the forwarding of PPS events to the host */ 1155 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 1156 /* enum: Get the time format used by this NIC for PTP operations */ 1157 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 1158 /* enum: Get the clock attributes. NOTE- extended version of 1159 * MC_CMD_PTP_OP_GET_TIME_FORMAT 1160 */ 1161 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 1162 /* enum: Get corrections that should be applied to the various different 1163 * timestamps 1164 */ 1165 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 1166 /* enum: Subscribe to receive periodic time events indicating the current NIC 1167 * time 1168 */ 1169 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 1170 /* enum: Unsubscribe to stop receiving time events */ 1171 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 1172 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS 1173 * input on the same NIC. 1174 */ 1175 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a 1176 /* enum: Set the PTP sync status. Status is used by firmware to report to event 1177 * subscribers. 1178 */ 1179 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b 1180 /* enum: Above this for future use. */ 1181 #define MC_CMD_PTP_OP_MAX 0x1c 1182 1183 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 1184 #define MC_CMD_PTP_IN_ENABLE_LEN 16 1185 #define MC_CMD_PTP_IN_CMD_OFST 0 1186 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 1187 /* Event queue for PTP events */ 1188 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 1189 /* PTP timestamping mode */ 1190 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 1191 /* enum: PTP, version 1 */ 1192 #define MC_CMD_PTP_MODE_V1 0x0 1193 /* enum: PTP, version 1, with VLAN headers - deprecated */ 1194 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 1195 /* enum: PTP, version 2 */ 1196 #define MC_CMD_PTP_MODE_V2 0x2 1197 /* enum: PTP, version 2, with VLAN headers - deprecated */ 1198 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 1199 /* enum: PTP, version 2, with improved UUID filtering */ 1200 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 1201 /* enum: FCoE (seconds and microseconds) */ 1202 #define MC_CMD_PTP_MODE_FCOE 0x5 1203 1204 /* MC_CMD_PTP_IN_DISABLE msgrequest */ 1205 #define MC_CMD_PTP_IN_DISABLE_LEN 8 1206 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1207 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1208 1209 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 1210 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 1211 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 1212 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 1213 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1214 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1215 /* Transmit packet length */ 1216 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 1217 /* Transmit packet data */ 1218 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 1219 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 1220 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 1221 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 1222 1223 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 1224 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 1225 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1226 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1227 1228 /* MC_CMD_PTP_IN_STATUS msgrequest */ 1229 #define MC_CMD_PTP_IN_STATUS_LEN 8 1230 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1231 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1232 1233 /* MC_CMD_PTP_IN_ADJUST msgrequest */ 1234 #define MC_CMD_PTP_IN_ADJUST_LEN 24 1235 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1236 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1237 /* Frequency adjustment 40 bit fixed point ns */ 1238 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 1239 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 1240 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 1241 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 1242 /* enum: Number of fractional bits in frequency adjustment */ 1243 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 1244 /* Time adjustment in seconds */ 1245 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 1246 /* Time adjustment major value */ 1247 #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 1248 /* Time adjustment in nanoseconds */ 1249 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 1250 /* Time adjustment minor value */ 1251 #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 1252 1253 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 1254 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 1255 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1256 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1257 /* Number of time readings to capture */ 1258 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 1259 /* Host address in which to write "synchronization started" indication (64 1260 * bits) 1261 */ 1262 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 1263 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 1264 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 1265 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 1266 1267 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 1268 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 1269 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1270 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1271 1272 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 1273 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 1274 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1275 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1276 /* Enable or disable packet testing */ 1277 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 1278 1279 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ 1280 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 1281 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1282 /* Reset PTP statistics */ 1283 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1284 1285 /* MC_CMD_PTP_IN_DEBUG msgrequest */ 1286 #define MC_CMD_PTP_IN_DEBUG_LEN 12 1287 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1288 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1289 /* Debug operations */ 1290 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 1291 1292 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ 1293 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 1294 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1295 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1296 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 1297 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 1298 1299 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ 1300 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 1301 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 1302 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) 1303 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1304 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1305 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 1306 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 1307 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 1308 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 1309 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 1310 1311 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ 1312 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 1313 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1314 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1315 /* Time adjustment in seconds */ 1316 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 1317 /* Time adjustment major value */ 1318 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 1319 /* Time adjustment in nanoseconds */ 1320 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 1321 /* Time adjustment minor value */ 1322 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 1323 1324 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ 1325 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 1326 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1327 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1328 /* Frequency adjustment 40 bit fixed point ns */ 1329 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 1330 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 1331 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 1332 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 1333 /* enum: Number of fractional bits in frequency adjustment */ 1334 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ 1335 1336 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ 1337 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 1338 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1339 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1340 /* Number of VLAN tags, 0 if not VLAN */ 1341 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 1342 /* Set of VLAN tags to filter against */ 1343 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 1344 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 1345 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 1346 1347 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ 1348 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 1349 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1350 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1351 /* 1 to enable UUID filtering, 0 to disable */ 1352 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 1353 /* UUID to filter against */ 1354 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 1355 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 1356 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 1357 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 1358 1359 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ 1360 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 1361 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1362 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1363 /* 1 to enable Domain filtering, 0 to disable */ 1364 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 1365 /* Domain number to filter against */ 1366 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 1367 1368 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ 1369 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 1370 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1371 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1372 /* Set the clock source. */ 1373 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 1374 /* enum: Internal. */ 1375 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 1376 /* enum: External. */ 1377 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 1378 1379 /* MC_CMD_PTP_IN_RST_CLK msgrequest */ 1380 #define MC_CMD_PTP_IN_RST_CLK_LEN 8 1381 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1382 /* Reset value of Timer Reg. */ 1383 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1384 1385 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ 1386 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 1387 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1388 /* Enable or disable */ 1389 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 1390 /* enum: Enable */ 1391 #define MC_CMD_PTP_ENABLE_PPS 0x0 1392 /* enum: Disable */ 1393 #define MC_CMD_PTP_DISABLE_PPS 0x1 1394 /* Queue id to send events back */ 1395 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 1396 1397 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ 1398 #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 1399 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1400 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1401 1402 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ 1403 #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 1404 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1405 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1406 1407 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ 1408 #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 1409 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1410 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1411 1412 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ 1413 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 1414 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1415 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1416 /* Original field containing queue ID. Now extended to include flags. */ 1417 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 1418 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0 1419 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16 1420 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31 1421 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1 1422 1423 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ 1424 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 1425 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1426 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1427 /* Unsubscribe options */ 1428 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 1429 /* enum: Unsubscribe a single queue */ 1430 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 1431 /* enum: Unsubscribe all queues */ 1432 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 1433 /* Event queue ID */ 1434 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 1435 1436 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ 1437 #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 1438 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1439 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1440 /* 1 to enable PPS test mode, 0 to disable and return result. */ 1441 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 1442 1443 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ 1444 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 1445 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1446 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1447 /* NIC - Host System Clock Synchronization status */ 1448 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 1449 /* enum: Host System clock and NIC clock are not in sync */ 1450 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 1451 /* enum: Host System clock and NIC clock are synchronized */ 1452 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 1453 /* If synchronized, number of seconds until clocks should be considered to be 1454 * no longer in sync. 1455 */ 1456 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 1457 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 1458 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 1459 1460 /* MC_CMD_PTP_OUT msgresponse */ 1461 #define MC_CMD_PTP_OUT_LEN 0 1462 1463 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 1464 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 1465 /* Value of seconds timestamp */ 1466 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 1467 /* Timestamp major value */ 1468 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 1469 /* Value of nanoseconds timestamp */ 1470 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 1471 /* Timestamp minor value */ 1472 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 1473 1474 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ 1475 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 1476 1477 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ 1478 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 1479 1480 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 1481 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 1482 /* Value of seconds timestamp */ 1483 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 1484 /* Timestamp major value */ 1485 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 1486 /* Value of nanoseconds timestamp */ 1487 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 1488 /* Timestamp minor value */ 1489 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 1490 1491 /* MC_CMD_PTP_OUT_STATUS msgresponse */ 1492 #define MC_CMD_PTP_OUT_STATUS_LEN 64 1493 /* Frequency of NIC's hardware clock */ 1494 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 1495 /* Number of packets transmitted and timestamped */ 1496 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 1497 /* Number of packets received and timestamped */ 1498 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 1499 /* Number of packets timestamped by the FPGA */ 1500 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 1501 /* Number of packets filter matched */ 1502 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 1503 /* Number of packets not filter matched */ 1504 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 1505 /* Number of PPS overflows (noise on input?) */ 1506 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 1507 /* Number of PPS bad periods */ 1508 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 1509 /* Minimum period of PPS pulse in nanoseconds */ 1510 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 1511 /* Maximum period of PPS pulse in nanoseconds */ 1512 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 1513 /* Last period of PPS pulse in nanoseconds */ 1514 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 1515 /* Mean period of PPS pulse in nanoseconds */ 1516 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 1517 /* Minimum offset of PPS pulse in nanoseconds (signed) */ 1518 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 1519 /* Maximum offset of PPS pulse in nanoseconds (signed) */ 1520 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 1521 /* Last offset of PPS pulse in nanoseconds (signed) */ 1522 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 1523 /* Mean offset of PPS pulse in nanoseconds (signed) */ 1524 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 1525 1526 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 1527 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 1528 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 1529 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 1530 /* A set of host and NIC times */ 1531 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 1532 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 1533 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 1534 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 1535 /* Host time immediately before NIC's hardware clock read */ 1536 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 1537 /* Value of seconds timestamp */ 1538 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 1539 /* Timestamp major value */ 1540 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 1541 /* Value of nanoseconds timestamp */ 1542 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 1543 /* Timestamp minor value */ 1544 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 1545 /* Host time immediately after NIC's hardware clock read */ 1546 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 1547 /* Number of nanoseconds waited after reading NIC's hardware clock */ 1548 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 1549 1550 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 1551 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 1552 /* Results of testing */ 1553 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 1554 /* enum: Successful test */ 1555 #define MC_CMD_PTP_MANF_SUCCESS 0x0 1556 /* enum: FPGA load failed */ 1557 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 1558 /* enum: FPGA version invalid */ 1559 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 1560 /* enum: FPGA registers incorrect */ 1561 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 1562 /* enum: Oscillator possibly not working? */ 1563 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 1564 /* enum: Timestamps not increasing */ 1565 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 1566 /* enum: Mismatched packet count */ 1567 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 1568 /* enum: Mismatched packet count (Siena filter and FPGA) */ 1569 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 1570 /* enum: Not enough packets to perform timestamp check */ 1571 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 1572 /* enum: Timestamp trigger GPIO not working */ 1573 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 1574 /* enum: Insufficient PPS events to perform checks */ 1575 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa 1576 /* enum: PPS time event period not sufficiently close to 1s. */ 1577 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb 1578 /* enum: PPS time event nS reading not sufficiently close to zero. */ 1579 #define MC_CMD_PTP_MANF_PPS_NS 0xc 1580 /* enum: PTP peripheral registers incorrect */ 1581 #define MC_CMD_PTP_MANF_REGISTERS 0xd 1582 /* enum: Failed to read time from PTP peripheral */ 1583 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe 1584 /* Presence of external oscillator */ 1585 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 1586 1587 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 1588 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 1589 /* Results of testing */ 1590 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 1591 /* Number of packets received by FPGA */ 1592 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 1593 /* Number of packets received by Siena filters */ 1594 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 1595 1596 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ 1597 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 1598 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 1599 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) 1600 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 1601 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 1602 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 1603 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 1604 1605 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ 1606 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 1607 /* Time format required/used by for this NIC. Applies to all PTP MCDI 1608 * operations that pass times between the host and firmware. If this operation 1609 * is not supported (older firmware) a format of seconds and nanoseconds should 1610 * be assumed. 1611 */ 1612 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 1613 /* enum: Times are in seconds and nanoseconds */ 1614 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 1615 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 1616 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 1617 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 1618 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 1619 1620 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ 1621 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 1622 /* Time format required/used by for this NIC. Applies to all PTP MCDI 1623 * operations that pass times between the host and firmware. If this operation 1624 * is not supported (older firmware) a format of seconds and nanoseconds should 1625 * be assumed. 1626 */ 1627 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 1628 /* enum: Times are in seconds and nanoseconds */ 1629 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 1630 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 1631 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 1632 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 1633 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 1634 /* Minimum acceptable value for a corrected synchronization timeset. When 1635 * comparing host and NIC clock times, the MC returns a set of samples that 1636 * contain the host start and end time, the MC time when the host start was 1637 * detected and the time the MC waited between reading the time and detecting 1638 * the host end. The corrected sync window is the difference between the host 1639 * end and start times minus the time that the MC waited for host end. 1640 */ 1641 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 1642 /* Various PTP capabilities */ 1643 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 1644 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 1645 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 1646 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 1647 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 1648 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 1649 1650 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ 1651 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 1652 /* Uncorrected error on transmit timestamps in NIC clock format */ 1653 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 1654 /* Uncorrected error on receive timestamps in NIC clock format */ 1655 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 1656 /* Uncorrected error on PPS output in NIC clock format */ 1657 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 1658 /* Uncorrected error on PPS input in NIC clock format */ 1659 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 1660 1661 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ 1662 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 1663 /* Results of testing */ 1664 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 1665 /* Enum values, see field(s): */ 1666 /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ 1667 1668 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ 1669 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 1670 1671 1672 /***********************************/ 1673 /* MC_CMD_CSR_READ32 1674 * Read 32bit words from the indirect memory map. 1675 */ 1676 #define MC_CMD_CSR_READ32 0xc 1677 1678 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1679 1680 /* MC_CMD_CSR_READ32_IN msgrequest */ 1681 #define MC_CMD_CSR_READ32_IN_LEN 12 1682 /* Address */ 1683 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 1684 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 1685 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 1686 1687 /* MC_CMD_CSR_READ32_OUT msgresponse */ 1688 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 1689 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 1690 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 1691 /* The last dword is the status, not a value read */ 1692 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 1693 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 1694 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 1695 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 1696 1697 1698 /***********************************/ 1699 /* MC_CMD_CSR_WRITE32 1700 * Write 32bit dwords to the indirect memory map. 1701 */ 1702 #define MC_CMD_CSR_WRITE32 0xd 1703 1704 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1705 1706 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 1707 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 1708 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 1709 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 1710 /* Address */ 1711 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 1712 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 1713 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 1714 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 1715 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 1716 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 1717 1718 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 1719 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 1720 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 1721 1722 1723 /***********************************/ 1724 /* MC_CMD_HP 1725 * These commands are used for HP related features. They are grouped under one 1726 * MCDI command to avoid creating too many MCDI commands. 1727 */ 1728 #define MC_CMD_HP 0x54 1729 1730 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1731 1732 /* MC_CMD_HP_IN msgrequest */ 1733 #define MC_CMD_HP_IN_LEN 16 1734 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 1735 * the specified address with the specified interval.When address is NULL, 1736 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 1737 * state / 2: (debug) Show temperature reported by one of the supported 1738 * sensors. 1739 */ 1740 #define MC_CMD_HP_IN_SUBCMD_OFST 0 1741 /* enum: OCSD (Option Card Sensor Data) sub-command. */ 1742 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 1743 /* enum: Last known valid HP sub-command. */ 1744 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 1745 /* The address to the array of sensor fields. (Or NULL to use a sub-command.) 1746 */ 1747 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 1748 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 1749 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 1750 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 1751 /* The requested update interval, in seconds. (Or the sub-command if ADDR is 1752 * NULL.) 1753 */ 1754 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 1755 1756 /* MC_CMD_HP_OUT msgresponse */ 1757 #define MC_CMD_HP_OUT_LEN 4 1758 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 1759 /* enum: OCSD stopped for this card. */ 1760 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 1761 /* enum: OCSD was successfully started with the address provided. */ 1762 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 1763 /* enum: OCSD was already started for this card. */ 1764 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 1765 1766 1767 /***********************************/ 1768 /* MC_CMD_STACKINFO 1769 * Get stack information. 1770 */ 1771 #define MC_CMD_STACKINFO 0xf 1772 1773 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1774 1775 /* MC_CMD_STACKINFO_IN msgrequest */ 1776 #define MC_CMD_STACKINFO_IN_LEN 0 1777 1778 /* MC_CMD_STACKINFO_OUT msgresponse */ 1779 #define MC_CMD_STACKINFO_OUT_LENMIN 12 1780 #define MC_CMD_STACKINFO_OUT_LENMAX 252 1781 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 1782 /* (thread ptr, stack size, free space) for each thread in system */ 1783 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 1784 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 1785 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 1786 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 1787 1788 1789 /***********************************/ 1790 /* MC_CMD_MDIO_READ 1791 * MDIO register read. 1792 */ 1793 #define MC_CMD_MDIO_READ 0x10 1794 1795 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1796 1797 /* MC_CMD_MDIO_READ_IN msgrequest */ 1798 #define MC_CMD_MDIO_READ_IN_LEN 16 1799 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 1800 * external devices. 1801 */ 1802 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 1803 /* enum: Internal. */ 1804 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 1805 /* enum: External. */ 1806 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 1807 /* Port address */ 1808 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 1809 /* Device Address or clause 22. */ 1810 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 1811 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 1812 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 1813 */ 1814 #define MC_CMD_MDIO_CLAUSE22 0x20 1815 /* Address */ 1816 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 1817 1818 /* MC_CMD_MDIO_READ_OUT msgresponse */ 1819 #define MC_CMD_MDIO_READ_OUT_LEN 8 1820 /* Value */ 1821 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 1822 /* Status the MDIO commands return the raw status bits from the MDIO block. A 1823 * "good" transaction should have the DONE bit set and all other bits clear. 1824 */ 1825 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 1826 /* enum: Good. */ 1827 #define MC_CMD_MDIO_STATUS_GOOD 0x8 1828 1829 1830 /***********************************/ 1831 /* MC_CMD_MDIO_WRITE 1832 * MDIO register write. 1833 */ 1834 #define MC_CMD_MDIO_WRITE 0x11 1835 1836 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1837 1838 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 1839 #define MC_CMD_MDIO_WRITE_IN_LEN 20 1840 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 1841 * external devices. 1842 */ 1843 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 1844 /* enum: Internal. */ 1845 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 1846 /* enum: External. */ 1847 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 1848 /* Port address */ 1849 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 1850 /* Device Address or clause 22. */ 1851 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 1852 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 1853 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 1854 */ 1855 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 1856 /* Address */ 1857 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 1858 /* Value */ 1859 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 1860 1861 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 1862 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 1863 /* Status; the MDIO commands return the raw status bits from the MDIO block. A 1864 * "good" transaction should have the DONE bit set and all other bits clear. 1865 */ 1866 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 1867 /* enum: Good. */ 1868 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 1869 1870 1871 /***********************************/ 1872 /* MC_CMD_DBI_WRITE 1873 * Write DBI register(s). 1874 */ 1875 #define MC_CMD_DBI_WRITE 0x12 1876 1877 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1878 1879 /* MC_CMD_DBI_WRITE_IN msgrequest */ 1880 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 1881 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 1882 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 1883 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 1884 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 1885 */ 1886 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 1887 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 1888 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 1889 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 1890 1891 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 1892 #define MC_CMD_DBI_WRITE_OUT_LEN 0 1893 1894 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 1895 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 1896 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 1897 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 1898 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 1899 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 1900 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 1901 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 1902 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 1903 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 1904 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 1905 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 1906 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 1907 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 1908 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 1909 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 1910 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 1911 1912 1913 /***********************************/ 1914 /* MC_CMD_PORT_READ32 1915 * Read a 32-bit register from the indirect port register map. The port to 1916 * access is implied by the Shared memory channel used. 1917 */ 1918 #define MC_CMD_PORT_READ32 0x14 1919 1920 /* MC_CMD_PORT_READ32_IN msgrequest */ 1921 #define MC_CMD_PORT_READ32_IN_LEN 4 1922 /* Address */ 1923 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 1924 1925 /* MC_CMD_PORT_READ32_OUT msgresponse */ 1926 #define MC_CMD_PORT_READ32_OUT_LEN 8 1927 /* Value */ 1928 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 1929 /* Status */ 1930 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 1931 1932 1933 /***********************************/ 1934 /* MC_CMD_PORT_WRITE32 1935 * Write a 32-bit register to the indirect port register map. The port to 1936 * access is implied by the Shared memory channel used. 1937 */ 1938 #define MC_CMD_PORT_WRITE32 0x15 1939 1940 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 1941 #define MC_CMD_PORT_WRITE32_IN_LEN 8 1942 /* Address */ 1943 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 1944 /* Value */ 1945 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 1946 1947 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 1948 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 1949 /* Status */ 1950 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 1951 1952 1953 /***********************************/ 1954 /* MC_CMD_PORT_READ128 1955 * Read a 128-bit register from the indirect port register map. The port to 1956 * access is implied by the Shared memory channel used. 1957 */ 1958 #define MC_CMD_PORT_READ128 0x16 1959 1960 /* MC_CMD_PORT_READ128_IN msgrequest */ 1961 #define MC_CMD_PORT_READ128_IN_LEN 4 1962 /* Address */ 1963 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 1964 1965 /* MC_CMD_PORT_READ128_OUT msgresponse */ 1966 #define MC_CMD_PORT_READ128_OUT_LEN 20 1967 /* Value */ 1968 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 1969 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 1970 /* Status */ 1971 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 1972 1973 1974 /***********************************/ 1975 /* MC_CMD_PORT_WRITE128 1976 * Write a 128-bit register to the indirect port register map. The port to 1977 * access is implied by the Shared memory channel used. 1978 */ 1979 #define MC_CMD_PORT_WRITE128 0x17 1980 1981 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 1982 #define MC_CMD_PORT_WRITE128_IN_LEN 20 1983 /* Address */ 1984 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 1985 /* Value */ 1986 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 1987 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 1988 1989 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 1990 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 1991 /* Status */ 1992 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 1993 1994 /* MC_CMD_CAPABILITIES structuredef */ 1995 #define MC_CMD_CAPABILITIES_LEN 4 1996 /* Small buf table. */ 1997 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 1998 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 1999 /* Turbo mode (for Maranello). */ 2000 #define MC_CMD_CAPABILITIES_TURBO_LBN 1 2001 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 2002 /* Turbo mode active (for Maranello). */ 2003 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 2004 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 2005 /* PTP offload. */ 2006 #define MC_CMD_CAPABILITIES_PTP_LBN 3 2007 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 2008 /* AOE mode. */ 2009 #define MC_CMD_CAPABILITIES_AOE_LBN 4 2010 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 2011 /* AOE mode active. */ 2012 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 2013 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 2014 /* AOE mode active. */ 2015 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 2016 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 2017 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 2018 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 2019 2020 2021 /***********************************/ 2022 /* MC_CMD_GET_BOARD_CFG 2023 * Returns the MC firmware configuration structure. 2024 */ 2025 #define MC_CMD_GET_BOARD_CFG 0x18 2026 2027 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2028 2029 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 2030 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 2031 2032 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 2033 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 2034 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 2035 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 2036 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 2037 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 2038 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 2039 /* See MC_CMD_CAPABILITIES */ 2040 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 2041 /* See MC_CMD_CAPABILITIES */ 2042 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 2043 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 2044 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 2045 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 2046 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 2047 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 2048 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 2049 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 2050 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 2051 /* This field contains a 16-bit value for each of the types of NVRAM area. The 2052 * values are defined in the firmware/mc/platform/.c file for a specific board 2053 * type, but otherwise have no meaning to the MC; they are used by the driver 2054 * to manage selection of appropriate firmware updates. 2055 */ 2056 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 2057 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 2058 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 2059 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 2060 2061 2062 /***********************************/ 2063 /* MC_CMD_DBI_READX 2064 * Read DBI register(s) -- extended functionality 2065 */ 2066 #define MC_CMD_DBI_READX 0x19 2067 2068 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2069 2070 /* MC_CMD_DBI_READX_IN msgrequest */ 2071 #define MC_CMD_DBI_READX_IN_LENMIN 8 2072 #define MC_CMD_DBI_READX_IN_LENMAX 248 2073 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 2074 /* Each Read op consists of an address (offset 0), VF/CS2) */ 2075 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 2076 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 2077 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 2078 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 2079 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 2080 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 2081 2082 /* MC_CMD_DBI_READX_OUT msgresponse */ 2083 #define MC_CMD_DBI_READX_OUT_LENMIN 4 2084 #define MC_CMD_DBI_READX_OUT_LENMAX 252 2085 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 2086 /* Value */ 2087 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 2088 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 2089 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 2090 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 2091 2092 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 2093 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 2094 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 2095 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 2096 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 2097 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 2098 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 2099 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 2100 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 2101 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 2102 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 2103 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 2104 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 2105 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 2106 2107 2108 /***********************************/ 2109 /* MC_CMD_SET_RAND_SEED 2110 * Set the 16byte seed for the MC pseudo-random generator. 2111 */ 2112 #define MC_CMD_SET_RAND_SEED 0x1a 2113 2114 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2115 2116 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 2117 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 2118 /* Seed value. */ 2119 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 2120 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 2121 2122 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 2123 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 2124 2125 2126 /***********************************/ 2127 /* MC_CMD_LTSSM_HIST 2128 * Retrieve the history of the LTSSM, if the build supports it. 2129 */ 2130 #define MC_CMD_LTSSM_HIST 0x1b 2131 2132 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 2133 #define MC_CMD_LTSSM_HIST_IN_LEN 0 2134 2135 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 2136 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 2137 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 2138 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 2139 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 2140 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 2141 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 2142 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 2143 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 2144 2145 2146 /***********************************/ 2147 /* MC_CMD_DRV_ATTACH 2148 * Inform MCPU that this port is managed on the host (i.e. driver active). For 2149 * Huntington, also request the preferred datapath firmware to use if possible 2150 * (it may not be possible for this request to be fulfilled; the driver must 2151 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which 2152 * features are actually available). The FIRMWARE_ID field is ignored by older 2153 * platforms. 2154 */ 2155 #define MC_CMD_DRV_ATTACH 0x1c 2156 2157 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2158 2159 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 2160 #define MC_CMD_DRV_ATTACH_IN_LEN 12 2161 /* new state (0=detached, 1=attached) to set if UPDATE=1 */ 2162 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 2163 /* 1 to set new state, or 0 to just report the existing state */ 2164 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 2165 /* preferred datapath firmware (for Huntington; ignored for Siena) */ 2166 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 2167 /* enum: Prefer to use full featured firmware */ 2168 #define MC_CMD_FW_FULL_FEATURED 0x0 2169 /* enum: Prefer to use firmware with fewer features but lower latency */ 2170 #define MC_CMD_FW_LOW_LATENCY 0x1 2171 /* enum: Prefer to use firmware for SolarCapture packed stream mode */ 2172 #define MC_CMD_FW_PACKED_STREAM 0x2 2173 /* enum: Prefer to use firmware with fewer features and simpler TX event 2174 * batching but higher TX packet rate 2175 */ 2176 #define MC_CMD_FW_HIGH_TX_RATE 0x3 2177 /* enum: Reserved value */ 2178 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 2179 /* enum: Only this option is allowed for non-admin functions */ 2180 #define MC_CMD_FW_DONT_CARE 0xffffffff 2181 2182 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 2183 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 2184 /* previous or existing state (0=detached, 1=attached) */ 2185 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 2186 2187 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ 2188 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 2189 /* previous or existing state (0=detached, 1=attached) */ 2190 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 2191 /* Flags associated with this function */ 2192 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 2193 /* enum: Labels the lowest-numbered function visible to the OS */ 2194 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 2195 /* enum: The function can control the link state of the physical port it is 2196 * bound to. 2197 */ 2198 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 2199 /* enum: The function can perform privileged operations */ 2200 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 2201 2202 2203 /***********************************/ 2204 /* MC_CMD_SHMUART 2205 * Route UART output to circular buffer in shared memory instead. 2206 */ 2207 #define MC_CMD_SHMUART 0x1f 2208 2209 /* MC_CMD_SHMUART_IN msgrequest */ 2210 #define MC_CMD_SHMUART_IN_LEN 4 2211 /* ??? */ 2212 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 2213 2214 /* MC_CMD_SHMUART_OUT msgresponse */ 2215 #define MC_CMD_SHMUART_OUT_LEN 0 2216 2217 2218 /***********************************/ 2219 /* MC_CMD_PORT_RESET 2220 * Generic per-port reset. There is no equivalent for per-board reset. Locks 2221 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - 2222 * use MC_CMD_ENTITY_RESET instead. 2223 */ 2224 #define MC_CMD_PORT_RESET 0x20 2225 2226 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2227 2228 /* MC_CMD_PORT_RESET_IN msgrequest */ 2229 #define MC_CMD_PORT_RESET_IN_LEN 0 2230 2231 /* MC_CMD_PORT_RESET_OUT msgresponse */ 2232 #define MC_CMD_PORT_RESET_OUT_LEN 0 2233 2234 2235 /***********************************/ 2236 /* MC_CMD_ENTITY_RESET 2237 * Generic per-resource reset. There is no equivalent for per-board reset. 2238 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an 2239 * extended version of the deprecated MC_CMD_PORT_RESET with added fields. 2240 */ 2241 #define MC_CMD_ENTITY_RESET 0x20 2242 /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ 2243 2244 /* MC_CMD_ENTITY_RESET_IN msgrequest */ 2245 #define MC_CMD_ENTITY_RESET_IN_LEN 4 2246 /* Optional flags field. Omitting this will perform a "legacy" reset action 2247 * (TBD). 2248 */ 2249 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 2250 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 2251 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 2252 2253 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 2254 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 2255 2256 2257 /***********************************/ 2258 /* MC_CMD_PCIE_CREDITS 2259 * Read instantaneous and minimum flow control thresholds. 2260 */ 2261 #define MC_CMD_PCIE_CREDITS 0x21 2262 2263 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 2264 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 2265 /* poll period. 0 is disabled */ 2266 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 2267 /* wipe statistics */ 2268 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 2269 2270 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 2271 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 2272 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 2273 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 2274 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 2275 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 2276 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 2277 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 2278 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 2279 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 2280 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 2281 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 2282 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 2283 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 2284 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 2285 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 2286 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 2287 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 2288 2289 2290 /***********************************/ 2291 /* MC_CMD_RXD_MONITOR 2292 * Get histogram of RX queue fill level. 2293 */ 2294 #define MC_CMD_RXD_MONITOR 0x22 2295 2296 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 2297 #define MC_CMD_RXD_MONITOR_IN_LEN 12 2298 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 2299 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 2300 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 2301 2302 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 2303 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 2304 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 2305 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 2306 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 2307 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 2308 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 2309 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 2310 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 2311 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 2312 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 2313 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 2314 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 2315 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 2316 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 2317 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 2318 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 2319 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 2320 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 2321 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 2322 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 2323 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 2324 2325 2326 /***********************************/ 2327 /* MC_CMD_PUTS 2328 * Copy the given ASCII string out onto UART and/or out of the network port. 2329 */ 2330 #define MC_CMD_PUTS 0x23 2331 2332 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2333 2334 /* MC_CMD_PUTS_IN msgrequest */ 2335 #define MC_CMD_PUTS_IN_LENMIN 13 2336 #define MC_CMD_PUTS_IN_LENMAX 252 2337 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 2338 #define MC_CMD_PUTS_IN_DEST_OFST 0 2339 #define MC_CMD_PUTS_IN_UART_LBN 0 2340 #define MC_CMD_PUTS_IN_UART_WIDTH 1 2341 #define MC_CMD_PUTS_IN_PORT_LBN 1 2342 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 2343 #define MC_CMD_PUTS_IN_DHOST_OFST 4 2344 #define MC_CMD_PUTS_IN_DHOST_LEN 6 2345 #define MC_CMD_PUTS_IN_STRING_OFST 12 2346 #define MC_CMD_PUTS_IN_STRING_LEN 1 2347 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 2348 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 2349 2350 /* MC_CMD_PUTS_OUT msgresponse */ 2351 #define MC_CMD_PUTS_OUT_LEN 0 2352 2353 2354 /***********************************/ 2355 /* MC_CMD_GET_PHY_CFG 2356 * Report PHY configuration. This guarantees to succeed even if the PHY is in a 2357 * 'zombie' state. Locks required: None 2358 */ 2359 #define MC_CMD_GET_PHY_CFG 0x24 2360 2361 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2362 2363 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 2364 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 2365 2366 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 2367 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 2368 /* flags */ 2369 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 2370 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 2371 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 2372 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 2373 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 2374 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 2375 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 2376 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 2377 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 2378 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 2379 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 2380 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 2381 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 2382 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 2383 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 2384 /* ?? */ 2385 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 2386 /* Bitmask of supported capabilities */ 2387 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 2388 #define MC_CMD_PHY_CAP_10HDX_LBN 1 2389 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 2390 #define MC_CMD_PHY_CAP_10FDX_LBN 2 2391 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 2392 #define MC_CMD_PHY_CAP_100HDX_LBN 3 2393 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 2394 #define MC_CMD_PHY_CAP_100FDX_LBN 4 2395 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 2396 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 2397 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 2398 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 2399 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 2400 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 2401 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 2402 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 2403 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 2404 #define MC_CMD_PHY_CAP_ASYM_LBN 9 2405 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 2406 #define MC_CMD_PHY_CAP_AN_LBN 10 2407 #define MC_CMD_PHY_CAP_AN_WIDTH 1 2408 #define MC_CMD_PHY_CAP_40000FDX_LBN 11 2409 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 2410 #define MC_CMD_PHY_CAP_DDM_LBN 12 2411 #define MC_CMD_PHY_CAP_DDM_WIDTH 1 2412 /* ?? */ 2413 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 2414 /* ?? */ 2415 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 2416 /* ?? */ 2417 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 2418 /* ?? */ 2419 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 2420 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 2421 /* ?? */ 2422 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 2423 /* enum: Xaui. */ 2424 #define MC_CMD_MEDIA_XAUI 0x1 2425 /* enum: CX4. */ 2426 #define MC_CMD_MEDIA_CX4 0x2 2427 /* enum: KX4. */ 2428 #define MC_CMD_MEDIA_KX4 0x3 2429 /* enum: XFP Far. */ 2430 #define MC_CMD_MEDIA_XFP 0x4 2431 /* enum: SFP+. */ 2432 #define MC_CMD_MEDIA_SFP_PLUS 0x5 2433 /* enum: 10GBaseT. */ 2434 #define MC_CMD_MEDIA_BASE_T 0x6 2435 /* enum: QSFP+. */ 2436 #define MC_CMD_MEDIA_QSFP_PLUS 0x7 2437 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 2438 /* enum: Native clause 22 */ 2439 #define MC_CMD_MMD_CLAUSE22 0x0 2440 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 2441 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 2442 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 2443 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 2444 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 2445 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 2446 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 2447 /* enum: Clause22 proxied over clause45 by PHY. */ 2448 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d 2449 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 2450 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 2451 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 2452 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 2453 2454 2455 /***********************************/ 2456 /* MC_CMD_START_BIST 2457 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST 2458 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 2459 */ 2460 #define MC_CMD_START_BIST 0x25 2461 2462 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2463 2464 /* MC_CMD_START_BIST_IN msgrequest */ 2465 #define MC_CMD_START_BIST_IN_LEN 4 2466 /* Type of test. */ 2467 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 2468 /* enum: Run the PHY's short cable BIST. */ 2469 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 2470 /* enum: Run the PHY's long cable BIST. */ 2471 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 2472 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ 2473 #define MC_CMD_BPX_SERDES_BIST 0x3 2474 /* enum: Run the MC loopback tests. */ 2475 #define MC_CMD_MC_LOOPBACK_BIST 0x4 2476 /* enum: Run the PHY's standard BIST. */ 2477 #define MC_CMD_PHY_BIST 0x5 2478 /* enum: Run MC RAM test. */ 2479 #define MC_CMD_MC_MEM_BIST 0x6 2480 /* enum: Run Port RAM test. */ 2481 #define MC_CMD_PORT_MEM_BIST 0x7 2482 /* enum: Run register test. */ 2483 #define MC_CMD_REG_BIST 0x8 2484 2485 /* MC_CMD_START_BIST_OUT msgresponse */ 2486 #define MC_CMD_START_BIST_OUT_LEN 0 2487 2488 2489 /***********************************/ 2490 /* MC_CMD_POLL_BIST 2491 * Poll for BIST completion. Returns a single status code, and optionally some 2492 * PHY specific bist output. The driver should only consume the BIST output 2493 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't 2494 * successfully parse the BIST output, it should still respect the pass/Fail in 2495 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, 2496 * EACCES (if PHY_LOCK is not held). 2497 */ 2498 #define MC_CMD_POLL_BIST 0x26 2499 2500 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2501 2502 /* MC_CMD_POLL_BIST_IN msgrequest */ 2503 #define MC_CMD_POLL_BIST_IN_LEN 0 2504 2505 /* MC_CMD_POLL_BIST_OUT msgresponse */ 2506 #define MC_CMD_POLL_BIST_OUT_LEN 8 2507 /* result */ 2508 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 2509 /* enum: Running. */ 2510 #define MC_CMD_POLL_BIST_RUNNING 0x1 2511 /* enum: Passed. */ 2512 #define MC_CMD_POLL_BIST_PASSED 0x2 2513 /* enum: Failed. */ 2514 #define MC_CMD_POLL_BIST_FAILED 0x3 2515 /* enum: Timed-out. */ 2516 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 2517 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 2518 2519 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 2520 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 2521 /* result */ 2522 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 2523 /* Enum values, see field(s): */ 2524 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 2525 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 2526 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 2527 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 2528 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 2529 /* Status of each channel A */ 2530 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 2531 /* enum: Ok. */ 2532 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 2533 /* enum: Open. */ 2534 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 2535 /* enum: Intra-pair short. */ 2536 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 2537 /* enum: Inter-pair short. */ 2538 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 2539 /* enum: Busy. */ 2540 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 2541 /* Status of each channel B */ 2542 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 2543 /* Enum values, see field(s): */ 2544 /* CABLE_STATUS_A */ 2545 /* Status of each channel C */ 2546 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 2547 /* Enum values, see field(s): */ 2548 /* CABLE_STATUS_A */ 2549 /* Status of each channel D */ 2550 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 2551 /* Enum values, see field(s): */ 2552 /* CABLE_STATUS_A */ 2553 2554 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 2555 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 2556 /* result */ 2557 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 2558 /* Enum values, see field(s): */ 2559 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 2560 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 2561 /* enum: Complete. */ 2562 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 2563 /* enum: Bus switch off I2C write. */ 2564 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 2565 /* enum: Bus switch off I2C no access IO exp. */ 2566 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 2567 /* enum: Bus switch off I2C no access module. */ 2568 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 2569 /* enum: IO exp I2C configure. */ 2570 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 2571 /* enum: Bus switch I2C no cross talk. */ 2572 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 2573 /* enum: Module presence. */ 2574 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 2575 /* enum: Module ID I2C access. */ 2576 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 2577 /* enum: Module ID sane value. */ 2578 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 2579 2580 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ 2581 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 2582 /* result */ 2583 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 2584 /* Enum values, see field(s): */ 2585 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 2586 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 2587 /* enum: Test has completed. */ 2588 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 2589 /* enum: RAM test - walk ones. */ 2590 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 2591 /* enum: RAM test - walk zeros. */ 2592 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 2593 /* enum: RAM test - walking inversions zeros/ones. */ 2594 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 2595 /* enum: RAM test - walking inversions checkerboard. */ 2596 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 2597 /* enum: Register test - set / clear individual bits. */ 2598 #define MC_CMD_POLL_BIST_MEM_REG 0x5 2599 /* enum: ECC error detected. */ 2600 #define MC_CMD_POLL_BIST_MEM_ECC 0x6 2601 /* Failure address, only valid if result is POLL_BIST_FAILED */ 2602 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 2603 /* Bus or address space to which the failure address corresponds */ 2604 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 2605 /* enum: MC MIPS bus. */ 2606 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 2607 /* enum: CSR IREG bus. */ 2608 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 2609 /* enum: RX DPCPU bus. */ 2610 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 2611 /* enum: TX0 DPCPU bus. */ 2612 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 2613 /* enum: TX1 DPCPU bus. */ 2614 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 2615 /* enum: RX DICPU bus. */ 2616 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 2617 /* enum: TX DICPU bus. */ 2618 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 2619 /* Pattern written to RAM / register */ 2620 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 2621 /* Actual value read from RAM / register */ 2622 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 2623 /* ECC error mask */ 2624 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 2625 /* ECC parity error mask */ 2626 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 2627 /* ECC fatal error mask */ 2628 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 2629 2630 2631 /***********************************/ 2632 /* MC_CMD_FLUSH_RX_QUEUES 2633 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 2634 * flushes should be initiated via this MCDI operation, rather than via 2635 * directly writing FLUSH_CMD. 2636 * 2637 * The flush is completed (either done/fail) asynchronously (after this command 2638 * returns). The driver must still wait for flush done/failure events as usual. 2639 */ 2640 #define MC_CMD_FLUSH_RX_QUEUES 0x27 2641 2642 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 2643 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 2644 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 2645 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 2646 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 2647 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 2648 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 2649 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 2650 2651 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 2652 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 2653 2654 2655 /***********************************/ 2656 /* MC_CMD_GET_LOOPBACK_MODES 2657 * Returns a bitmask of loopback modes available at each speed. 2658 */ 2659 #define MC_CMD_GET_LOOPBACK_MODES 0x28 2660 2661 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2662 2663 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 2664 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 2665 2666 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 2667 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 2668 /* Supported loopbacks. */ 2669 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 2670 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 2671 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 2672 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 2673 /* enum: None. */ 2674 #define MC_CMD_LOOPBACK_NONE 0x0 2675 /* enum: Data. */ 2676 #define MC_CMD_LOOPBACK_DATA 0x1 2677 /* enum: GMAC. */ 2678 #define MC_CMD_LOOPBACK_GMAC 0x2 2679 /* enum: XGMII. */ 2680 #define MC_CMD_LOOPBACK_XGMII 0x3 2681 /* enum: XGXS. */ 2682 #define MC_CMD_LOOPBACK_XGXS 0x4 2683 /* enum: XAUI. */ 2684 #define MC_CMD_LOOPBACK_XAUI 0x5 2685 /* enum: GMII. */ 2686 #define MC_CMD_LOOPBACK_GMII 0x6 2687 /* enum: SGMII. */ 2688 #define MC_CMD_LOOPBACK_SGMII 0x7 2689 /* enum: XGBR. */ 2690 #define MC_CMD_LOOPBACK_XGBR 0x8 2691 /* enum: XFI. */ 2692 #define MC_CMD_LOOPBACK_XFI 0x9 2693 /* enum: XAUI Far. */ 2694 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa 2695 /* enum: GMII Far. */ 2696 #define MC_CMD_LOOPBACK_GMII_FAR 0xb 2697 /* enum: SGMII Far. */ 2698 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc 2699 /* enum: XFI Far. */ 2700 #define MC_CMD_LOOPBACK_XFI_FAR 0xd 2701 /* enum: GPhy. */ 2702 #define MC_CMD_LOOPBACK_GPHY 0xe 2703 /* enum: PhyXS. */ 2704 #define MC_CMD_LOOPBACK_PHYXS 0xf 2705 /* enum: PCS. */ 2706 #define MC_CMD_LOOPBACK_PCS 0x10 2707 /* enum: PMA-PMD. */ 2708 #define MC_CMD_LOOPBACK_PMAPMD 0x11 2709 /* enum: Cross-Port. */ 2710 #define MC_CMD_LOOPBACK_XPORT 0x12 2711 /* enum: XGMII-Wireside. */ 2712 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 2713 /* enum: XAUI Wireside. */ 2714 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 2715 /* enum: XAUI Wireside Far. */ 2716 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 2717 /* enum: XAUI Wireside near. */ 2718 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 2719 /* enum: GMII Wireside. */ 2720 #define MC_CMD_LOOPBACK_GMII_WS 0x17 2721 /* enum: XFI Wireside. */ 2722 #define MC_CMD_LOOPBACK_XFI_WS 0x18 2723 /* enum: XFI Wireside Far. */ 2724 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 2725 /* enum: PhyXS Wireside. */ 2726 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a 2727 /* enum: PMA lanes MAC-Serdes. */ 2728 #define MC_CMD_LOOPBACK_PMA_INT 0x1b 2729 /* enum: KR Serdes Parallel (Encoder). */ 2730 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c 2731 /* enum: KR Serdes Serial. */ 2732 #define MC_CMD_LOOPBACK_SD_FAR 0x1d 2733 /* enum: PMA lanes MAC-Serdes Wireside. */ 2734 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e 2735 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 2736 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f 2737 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 2738 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 2739 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 2740 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 2741 /* enum: KR Serdes Serial Wireside. */ 2742 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 2743 /* enum: Near side of AOE Siena side port */ 2744 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 2745 /* enum: Medford Wireside datapath loopback */ 2746 #define MC_CMD_LOOPBACK_DATA_WS 0x24 2747 /* enum: Force link up without setting up any physical loopback (snapper use 2748 * only) 2749 */ 2750 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 2751 /* Supported loopbacks. */ 2752 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 2753 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 2754 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 2755 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 2756 /* Enum values, see field(s): */ 2757 /* 100M */ 2758 /* Supported loopbacks. */ 2759 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 2760 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 2761 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 2762 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 2763 /* Enum values, see field(s): */ 2764 /* 100M */ 2765 /* Supported loopbacks. */ 2766 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 2767 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 2768 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 2769 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 2770 /* Enum values, see field(s): */ 2771 /* 100M */ 2772 /* Supported loopbacks. */ 2773 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 2774 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 2775 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 2776 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 2777 /* Enum values, see field(s): */ 2778 /* 100M */ 2779 2780 2781 /***********************************/ 2782 /* MC_CMD_GET_LINK 2783 * Read the unified MAC/PHY link state. Locks required: None Return code: 0, 2784 * ETIME. 2785 */ 2786 #define MC_CMD_GET_LINK 0x29 2787 2788 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2789 2790 /* MC_CMD_GET_LINK_IN msgrequest */ 2791 #define MC_CMD_GET_LINK_IN_LEN 0 2792 2793 /* MC_CMD_GET_LINK_OUT msgresponse */ 2794 #define MC_CMD_GET_LINK_OUT_LEN 28 2795 /* near-side advertised capabilities */ 2796 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 2797 /* link-partner advertised capabilities */ 2798 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 2799 /* Autonegotiated speed in mbit/s. The link may still be down even if this 2800 * reads non-zero. 2801 */ 2802 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 2803 /* Current loopback setting. */ 2804 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 2805 /* Enum values, see field(s): */ 2806 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 2807 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 2808 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 2809 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 2810 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 2811 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 2812 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 2813 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 2814 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 2815 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 2816 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 2817 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 2818 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 2819 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 2820 /* This returns the negotiated flow control value. */ 2821 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 2822 /* Enum values, see field(s): */ 2823 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 2824 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 2825 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 2826 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 2827 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 2828 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 2829 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 2830 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 2831 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 2832 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 2833 2834 2835 /***********************************/ 2836 /* MC_CMD_SET_LINK 2837 * Write the unified MAC/PHY link configuration. Locks required: None. Return 2838 * code: 0, EINVAL, ETIME 2839 */ 2840 #define MC_CMD_SET_LINK 0x2a 2841 2842 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK 2843 2844 /* MC_CMD_SET_LINK_IN msgrequest */ 2845 #define MC_CMD_SET_LINK_IN_LEN 16 2846 /* ??? */ 2847 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 2848 /* Flags */ 2849 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 2850 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 2851 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 2852 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 2853 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 2854 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 2855 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 2856 /* Loopback mode. */ 2857 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 2858 /* Enum values, see field(s): */ 2859 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 2860 /* A loopback speed of "0" is supported, and means (choose any available 2861 * speed). 2862 */ 2863 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 2864 2865 /* MC_CMD_SET_LINK_OUT msgresponse */ 2866 #define MC_CMD_SET_LINK_OUT_LEN 0 2867 2868 2869 /***********************************/ 2870 /* MC_CMD_SET_ID_LED 2871 * Set identification LED state. Locks required: None. Return code: 0, EINVAL 2872 */ 2873 #define MC_CMD_SET_ID_LED 0x2b 2874 2875 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK 2876 2877 /* MC_CMD_SET_ID_LED_IN msgrequest */ 2878 #define MC_CMD_SET_ID_LED_IN_LEN 4 2879 /* Set LED state. */ 2880 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 2881 #define MC_CMD_LED_OFF 0x0 /* enum */ 2882 #define MC_CMD_LED_ON 0x1 /* enum */ 2883 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 2884 2885 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 2886 #define MC_CMD_SET_ID_LED_OUT_LEN 0 2887 2888 2889 /***********************************/ 2890 /* MC_CMD_SET_MAC 2891 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL 2892 */ 2893 #define MC_CMD_SET_MAC 0x2c 2894 2895 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_LINK 2896 2897 /* MC_CMD_SET_MAC_IN msgrequest */ 2898 #define MC_CMD_SET_MAC_IN_LEN 28 2899 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 2900 * EtherII, VLAN, bug16011 padding). 2901 */ 2902 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 2903 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 2904 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 2905 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 2906 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 2907 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 2908 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 2909 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 2910 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 2911 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 2912 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 2913 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 2914 /* enum: Flow control is off. */ 2915 #define MC_CMD_FCNTL_OFF 0x0 2916 /* enum: Respond to flow control. */ 2917 #define MC_CMD_FCNTL_RESPOND 0x1 2918 /* enum: Respond to and Issue flow control. */ 2919 #define MC_CMD_FCNTL_BIDIR 0x2 2920 /* enum: Auto neg flow control. */ 2921 #define MC_CMD_FCNTL_AUTO 0x3 2922 /* enum: Priority flow control (eftest builds only). */ 2923 #define MC_CMD_FCNTL_QBB 0x4 2924 /* enum: Issue flow control. */ 2925 #define MC_CMD_FCNTL_GENERATE 0x5 2926 #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 2927 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 2928 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 2929 2930 /* MC_CMD_SET_MAC_OUT msgresponse */ 2931 #define MC_CMD_SET_MAC_OUT_LEN 0 2932 2933 2934 /***********************************/ 2935 /* MC_CMD_PHY_STATS 2936 * Get generic PHY statistics. This call returns the statistics for a generic 2937 * PHY in a sparse array (indexed by the enumerate). Each value is represented 2938 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the 2939 * statistics may be read from the message response. If DMA_ADDR != 0, then the 2940 * statistics are dmad to that (page-aligned location). Locks required: None. 2941 * Returns: 0, ETIME 2942 */ 2943 #define MC_CMD_PHY_STATS 0x2d 2944 2945 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK 2946 2947 /* MC_CMD_PHY_STATS_IN msgrequest */ 2948 #define MC_CMD_PHY_STATS_IN_LEN 8 2949 /* ??? */ 2950 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 2951 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 2952 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 2953 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 2954 2955 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 2956 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 2957 2958 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 2959 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 2960 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 2961 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 2962 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 2963 /* enum: OUI. */ 2964 #define MC_CMD_OUI 0x0 2965 /* enum: PMA-PMD Link Up. */ 2966 #define MC_CMD_PMA_PMD_LINK_UP 0x1 2967 /* enum: PMA-PMD RX Fault. */ 2968 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 2969 /* enum: PMA-PMD TX Fault. */ 2970 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 2971 /* enum: PMA-PMD Signal */ 2972 #define MC_CMD_PMA_PMD_SIGNAL 0x4 2973 /* enum: PMA-PMD SNR A. */ 2974 #define MC_CMD_PMA_PMD_SNR_A 0x5 2975 /* enum: PMA-PMD SNR B. */ 2976 #define MC_CMD_PMA_PMD_SNR_B 0x6 2977 /* enum: PMA-PMD SNR C. */ 2978 #define MC_CMD_PMA_PMD_SNR_C 0x7 2979 /* enum: PMA-PMD SNR D. */ 2980 #define MC_CMD_PMA_PMD_SNR_D 0x8 2981 /* enum: PCS Link Up. */ 2982 #define MC_CMD_PCS_LINK_UP 0x9 2983 /* enum: PCS RX Fault. */ 2984 #define MC_CMD_PCS_RX_FAULT 0xa 2985 /* enum: PCS TX Fault. */ 2986 #define MC_CMD_PCS_TX_FAULT 0xb 2987 /* enum: PCS BER. */ 2988 #define MC_CMD_PCS_BER 0xc 2989 /* enum: PCS Block Errors. */ 2990 #define MC_CMD_PCS_BLOCK_ERRORS 0xd 2991 /* enum: PhyXS Link Up. */ 2992 #define MC_CMD_PHYXS_LINK_UP 0xe 2993 /* enum: PhyXS RX Fault. */ 2994 #define MC_CMD_PHYXS_RX_FAULT 0xf 2995 /* enum: PhyXS TX Fault. */ 2996 #define MC_CMD_PHYXS_TX_FAULT 0x10 2997 /* enum: PhyXS Align. */ 2998 #define MC_CMD_PHYXS_ALIGN 0x11 2999 /* enum: PhyXS Sync. */ 3000 #define MC_CMD_PHYXS_SYNC 0x12 3001 /* enum: AN link-up. */ 3002 #define MC_CMD_AN_LINK_UP 0x13 3003 /* enum: AN Complete. */ 3004 #define MC_CMD_AN_COMPLETE 0x14 3005 /* enum: AN 10GBaseT Status. */ 3006 #define MC_CMD_AN_10GBT_STATUS 0x15 3007 /* enum: Clause 22 Link-Up. */ 3008 #define MC_CMD_CL22_LINK_UP 0x16 3009 /* enum: (Last entry) */ 3010 #define MC_CMD_PHY_NSTATS 0x17 3011 3012 3013 /***********************************/ 3014 /* MC_CMD_MAC_STATS 3015 * Get generic MAC statistics. This call returns unified statistics maintained 3016 * by the MC as it switches between the GMAC and XMAC. The MC will write out 3017 * all supported stats. The driver should zero initialise the buffer to 3018 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is 3019 * performed, and the statistics may be read from the message response. If 3020 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). 3021 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no 3022 * effect. Returns: 0, ETIME 3023 */ 3024 #define MC_CMD_MAC_STATS 0x2e 3025 3026 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3027 3028 /* MC_CMD_MAC_STATS_IN msgrequest */ 3029 #define MC_CMD_MAC_STATS_IN_LEN 20 3030 /* ??? */ 3031 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 3032 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 3033 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 3034 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 3035 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 3036 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 3037 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 3038 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 3039 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 3040 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 3041 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 3042 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 3043 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 3044 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 3045 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 3046 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 3047 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 3048 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 3049 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 3050 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 3051 /* port id so vadapter stats can be provided */ 3052 #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 3053 3054 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 3055 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 3056 3057 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 3058 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 3059 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 3060 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 3061 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 3062 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 3063 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 3064 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 3065 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ 3066 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 3067 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 3068 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 3069 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 3070 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 3071 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 3072 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 3073 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 3074 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 3075 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 3076 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 3077 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 3078 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 3079 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 3080 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 3081 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 3082 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 3083 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 3084 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 3085 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 3086 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 3087 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 3088 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 3089 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 3090 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 3091 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 3092 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 3093 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 3094 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 3095 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 3096 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 3097 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 3098 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 3099 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 3100 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 3101 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 3102 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 3103 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 3104 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 3105 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 3106 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 3107 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 3108 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 3109 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 3110 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 3111 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 3112 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 3113 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 3114 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 3115 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 3116 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 3117 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 3118 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 3119 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 3120 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 3121 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 3122 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 3123 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 3124 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 3125 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3126 * capability only. 3127 */ 3128 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c 3129 /* enum: PM discard_bb_overflow counter. Valid for EF10 with 3130 * PM_AND_RXDP_COUNTERS capability only. 3131 */ 3132 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d 3133 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3134 * capability only. 3135 */ 3136 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e 3137 /* enum: PM discard_vfifo_full counter. Valid for EF10 with 3138 * PM_AND_RXDP_COUNTERS capability only. 3139 */ 3140 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f 3141 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3142 * capability only. 3143 */ 3144 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40 3145 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3146 * capability only. 3147 */ 3148 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41 3149 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3150 * capability only. 3151 */ 3152 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 3153 /* enum: RXDP counter: Number of packets dropped due to the queue being 3154 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 3155 */ 3156 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 3157 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 3158 * with PM_AND_RXDP_COUNTERS capability only. 3159 */ 3160 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 3161 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with 3162 * PM_AND_RXDP_COUNTERS capability only. 3163 */ 3164 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 3165 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed. 3166 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 3167 */ 3168 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 3169 /* enum: RXDP counter: Number of times the DPCPU waited for an existing 3170 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 3171 */ 3172 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 3173 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */ 3174 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */ 3175 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */ 3176 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */ 3177 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */ 3178 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */ 3179 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */ 3180 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */ 3181 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */ 3182 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */ 3183 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */ 3184 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */ 3185 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */ 3186 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */ 3187 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */ 3188 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */ 3189 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */ 3190 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */ 3191 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */ 3192 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */ 3193 /* enum: Start of GMAC stats buffer space, for Siena only. */ 3194 #define MC_CMD_GMAC_DMABUF_START 0x40 3195 /* enum: End of GMAC stats buffer space, for Siena only. */ 3196 #define MC_CMD_GMAC_DMABUF_END 0x5f 3197 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ 3198 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 3199 3200 3201 /***********************************/ 3202 /* MC_CMD_SRIOV 3203 * to be documented 3204 */ 3205 #define MC_CMD_SRIOV 0x30 3206 3207 /* MC_CMD_SRIOV_IN msgrequest */ 3208 #define MC_CMD_SRIOV_IN_LEN 12 3209 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 3210 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 3211 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 3212 3213 /* MC_CMD_SRIOV_OUT msgresponse */ 3214 #define MC_CMD_SRIOV_OUT_LEN 8 3215 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 3216 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 3217 3218 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 3219 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 3220 /* this is only used for the first record */ 3221 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 3222 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 3223 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 3224 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 3225 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 3226 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 3227 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 3228 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 3229 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 3230 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 3231 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 3232 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 3233 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 3234 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 3235 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 3236 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 3237 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 3238 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 3239 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 3240 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 3241 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 3242 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 3243 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 3244 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 3245 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 3246 3247 3248 /***********************************/ 3249 /* MC_CMD_MEMCPY 3250 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 3251 * embedded directly in the command. 3252 * 3253 * A common pattern is for a client to use generation counts to signal a dma 3254 * update of a datastructure. To facilitate this, this MCDI operation can 3255 * contain multiple requests which are executed in strict order. Requests take 3256 * the form of duplicating the entire MCDI request continuously (including the 3257 * requests record, which is ignored in all but the first structure) 3258 * 3259 * The source data can either come from a DMA from the host, or it can be 3260 * embedded within the request directly, thereby eliminating a DMA read. To 3261 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 3262 * ADDR_LO=offset, and inserts the data at %offset from the start of the 3263 * payload. It's the callers responsibility to ensure that the embedded data 3264 * doesn't overlap the records. 3265 * 3266 * Returns: 0, EINVAL (invalid RID) 3267 */ 3268 #define MC_CMD_MEMCPY 0x31 3269 3270 /* MC_CMD_MEMCPY_IN msgrequest */ 3271 #define MC_CMD_MEMCPY_IN_LENMIN 32 3272 #define MC_CMD_MEMCPY_IN_LENMAX 224 3273 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 3274 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 3275 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 3276 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 3277 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 3278 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 3279 3280 /* MC_CMD_MEMCPY_OUT msgresponse */ 3281 #define MC_CMD_MEMCPY_OUT_LEN 0 3282 3283 3284 /***********************************/ 3285 /* MC_CMD_WOL_FILTER_SET 3286 * Set a WoL filter. 3287 */ 3288 #define MC_CMD_WOL_FILTER_SET 0x32 3289 3290 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK 3291 3292 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 3293 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 3294 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 3295 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 3296 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 3297 /* A type value of 1 is unused. */ 3298 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 3299 /* enum: Magic */ 3300 #define MC_CMD_WOL_TYPE_MAGIC 0x0 3301 /* enum: MS Windows Magic */ 3302 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 3303 /* enum: IPv4 Syn */ 3304 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 3305 /* enum: IPv6 Syn */ 3306 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 3307 /* enum: Bitmap */ 3308 #define MC_CMD_WOL_TYPE_BITMAP 0x5 3309 /* enum: Link */ 3310 #define MC_CMD_WOL_TYPE_LINK 0x6 3311 /* enum: (Above this for future use) */ 3312 #define MC_CMD_WOL_TYPE_MAX 0x7 3313 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 3314 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 3315 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 3316 3317 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 3318 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 3319 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3320 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3321 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 3322 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 3323 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 3324 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 3325 3326 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 3327 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 3328 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3329 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3330 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 3331 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 3332 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 3333 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 3334 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 3335 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 3336 3337 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 3338 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 3339 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3340 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3341 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 3342 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 3343 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 3344 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 3345 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 3346 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 3347 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 3348 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 3349 3350 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 3351 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 3352 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3353 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3354 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 3355 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 3356 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 3357 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 3358 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 3359 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 3360 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 3361 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 3362 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 3363 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 3364 3365 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 3366 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 3367 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3368 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3369 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 3370 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 3371 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 3372 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 3373 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 3374 3375 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 3376 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 3377 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 3378 3379 3380 /***********************************/ 3381 /* MC_CMD_WOL_FILTER_REMOVE 3382 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS 3383 */ 3384 #define MC_CMD_WOL_FILTER_REMOVE 0x33 3385 3386 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK 3387 3388 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 3389 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 3390 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 3391 3392 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 3393 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 3394 3395 3396 /***********************************/ 3397 /* MC_CMD_WOL_FILTER_RESET 3398 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, 3399 * ENOSYS 3400 */ 3401 #define MC_CMD_WOL_FILTER_RESET 0x34 3402 3403 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK 3404 3405 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 3406 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 3407 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 3408 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 3409 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 3410 3411 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 3412 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 3413 3414 3415 /***********************************/ 3416 /* MC_CMD_SET_MCAST_HASH 3417 * Set the MCAST hash value without otherwise reconfiguring the MAC 3418 */ 3419 #define MC_CMD_SET_MCAST_HASH 0x35 3420 3421 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 3422 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 3423 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 3424 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 3425 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 3426 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 3427 3428 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 3429 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 3430 3431 3432 /***********************************/ 3433 /* MC_CMD_NVRAM_TYPES 3434 * Return bitfield indicating available types of virtual NVRAM partitions. 3435 * Locks required: none. Returns: 0 3436 */ 3437 #define MC_CMD_NVRAM_TYPES 0x36 3438 3439 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3440 3441 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 3442 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 3443 3444 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 3445 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 3446 /* Bit mask of supported types. */ 3447 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 3448 /* enum: Disabled callisto. */ 3449 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 3450 /* enum: MC firmware. */ 3451 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 3452 /* enum: MC backup firmware. */ 3453 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 3454 /* enum: Static configuration Port0. */ 3455 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 3456 /* enum: Static configuration Port1. */ 3457 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 3458 /* enum: Dynamic configuration Port0. */ 3459 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 3460 /* enum: Dynamic configuration Port1. */ 3461 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 3462 /* enum: Expansion Rom. */ 3463 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 3464 /* enum: Expansion Rom Configuration Port0. */ 3465 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 3466 /* enum: Expansion Rom Configuration Port1. */ 3467 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 3468 /* enum: Phy Configuration Port0. */ 3469 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa 3470 /* enum: Phy Configuration Port1. */ 3471 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb 3472 /* enum: Log. */ 3473 #define MC_CMD_NVRAM_TYPE_LOG 0xc 3474 /* enum: FPGA image. */ 3475 #define MC_CMD_NVRAM_TYPE_FPGA 0xd 3476 /* enum: FPGA backup image */ 3477 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe 3478 /* enum: FC firmware. */ 3479 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf 3480 /* enum: FC backup firmware. */ 3481 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 3482 /* enum: CPLD image. */ 3483 #define MC_CMD_NVRAM_TYPE_CPLD 0x11 3484 /* enum: Licensing information. */ 3485 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 3486 /* enum: FC Log. */ 3487 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 3488 /* enum: Additional flash on FPGA. */ 3489 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 3490 3491 3492 /***********************************/ 3493 /* MC_CMD_NVRAM_INFO 3494 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, 3495 * EINVAL (bad type). 3496 */ 3497 #define MC_CMD_NVRAM_INFO 0x37 3498 3499 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3500 3501 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 3502 #define MC_CMD_NVRAM_INFO_IN_LEN 4 3503 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 3504 /* Enum values, see field(s): */ 3505 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3506 3507 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 3508 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 3509 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 3510 /* Enum values, see field(s): */ 3511 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3512 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 3513 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 3514 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 3515 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 3516 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 3517 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 3518 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 3519 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 3520 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 3521 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 3522 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 3523 3524 3525 /***********************************/ 3526 /* MC_CMD_NVRAM_UPDATE_START 3527 * Start a group of update operations on a virtual NVRAM partition. Locks 3528 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if 3529 * PHY_LOCK required and not held). 3530 */ 3531 #define MC_CMD_NVRAM_UPDATE_START 0x38 3532 3533 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3534 3535 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */ 3536 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 3537 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 3538 /* Enum values, see field(s): */ 3539 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3540 3541 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 3542 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 3543 3544 3545 /***********************************/ 3546 /* MC_CMD_NVRAM_READ 3547 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if 3548 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 3549 * PHY_LOCK required and not held) 3550 */ 3551 #define MC_CMD_NVRAM_READ 0x39 3552 3553 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3554 3555 /* MC_CMD_NVRAM_READ_IN msgrequest */ 3556 #define MC_CMD_NVRAM_READ_IN_LEN 12 3557 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 3558 /* Enum values, see field(s): */ 3559 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3560 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 3561 /* amount to read in bytes */ 3562 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 3563 3564 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 3565 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 3566 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 3567 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 3568 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 3569 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 3570 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 3571 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 3572 3573 3574 /***********************************/ 3575 /* MC_CMD_NVRAM_WRITE 3576 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if 3577 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 3578 * PHY_LOCK required and not held) 3579 */ 3580 #define MC_CMD_NVRAM_WRITE 0x3a 3581 3582 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3583 3584 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 3585 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 3586 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 3587 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 3588 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 3589 /* Enum values, see field(s): */ 3590 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3591 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 3592 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 3593 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 3594 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 3595 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 3596 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 3597 3598 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 3599 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 3600 3601 3602 /***********************************/ 3603 /* MC_CMD_NVRAM_ERASE 3604 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if 3605 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 3606 * PHY_LOCK required and not held) 3607 */ 3608 #define MC_CMD_NVRAM_ERASE 0x3b 3609 3610 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3611 3612 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 3613 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 3614 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 3615 /* Enum values, see field(s): */ 3616 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3617 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 3618 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 3619 3620 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 3621 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 3622 3623 3624 /***********************************/ 3625 /* MC_CMD_NVRAM_UPDATE_FINISH 3626 * Finish a group of update operations on a virtual NVRAM partition. Locks 3627 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad 3628 * type/offset/length), EACCES (if PHY_LOCK required and not held) 3629 */ 3630 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 3631 3632 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3633 3634 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */ 3635 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 3636 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 3637 /* Enum values, see field(s): */ 3638 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3639 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 3640 3641 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */ 3642 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 3643 3644 3645 /***********************************/ 3646 /* MC_CMD_REBOOT 3647 * Reboot the MC. 3648 * 3649 * The AFTER_ASSERTION flag is intended to be used when the driver notices an 3650 * assertion failure (at which point it is expected to perform a complete tear 3651 * down and reinitialise), to allow both ports to reset the MC once in an 3652 * atomic fashion. 3653 * 3654 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 3655 * which means that they will automatically reboot out of the assertion 3656 * handler, so this is in practise an optional operation. It is still 3657 * recommended that drivers execute this to support custom firmwares with 3658 * REBOOT_ON_ASSERT=0. 3659 * 3660 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, 3661 * DATALEN=0 3662 */ 3663 #define MC_CMD_REBOOT 0x3d 3664 3665 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3666 3667 /* MC_CMD_REBOOT_IN msgrequest */ 3668 #define MC_CMD_REBOOT_IN_LEN 4 3669 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 3670 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 3671 3672 /* MC_CMD_REBOOT_OUT msgresponse */ 3673 #define MC_CMD_REBOOT_OUT_LEN 0 3674 3675 3676 /***********************************/ 3677 /* MC_CMD_SCHEDINFO 3678 * Request scheduler info. Locks required: NONE. Returns: An array of 3679 * (timeslice,maximum overrun), one for each thread, in ascending order of 3680 * thread address. 3681 */ 3682 #define MC_CMD_SCHEDINFO 0x3e 3683 3684 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3685 3686 /* MC_CMD_SCHEDINFO_IN msgrequest */ 3687 #define MC_CMD_SCHEDINFO_IN_LEN 0 3688 3689 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 3690 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 3691 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 3692 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 3693 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 3694 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 3695 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 3696 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 3697 3698 3699 /***********************************/ 3700 /* MC_CMD_REBOOT_MODE 3701 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 3702 * mode to the specified value. Returns the old mode. 3703 */ 3704 #define MC_CMD_REBOOT_MODE 0x3f 3705 3706 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3707 3708 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 3709 #define MC_CMD_REBOOT_MODE_IN_LEN 4 3710 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 3711 /* enum: Normal. */ 3712 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 3713 /* enum: Power-on Reset. */ 3714 #define MC_CMD_REBOOT_MODE_POR 0x2 3715 /* enum: Snapper. */ 3716 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 3717 /* enum: snapper fake POR */ 3718 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 3719 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 3720 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 3721 3722 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 3723 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 3724 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 3725 3726 3727 /***********************************/ 3728 /* MC_CMD_SENSOR_INFO 3729 * Returns information about every available sensor. 3730 * 3731 * Each sensor has a single (16bit) value, and a corresponding state. The 3732 * mapping between value and state is nominally determined by the MC, but may 3733 * be implemented using up to 2 ranges per sensor. 3734 * 3735 * This call returns a mask (32bit) of the sensors that are supported by this 3736 * platform, then an array of sensor information structures, in order of sensor 3737 * type (but without gaps for unimplemented sensors). Each structure defines 3738 * the ranges for the corresponding sensor. An unused range is indicated by 3739 * equal limit values. If one range is used, a value outside that range results 3740 * in STATE_FATAL. If two ranges are used, a value outside the second range 3741 * results in STATE_FATAL while a value outside the first and inside the second 3742 * range results in STATE_WARNING. 3743 * 3744 * Sensor masks and sensor information arrays are organised into pages. For 3745 * backward compatibility, older host software can only use sensors in page 0. 3746 * Bit 32 in the sensor mask was previously unused, and is no reserved for use 3747 * as the next page flag. 3748 * 3749 * If the request does not contain a PAGE value then firmware will only return 3750 * page 0 of sensor information, with bit 31 in the sensor mask cleared. 3751 * 3752 * If the request contains a PAGE value then firmware responds with the sensor 3753 * mask and sensor information array for that page of sensors. In this case bit 3754 * 31 in the mask is set if another page exists. 3755 * 3756 * Locks required: None Returns: 0 3757 */ 3758 #define MC_CMD_SENSOR_INFO 0x41 3759 3760 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3761 3762 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 3763 #define MC_CMD_SENSOR_INFO_IN_LEN 0 3764 3765 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ 3766 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 3767 /* Which page of sensors to report. 3768 * 3769 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 3770 * 3771 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 3772 */ 3773 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 3774 3775 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 3776 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 3777 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 3778 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 3779 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 3780 /* enum: Controller temperature: degC */ 3781 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 3782 /* enum: Phy common temperature: degC */ 3783 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 3784 /* enum: Controller cooling: bool */ 3785 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 3786 /* enum: Phy 0 temperature: degC */ 3787 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 3788 /* enum: Phy 0 cooling: bool */ 3789 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 3790 /* enum: Phy 1 temperature: degC */ 3791 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 3792 /* enum: Phy 1 cooling: bool */ 3793 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 3794 /* enum: 1.0v power: mV */ 3795 #define MC_CMD_SENSOR_IN_1V0 0x7 3796 /* enum: 1.2v power: mV */ 3797 #define MC_CMD_SENSOR_IN_1V2 0x8 3798 /* enum: 1.8v power: mV */ 3799 #define MC_CMD_SENSOR_IN_1V8 0x9 3800 /* enum: 2.5v power: mV */ 3801 #define MC_CMD_SENSOR_IN_2V5 0xa 3802 /* enum: 3.3v power: mV */ 3803 #define MC_CMD_SENSOR_IN_3V3 0xb 3804 /* enum: 12v power: mV */ 3805 #define MC_CMD_SENSOR_IN_12V0 0xc 3806 /* enum: 1.2v analogue power: mV */ 3807 #define MC_CMD_SENSOR_IN_1V2A 0xd 3808 /* enum: reference voltage: mV */ 3809 #define MC_CMD_SENSOR_IN_VREF 0xe 3810 /* enum: AOE FPGA power: mV */ 3811 #define MC_CMD_SENSOR_OUT_VAOE 0xf 3812 /* enum: AOE FPGA temperature: degC */ 3813 #define MC_CMD_SENSOR_AOE_TEMP 0x10 3814 /* enum: AOE FPGA PSU temperature: degC */ 3815 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 3816 /* enum: AOE PSU temperature: degC */ 3817 #define MC_CMD_SENSOR_PSU_TEMP 0x12 3818 /* enum: Fan 0 speed: RPM */ 3819 #define MC_CMD_SENSOR_FAN_0 0x13 3820 /* enum: Fan 1 speed: RPM */ 3821 #define MC_CMD_SENSOR_FAN_1 0x14 3822 /* enum: Fan 2 speed: RPM */ 3823 #define MC_CMD_SENSOR_FAN_2 0x15 3824 /* enum: Fan 3 speed: RPM */ 3825 #define MC_CMD_SENSOR_FAN_3 0x16 3826 /* enum: Fan 4 speed: RPM */ 3827 #define MC_CMD_SENSOR_FAN_4 0x17 3828 /* enum: AOE FPGA input power: mV */ 3829 #define MC_CMD_SENSOR_IN_VAOE 0x18 3830 /* enum: AOE FPGA current: mA */ 3831 #define MC_CMD_SENSOR_OUT_IAOE 0x19 3832 /* enum: AOE FPGA input current: mA */ 3833 #define MC_CMD_SENSOR_IN_IAOE 0x1a 3834 /* enum: NIC power consumption: W */ 3835 #define MC_CMD_SENSOR_NIC_POWER 0x1b 3836 /* enum: 0.9v power voltage: mV */ 3837 #define MC_CMD_SENSOR_IN_0V9 0x1c 3838 /* enum: 0.9v power current: mA */ 3839 #define MC_CMD_SENSOR_IN_I0V9 0x1d 3840 /* enum: 1.2v power current: mA */ 3841 #define MC_CMD_SENSOR_IN_I1V2 0x1e 3842 /* enum: Not a sensor: reserved for the next page flag */ 3843 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f 3844 /* enum: 0.9v power voltage (at ADC): mV */ 3845 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 3846 /* enum: Controller temperature 2: degC */ 3847 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 3848 /* enum: Voltage regulator internal temperature: degC */ 3849 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 3850 /* enum: 0.9V voltage regulator temperature: degC */ 3851 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 3852 /* enum: 1.2V voltage regulator temperature: degC */ 3853 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 3854 /* enum: controller internal temperature sensor voltage (internal ADC): mV */ 3855 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 3856 /* enum: controller internal temperature (internal ADC): degC */ 3857 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 3858 /* enum: controller internal temperature sensor voltage (external ADC): mV */ 3859 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 3860 /* enum: controller internal temperature (external ADC): degC */ 3861 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 3862 /* enum: ambient temperature: degC */ 3863 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 3864 /* enum: air flow: bool */ 3865 #define MC_CMD_SENSOR_AIRFLOW 0x2a 3866 /* enum: voltage between VSS08D and VSS08D at CSR: mV */ 3867 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b 3868 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ 3869 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c 3870 /* enum: Hotpoint temperature: degC */ 3871 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d 3872 /* enum: Port 0 PHY power switch over-current: bool */ 3873 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e 3874 /* enum: Port 1 PHY power switch over-current: bool */ 3875 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f 3876 /* enum: Mop-up microcontroller reference voltage (millivolts) */ 3877 #define MC_CMD_SENSOR_MUM_VCC 0x30 3878 /* enum: 0.9v power phase A voltage: mV */ 3879 #define MC_CMD_SENSOR_IN_0V9_A 0x31 3880 /* enum: 0.9v power phase A current: mA */ 3881 #define MC_CMD_SENSOR_IN_I0V9_A 0x32 3882 /* enum: 0.9V voltage regulator phase A temperature: degC */ 3883 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 3884 /* enum: 0.9v power phase B voltage: mV */ 3885 #define MC_CMD_SENSOR_IN_0V9_B 0x34 3886 /* enum: 0.9v power phase B current: mA */ 3887 #define MC_CMD_SENSOR_IN_I0V9_B 0x35 3888 /* enum: 0.9V voltage regulator phase B temperature: degC */ 3889 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 3890 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ 3891 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 3892 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */ 3893 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 3894 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ 3895 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 3896 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */ 3897 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a 3898 /* enum: Not a sensor: reserved for the next page flag */ 3899 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f 3900 /* enum: controller internal temperature sensor voltage on master core 3901 * (internal ADC): mV 3902 */ 3903 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 3904 /* enum: controller internal temperature on master core (internal ADC): degC */ 3905 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 3906 /* enum: controller internal temperature sensor voltage on master core 3907 * (external ADC): mV 3908 */ 3909 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 3910 /* enum: controller internal temperature on master core (external ADC): degC */ 3911 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 3912 /* enum: controller internal temperature on slave core sensor voltage (internal 3913 * ADC): mV 3914 */ 3915 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 3916 /* enum: controller internal temperature on slave core (internal ADC): degC */ 3917 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 3918 /* enum: controller internal temperature on slave core sensor voltage (external 3919 * ADC): mV 3920 */ 3921 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 3922 /* enum: controller internal temperature on slave core (external ADC): degC */ 3923 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 3924 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */ 3925 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49 3926 /* enum: Temperature of SODIMM 0 (if installed): degC */ 3927 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a 3928 /* enum: Temperature of SODIMM 1 (if installed): degC */ 3929 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b 3930 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ 3931 #define MC_CMD_SENSOR_PHY0_VCC 0x4c 3932 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ 3933 #define MC_CMD_SENSOR_PHY1_VCC 0x4d 3934 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 3935 #define MC_CMD_SENSOR_ENTRY_OFST 4 3936 #define MC_CMD_SENSOR_ENTRY_LEN 8 3937 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 3938 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 3939 #define MC_CMD_SENSOR_ENTRY_MINNUM 0 3940 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 3941 3942 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ 3943 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 3944 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 3945 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) 3946 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 3947 /* Enum values, see field(s): */ 3948 /* MC_CMD_SENSOR_INFO_OUT */ 3949 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 3950 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 3951 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 3952 /* MC_CMD_SENSOR_ENTRY_OFST 4 */ 3953 /* MC_CMD_SENSOR_ENTRY_LEN 8 */ 3954 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ 3955 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ 3956 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ 3957 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ 3958 3959 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 3960 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 3961 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 3962 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 3963 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 3964 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 3965 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 3966 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 3967 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 3968 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 3969 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 3970 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 3971 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 3972 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 3973 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 3974 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 3975 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 3976 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 3977 3978 3979 /***********************************/ 3980 /* MC_CMD_READ_SENSORS 3981 * Returns the current reading from each sensor. DMAs an array of sensor 3982 * readings, in order of sensor type (but without gaps for unimplemented 3983 * sensors), into host memory. Each array element is a 3984 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. 3985 * 3986 * If the request does not contain the LENGTH field then only sensors 0 to 30 3987 * are reported, to avoid DMA buffer overflow in older host software. If the 3988 * sensor reading require more space than the LENGTH allows, then return 3989 * EINVAL. 3990 * 3991 * The MC will send a SENSOREVT event every time any sensor changes state. The 3992 * driver is responsible for ensuring that it doesn't miss any events. The 3993 * board will function normally if all sensors are in STATE_OK or 3994 * STATE_WARNING. Otherwise the board should not be expected to function. 3995 */ 3996 #define MC_CMD_READ_SENSORS 0x42 3997 3998 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3999 4000 /* MC_CMD_READ_SENSORS_IN msgrequest */ 4001 #define MC_CMD_READ_SENSORS_IN_LEN 8 4002 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 4003 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 4004 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 4005 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 4006 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 4007 4008 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ 4009 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 4010 /* DMA address of host buffer for sensor readings */ 4011 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 4012 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 4013 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 4014 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 4015 /* Size in bytes of host buffer. */ 4016 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 4017 4018 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 4019 #define MC_CMD_READ_SENSORS_OUT_LEN 0 4020 4021 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ 4022 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 4023 4024 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 4025 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 4026 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 4027 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 4028 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 4029 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 4030 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 4031 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 4032 /* enum: Ok. */ 4033 #define MC_CMD_SENSOR_STATE_OK 0x0 4034 /* enum: Breached warning threshold. */ 4035 #define MC_CMD_SENSOR_STATE_WARNING 0x1 4036 /* enum: Breached fatal threshold. */ 4037 #define MC_CMD_SENSOR_STATE_FATAL 0x2 4038 /* enum: Fault with sensor. */ 4039 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 4040 /* enum: Sensor is working but does not currently have a reading. */ 4041 #define MC_CMD_SENSOR_STATE_NO_READING 0x4 4042 /* enum: Sensor initialisation failed. */ 4043 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5 4044 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 4045 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 4046 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 4047 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 4048 /* Enum values, see field(s): */ 4049 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 4050 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 4051 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 4052 4053 4054 /***********************************/ 4055 /* MC_CMD_GET_PHY_STATE 4056 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot 4057 * (e.g. due to missing or corrupted firmware). Locks required: None. Return 4058 * code: 0 4059 */ 4060 #define MC_CMD_GET_PHY_STATE 0x43 4061 4062 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4063 4064 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 4065 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 4066 4067 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 4068 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 4069 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 4070 /* enum: Ok. */ 4071 #define MC_CMD_PHY_STATE_OK 0x1 4072 /* enum: Faulty. */ 4073 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 4074 4075 4076 /***********************************/ 4077 /* MC_CMD_SETUP_8021QBB 4078 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 4079 * disable 802.Qbb for a given priority. 4080 */ 4081 #define MC_CMD_SETUP_8021QBB 0x44 4082 4083 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 4084 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 4085 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 4086 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 4087 4088 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 4089 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 4090 4091 4092 /***********************************/ 4093 /* MC_CMD_WOL_FILTER_GET 4094 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS 4095 */ 4096 #define MC_CMD_WOL_FILTER_GET 0x45 4097 4098 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK 4099 4100 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 4101 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 4102 4103 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 4104 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 4105 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 4106 4107 4108 /***********************************/ 4109 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 4110 * Add a protocol offload to NIC for lights-out state. Locks required: None. 4111 * Returns: 0, ENOSYS 4112 */ 4113 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 4114 4115 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK 4116 4117 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 4118 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 4119 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 4120 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 4121 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 4122 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 4123 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 4124 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 4125 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 4126 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 4127 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 4128 4129 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 4130 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 4131 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 4132 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 4133 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 4134 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 4135 4136 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 4137 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 4138 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 4139 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 4140 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 4141 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 4142 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 4143 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 4144 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 4145 4146 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 4147 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 4148 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 4149 4150 4151 /***********************************/ 4152 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 4153 * Remove a protocol offload from NIC for lights-out state. Locks required: 4154 * None. Returns: 0, ENOSYS 4155 */ 4156 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 4157 4158 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK 4159 4160 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 4161 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 4162 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 4163 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 4164 4165 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 4166 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 4167 4168 4169 /***********************************/ 4170 /* MC_CMD_MAC_RESET_RESTORE 4171 * Restore MAC after block reset. Locks required: None. Returns: 0. 4172 */ 4173 #define MC_CMD_MAC_RESET_RESTORE 0x48 4174 4175 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 4176 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 4177 4178 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 4179 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 4180 4181 4182 /***********************************/ 4183 /* MC_CMD_TESTASSERT 4184 * Deliberately trigger an assert-detonation in the firmware for testing 4185 * purposes (i.e. to allow tests that the driver copes gracefully). Locks 4186 * required: None Returns: 0 4187 */ 4188 #define MC_CMD_TESTASSERT 0x49 4189 4190 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4191 4192 /* MC_CMD_TESTASSERT_IN msgrequest */ 4193 #define MC_CMD_TESTASSERT_IN_LEN 0 4194 4195 /* MC_CMD_TESTASSERT_OUT msgresponse */ 4196 #define MC_CMD_TESTASSERT_OUT_LEN 0 4197 4198 4199 /***********************************/ 4200 /* MC_CMD_WORKAROUND 4201 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't 4202 * understand the given workaround number - which should not be treated as a 4203 * hard error by client code. This op does not imply any semantics about each 4204 * workaround, that's between the driver and the mcfw on a per-workaround 4205 * basis. Locks required: None. Returns: 0, EINVAL . 4206 */ 4207 #define MC_CMD_WORKAROUND 0x4a 4208 4209 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4210 4211 /* MC_CMD_WORKAROUND_IN msgrequest */ 4212 #define MC_CMD_WORKAROUND_IN_LEN 8 4213 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ 4214 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 4215 /* enum: Bug 17230 work around. */ 4216 #define MC_CMD_WORKAROUND_BUG17230 0x1 4217 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 4218 #define MC_CMD_WORKAROUND_BUG35388 0x2 4219 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 4220 #define MC_CMD_WORKAROUND_BUG35017 0x3 4221 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 4222 #define MC_CMD_WORKAROUND_BUG41750 0x4 4223 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 4224 * - before adding code that queries this workaround, remember that there's 4225 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 4226 * and will hence (incorrectly) report that the bug doesn't exist. 4227 */ 4228 #define MC_CMD_WORKAROUND_BUG42008 0x5 4229 /* enum: Bug 26807 features present in firmware (multicast filter chaining) 4230 * This feature cannot be turned on/off while there are any filters already 4231 * present. The behaviour in such case depends on the acting client's privilege 4232 * level. If the client has the admin privilege, then all functions that have 4233 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise 4234 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT. 4235 */ 4236 #define MC_CMD_WORKAROUND_BUG26807 0x6 4237 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable 4238 * the workaround 4239 */ 4240 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 4241 4242 /* MC_CMD_WORKAROUND_OUT msgresponse */ 4243 #define MC_CMD_WORKAROUND_OUT_LEN 0 4244 4245 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used 4246 * when (TYPE == MC_CMD_WORKAROUND_BUG26807) 4247 */ 4248 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 4249 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 4250 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 4251 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 4252 4253 4254 /***********************************/ 4255 /* MC_CMD_GET_PHY_MEDIA_INFO 4256 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 4257 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG 4258 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the 4259 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 4260 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. 4261 * Anything else: currently undefined. Locks required: None. Return code: 0. 4262 */ 4263 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 4264 4265 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4266 4267 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 4268 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 4269 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 4270 4271 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 4272 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 4273 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 4274 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 4275 /* in bytes */ 4276 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 4277 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 4278 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 4279 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 4280 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 4281 4282 4283 /***********************************/ 4284 /* MC_CMD_NVRAM_TEST 4285 * Test a particular NVRAM partition for valid contents (where "valid" depends 4286 * on the type of partition). 4287 */ 4288 #define MC_CMD_NVRAM_TEST 0x4c 4289 4290 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4291 4292 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 4293 #define MC_CMD_NVRAM_TEST_IN_LEN 4 4294 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 4295 /* Enum values, see field(s): */ 4296 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4297 4298 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 4299 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 4300 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 4301 /* enum: Passed. */ 4302 #define MC_CMD_NVRAM_TEST_PASS 0x0 4303 /* enum: Failed. */ 4304 #define MC_CMD_NVRAM_TEST_FAIL 0x1 4305 /* enum: Not supported. */ 4306 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 4307 4308 4309 /***********************************/ 4310 /* MC_CMD_MRSFP_TWEAK 4311 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 4312 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 4313 * they are configured first. Locks required: None. Return code: 0, EINVAL. 4314 */ 4315 #define MC_CMD_MRSFP_TWEAK 0x4d 4316 4317 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 4318 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 4319 /* 0-6 low->high de-emph. */ 4320 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 4321 /* 0-8 low->high ref.V */ 4322 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 4323 /* 0-8 0-8 low->high boost */ 4324 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 4325 /* 0-8 low->high ref.V */ 4326 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 4327 4328 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 4329 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 4330 4331 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 4332 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 4333 /* input bits */ 4334 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 4335 /* output bits */ 4336 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 4337 /* direction */ 4338 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 4339 /* enum: Out. */ 4340 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 4341 /* enum: In. */ 4342 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 4343 4344 4345 /***********************************/ 4346 /* MC_CMD_SENSOR_SET_LIMS 4347 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 4348 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 4349 * of range. 4350 */ 4351 #define MC_CMD_SENSOR_SET_LIMS 0x4e 4352 4353 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4354 4355 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 4356 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 4357 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 4358 /* Enum values, see field(s): */ 4359 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 4360 /* interpretation is is sensor-specific. */ 4361 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 4362 /* interpretation is is sensor-specific. */ 4363 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 4364 /* interpretation is is sensor-specific. */ 4365 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 4366 /* interpretation is is sensor-specific. */ 4367 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 4368 4369 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 4370 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 4371 4372 4373 /***********************************/ 4374 /* MC_CMD_GET_RESOURCE_LIMITS 4375 */ 4376 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 4377 4378 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 4379 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 4380 4381 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 4382 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 4383 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 4384 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 4385 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 4386 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 4387 4388 4389 /***********************************/ 4390 /* MC_CMD_NVRAM_PARTITIONS 4391 * Reads the list of available virtual NVRAM partition types. Locks required: 4392 * none. Returns: 0, EINVAL (bad type). 4393 */ 4394 #define MC_CMD_NVRAM_PARTITIONS 0x51 4395 4396 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4397 4398 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ 4399 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 4400 4401 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ 4402 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 4403 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 4404 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) 4405 /* total number of partitions */ 4406 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 4407 /* type ID code for each of NUM_PARTITIONS partitions */ 4408 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 4409 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 4410 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 4411 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 4412 4413 4414 /***********************************/ 4415 /* MC_CMD_NVRAM_METADATA 4416 * Reads soft metadata for a virtual NVRAM partition type. Locks required: 4417 * none. Returns: 0, EINVAL (bad type). 4418 */ 4419 #define MC_CMD_NVRAM_METADATA 0x52 4420 4421 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4422 4423 /* MC_CMD_NVRAM_METADATA_IN msgrequest */ 4424 #define MC_CMD_NVRAM_METADATA_IN_LEN 4 4425 /* Partition type ID code */ 4426 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 4427 4428 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ 4429 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 4430 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 4431 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) 4432 /* Partition type ID code */ 4433 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 4434 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 4435 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 4436 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 4437 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 4438 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 4439 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 4440 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 4441 /* Subtype ID code for content of this partition */ 4442 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 4443 /* 1st component of W.X.Y.Z version number for content of this partition */ 4444 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 4445 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 4446 /* 2nd component of W.X.Y.Z version number for content of this partition */ 4447 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 4448 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 4449 /* 3rd component of W.X.Y.Z version number for content of this partition */ 4450 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 4451 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 4452 /* 4th component of W.X.Y.Z version number for content of this partition */ 4453 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 4454 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 4455 /* Zero-terminated string describing the content of this partition */ 4456 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 4457 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 4458 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 4459 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 4460 4461 4462 /***********************************/ 4463 /* MC_CMD_GET_MAC_ADDRESSES 4464 * Returns the base MAC, count and stride for the requesting function 4465 */ 4466 #define MC_CMD_GET_MAC_ADDRESSES 0x55 4467 4468 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4469 4470 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ 4471 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 4472 4473 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ 4474 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 4475 /* Base MAC address */ 4476 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 4477 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 4478 /* Padding */ 4479 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 4480 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 4481 /* Number of allocated MAC addresses */ 4482 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 4483 /* Spacing of allocated MAC addresses */ 4484 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 4485 4486 4487 /***********************************/ 4488 /* MC_CMD_CLP 4489 * Perform a CLP related operation 4490 */ 4491 #define MC_CMD_CLP 0x56 4492 4493 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4494 4495 /* MC_CMD_CLP_IN msgrequest */ 4496 #define MC_CMD_CLP_IN_LEN 4 4497 /* Sub operation */ 4498 #define MC_CMD_CLP_IN_OP_OFST 0 4499 /* enum: Return to factory default settings */ 4500 #define MC_CMD_CLP_OP_DEFAULT 0x1 4501 /* enum: Set MAC address */ 4502 #define MC_CMD_CLP_OP_SET_MAC 0x2 4503 /* enum: Get MAC address */ 4504 #define MC_CMD_CLP_OP_GET_MAC 0x3 4505 /* enum: Set UEFI/GPXE boot mode */ 4506 #define MC_CMD_CLP_OP_SET_BOOT 0x4 4507 /* enum: Get UEFI/GPXE boot mode */ 4508 #define MC_CMD_CLP_OP_GET_BOOT 0x5 4509 4510 /* MC_CMD_CLP_OUT msgresponse */ 4511 #define MC_CMD_CLP_OUT_LEN 0 4512 4513 /* MC_CMD_CLP_IN_DEFAULT msgrequest */ 4514 #define MC_CMD_CLP_IN_DEFAULT_LEN 4 4515 /* MC_CMD_CLP_IN_OP_OFST 0 */ 4516 4517 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ 4518 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 4519 4520 /* MC_CMD_CLP_IN_SET_MAC msgrequest */ 4521 #define MC_CMD_CLP_IN_SET_MAC_LEN 12 4522 /* MC_CMD_CLP_IN_OP_OFST 0 */ 4523 /* MAC address assigned to port */ 4524 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 4525 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 4526 /* Padding */ 4527 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 4528 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 4529 4530 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ 4531 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 4532 4533 /* MC_CMD_CLP_IN_GET_MAC msgrequest */ 4534 #define MC_CMD_CLP_IN_GET_MAC_LEN 4 4535 /* MC_CMD_CLP_IN_OP_OFST 0 */ 4536 4537 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ 4538 #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 4539 /* MAC address assigned to port */ 4540 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 4541 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 4542 /* Padding */ 4543 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 4544 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 4545 4546 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ 4547 #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 4548 /* MC_CMD_CLP_IN_OP_OFST 0 */ 4549 /* Boot flag */ 4550 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 4551 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 4552 4553 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ 4554 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 4555 4556 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ 4557 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 4558 /* MC_CMD_CLP_IN_OP_OFST 0 */ 4559 4560 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ 4561 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 4562 /* Boot flag */ 4563 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 4564 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 4565 /* Padding */ 4566 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 4567 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 4568 4569 4570 /***********************************/ 4571 /* MC_CMD_MUM 4572 * Perform a MUM operation 4573 */ 4574 #define MC_CMD_MUM 0x57 4575 4576 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4577 4578 /* MC_CMD_MUM_IN msgrequest */ 4579 #define MC_CMD_MUM_IN_LEN 4 4580 #define MC_CMD_MUM_IN_OP_HDR_OFST 0 4581 #define MC_CMD_MUM_IN_OP_LBN 0 4582 #define MC_CMD_MUM_IN_OP_WIDTH 8 4583 /* enum: NULL MCDI command to MUM */ 4584 #define MC_CMD_MUM_OP_NULL 0x1 4585 /* enum: Get MUM version */ 4586 #define MC_CMD_MUM_OP_GET_VERSION 0x2 4587 /* enum: Issue raw I2C command to MUM */ 4588 #define MC_CMD_MUM_OP_RAW_CMD 0x3 4589 /* enum: Read from registers on devices connected to MUM. */ 4590 #define MC_CMD_MUM_OP_READ 0x4 4591 /* enum: Write to registers on devices connected to MUM. */ 4592 #define MC_CMD_MUM_OP_WRITE 0x5 4593 /* enum: Control UART logging. */ 4594 #define MC_CMD_MUM_OP_LOG 0x6 4595 /* enum: Operations on MUM GPIO lines */ 4596 #define MC_CMD_MUM_OP_GPIO 0x7 4597 /* enum: Get sensor readings from MUM */ 4598 #define MC_CMD_MUM_OP_READ_SENSORS 0x8 4599 /* enum: Initiate clock programming on the MUM */ 4600 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 4601 /* enum: Initiate FPGA load from flash on the MUM */ 4602 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa 4603 /* enum: Request sensor reading from MUM ADC resulting from earlier request via 4604 * MUM ATB 4605 */ 4606 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb 4607 /* enum: Send commands relating to the QSFP ports via the MUM for PHY 4608 * operations 4609 */ 4610 #define MC_CMD_MUM_OP_QSFP 0xc 4611 4612 /* MC_CMD_MUM_IN_NULL msgrequest */ 4613 #define MC_CMD_MUM_IN_NULL_LEN 4 4614 /* MUM cmd header */ 4615 #define MC_CMD_MUM_IN_CMD_OFST 0 4616 4617 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */ 4618 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4 4619 /* MUM cmd header */ 4620 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4621 4622 /* MC_CMD_MUM_IN_READ msgrequest */ 4623 #define MC_CMD_MUM_IN_READ_LEN 16 4624 /* MUM cmd header */ 4625 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4626 /* ID of (device connected to MUM) to read from registers of */ 4627 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 4628 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 4629 #define MC_CMD_MUM_DEV_HITTITE 0x1 4630 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ 4631 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 4632 /* 32-bit address to read from */ 4633 #define MC_CMD_MUM_IN_READ_ADDR_OFST 8 4634 /* Number of words to read. */ 4635 #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 4636 4637 /* MC_CMD_MUM_IN_WRITE msgrequest */ 4638 #define MC_CMD_MUM_IN_WRITE_LENMIN 16 4639 #define MC_CMD_MUM_IN_WRITE_LENMAX 252 4640 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) 4641 /* MUM cmd header */ 4642 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4643 /* ID of (device connected to MUM) to write to registers of */ 4644 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 4645 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 4646 /* MC_CMD_MUM_DEV_HITTITE 0x1 */ 4647 /* 32-bit address to write to */ 4648 #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 4649 /* Words to write */ 4650 #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 4651 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 4652 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 4653 #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 4654 4655 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */ 4656 #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 4657 #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 4658 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) 4659 /* MUM cmd header */ 4660 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4661 /* MUM I2C cmd code */ 4662 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 4663 /* Number of bytes to write */ 4664 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 4665 /* Number of bytes to read */ 4666 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 4667 /* Bytes to write */ 4668 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 4669 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 4670 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 4671 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 4672 4673 /* MC_CMD_MUM_IN_LOG msgrequest */ 4674 #define MC_CMD_MUM_IN_LOG_LEN 8 4675 /* MUM cmd header */ 4676 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4677 #define MC_CMD_MUM_IN_LOG_OP_OFST 4 4678 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ 4679 4680 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ 4681 #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 4682 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4683 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ 4684 /* Enable/disable debug output to UART */ 4685 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 4686 4687 /* MC_CMD_MUM_IN_GPIO msgrequest */ 4688 #define MC_CMD_MUM_IN_GPIO_LEN 8 4689 /* MUM cmd header */ 4690 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4691 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 4692 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 4693 #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 4694 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ 4695 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ 4696 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ 4697 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ 4698 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ 4699 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ 4700 4701 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ 4702 #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 4703 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4704 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 4705 4706 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ 4707 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 4708 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4709 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 4710 /* The first 32-bit word to be written to the GPIO OUT register. */ 4711 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 4712 /* The second 32-bit word to be written to the GPIO OUT register. */ 4713 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 4714 4715 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ 4716 #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 4717 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4718 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 4719 4720 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ 4721 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 4722 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4723 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 4724 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ 4725 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 4726 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ 4727 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 4728 4729 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ 4730 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 4731 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4732 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 4733 4734 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */ 4735 #define MC_CMD_MUM_IN_GPIO_OP_LEN 8 4736 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4737 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 4738 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 4739 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 4740 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ 4741 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ 4742 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ 4743 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ 4744 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 4745 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 4746 4747 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ 4748 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 4749 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4750 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 4751 4752 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ 4753 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 4754 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4755 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 4756 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 4757 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 4758 4759 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ 4760 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 4761 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4762 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 4763 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 4764 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 4765 4766 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ 4767 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 4768 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4769 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 4770 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 4771 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 4772 4773 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ 4774 #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 4775 /* MUM cmd header */ 4776 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4777 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 4778 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 4779 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 4780 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 4781 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 4782 4783 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ 4784 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 4785 /* MUM cmd header */ 4786 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4787 /* Bit-mask of clocks to be programmed */ 4788 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 4789 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ 4790 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ 4791 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ 4792 /* Control flags for clock programming */ 4793 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 4794 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 4795 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 4796 4797 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ 4798 #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 4799 /* MUM cmd header */ 4800 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4801 /* Enable/Disable FPGA config from flash */ 4802 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 4803 4804 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ 4805 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 4806 /* MUM cmd header */ 4807 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4808 4809 /* MC_CMD_MUM_IN_QSFP msgrequest */ 4810 #define MC_CMD_MUM_IN_QSFP_LEN 12 4811 /* MUM cmd header */ 4812 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4813 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 4814 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 4815 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 4816 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ 4817 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ 4818 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ 4819 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ 4820 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ 4821 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ 4822 #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 4823 4824 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ 4825 #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 4826 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4827 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 4828 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 4829 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 4830 4831 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ 4832 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 4833 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4834 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 4835 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 4836 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 4837 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 4838 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 4839 4840 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ 4841 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 4842 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4843 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 4844 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 4845 4846 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ 4847 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 4848 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4849 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 4850 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 4851 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 4852 4853 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ 4854 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 4855 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4856 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 4857 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 4858 4859 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ 4860 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 4861 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4862 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 4863 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 4864 4865 /* MC_CMD_MUM_OUT msgresponse */ 4866 #define MC_CMD_MUM_OUT_LEN 0 4867 4868 /* MC_CMD_MUM_OUT_NULL msgresponse */ 4869 #define MC_CMD_MUM_OUT_NULL_LEN 0 4870 4871 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ 4872 #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 4873 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 4874 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 4875 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 4876 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 4877 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 4878 4879 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ 4880 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 4881 #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 4882 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) 4883 /* returned data */ 4884 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 4885 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 4886 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 4887 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 4888 4889 /* MC_CMD_MUM_OUT_READ msgresponse */ 4890 #define MC_CMD_MUM_OUT_READ_LENMIN 4 4891 #define MC_CMD_MUM_OUT_READ_LENMAX 252 4892 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) 4893 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 4894 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 4895 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 4896 #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 4897 4898 /* MC_CMD_MUM_OUT_WRITE msgresponse */ 4899 #define MC_CMD_MUM_OUT_WRITE_LEN 0 4900 4901 /* MC_CMD_MUM_OUT_LOG msgresponse */ 4902 #define MC_CMD_MUM_OUT_LOG_LEN 0 4903 4904 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ 4905 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 4906 4907 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ 4908 #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 4909 /* The first 32-bit word read from the GPIO IN register. */ 4910 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 4911 /* The second 32-bit word read from the GPIO IN register. */ 4912 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 4913 4914 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ 4915 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 4916 4917 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ 4918 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 4919 /* The first 32-bit word read from the GPIO OUT register. */ 4920 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 4921 /* The second 32-bit word read from the GPIO OUT register. */ 4922 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 4923 4924 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ 4925 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 4926 4927 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ 4928 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 4929 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 4930 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 4931 4932 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ 4933 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 4934 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 4935 4936 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ 4937 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 4938 4939 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ 4940 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 4941 4942 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ 4943 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 4944 4945 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ 4946 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 4947 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 4948 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) 4949 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 4950 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 4951 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 4952 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 4953 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 4954 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 4955 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 4956 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 4957 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 4958 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 4959 4960 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ 4961 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 4962 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 4963 4964 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ 4965 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 4966 4967 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ 4968 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 4969 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 4970 4971 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ 4972 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 4973 4974 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ 4975 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 4976 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 4977 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 4978 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 4979 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 4980 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 4981 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 4982 4983 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ 4984 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 4985 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 4986 4987 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ 4988 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 4989 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 4990 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) 4991 /* in bytes */ 4992 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 4993 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 4994 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 4995 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 4996 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 4997 4998 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ 4999 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 5000 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 5001 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 5002 5003 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ 5004 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 5005 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 5006 5007 /* MC_CMD_RESOURCE_SPECIFIER enum */ 5008 /* enum: Any */ 5009 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff 5010 /* enum: None */ 5011 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe 5012 5013 /* EVB_PORT_ID structuredef */ 5014 #define EVB_PORT_ID_LEN 4 5015 #define EVB_PORT_ID_PORT_ID_OFST 0 5016 /* enum: An invalid port handle. */ 5017 #define EVB_PORT_ID_NULL 0x0 5018 /* enum: The port assigned to this function.. */ 5019 #define EVB_PORT_ID_ASSIGNED 0x1000000 5020 /* enum: External network port 0 */ 5021 #define EVB_PORT_ID_MAC0 0x2000000 5022 /* enum: External network port 1 */ 5023 #define EVB_PORT_ID_MAC1 0x2000001 5024 /* enum: External network port 2 */ 5025 #define EVB_PORT_ID_MAC2 0x2000002 5026 /* enum: External network port 3 */ 5027 #define EVB_PORT_ID_MAC3 0x2000003 5028 #define EVB_PORT_ID_PORT_ID_LBN 0 5029 #define EVB_PORT_ID_PORT_ID_WIDTH 32 5030 5031 /* EVB_VLAN_TAG structuredef */ 5032 #define EVB_VLAN_TAG_LEN 2 5033 /* The VLAN tag value */ 5034 #define EVB_VLAN_TAG_VLAN_ID_LBN 0 5035 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 5036 #define EVB_VLAN_TAG_MODE_LBN 12 5037 #define EVB_VLAN_TAG_MODE_WIDTH 4 5038 /* enum: Insert the VLAN. */ 5039 #define EVB_VLAN_TAG_INSERT 0x0 5040 /* enum: Replace the VLAN if already present. */ 5041 #define EVB_VLAN_TAG_REPLACE 0x1 5042 5043 /* BUFTBL_ENTRY structuredef */ 5044 #define BUFTBL_ENTRY_LEN 12 5045 /* the owner ID */ 5046 #define BUFTBL_ENTRY_OID_OFST 0 5047 #define BUFTBL_ENTRY_OID_LEN 2 5048 #define BUFTBL_ENTRY_OID_LBN 0 5049 #define BUFTBL_ENTRY_OID_WIDTH 16 5050 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 5051 #define BUFTBL_ENTRY_PGSZ_OFST 2 5052 #define BUFTBL_ENTRY_PGSZ_LEN 2 5053 #define BUFTBL_ENTRY_PGSZ_LBN 16 5054 #define BUFTBL_ENTRY_PGSZ_WIDTH 16 5055 /* the raw 64-bit address field from the SMC, not adjusted for page size */ 5056 #define BUFTBL_ENTRY_RAWADDR_OFST 4 5057 #define BUFTBL_ENTRY_RAWADDR_LEN 8 5058 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 5059 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 5060 #define BUFTBL_ENTRY_RAWADDR_LBN 32 5061 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 5062 5063 /* NVRAM_PARTITION_TYPE structuredef */ 5064 #define NVRAM_PARTITION_TYPE_LEN 2 5065 #define NVRAM_PARTITION_TYPE_ID_OFST 0 5066 #define NVRAM_PARTITION_TYPE_ID_LEN 2 5067 /* enum: Primary MC firmware partition */ 5068 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 5069 /* enum: Secondary MC firmware partition */ 5070 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 5071 /* enum: Expansion ROM partition */ 5072 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 5073 /* enum: Static configuration TLV partition */ 5074 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 5075 /* enum: Dynamic configuration TLV partition */ 5076 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 5077 /* enum: Expansion ROM configuration data for port 0 */ 5078 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 5079 /* enum: Expansion ROM configuration data for port 1 */ 5080 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 5081 /* enum: Expansion ROM configuration data for port 2 */ 5082 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 5083 /* enum: Expansion ROM configuration data for port 3 */ 5084 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 5085 /* enum: Non-volatile log output partition */ 5086 #define NVRAM_PARTITION_TYPE_LOG 0x700 5087 /* enum: Device state dump output partition */ 5088 #define NVRAM_PARTITION_TYPE_DUMP 0x800 5089 /* enum: Application license key storage partition */ 5090 #define NVRAM_PARTITION_TYPE_LICENSE 0x900 5091 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ 5092 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 5093 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ 5094 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff 5095 /* enum: Primary FPGA partition */ 5096 #define NVRAM_PARTITION_TYPE_FPGA 0xb00 5097 /* enum: Secondary FPGA partition */ 5098 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01 5099 /* enum: FC firmware partition */ 5100 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02 5101 /* enum: FC License partition */ 5102 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03 5103 /* enum: Non-volatile log output partition for FC */ 5104 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04 5105 /* enum: MUM firmware partition */ 5106 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00 5107 /* enum: MUM Non-volatile log output partition. */ 5108 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01 5109 /* enum: MUM Application table partition. */ 5110 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02 5111 /* enum: MUM boot rom partition. */ 5112 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03 5113 /* enum: MUM production signatures & calibration rom partition. */ 5114 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04 5115 /* enum: MUM user signatures & calibration rom partition. */ 5116 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 5117 /* enum: MUM fuses and lockbits partition. */ 5118 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 5119 /* enum: Start of reserved value range (firmware may use for any purpose) */ 5120 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 5121 /* enum: End of reserved value range (firmware may use for any purpose) */ 5122 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd 5123 /* enum: Recovery partition map (provided if real map is missing or corrupt) */ 5124 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe 5125 /* enum: Partition map (real map as stored in flash) */ 5126 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff 5127 #define NVRAM_PARTITION_TYPE_ID_LBN 0 5128 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 5129 5130 /* LICENSED_APP_ID structuredef */ 5131 #define LICENSED_APP_ID_LEN 4 5132 #define LICENSED_APP_ID_ID_OFST 0 5133 /* enum: OpenOnload */ 5134 #define LICENSED_APP_ID_ONLOAD 0x1 5135 /* enum: PTP timestamping */ 5136 #define LICENSED_APP_ID_PTP 0x2 5137 /* enum: SolarCapture Pro */ 5138 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 5139 /* enum: SolarSecure filter engine */ 5140 #define LICENSED_APP_ID_SOLARSECURE 0x8 5141 /* enum: Performance monitor */ 5142 #define LICENSED_APP_ID_PERF_MONITOR 0x10 5143 /* enum: SolarCapture Live */ 5144 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20 5145 /* enum: Capture SolarSystem */ 5146 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40 5147 /* enum: Network Access Control */ 5148 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80 5149 #define LICENSED_APP_ID_ID_LBN 0 5150 #define LICENSED_APP_ID_ID_WIDTH 32 5151 5152 /* TX_TIMESTAMP_EVENT structuredef */ 5153 #define TX_TIMESTAMP_EVENT_LEN 6 5154 /* lower 16 bits of timestamp data */ 5155 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 5156 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 5157 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 5158 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 5159 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp 5160 */ 5161 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 5162 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 5163 /* enum: This is a TX completion event, not a timestamp */ 5164 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 5165 /* enum: This is the low part of a TX timestamp event */ 5166 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 5167 /* enum: This is the high part of a TX timestamp event */ 5168 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 5169 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 5170 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 5171 /* upper 16 bits of timestamp data */ 5172 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 5173 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 5174 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 5175 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16 5176 5177 /* RSS_MODE structuredef */ 5178 #define RSS_MODE_LEN 1 5179 /* The RSS mode for a particular packet type is a value from 0 - 15 which can 5180 * be considered as 4 bits selecting which fields are included in the hash. (A 5181 * value 0 effectively disables RSS spreading for the packet type.) The YAML 5182 * generation tools require this structure to be a whole number of bytes wide, 5183 * but only 4 bits are relevant. 5184 */ 5185 #define RSS_MODE_HASH_SELECTOR_OFST 0 5186 #define RSS_MODE_HASH_SELECTOR_LEN 1 5187 #define RSS_MODE_HASH_SRC_ADDR_LBN 0 5188 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 5189 #define RSS_MODE_HASH_DST_ADDR_LBN 1 5190 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1 5191 #define RSS_MODE_HASH_SRC_PORT_LBN 2 5192 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1 5193 #define RSS_MODE_HASH_DST_PORT_LBN 3 5194 #define RSS_MODE_HASH_DST_PORT_WIDTH 1 5195 #define RSS_MODE_HASH_SELECTOR_LBN 0 5196 #define RSS_MODE_HASH_SELECTOR_WIDTH 8 5197 5198 5199 /***********************************/ 5200 /* MC_CMD_READ_REGS 5201 * Get a dump of the MCPU registers 5202 */ 5203 #define MC_CMD_READ_REGS 0x50 5204 5205 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5206 5207 /* MC_CMD_READ_REGS_IN msgrequest */ 5208 #define MC_CMD_READ_REGS_IN_LEN 0 5209 5210 /* MC_CMD_READ_REGS_OUT msgresponse */ 5211 #define MC_CMD_READ_REGS_OUT_LEN 308 5212 /* Whether the corresponding register entry contains a valid value */ 5213 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 5214 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 5215 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 5216 * fir, fp) 5217 */ 5218 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 5219 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 5220 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 5221 5222 5223 /***********************************/ 5224 /* MC_CMD_INIT_EVQ 5225 * Set up an event queue according to the supplied parameters. The IN arguments 5226 * end with an address for each 4k of host memory required to back the EVQ. 5227 */ 5228 #define MC_CMD_INIT_EVQ 0x80 5229 5230 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5231 5232 /* MC_CMD_INIT_EVQ_IN msgrequest */ 5233 #define MC_CMD_INIT_EVQ_IN_LENMIN 44 5234 #define MC_CMD_INIT_EVQ_IN_LENMAX 548 5235 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) 5236 /* Size, in entries */ 5237 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 5238 /* Desired instance. Must be set to a specific instance, which is a function 5239 * local queue index. 5240 */ 5241 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 5242 /* The initial timer value. The load value is ignored if the timer mode is DIS. 5243 */ 5244 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 5245 /* The reload value is ignored in one-shot modes */ 5246 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 5247 /* tbd */ 5248 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 5249 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 5250 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 5251 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 5252 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 5253 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 5254 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 5255 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 5256 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 5257 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 5258 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 5259 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 5260 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 5261 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 5262 /* enum: Disabled */ 5263 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 5264 /* enum: Immediate */ 5265 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 5266 /* enum: Triggered */ 5267 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 5268 /* enum: Hold-off */ 5269 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 5270 /* Target EVQ for wakeups if in wakeup mode. */ 5271 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 5272 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 5273 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 5274 * purposes. 5275 */ 5276 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 5277 /* Event Counter Mode. */ 5278 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 5279 /* enum: Disabled */ 5280 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 5281 /* enum: Disabled */ 5282 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 5283 /* enum: Disabled */ 5284 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 5285 /* enum: Disabled */ 5286 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 5287 /* Event queue packet count threshold. */ 5288 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 5289 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 5290 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 5291 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 5292 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 5293 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 5294 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 5295 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 5296 5297 /* MC_CMD_INIT_EVQ_OUT msgresponse */ 5298 #define MC_CMD_INIT_EVQ_OUT_LEN 4 5299 /* Only valid if INTRFLAG was true */ 5300 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 5301 5302 /* QUEUE_CRC_MODE structuredef */ 5303 #define QUEUE_CRC_MODE_LEN 1 5304 #define QUEUE_CRC_MODE_MODE_LBN 0 5305 #define QUEUE_CRC_MODE_MODE_WIDTH 4 5306 /* enum: No CRC. */ 5307 #define QUEUE_CRC_MODE_NONE 0x0 5308 /* enum: CRC Fiber channel over ethernet. */ 5309 #define QUEUE_CRC_MODE_FCOE 0x1 5310 /* enum: CRC (digest) iSCSI header only. */ 5311 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 5312 /* enum: CRC (digest) iSCSI header and payload. */ 5313 #define QUEUE_CRC_MODE_ISCSI 0x3 5314 /* enum: CRC Fiber channel over IP over ethernet. */ 5315 #define QUEUE_CRC_MODE_FCOIPOE 0x4 5316 /* enum: CRC MPA. */ 5317 #define QUEUE_CRC_MODE_MPA 0x5 5318 #define QUEUE_CRC_MODE_SPARE_LBN 4 5319 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 5320 5321 5322 /***********************************/ 5323 /* MC_CMD_INIT_RXQ 5324 * set up a receive queue according to the supplied parameters. The IN 5325 * arguments end with an address for each 4k of host memory required to back 5326 * the RXQ. 5327 */ 5328 #define MC_CMD_INIT_RXQ 0x81 5329 5330 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5331 5332 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version 5333 * in new code. 5334 */ 5335 #define MC_CMD_INIT_RXQ_IN_LENMIN 36 5336 #define MC_CMD_INIT_RXQ_IN_LENMAX 252 5337 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) 5338 /* Size, in entries */ 5339 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 5340 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 5341 */ 5342 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 5343 /* The value to put in the event data. Check hardware spec. for valid range. */ 5344 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 5345 /* Desired instance. Must be set to a specific instance, which is a function 5346 * local queue index. 5347 */ 5348 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 5349 /* There will be more flags here. */ 5350 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 5351 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 5352 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 5353 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 5354 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 5355 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 5356 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 5357 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 5358 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 5359 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 5360 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 5361 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 5362 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 5363 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 5364 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 5365 /* Owner ID to use if in buffer mode (zero if physical) */ 5366 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 5367 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 5368 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 5369 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 5370 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 5371 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 5372 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 5373 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 5374 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 5375 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 5376 5377 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode 5378 * flags 5379 */ 5380 #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 5381 /* Size, in entries */ 5382 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 5383 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 5384 */ 5385 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 5386 /* The value to put in the event data. Check hardware spec. for valid range. */ 5387 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 5388 /* Desired instance. Must be set to a specific instance, which is a function 5389 * local queue index. 5390 */ 5391 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 5392 /* There will be more flags here. */ 5393 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 5394 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 5395 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 5396 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 5397 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 5398 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 5399 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 5400 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 5401 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 5402 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 5403 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 5404 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 5405 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 5406 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 5407 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 5408 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 5409 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 5410 /* enum: One packet per descriptor (for normal networking) */ 5411 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 5412 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 5413 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 5414 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 5415 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 5416 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 5417 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 5418 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ 5419 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ 5420 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ 5421 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ 5422 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ 5423 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 5424 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 5425 /* Owner ID to use if in buffer mode (zero if physical) */ 5426 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 5427 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 5428 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 5429 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 5430 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 5431 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 5432 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 5433 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 5434 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 5435 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 5436 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 5437 5438 /* MC_CMD_INIT_RXQ_OUT msgresponse */ 5439 #define MC_CMD_INIT_RXQ_OUT_LEN 0 5440 5441 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */ 5442 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0 5443 5444 5445 /***********************************/ 5446 /* MC_CMD_INIT_TXQ 5447 */ 5448 #define MC_CMD_INIT_TXQ 0x82 5449 5450 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5451 5452 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version 5453 * in new code. 5454 */ 5455 #define MC_CMD_INIT_TXQ_IN_LENMIN 36 5456 #define MC_CMD_INIT_TXQ_IN_LENMAX 252 5457 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) 5458 /* Size, in entries */ 5459 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 5460 /* The EVQ to send events to. This is an index originally specified to 5461 * INIT_EVQ. 5462 */ 5463 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 5464 /* The value to put in the event data. Check hardware spec. for valid range. */ 5465 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 5466 /* Desired instance. Must be set to a specific instance, which is a function 5467 * local queue index. 5468 */ 5469 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 5470 /* There will be more flags here. */ 5471 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 5472 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 5473 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 5474 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 5475 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 5476 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 5477 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 5478 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 5479 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 5480 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 5481 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 5482 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 5483 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 5484 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 5485 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 5486 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 5487 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 5488 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 5489 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 5490 /* Owner ID to use if in buffer mode (zero if physical) */ 5491 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 5492 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 5493 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 5494 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 5495 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 5496 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 5497 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 5498 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 5499 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 5500 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 5501 5502 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode 5503 * flags 5504 */ 5505 #define MC_CMD_INIT_TXQ_EXT_IN_LEN 544 5506 /* Size, in entries */ 5507 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0 5508 /* The EVQ to send events to. This is an index originally specified to 5509 * INIT_EVQ. 5510 */ 5511 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4 5512 /* The value to put in the event data. Check hardware spec. for valid range. */ 5513 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8 5514 /* Desired instance. Must be set to a specific instance, which is a function 5515 * local queue index. 5516 */ 5517 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12 5518 /* There will be more flags here. */ 5519 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16 5520 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 5521 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 5522 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1 5523 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1 5524 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2 5525 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 5526 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3 5527 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 5528 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4 5529 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4 5530 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8 5531 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 5532 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9 5533 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1 5534 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 5535 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 5536 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 5537 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 5538 /* Owner ID to use if in buffer mode (zero if physical) */ 5539 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 5540 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 5541 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24 5542 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 5543 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28 5544 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8 5545 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28 5546 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32 5547 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1 5548 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64 5549 /* Flags related to Qbb flow control mode. */ 5550 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540 5551 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0 5552 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1 5553 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1 5554 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3 5555 5556 /* MC_CMD_INIT_TXQ_OUT msgresponse */ 5557 #define MC_CMD_INIT_TXQ_OUT_LEN 0 5558 5559 5560 /***********************************/ 5561 /* MC_CMD_FINI_EVQ 5562 * Teardown an EVQ. 5563 * 5564 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first 5565 * or the operation will fail with EBUSY 5566 */ 5567 #define MC_CMD_FINI_EVQ 0x83 5568 5569 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5570 5571 /* MC_CMD_FINI_EVQ_IN msgrequest */ 5572 #define MC_CMD_FINI_EVQ_IN_LEN 4 5573 /* Instance of EVQ to destroy. Should be the same instance as that previously 5574 * passed to INIT_EVQ 5575 */ 5576 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 5577 5578 /* MC_CMD_FINI_EVQ_OUT msgresponse */ 5579 #define MC_CMD_FINI_EVQ_OUT_LEN 0 5580 5581 5582 /***********************************/ 5583 /* MC_CMD_FINI_RXQ 5584 * Teardown a RXQ. 5585 */ 5586 #define MC_CMD_FINI_RXQ 0x84 5587 5588 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5589 5590 /* MC_CMD_FINI_RXQ_IN msgrequest */ 5591 #define MC_CMD_FINI_RXQ_IN_LEN 4 5592 /* Instance of RXQ to destroy */ 5593 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 5594 5595 /* MC_CMD_FINI_RXQ_OUT msgresponse */ 5596 #define MC_CMD_FINI_RXQ_OUT_LEN 0 5597 5598 5599 /***********************************/ 5600 /* MC_CMD_FINI_TXQ 5601 * Teardown a TXQ. 5602 */ 5603 #define MC_CMD_FINI_TXQ 0x85 5604 5605 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5606 5607 /* MC_CMD_FINI_TXQ_IN msgrequest */ 5608 #define MC_CMD_FINI_TXQ_IN_LEN 4 5609 /* Instance of TXQ to destroy */ 5610 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 5611 5612 /* MC_CMD_FINI_TXQ_OUT msgresponse */ 5613 #define MC_CMD_FINI_TXQ_OUT_LEN 0 5614 5615 5616 /***********************************/ 5617 /* MC_CMD_DRIVER_EVENT 5618 * Generate an event on an EVQ belonging to the function issuing the command. 5619 */ 5620 #define MC_CMD_DRIVER_EVENT 0x86 5621 5622 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5623 5624 /* MC_CMD_DRIVER_EVENT_IN msgrequest */ 5625 #define MC_CMD_DRIVER_EVENT_IN_LEN 12 5626 /* Handle of target EVQ */ 5627 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 5628 /* Bits 0 - 63 of event */ 5629 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 5630 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 5631 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 5632 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 5633 5634 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ 5635 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 5636 5637 5638 /***********************************/ 5639 /* MC_CMD_PROXY_CMD 5640 * Execute an arbitrary MCDI command on behalf of a different function, subject 5641 * to security restrictions. The command to be proxied follows immediately 5642 * afterward in the host buffer (or on the UART). This command supercedes 5643 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. 5644 */ 5645 #define MC_CMD_PROXY_CMD 0x5b 5646 5647 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5648 5649 /* MC_CMD_PROXY_CMD_IN msgrequest */ 5650 #define MC_CMD_PROXY_CMD_IN_LEN 4 5651 /* The handle of the target function. */ 5652 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 5653 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 5654 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 5655 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 5656 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 5657 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ 5658 5659 /* MC_CMD_PROXY_CMD_OUT msgresponse */ 5660 #define MC_CMD_PROXY_CMD_OUT_LEN 0 5661 5662 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to 5663 * manage proxied requests 5664 */ 5665 #define MC_PROXY_STATUS_BUFFER_LEN 16 5666 /* Handle allocated by the firmware for this proxy transaction */ 5667 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 5668 /* enum: An invalid handle. */ 5669 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 5670 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 5671 #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 5672 /* The requesting physical function number */ 5673 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4 5674 #define MC_PROXY_STATUS_BUFFER_PF_LEN 2 5675 #define MC_PROXY_STATUS_BUFFER_PF_LBN 32 5676 #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 5677 /* The requesting virtual function number. Set to VF_NULL if the target is a 5678 * PF. 5679 */ 5680 #define MC_PROXY_STATUS_BUFFER_VF_OFST 6 5681 #define MC_PROXY_STATUS_BUFFER_VF_LEN 2 5682 #define MC_PROXY_STATUS_BUFFER_VF_LBN 48 5683 #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 5684 /* The target function RID. */ 5685 #define MC_PROXY_STATUS_BUFFER_RID_OFST 8 5686 #define MC_PROXY_STATUS_BUFFER_RID_LEN 2 5687 #define MC_PROXY_STATUS_BUFFER_RID_LBN 64 5688 #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 5689 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ 5690 #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 5691 #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 5692 #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 5693 #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 5694 /* If a request is authorized rather than carried out by the host, this is the 5695 * elevated privilege mask granted to the requesting function. 5696 */ 5697 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 5698 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 5699 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 5700 5701 5702 /***********************************/ 5703 /* MC_CMD_PROXY_CONFIGURE 5704 * Enable/disable authorization of MCDI requests from unprivileged functions by 5705 * a designated admin function 5706 */ 5707 #define MC_CMD_PROXY_CONFIGURE 0x58 5708 5709 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5710 5711 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ 5712 #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 5713 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 5714 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 5715 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 5716 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 5717 * of blocks, each of the size REQUEST_BLOCK_SIZE. 5718 */ 5719 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 5720 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 5721 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 5722 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 5723 /* Must be a power of 2 */ 5724 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 5725 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 5726 * of blocks, each of the size REPLY_BLOCK_SIZE. 5727 */ 5728 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 5729 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 5730 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 5731 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 5732 /* Must be a power of 2 */ 5733 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 5734 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 5735 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 5736 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 5737 */ 5738 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 5739 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 5740 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 5741 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 5742 /* Must be a power of 2, or zero if this buffer is not provided */ 5743 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 5744 /* Applies to all three buffers */ 5745 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 5746 /* A bit mask defining which MCDI operations may be proxied */ 5747 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 5748 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 5749 5750 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ 5751 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 5752 5753 5754 /***********************************/ 5755 /* MC_CMD_PROXY_COMPLETE 5756 * Tells FW that a requested proxy operation has either been completed (by 5757 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the 5758 * function that enabled proxying/authorization (by using 5759 * MC_CMD_PROXY_CONFIGURE). 5760 */ 5761 #define MC_CMD_PROXY_COMPLETE 0x5f 5762 5763 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5764 5765 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */ 5766 #define MC_CMD_PROXY_COMPLETE_IN_LEN 12 5767 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 5768 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 5769 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply 5770 * is stored in the REPLY_BUFF. 5771 */ 5772 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 5773 /* enum: The operation has been authorized. The originating function may now 5774 * try again. 5775 */ 5776 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 5777 /* enum: The operation has been declined. */ 5778 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 5779 /* enum: The authorization failed because the relevant application did not 5780 * respond in time. 5781 */ 5782 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 5783 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 5784 5785 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ 5786 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 5787 5788 5789 /***********************************/ 5790 /* MC_CMD_ALLOC_BUFTBL_CHUNK 5791 * Allocate a set of buffer table entries using the specified owner ID. This 5792 * operation allocates the required buffer table entries (and fails if it 5793 * cannot do so). The buffer table entries will initially be zeroed. 5794 */ 5795 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 5796 5797 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 5798 5799 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 5800 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 5801 /* Owner ID to use */ 5802 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 5803 /* Size of buffer table pages to use, in bytes (note that only a few values are 5804 * legal on any specific hardware). 5805 */ 5806 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 5807 5808 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 5809 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 5810 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 5811 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 5812 /* Buffer table IDs for use in DMA descriptors. */ 5813 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 5814 5815 5816 /***********************************/ 5817 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES 5818 * Reprogram a set of buffer table entries in the specified chunk. 5819 */ 5820 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 5821 5822 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 5823 5824 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 5825 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 5826 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 5827 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 5828 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 5829 /* ID */ 5830 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 5831 /* Num entries */ 5832 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 5833 /* Buffer table entry address */ 5834 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 5835 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 5836 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 5837 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 5838 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 5839 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 5840 5841 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 5842 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 5843 5844 5845 /***********************************/ 5846 /* MC_CMD_FREE_BUFTBL_CHUNK 5847 */ 5848 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 5849 5850 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 5851 5852 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 5853 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 5854 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 5855 5856 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 5857 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 5858 5859 /* PORT_CONFIG_ENTRY structuredef */ 5860 #define PORT_CONFIG_ENTRY_LEN 16 5861 /* External port number (label) */ 5862 #define PORT_CONFIG_ENTRY_EXT_NUMBER_OFST 0 5863 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LEN 1 5864 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LBN 0 5865 #define PORT_CONFIG_ENTRY_EXT_NUMBER_WIDTH 8 5866 /* Port core location */ 5867 #define PORT_CONFIG_ENTRY_CORE_OFST 1 5868 #define PORT_CONFIG_ENTRY_CORE_LEN 1 5869 #define PORT_CONFIG_ENTRY_STANDALONE 0x0 /* enum */ 5870 #define PORT_CONFIG_ENTRY_MASTER 0x1 /* enum */ 5871 #define PORT_CONFIG_ENTRY_SLAVE 0x2 /* enum */ 5872 #define PORT_CONFIG_ENTRY_CORE_LBN 8 5873 #define PORT_CONFIG_ENTRY_CORE_WIDTH 8 5874 /* Internal number (HW resource) relative to the core */ 5875 #define PORT_CONFIG_ENTRY_INT_NUMBER_OFST 2 5876 #define PORT_CONFIG_ENTRY_INT_NUMBER_LEN 1 5877 #define PORT_CONFIG_ENTRY_INT_NUMBER_LBN 16 5878 #define PORT_CONFIG_ENTRY_INT_NUMBER_WIDTH 8 5879 /* Reserved */ 5880 #define PORT_CONFIG_ENTRY_RSVD_OFST 3 5881 #define PORT_CONFIG_ENTRY_RSVD_LEN 1 5882 #define PORT_CONFIG_ENTRY_RSVD_LBN 24 5883 #define PORT_CONFIG_ENTRY_RSVD_WIDTH 8 5884 /* Bitmask of KR lanes used by the port */ 5885 #define PORT_CONFIG_ENTRY_LANES_OFST 4 5886 #define PORT_CONFIG_ENTRY_LANES_LBN 32 5887 #define PORT_CONFIG_ENTRY_LANES_WIDTH 32 5888 /* Port capabilities (MC_CMD_PHY_CAP_*) */ 5889 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_OFST 8 5890 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_LBN 64 5891 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_WIDTH 32 5892 /* Reserved (align to 16 bytes) */ 5893 #define PORT_CONFIG_ENTRY_RSVD2_OFST 12 5894 #define PORT_CONFIG_ENTRY_RSVD2_LBN 96 5895 #define PORT_CONFIG_ENTRY_RSVD2_WIDTH 32 5896 5897 5898 /***********************************/ 5899 /* MC_CMD_FILTER_OP 5900 * Multiplexed MCDI call for filter operations 5901 */ 5902 #define MC_CMD_FILTER_OP 0x8a 5903 5904 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5905 5906 /* MC_CMD_FILTER_OP_IN msgrequest */ 5907 #define MC_CMD_FILTER_OP_IN_LEN 108 5908 /* identifies the type of operation requested */ 5909 #define MC_CMD_FILTER_OP_IN_OP_OFST 0 5910 /* enum: single-recipient filter insert */ 5911 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 5912 /* enum: single-recipient filter remove */ 5913 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 5914 /* enum: multi-recipient filter subscribe */ 5915 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 5916 /* enum: multi-recipient filter unsubscribe */ 5917 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 5918 /* enum: replace one recipient with another (warning - the filter handle may 5919 * change) 5920 */ 5921 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 5922 /* filter handle (for remove / unsubscribe operations) */ 5923 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 5924 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 5925 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 5926 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 5927 /* The port ID associated with the v-adaptor which should contain this filter. 5928 */ 5929 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 5930 /* fields to include in match criteria */ 5931 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 5932 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 5933 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 5934 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 5935 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 5936 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 5937 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 5938 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 5939 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 5940 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 5941 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 5942 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 5943 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 5944 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 5945 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 5946 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 5947 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 5948 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 5949 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 5950 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 5951 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 5952 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 5953 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 5954 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 5955 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 5956 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 5957 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 5958 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 5959 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 5960 /* receive destination */ 5961 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 5962 /* enum: drop packets */ 5963 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 5964 /* enum: receive to host */ 5965 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 5966 /* enum: receive to MC */ 5967 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 5968 /* enum: loop back to TXDP 0 */ 5969 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 5970 /* enum: loop back to TXDP 1 */ 5971 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 5972 /* receive queue handle (for multiple queue modes, this is the base queue) */ 5973 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 5974 /* receive mode */ 5975 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 5976 /* enum: receive to just the specified queue */ 5977 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 5978 /* enum: receive to multiple queues using RSS context */ 5979 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 5980 /* enum: receive to multiple queues using .1p mapping */ 5981 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 5982 /* enum: install a filter entry that will never match; for test purposes only 5983 */ 5984 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 5985 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 5986 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 5987 * MC_CMD_DOT1P_MAPPING_ALLOC. 5988 */ 5989 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 5990 /* transmit domain (reserved; set to 0) */ 5991 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 5992 /* transmit destination (either set the MAC and/or PM bits for explicit 5993 * control, or set this field to TX_DEST_DEFAULT for sensible default 5994 * behaviour) 5995 */ 5996 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 5997 /* enum: request default behaviour (based on filter type) */ 5998 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff 5999 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 6000 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 6001 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 6002 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 6003 /* source MAC address to match (as bytes in network order) */ 6004 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 6005 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 6006 /* source port to match (as bytes in network order) */ 6007 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 6008 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 6009 /* destination MAC address to match (as bytes in network order) */ 6010 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 6011 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 6012 /* destination port to match (as bytes in network order) */ 6013 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 6014 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 6015 /* Ethernet type to match (as bytes in network order) */ 6016 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 6017 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 6018 /* Inner VLAN tag to match (as bytes in network order) */ 6019 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 6020 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 6021 /* Outer VLAN tag to match (as bytes in network order) */ 6022 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 6023 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 6024 /* IP protocol to match (in low byte; set high byte to 0) */ 6025 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 6026 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 6027 /* Firmware defined register 0 to match (reserved; set to 0) */ 6028 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 6029 /* Firmware defined register 1 to match (reserved; set to 0) */ 6030 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 6031 /* source IP address to match (as bytes in network order; set last 12 bytes to 6032 * 0 for IPv4 address) 6033 */ 6034 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 6035 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 6036 /* destination IP address to match (as bytes in network order; set last 12 6037 * bytes to 0 for IPv4 address) 6038 */ 6039 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 6040 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 6041 6042 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to 6043 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is 6044 * supported on Medford only). 6045 */ 6046 #define MC_CMD_FILTER_OP_EXT_IN_LEN 172 6047 /* identifies the type of operation requested */ 6048 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 6049 /* Enum values, see field(s): */ 6050 /* MC_CMD_FILTER_OP_IN/OP */ 6051 /* filter handle (for remove / unsubscribe operations) */ 6052 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 6053 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 6054 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 6055 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 6056 /* The port ID associated with the v-adaptor which should contain this filter. 6057 */ 6058 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 6059 /* fields to include in match criteria */ 6060 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 6061 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 6062 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 6063 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 6064 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 6065 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 6066 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 6067 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 6068 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 6069 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 6070 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 6071 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 6072 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 6073 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 6074 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 6075 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 6076 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 6077 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 6078 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 6079 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 6080 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 6081 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 6082 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 6083 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 6084 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 6085 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 6086 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 6087 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 6088 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 6089 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 6090 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 6091 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 6092 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 6093 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 6094 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 6095 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 6096 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 6097 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 6098 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 6099 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 6100 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 6101 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 6102 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 6103 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 6104 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 6105 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 6106 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 6107 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 6108 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 6109 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 6110 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 6111 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 6112 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 6113 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 6114 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 6115 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 6116 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 6117 /* receive destination */ 6118 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 6119 /* enum: drop packets */ 6120 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 6121 /* enum: receive to host */ 6122 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 6123 /* enum: receive to MC */ 6124 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 6125 /* enum: loop back to TXDP 0 */ 6126 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 6127 /* enum: loop back to TXDP 1 */ 6128 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 6129 /* receive queue handle (for multiple queue modes, this is the base queue) */ 6130 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 6131 /* receive mode */ 6132 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 6133 /* enum: receive to just the specified queue */ 6134 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 6135 /* enum: receive to multiple queues using RSS context */ 6136 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 6137 /* enum: receive to multiple queues using .1p mapping */ 6138 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 6139 /* enum: install a filter entry that will never match; for test purposes only 6140 */ 6141 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 6142 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 6143 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 6144 * MC_CMD_DOT1P_MAPPING_ALLOC. 6145 */ 6146 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 6147 /* transmit domain (reserved; set to 0) */ 6148 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 6149 /* transmit destination (either set the MAC and/or PM bits for explicit 6150 * control, or set this field to TX_DEST_DEFAULT for sensible default 6151 * behaviour) 6152 */ 6153 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 6154 /* enum: request default behaviour (based on filter type) */ 6155 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff 6156 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 6157 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 6158 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 6159 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 6160 /* source MAC address to match (as bytes in network order) */ 6161 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 6162 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 6163 /* source port to match (as bytes in network order) */ 6164 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 6165 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 6166 /* destination MAC address to match (as bytes in network order) */ 6167 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 6168 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 6169 /* destination port to match (as bytes in network order) */ 6170 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 6171 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 6172 /* Ethernet type to match (as bytes in network order) */ 6173 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 6174 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 6175 /* Inner VLAN tag to match (as bytes in network order) */ 6176 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 6177 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 6178 /* Outer VLAN tag to match (as bytes in network order) */ 6179 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 6180 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 6181 /* IP protocol to match (in low byte; set high byte to 0) */ 6182 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 6183 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 6184 /* Firmware defined register 0 to match (reserved; set to 0) */ 6185 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 6186 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 6187 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 6188 * VXLAN/NVGRE, or 1 for Geneve) 6189 */ 6190 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 6191 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 6192 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 6193 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 6194 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 6195 /* enum: Match VXLAN traffic with this VNI */ 6196 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 6197 /* enum: Match Geneve traffic with this VNI */ 6198 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 6199 /* enum: Reserved for experimental development use */ 6200 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe 6201 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 6202 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 6203 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 6204 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 6205 /* enum: Match NVGRE traffic with this VSID */ 6206 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 6207 /* source IP address to match (as bytes in network order; set last 12 bytes to 6208 * 0 for IPv4 address) 6209 */ 6210 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 6211 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 6212 /* destination IP address to match (as bytes in network order; set last 12 6213 * bytes to 0 for IPv4 address) 6214 */ 6215 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 6216 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 6217 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 6218 * order) 6219 */ 6220 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 6221 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 6222 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 6223 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 6224 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 6225 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 6226 * network order) 6227 */ 6228 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 6229 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 6230 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network 6231 * order) 6232 */ 6233 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 6234 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 6235 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 6236 */ 6237 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 6238 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 6239 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 6240 */ 6241 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 6242 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 6243 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 6244 */ 6245 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 6246 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 6247 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 6248 * 0) 6249 */ 6250 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 6251 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 6252 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 6253 * to 0) 6254 */ 6255 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 6256 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 6257 * to 0) 6258 */ 6259 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 6260 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 6261 * order; set last 12 bytes to 0 for IPv4 address) 6262 */ 6263 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 6264 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 6265 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 6266 * order; set last 12 bytes to 0 for IPv4 address) 6267 */ 6268 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 6269 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16 6270 6271 /* MC_CMD_FILTER_OP_OUT msgresponse */ 6272 #define MC_CMD_FILTER_OP_OUT_LEN 12 6273 /* identifies the type of operation requested */ 6274 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 6275 /* Enum values, see field(s): */ 6276 /* MC_CMD_FILTER_OP_IN/OP */ 6277 /* Returned filter handle (for insert / subscribe operations). Note that these 6278 * handles should be considered opaque to the host, although a value of 6279 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 6280 */ 6281 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 6282 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 6283 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 6284 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 6285 /* enum: guaranteed invalid filter handle (low 32 bits) */ 6286 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff 6287 /* enum: guaranteed invalid filter handle (high 32 bits) */ 6288 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff 6289 6290 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ 6291 #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 6292 /* identifies the type of operation requested */ 6293 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 6294 /* Enum values, see field(s): */ 6295 /* MC_CMD_FILTER_OP_EXT_IN/OP */ 6296 /* Returned filter handle (for insert / subscribe operations). Note that these 6297 * handles should be considered opaque to the host, although a value of 6298 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 6299 */ 6300 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 6301 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 6302 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 6303 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 6304 /* Enum values, see field(s): */ 6305 /* MC_CMD_FILTER_OP_OUT/HANDLE */ 6306 6307 6308 /***********************************/ 6309 /* MC_CMD_GET_PARSER_DISP_INFO 6310 * Get information related to the parser-dispatcher subsystem 6311 */ 6312 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 6313 6314 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6315 6316 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ 6317 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 6318 /* identifies the type of operation requested */ 6319 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 6320 /* enum: read the list of supported RX filter matches */ 6321 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 6322 /* enum: read flags indicating restrictions on filter insertion for the calling 6323 * client 6324 */ 6325 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 6326 6327 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 6328 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 6329 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 6330 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) 6331 /* identifies the type of operation requested */ 6332 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 6333 /* Enum values, see field(s): */ 6334 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 6335 /* number of supported match types */ 6336 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 6337 /* array of supported match types (valid MATCH_FIELDS values for 6338 * MC_CMD_FILTER_OP) sorted in decreasing priority order 6339 */ 6340 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 6341 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 6342 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 6343 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 6344 6345 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */ 6346 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8 6347 /* identifies the type of operation requested */ 6348 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0 6349 /* Enum values, see field(s): */ 6350 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 6351 /* bitfield of filter insertion restrictions */ 6352 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4 6353 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 6354 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 6355 6356 6357 /***********************************/ 6358 /* MC_CMD_PARSER_DISP_RW 6359 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging 6360 */ 6361 #define MC_CMD_PARSER_DISP_RW 0xe5 6362 6363 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6364 6365 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 6366 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 6367 /* identifies the target of the operation */ 6368 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 6369 /* enum: RX dispatcher CPU */ 6370 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 6371 /* enum: TX dispatcher CPU */ 6372 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 6373 /* enum: Lookup engine (with original metadata format) */ 6374 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 6375 /* enum: Lookup engine (with requested metadata format) */ 6376 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 6377 /* identifies the type of operation requested */ 6378 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 6379 /* enum: read a word of DICPU DMEM or a LUE entry */ 6380 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 6381 /* enum: write a word of DICPU DMEM or a LUE entry */ 6382 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 6383 /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ 6384 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 6385 /* data memory address or LUE index */ 6386 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 6387 /* value to write (for DMEM writes) */ 6388 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 6389 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 6390 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 6391 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 6392 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 6393 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ 6394 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 6395 /* value to write (for LUE writes) */ 6396 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 6397 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 6398 6399 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 6400 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 6401 /* value read (for DMEM reads) */ 6402 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 6403 /* value read (for LUE reads) */ 6404 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 6405 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 6406 /* up to 8 32-bit words of additional soft state from the LUE manager (the 6407 * exact content is firmware-dependent and intended only for debug use) 6408 */ 6409 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 6410 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 6411 6412 6413 /***********************************/ 6414 /* MC_CMD_GET_PF_COUNT 6415 * Get number of PFs on the device. 6416 */ 6417 #define MC_CMD_GET_PF_COUNT 0xb6 6418 6419 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6420 6421 /* MC_CMD_GET_PF_COUNT_IN msgrequest */ 6422 #define MC_CMD_GET_PF_COUNT_IN_LEN 0 6423 6424 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 6425 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 6426 /* Identifies the number of PFs on the device. */ 6427 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 6428 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 6429 6430 6431 /***********************************/ 6432 /* MC_CMD_SET_PF_COUNT 6433 * Set number of PFs on the device. 6434 */ 6435 #define MC_CMD_SET_PF_COUNT 0xb7 6436 6437 /* MC_CMD_SET_PF_COUNT_IN msgrequest */ 6438 #define MC_CMD_SET_PF_COUNT_IN_LEN 4 6439 /* New number of PFs on the device. */ 6440 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 6441 6442 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 6443 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 6444 6445 6446 /***********************************/ 6447 /* MC_CMD_GET_PORT_ASSIGNMENT 6448 * Get port assignment for current PCI function. 6449 */ 6450 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 6451 6452 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6453 6454 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 6455 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 6456 6457 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 6458 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 6459 /* Identifies the port assignment for this function. */ 6460 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 6461 6462 6463 /***********************************/ 6464 /* MC_CMD_SET_PORT_ASSIGNMENT 6465 * Set port assignment for current PCI function. 6466 */ 6467 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 6468 6469 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6470 6471 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 6472 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 6473 /* Identifies the port assignment for this function. */ 6474 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 6475 6476 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 6477 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 6478 6479 6480 /***********************************/ 6481 /* MC_CMD_ALLOC_VIS 6482 * Allocate VIs for current PCI function. 6483 */ 6484 #define MC_CMD_ALLOC_VIS 0x8b 6485 6486 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6487 6488 /* MC_CMD_ALLOC_VIS_IN msgrequest */ 6489 #define MC_CMD_ALLOC_VIS_IN_LEN 8 6490 /* The minimum number of VIs that is acceptable */ 6491 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 6492 /* The maximum number of VIs that would be useful */ 6493 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 6494 6495 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. 6496 * Use extended version in new code. 6497 */ 6498 #define MC_CMD_ALLOC_VIS_OUT_LEN 8 6499 /* The number of VIs allocated on this function */ 6500 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 6501 /* The base absolute VI number allocated to this function. Required to 6502 * correctly interpret wakeup events. 6503 */ 6504 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 6505 6506 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ 6507 #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 6508 /* The number of VIs allocated on this function */ 6509 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 6510 /* The base absolute VI number allocated to this function. Required to 6511 * correctly interpret wakeup events. 6512 */ 6513 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 6514 /* Function's port vi_shift value (always 0 on Huntington) */ 6515 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 6516 6517 6518 /***********************************/ 6519 /* MC_CMD_FREE_VIS 6520 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, 6521 * but not freed. 6522 */ 6523 #define MC_CMD_FREE_VIS 0x8c 6524 6525 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6526 6527 /* MC_CMD_FREE_VIS_IN msgrequest */ 6528 #define MC_CMD_FREE_VIS_IN_LEN 0 6529 6530 /* MC_CMD_FREE_VIS_OUT msgresponse */ 6531 #define MC_CMD_FREE_VIS_OUT_LEN 0 6532 6533 6534 /***********************************/ 6535 /* MC_CMD_GET_SRIOV_CFG 6536 * Get SRIOV config for this PF. 6537 */ 6538 #define MC_CMD_GET_SRIOV_CFG 0xba 6539 6540 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6541 6542 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 6543 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 6544 6545 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 6546 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 6547 /* Number of VFs currently enabled. */ 6548 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 6549 /* Max number of VFs before sriov stride and offset may need to be changed. */ 6550 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 6551 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 6552 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 6553 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 6554 /* RID offset of first VF from PF. */ 6555 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 6556 /* RID offset of each subsequent VF from the previous. */ 6557 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 6558 6559 6560 /***********************************/ 6561 /* MC_CMD_SET_SRIOV_CFG 6562 * Set SRIOV config for this PF. 6563 */ 6564 #define MC_CMD_SET_SRIOV_CFG 0xbb 6565 6566 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6567 6568 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 6569 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 6570 /* Number of VFs currently enabled. */ 6571 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 6572 /* Max number of VFs before sriov stride and offset may need to be changed. */ 6573 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 6574 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 6575 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 6576 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 6577 /* RID offset of first VF from PF, or 0 for no change, or 6578 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 6579 */ 6580 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 6581 /* RID offset of each subsequent VF from the previous, 0 for no change, or 6582 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 6583 */ 6584 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 6585 6586 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 6587 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 6588 6589 6590 /***********************************/ 6591 /* MC_CMD_GET_VI_ALLOC_INFO 6592 * Get information about number of VI's and base VI number allocated to this 6593 * function. 6594 */ 6595 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d 6596 6597 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6598 6599 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 6600 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 6601 6602 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 6603 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 6604 /* The number of VIs allocated on this function */ 6605 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 6606 /* The base absolute VI number allocated to this function. Required to 6607 * correctly interpret wakeup events. 6608 */ 6609 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 6610 /* Function's port vi_shift value (always 0 on Huntington) */ 6611 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 6612 6613 6614 /***********************************/ 6615 /* MC_CMD_DUMP_VI_STATE 6616 * For CmdClient use. Dump pertinent information on a specific absolute VI. 6617 */ 6618 #define MC_CMD_DUMP_VI_STATE 0x8e 6619 6620 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6621 6622 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 6623 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 6624 /* The VI number to query. */ 6625 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 6626 6627 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 6628 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 6629 /* The PF part of the function owning this VI. */ 6630 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 6631 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 6632 /* The VF part of the function owning this VI. */ 6633 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 6634 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 6635 /* Base of VIs allocated to this function. */ 6636 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 6637 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 6638 /* Count of VIs allocated to the owner function. */ 6639 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 6640 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 6641 /* Base interrupt vector allocated to this function. */ 6642 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 6643 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 6644 /* Number of interrupt vectors allocated to this function. */ 6645 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 6646 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 6647 /* Raw evq ptr table data. */ 6648 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 6649 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 6650 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 6651 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 6652 /* Raw evq timer table data. */ 6653 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 6654 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 6655 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 6656 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 6657 /* Combined metadata field. */ 6658 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 6659 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 6660 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 6661 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 6662 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 6663 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 6664 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 6665 /* TXDPCPU raw table data for queue. */ 6666 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 6667 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 6668 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 6669 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 6670 /* TXDPCPU raw table data for queue. */ 6671 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 6672 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 6673 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 6674 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 6675 /* TXDPCPU raw table data for queue. */ 6676 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 6677 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 6678 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 6679 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 6680 /* Combined metadata field. */ 6681 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 6682 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 6683 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 6684 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 6685 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 6686 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 6687 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 6688 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 6689 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 6690 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 6691 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 6692 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 6693 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 6694 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 6695 /* RXDPCPU raw table data for queue. */ 6696 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 6697 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 6698 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 6699 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 6700 /* RXDPCPU raw table data for queue. */ 6701 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 6702 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 6703 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 6704 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 6705 /* Reserved, currently 0. */ 6706 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 6707 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 6708 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 6709 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 6710 /* Combined metadata field. */ 6711 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 6712 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 6713 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 6714 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 6715 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 6716 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 6717 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 6718 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 6719 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 6720 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 6721 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 6722 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 6723 6724 6725 /***********************************/ 6726 /* MC_CMD_ALLOC_PIOBUF 6727 * Allocate a push I/O buffer for later use with a tx queue. 6728 */ 6729 #define MC_CMD_ALLOC_PIOBUF 0x8f 6730 6731 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 6732 6733 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 6734 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 6735 6736 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 6737 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 6738 /* Handle for allocated push I/O buffer. */ 6739 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 6740 6741 6742 /***********************************/ 6743 /* MC_CMD_FREE_PIOBUF 6744 * Free a push I/O buffer. 6745 */ 6746 #define MC_CMD_FREE_PIOBUF 0x90 6747 6748 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 6749 6750 /* MC_CMD_FREE_PIOBUF_IN msgrequest */ 6751 #define MC_CMD_FREE_PIOBUF_IN_LEN 4 6752 /* Handle for allocated push I/O buffer. */ 6753 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 6754 6755 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 6756 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 6757 6758 6759 /***********************************/ 6760 /* MC_CMD_GET_VI_TLP_PROCESSING 6761 * Get TLP steering and ordering information for a VI. 6762 */ 6763 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 6764 6765 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6766 6767 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 6768 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 6769 /* VI number to get information for. */ 6770 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 6771 6772 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 6773 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 6774 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 6775 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 6776 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 6777 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 6778 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 6779 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 6780 /* Use Relaxed ordering model for TLPs on this VI. */ 6781 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 6782 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 6783 /* Use ID based ordering for TLPs on this VI. */ 6784 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 6785 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 6786 /* Set no snoop bit for TLPs on this VI. */ 6787 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 6788 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 6789 /* Enable TPH for TLPs on this VI. */ 6790 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 6791 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 6792 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 6793 6794 6795 /***********************************/ 6796 /* MC_CMD_SET_VI_TLP_PROCESSING 6797 * Set TLP steering and ordering information for a VI. 6798 */ 6799 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 6800 6801 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6802 6803 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 6804 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 6805 /* VI number to set information for. */ 6806 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 6807 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 6808 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 6809 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 6810 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 6811 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 6812 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 6813 /* Use Relaxed ordering model for TLPs on this VI. */ 6814 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 6815 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 6816 /* Use ID based ordering for TLPs on this VI. */ 6817 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 6818 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 6819 /* Set the no snoop bit for TLPs on this VI. */ 6820 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 6821 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 6822 /* Enable TPH for TLPs on this VI. */ 6823 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 6824 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 6825 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 6826 6827 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 6828 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 6829 6830 6831 /***********************************/ 6832 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS 6833 * Get global PCIe steering and transaction processing configuration. 6834 */ 6835 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 6836 6837 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6838 6839 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 6840 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 6841 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 6842 /* enum: MISC. */ 6843 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 6844 /* enum: IDO. */ 6845 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 6846 /* enum: RO. */ 6847 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 6848 /* enum: TPH Type. */ 6849 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 6850 6851 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 6852 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 6853 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 6854 /* Enum values, see field(s): */ 6855 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 6856 /* Amalgamated TLP info word. */ 6857 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 6858 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 6859 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 6860 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 6861 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 6862 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 6863 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 6864 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 6865 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 6866 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 6867 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 6868 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 6869 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 6870 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 6871 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 6872 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 6873 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 6874 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 6875 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 6876 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 6877 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 6878 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 6879 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 6880 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 6881 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 6882 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 6883 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 6884 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 6885 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 6886 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 6887 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 6888 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 6889 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 6890 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 6891 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 6892 6893 6894 /***********************************/ 6895 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS 6896 * Set global PCIe steering and transaction processing configuration. 6897 */ 6898 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 6899 6900 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6901 6902 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 6903 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 6904 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 6905 /* Enum values, see field(s): */ 6906 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 6907 /* Amalgamated TLP info word. */ 6908 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 6909 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 6910 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 6911 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 6912 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 6913 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 6914 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 6915 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 6916 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 6917 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 6918 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 6919 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 6920 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 6921 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 6922 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 6923 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 6924 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 6925 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 6926 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 6927 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 6928 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 6929 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 6930 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 6931 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 6932 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 6933 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 6934 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 6935 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 6936 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 6937 6938 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 6939 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 6940 6941 6942 /***********************************/ 6943 /* MC_CMD_SATELLITE_DOWNLOAD 6944 * Download a new set of images to the satellite CPUs from the host. 6945 */ 6946 #define MC_CMD_SATELLITE_DOWNLOAD 0x91 6947 6948 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6949 6950 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 6951 * are subtle, and so downloads must proceed in a number of phases. 6952 * 6953 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 6954 * 6955 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 6956 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 6957 * be a checksum (a simple 32-bit sum) of the transferred data. An individual 6958 * download may be aborted using CHUNK_ID_ABORT. 6959 * 6960 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 6961 * similar to PHASE_IMEMS. 6962 * 6963 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 6964 * 6965 * After any error (a requested abort is not considered to be an error) the 6966 * sequence must be restarted from PHASE_RESET. 6967 */ 6968 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 6969 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 6970 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 6971 /* Download phase. (Note: the IDLE phase is used internally and is never valid 6972 * in a command from the host.) 6973 */ 6974 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 6975 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 6976 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 6977 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 6978 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 6979 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 6980 /* Target for download. (These match the blob numbers defined in 6981 * mc_flash_layout.h.) 6982 */ 6983 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 6984 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 6985 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 6986 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 6987 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 6988 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 6989 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 6990 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 6991 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 6992 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 6993 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 6994 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 6995 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 6996 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 6997 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 6998 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 6999 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 7000 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7001 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 7002 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7003 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 7004 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7005 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 7006 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7007 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 7008 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 7009 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 7010 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 7011 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 7012 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 7013 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 7014 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 7015 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 7016 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 7017 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 7018 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 7019 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 7020 /* enum: Last chunk, containing checksum rather than data */ 7021 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 7022 /* enum: Abort download of this item */ 7023 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 7024 /* Length of this chunk in bytes */ 7025 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 7026 /* Data for this chunk */ 7027 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 7028 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 7029 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 7030 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 7031 7032 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 7033 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 7034 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 7035 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 7036 /* Extra status information */ 7037 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 7038 /* enum: Code download OK, completed. */ 7039 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 7040 /* enum: Code download aborted as requested. */ 7041 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 7042 /* enum: Code download OK so far, send next chunk. */ 7043 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 7044 /* enum: Download phases out of sequence */ 7045 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 7046 /* enum: Bad target for this phase */ 7047 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 7048 /* enum: Chunk ID out of sequence */ 7049 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 7050 /* enum: Chunk length zero or too large */ 7051 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 7052 /* enum: Checksum was incorrect */ 7053 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 7054 7055 7056 /***********************************/ 7057 /* MC_CMD_GET_CAPABILITIES 7058 * Get device capabilities. 7059 * 7060 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 7061 * reference inherent device capabilities as opposed to current NVRAM config. 7062 */ 7063 #define MC_CMD_GET_CAPABILITIES 0xbe 7064 7065 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7066 7067 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ 7068 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 7069 7070 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ 7071 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 7072 /* First word of flags. */ 7073 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 7074 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 7075 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 7076 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 7077 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 7078 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14 7079 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1 7080 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 7081 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 7082 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16 7083 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1 7084 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17 7085 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1 7086 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18 7087 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1 7088 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 7089 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 7090 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 7091 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 7092 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 7093 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 7094 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 7095 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 7096 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 7097 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 7098 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 7099 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 7100 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 7101 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 7102 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 7103 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 7104 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 7105 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 7106 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28 7107 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1 7108 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 7109 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 7110 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30 7111 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1 7112 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31 7113 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1 7114 /* RxDPCPU firmware id. */ 7115 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 7116 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 7117 /* enum: Standard RXDP firmware */ 7118 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 7119 /* enum: Low latency RXDP firmware */ 7120 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 7121 /* enum: Packed stream RXDP firmware */ 7122 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2 7123 /* enum: BIST RXDP firmware */ 7124 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a 7125 /* enum: RXDP Test firmware image 1 */ 7126 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 7127 /* enum: RXDP Test firmware image 2 */ 7128 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 7129 /* enum: RXDP Test firmware image 3 */ 7130 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 7131 /* enum: RXDP Test firmware image 4 */ 7132 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 7133 /* enum: RXDP Test firmware image 5 */ 7134 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 7135 /* enum: RXDP Test firmware image 6 */ 7136 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 7137 /* enum: RXDP Test firmware image 7 */ 7138 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 7139 /* enum: RXDP Test firmware image 8 */ 7140 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 7141 /* TxDPCPU firmware id. */ 7142 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 7143 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 7144 /* enum: Standard TXDP firmware */ 7145 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 7146 /* enum: Low latency TXDP firmware */ 7147 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 7148 /* enum: High packet rate TXDP firmware */ 7149 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3 7150 /* enum: BIST TXDP firmware */ 7151 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d 7152 /* enum: TXDP Test firmware image 1 */ 7153 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 7154 /* enum: TXDP Test firmware image 2 */ 7155 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 7156 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 7157 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 7158 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 7159 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 7160 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 7161 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 7162 /* enum: reserved value - do not use (may indicate alternative interpretation 7163 * of REV field in future) 7164 */ 7165 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0 7166 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 7167 * development only) 7168 */ 7169 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 7170 /* enum: RX PD firmware with approximately Siena-compatible behaviour 7171 * (Huntington development only) 7172 */ 7173 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 7174 /* enum: Virtual switching (full feature) RX PD production firmware */ 7175 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 7176 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 7177 * (Huntington development only) 7178 */ 7179 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 7180 /* enum: Low latency RX PD production firmware */ 7181 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 7182 /* enum: Packed stream RX PD production firmware */ 7183 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 7184 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 7185 * tests (Medford development only) 7186 */ 7187 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 7188 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 7189 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 7190 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 7191 * encapsulations (Medford development only) 7192 */ 7193 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 7194 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 7195 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 7196 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 7197 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 7198 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 7199 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 7200 /* enum: reserved value - do not use (may indicate alternative interpretation 7201 * of REV field in future) 7202 */ 7203 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0 7204 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 7205 * development only) 7206 */ 7207 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 7208 /* enum: TX PD firmware with approximately Siena-compatible behaviour 7209 * (Huntington development only) 7210 */ 7211 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 7212 /* enum: Virtual switching (full feature) TX PD production firmware */ 7213 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 7214 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 7215 * (Huntington development only) 7216 */ 7217 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 7218 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 7219 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 7220 * tests (Medford development only) 7221 */ 7222 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 7223 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 7224 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 7225 /* Hardware capabilities of NIC */ 7226 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 7227 /* Licensed capabilities */ 7228 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 7229 7230 7231 /***********************************/ 7232 /* MC_CMD_V2_EXTN 7233 * Encapsulation for a v2 extended command 7234 */ 7235 #define MC_CMD_V2_EXTN 0x7f 7236 7237 /* MC_CMD_V2_EXTN_IN msgrequest */ 7238 #define MC_CMD_V2_EXTN_IN_LEN 4 7239 /* the extended command number */ 7240 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 7241 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 7242 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 7243 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 7244 /* the actual length of the encapsulated command (which is not in the v1 7245 * header) 7246 */ 7247 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 7248 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 7249 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 7250 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 7251 7252 7253 /***********************************/ 7254 /* MC_CMD_TCM_BUCKET_ALLOC 7255 * Allocate a pacer bucket (for qau rp or a snapper test) 7256 */ 7257 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 7258 7259 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7260 7261 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 7262 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 7263 7264 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 7265 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 7266 /* the bucket id */ 7267 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 7268 7269 7270 /***********************************/ 7271 /* MC_CMD_TCM_BUCKET_FREE 7272 * Free a pacer bucket 7273 */ 7274 #define MC_CMD_TCM_BUCKET_FREE 0xb3 7275 7276 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7277 7278 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 7279 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 7280 /* the bucket id */ 7281 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 7282 7283 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 7284 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 7285 7286 7287 /***********************************/ 7288 /* MC_CMD_TCM_BUCKET_INIT 7289 * Initialise pacer bucket with a given rate 7290 */ 7291 #define MC_CMD_TCM_BUCKET_INIT 0xb4 7292 7293 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7294 7295 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 7296 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 7297 /* the bucket id */ 7298 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 7299 /* the rate in mbps */ 7300 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 7301 7302 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ 7303 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 7304 /* the bucket id */ 7305 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 7306 /* the rate in mbps */ 7307 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 7308 /* the desired maximum fill level */ 7309 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 7310 7311 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 7312 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 7313 7314 7315 /***********************************/ 7316 /* MC_CMD_TCM_TXQ_INIT 7317 * Initialise txq in pacer with given options or set options 7318 */ 7319 #define MC_CMD_TCM_TXQ_INIT 0xb5 7320 7321 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7322 7323 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 7324 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 7325 /* the txq id */ 7326 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 7327 /* the static priority associated with the txq */ 7328 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 7329 /* bitmask of the priority queues this txq is inserted into when inserted. */ 7330 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 7331 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 7332 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 7333 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 7334 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 7335 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 7336 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 7337 /* the reaction point (RP) bucket */ 7338 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 7339 /* an already reserved bucket (typically set to bucket associated with outer 7340 * vswitch) 7341 */ 7342 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 7343 /* an already reserved bucket (typically set to bucket associated with inner 7344 * vswitch) 7345 */ 7346 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 7347 /* the min bucket (typically for ETS/minimum bandwidth) */ 7348 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 7349 7350 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ 7351 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 7352 /* the txq id */ 7353 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 7354 /* the static priority associated with the txq */ 7355 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 7356 /* bitmask of the priority queues this txq is inserted into when inserted. */ 7357 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 7358 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 7359 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 7360 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 7361 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 7362 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 7363 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 7364 /* the reaction point (RP) bucket */ 7365 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 7366 /* an already reserved bucket (typically set to bucket associated with outer 7367 * vswitch) 7368 */ 7369 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 7370 /* an already reserved bucket (typically set to bucket associated with inner 7371 * vswitch) 7372 */ 7373 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 7374 /* the min bucket (typically for ETS/minimum bandwidth) */ 7375 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 7376 /* the static priority associated with the txq */ 7377 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 7378 7379 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 7380 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 7381 7382 7383 /***********************************/ 7384 /* MC_CMD_LINK_PIOBUF 7385 * Link a push I/O buffer to a TxQ 7386 */ 7387 #define MC_CMD_LINK_PIOBUF 0x92 7388 7389 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 7390 7391 /* MC_CMD_LINK_PIOBUF_IN msgrequest */ 7392 #define MC_CMD_LINK_PIOBUF_IN_LEN 8 7393 /* Handle for allocated push I/O buffer. */ 7394 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 7395 /* Function Local Instance (VI) number. */ 7396 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 7397 7398 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ 7399 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 7400 7401 7402 /***********************************/ 7403 /* MC_CMD_UNLINK_PIOBUF 7404 * Unlink a push I/O buffer from a TxQ 7405 */ 7406 #define MC_CMD_UNLINK_PIOBUF 0x93 7407 7408 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 7409 7410 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ 7411 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 7412 /* Function Local Instance (VI) number. */ 7413 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 7414 7415 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ 7416 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 7417 7418 7419 /***********************************/ 7420 /* MC_CMD_VSWITCH_ALLOC 7421 * allocate and initialise a v-switch. 7422 */ 7423 #define MC_CMD_VSWITCH_ALLOC 0x94 7424 7425 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7426 7427 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ 7428 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 7429 /* The port to connect to the v-switch's upstream port. */ 7430 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 7431 /* The type of v-switch to create. */ 7432 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 7433 /* enum: VLAN */ 7434 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 7435 /* enum: VEB */ 7436 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 7437 /* enum: VEPA (obsolete) */ 7438 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 7439 /* enum: MUX */ 7440 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4 7441 /* enum: Snapper specific; semantics TBD */ 7442 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5 7443 /* Flags controlling v-port creation */ 7444 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 7445 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 7446 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 7447 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators, 7448 * this must be one or greated, and the attached v-ports must have exactly this 7449 * number of tags. For other v-switch types, this must be zero of greater, and 7450 * is an upper limit on the number of VLAN tags for attached v-ports. An error 7451 * will be returned if existing configuration means we can't support attached 7452 * v-ports with this number of tags. 7453 */ 7454 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 7455 7456 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ 7457 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 7458 7459 7460 /***********************************/ 7461 /* MC_CMD_VSWITCH_FREE 7462 * de-allocate a v-switch. 7463 */ 7464 #define MC_CMD_VSWITCH_FREE 0x95 7465 7466 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7467 7468 /* MC_CMD_VSWITCH_FREE_IN msgrequest */ 7469 #define MC_CMD_VSWITCH_FREE_IN_LEN 4 7470 /* The port to which the v-switch is connected. */ 7471 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 7472 7473 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 7474 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 7475 7476 7477 /***********************************/ 7478 /* MC_CMD_VPORT_ALLOC 7479 * allocate a v-port. 7480 */ 7481 #define MC_CMD_VPORT_ALLOC 0x96 7482 7483 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7484 7485 /* MC_CMD_VPORT_ALLOC_IN msgrequest */ 7486 #define MC_CMD_VPORT_ALLOC_IN_LEN 20 7487 /* The port to which the v-switch is connected. */ 7488 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 7489 /* The type of the new v-port. */ 7490 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 7491 /* enum: VLAN (obsolete) */ 7492 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 7493 /* enum: VEB (obsolete) */ 7494 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 7495 /* enum: VEPA (obsolete) */ 7496 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 7497 /* enum: A normal v-port receives packets which match a specified MAC and/or 7498 * VLAN. 7499 */ 7500 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 7501 /* enum: An expansion v-port packets traffic which don't match any other 7502 * v-port. 7503 */ 7504 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 7505 /* enum: An test v-port receives packets which match any filters installed by 7506 * its downstream components. 7507 */ 7508 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 7509 /* Flags controlling v-port creation */ 7510 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 7511 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 7512 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 7513 /* The number of VLAN tags to insert/remove. An error will be returned if 7514 * incompatible with the number of VLAN tags specified for the upstream 7515 * v-switch. 7516 */ 7517 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 7518 /* The actual VLAN tags to insert/remove */ 7519 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 7520 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 7521 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 7522 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 7523 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 7524 7525 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ 7526 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 7527 /* The handle of the new v-port */ 7528 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 7529 7530 7531 /***********************************/ 7532 /* MC_CMD_VPORT_FREE 7533 * de-allocate a v-port. 7534 */ 7535 #define MC_CMD_VPORT_FREE 0x97 7536 7537 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7538 7539 /* MC_CMD_VPORT_FREE_IN msgrequest */ 7540 #define MC_CMD_VPORT_FREE_IN_LEN 4 7541 /* The handle of the v-port */ 7542 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 7543 7544 /* MC_CMD_VPORT_FREE_OUT msgresponse */ 7545 #define MC_CMD_VPORT_FREE_OUT_LEN 0 7546 7547 7548 /***********************************/ 7549 /* MC_CMD_VADAPTOR_ALLOC 7550 * allocate a v-adaptor. 7551 */ 7552 #define MC_CMD_VADAPTOR_ALLOC 0x98 7553 7554 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7555 7556 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ 7557 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 7558 /* The port to connect to the v-adaptor's port. */ 7559 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 7560 /* Flags controlling v-adaptor creation */ 7561 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 7562 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 7563 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 7564 /* The number of VLAN tags to strip on receive */ 7565 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 7566 /* The number of VLAN tags to transparently insert/remove. */ 7567 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 7568 /* The actual VLAN tags to insert/remove */ 7569 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 7570 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 7571 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 7572 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 7573 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 7574 /* The MAC address to assign to this v-adaptor */ 7575 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 7576 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 7577 /* enum: Derive the MAC address from the upstream port */ 7578 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 7579 7580 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ 7581 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 7582 7583 7584 /***********************************/ 7585 /* MC_CMD_VADAPTOR_FREE 7586 * de-allocate a v-adaptor. 7587 */ 7588 #define MC_CMD_VADAPTOR_FREE 0x99 7589 7590 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7591 7592 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ 7593 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 7594 /* The port to which the v-adaptor is connected. */ 7595 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 7596 7597 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ 7598 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 7599 7600 7601 /***********************************/ 7602 /* MC_CMD_VADAPTOR_SET_MAC 7603 * assign a new MAC address to a v-adaptor. 7604 */ 7605 #define MC_CMD_VADAPTOR_SET_MAC 0x5d 7606 7607 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7608 7609 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ 7610 #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 7611 /* The port to which the v-adaptor is connected. */ 7612 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 7613 /* The new MAC address to assign to this v-adaptor */ 7614 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 7615 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 7616 7617 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ 7618 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 7619 7620 7621 /***********************************/ 7622 /* MC_CMD_VADAPTOR_GET_MAC 7623 * read the MAC address assigned to a v-adaptor. 7624 */ 7625 #define MC_CMD_VADAPTOR_GET_MAC 0x5e 7626 7627 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7628 7629 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ 7630 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 7631 /* The port to which the v-adaptor is connected. */ 7632 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 7633 7634 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ 7635 #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 7636 /* The MAC address assigned to this v-adaptor */ 7637 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 7638 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 7639 7640 7641 /***********************************/ 7642 /* MC_CMD_EVB_PORT_ASSIGN 7643 * assign a port to a PCI function. 7644 */ 7645 #define MC_CMD_EVB_PORT_ASSIGN 0x9a 7646 7647 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7648 7649 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ 7650 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 7651 /* The port to assign. */ 7652 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 7653 /* The target function to modify. */ 7654 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 7655 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 7656 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 7657 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 7658 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 7659 7660 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 7661 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 7662 7663 7664 /***********************************/ 7665 /* MC_CMD_RDWR_A64_REGIONS 7666 * Assign the 64 bit region addresses. 7667 */ 7668 #define MC_CMD_RDWR_A64_REGIONS 0x9b 7669 7670 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7671 7672 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 7673 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 7674 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 7675 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 7676 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 7677 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 7678 /* Write enable bits 0-3, set to write, clear to read. */ 7679 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 7680 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 7681 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 7682 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 7683 7684 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 7685 * regardless of state of write bits in the request. 7686 */ 7687 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 7688 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 7689 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 7690 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 7691 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 7692 7693 7694 /***********************************/ 7695 /* MC_CMD_ONLOAD_STACK_ALLOC 7696 * Allocate an Onload stack ID. 7697 */ 7698 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 7699 7700 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 7701 7702 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 7703 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 7704 /* The handle of the owning upstream port */ 7705 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 7706 7707 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 7708 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 7709 /* The handle of the new Onload stack */ 7710 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 7711 7712 7713 /***********************************/ 7714 /* MC_CMD_ONLOAD_STACK_FREE 7715 * Free an Onload stack ID. 7716 */ 7717 #define MC_CMD_ONLOAD_STACK_FREE 0x9d 7718 7719 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 7720 7721 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 7722 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 7723 /* The handle of the Onload stack */ 7724 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 7725 7726 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 7727 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 7728 7729 7730 /***********************************/ 7731 /* MC_CMD_RSS_CONTEXT_ALLOC 7732 * Allocate an RSS context. 7733 */ 7734 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e 7735 7736 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7737 7738 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ 7739 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 7740 /* The handle of the owning upstream port */ 7741 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 7742 /* The type of context to allocate */ 7743 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 7744 /* enum: Allocate a context for exclusive use. The key and indirection table 7745 * must be explicitly configured. 7746 */ 7747 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 7748 /* enum: Allocate a context for shared use; this will spread across a range of 7749 * queues, but the key and indirection table are pre-configured and may not be 7750 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 7751 */ 7752 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 7753 /* Number of queues spanned by this context, in the range 1-64; valid offsets 7754 * in the indirection table will be in the range 0 to NUM_QUEUES-1. 7755 */ 7756 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 7757 7758 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ 7759 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 7760 /* The handle of the new RSS context. This should be considered opaque to the 7761 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 7762 * handle. 7763 */ 7764 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 7765 /* enum: guaranteed invalid RSS context handle value */ 7766 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff 7767 7768 7769 /***********************************/ 7770 /* MC_CMD_RSS_CONTEXT_FREE 7771 * Free an RSS context. 7772 */ 7773 #define MC_CMD_RSS_CONTEXT_FREE 0x9f 7774 7775 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7776 7777 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ 7778 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 7779 /* The handle of the RSS context */ 7780 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 7781 7782 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ 7783 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 7784 7785 7786 /***********************************/ 7787 /* MC_CMD_RSS_CONTEXT_SET_KEY 7788 * Set the Toeplitz hash key for an RSS context. 7789 */ 7790 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 7791 7792 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7793 7794 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ 7795 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 7796 /* The handle of the RSS context */ 7797 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 7798 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 7799 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 7800 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 7801 7802 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ 7803 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 7804 7805 7806 /***********************************/ 7807 /* MC_CMD_RSS_CONTEXT_GET_KEY 7808 * Get the Toeplitz hash key for an RSS context. 7809 */ 7810 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 7811 7812 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7813 7814 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ 7815 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 7816 /* The handle of the RSS context */ 7817 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 7818 7819 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ 7820 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 7821 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 7822 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 7823 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 7824 7825 7826 /***********************************/ 7827 /* MC_CMD_RSS_CONTEXT_SET_TABLE 7828 * Set the indirection table for an RSS context. 7829 */ 7830 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 7831 7832 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7833 7834 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ 7835 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 7836 /* The handle of the RSS context */ 7837 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 7838 /* The 128-byte indirection table (1 byte per entry) */ 7839 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 7840 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 7841 7842 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ 7843 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 7844 7845 7846 /***********************************/ 7847 /* MC_CMD_RSS_CONTEXT_GET_TABLE 7848 * Get the indirection table for an RSS context. 7849 */ 7850 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 7851 7852 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7853 7854 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ 7855 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 7856 /* The handle of the RSS context */ 7857 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 7858 7859 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ 7860 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 7861 /* The 128-byte indirection table (1 byte per entry) */ 7862 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 7863 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 7864 7865 7866 /***********************************/ 7867 /* MC_CMD_RSS_CONTEXT_SET_FLAGS 7868 * Set various control flags for an RSS context. 7869 */ 7870 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 7871 7872 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7873 7874 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ 7875 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 7876 /* The handle of the RSS context */ 7877 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 7878 /* Hash control flags. The _EN bits are always supported. The _MODE bits only 7879 * work when the firmware reports ADDITIONAL_RSS_MODES in 7880 * MC_CMD_GET_CAPABILITIES and override the _EN bits if any of them are not 0. 7881 * See the RSS_MODE structure for the meaning of the mode bits. 7882 */ 7883 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 7884 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 7885 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 7886 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 7887 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 7888 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 7889 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 7890 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 7891 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 7892 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4 7893 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4 7894 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8 7895 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4 7896 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12 7897 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4 7898 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16 7899 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4 7900 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20 7901 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4 7902 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24 7903 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4 7904 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28 7905 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4 7906 7907 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ 7908 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 7909 7910 7911 /***********************************/ 7912 /* MC_CMD_RSS_CONTEXT_GET_FLAGS 7913 * Get various control flags for an RSS context. 7914 */ 7915 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 7916 7917 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7918 7919 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ 7920 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 7921 /* The handle of the RSS context */ 7922 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 7923 7924 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ 7925 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 7926 /* Hash control flags. If any _MODE bits are non-zero (which will only be true 7927 * when the firmware reports ADDITIONAL_RSS_MODES) then the _EN bits should be 7928 * disregarded (but are guaranteed to be consistent with the _MODE bits if 7929 * RSS_CONTEXT_SET_FLAGS has never been called for this context since it was 7930 * allocated). 7931 */ 7932 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 7933 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 7934 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 7935 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 7936 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 7937 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 7938 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 7939 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 7940 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 7941 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4 7942 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4 7943 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8 7944 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4 7945 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12 7946 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4 7947 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16 7948 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4 7949 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20 7950 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4 7951 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24 7952 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4 7953 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 7954 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 7955 7956 7957 /***********************************/ 7958 /* MC_CMD_DOT1P_MAPPING_ALLOC 7959 * Allocate a .1p mapping. 7960 */ 7961 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 7962 7963 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7964 7965 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 7966 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 7967 /* The handle of the owning upstream port */ 7968 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 7969 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed 7970 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 7971 * referenced RSS contexts must span no more than this number. 7972 */ 7973 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 7974 7975 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 7976 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 7977 /* The handle of the new .1p mapping. This should be considered opaque to the 7978 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 7979 * handle. 7980 */ 7981 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 7982 /* enum: guaranteed invalid .1p mapping handle value */ 7983 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff 7984 7985 7986 /***********************************/ 7987 /* MC_CMD_DOT1P_MAPPING_FREE 7988 * Free a .1p mapping. 7989 */ 7990 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 7991 7992 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7993 7994 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 7995 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 7996 /* The handle of the .1p mapping */ 7997 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 7998 7999 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 8000 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 8001 8002 8003 /***********************************/ 8004 /* MC_CMD_DOT1P_MAPPING_SET_TABLE 8005 * Set the mapping table for a .1p mapping. 8006 */ 8007 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 8008 8009 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8010 8011 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 8012 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 8013 /* The handle of the .1p mapping */ 8014 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 8015 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 8016 * handle) 8017 */ 8018 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 8019 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 8020 8021 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 8022 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 8023 8024 8025 /***********************************/ 8026 /* MC_CMD_DOT1P_MAPPING_GET_TABLE 8027 * Get the mapping table for a .1p mapping. 8028 */ 8029 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 8030 8031 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8032 8033 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 8034 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 8035 /* The handle of the .1p mapping */ 8036 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 8037 8038 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 8039 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 8040 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 8041 * handle) 8042 */ 8043 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 8044 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 8045 8046 8047 /***********************************/ 8048 /* MC_CMD_GET_VECTOR_CFG 8049 * Get Interrupt Vector config for this PF. 8050 */ 8051 #define MC_CMD_GET_VECTOR_CFG 0xbf 8052 8053 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8054 8055 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 8056 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 8057 8058 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 8059 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 8060 /* Base absolute interrupt vector number. */ 8061 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 8062 /* Number of interrupt vectors allocate to this PF. */ 8063 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 8064 /* Number of interrupt vectors to allocate per VF. */ 8065 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 8066 8067 8068 /***********************************/ 8069 /* MC_CMD_SET_VECTOR_CFG 8070 * Set Interrupt Vector config for this PF. 8071 */ 8072 #define MC_CMD_SET_VECTOR_CFG 0xc0 8073 8074 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8075 8076 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 8077 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 8078 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 8079 * let the system find a suitable base. 8080 */ 8081 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 8082 /* Number of interrupt vectors allocate to this PF. */ 8083 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 8084 /* Number of interrupt vectors to allocate per VF. */ 8085 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 8086 8087 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 8088 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 8089 8090 8091 /***********************************/ 8092 /* MC_CMD_VPORT_ADD_MAC_ADDRESS 8093 * Add a MAC address to a v-port 8094 */ 8095 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 8096 8097 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8098 8099 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ 8100 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 8101 /* The handle of the v-port */ 8102 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 8103 /* MAC address to add */ 8104 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 8105 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 8106 8107 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ 8108 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 8109 8110 8111 /***********************************/ 8112 /* MC_CMD_VPORT_DEL_MAC_ADDRESS 8113 * Delete a MAC address from a v-port 8114 */ 8115 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 8116 8117 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8118 8119 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ 8120 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 8121 /* The handle of the v-port */ 8122 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 8123 /* MAC address to add */ 8124 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 8125 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 8126 8127 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ 8128 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 8129 8130 8131 /***********************************/ 8132 /* MC_CMD_VPORT_GET_MAC_ADDRESSES 8133 * Delete a MAC address from a v-port 8134 */ 8135 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa 8136 8137 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8138 8139 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ 8140 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 8141 /* The handle of the v-port */ 8142 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 8143 8144 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ 8145 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 8146 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 8147 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) 8148 /* The number of MAC addresses returned */ 8149 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 8150 /* Array of MAC addresses */ 8151 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 8152 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 8153 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 8154 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 8155 8156 8157 /***********************************/ 8158 /* MC_CMD_DUMP_BUFTBL_ENTRIES 8159 * Dump buffer table entries, mainly for command client debug use. Dumps 8160 * absolute entries, and does not use chunk handles. All entries must be in 8161 * range, and used for q page mapping, Although the latter restriction may be 8162 * lifted in future. 8163 */ 8164 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 8165 8166 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8167 8168 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 8169 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 8170 /* Index of the first buffer table entry. */ 8171 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 8172 /* Number of buffer table entries to dump. */ 8173 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 8174 8175 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 8176 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 8177 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 8178 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 8179 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ 8180 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 8181 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 8182 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 8183 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 8184 8185 8186 /***********************************/ 8187 /* MC_CMD_SET_RXDP_CONFIG 8188 * Set global RXDP configuration settings 8189 */ 8190 #define MC_CMD_SET_RXDP_CONFIG 0xc1 8191 8192 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8193 8194 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 8195 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 8196 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 8197 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 8198 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 8199 8200 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 8201 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 8202 8203 8204 /***********************************/ 8205 /* MC_CMD_GET_RXDP_CONFIG 8206 * Get global RXDP configuration settings 8207 */ 8208 #define MC_CMD_GET_RXDP_CONFIG 0xc2 8209 8210 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8211 8212 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 8213 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 8214 8215 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 8216 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 8217 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 8218 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 8219 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 8220 8221 8222 /***********************************/ 8223 /* MC_CMD_GET_CLOCK 8224 * Return the system and PDCPU clock frequencies. 8225 */ 8226 #define MC_CMD_GET_CLOCK 0xac 8227 8228 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8229 8230 /* MC_CMD_GET_CLOCK_IN msgrequest */ 8231 #define MC_CMD_GET_CLOCK_IN_LEN 0 8232 8233 /* MC_CMD_GET_CLOCK_OUT msgresponse */ 8234 #define MC_CMD_GET_CLOCK_OUT_LEN 8 8235 /* System frequency, MHz */ 8236 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 8237 /* DPCPU frequency, MHz */ 8238 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 8239 8240 8241 /***********************************/ 8242 /* MC_CMD_SET_CLOCK 8243 * Control the system and DPCPU clock frequencies. Changes are lost reboot. 8244 */ 8245 #define MC_CMD_SET_CLOCK 0xad 8246 8247 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8248 8249 /* MC_CMD_SET_CLOCK_IN msgrequest */ 8250 #define MC_CMD_SET_CLOCK_IN_LEN 28 8251 /* Requested frequency in MHz for system clock domain */ 8252 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 8253 /* enum: Leave the system clock domain frequency unchanged */ 8254 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 8255 /* Requested frequency in MHz for inter-core clock domain */ 8256 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 8257 /* enum: Leave the inter-core clock domain frequency unchanged */ 8258 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 8259 /* Requested frequency in MHz for DPCPU clock domain */ 8260 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 8261 /* enum: Leave the DPCPU clock domain frequency unchanged */ 8262 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 8263 /* Requested frequency in MHz for PCS clock domain */ 8264 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 8265 /* enum: Leave the PCS clock domain frequency unchanged */ 8266 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 8267 /* Requested frequency in MHz for MC clock domain */ 8268 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 8269 /* enum: Leave the MC clock domain frequency unchanged */ 8270 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 8271 /* Requested frequency in MHz for rmon clock domain */ 8272 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 8273 /* enum: Leave the rmon clock domain frequency unchanged */ 8274 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 8275 /* Requested frequency in MHz for vswitch clock domain */ 8276 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 8277 /* enum: Leave the vswitch clock domain frequency unchanged */ 8278 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 8279 8280 /* MC_CMD_SET_CLOCK_OUT msgresponse */ 8281 #define MC_CMD_SET_CLOCK_OUT_LEN 28 8282 /* Resulting system frequency in MHz */ 8283 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 8284 /* enum: The system clock domain doesn't exist */ 8285 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 8286 /* Resulting inter-core frequency in MHz */ 8287 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 8288 /* enum: The inter-core clock domain doesn't exist / isn't used */ 8289 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 8290 /* Resulting DPCPU frequency in MHz */ 8291 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 8292 /* enum: The dpcpu clock domain doesn't exist */ 8293 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 8294 /* Resulting PCS frequency in MHz */ 8295 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 8296 /* enum: The PCS clock domain doesn't exist / isn't controlled */ 8297 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 8298 /* Resulting MC frequency in MHz */ 8299 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 8300 /* enum: The MC clock domain doesn't exist / isn't controlled */ 8301 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 8302 /* Resulting rmon frequency in MHz */ 8303 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 8304 /* enum: The rmon clock domain doesn't exist / isn't controlled */ 8305 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 8306 /* Resulting vswitch frequency in MHz */ 8307 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 8308 /* enum: The vswitch clock domain doesn't exist / isn't controlled */ 8309 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 8310 8311 8312 /***********************************/ 8313 /* MC_CMD_DPCPU_RPC 8314 * Send an arbitrary DPCPU message. 8315 */ 8316 #define MC_CMD_DPCPU_RPC 0xae 8317 8318 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8319 8320 /* MC_CMD_DPCPU_RPC_IN msgrequest */ 8321 #define MC_CMD_DPCPU_RPC_IN_LEN 36 8322 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 8323 /* enum: RxDPCPU0 */ 8324 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 8325 /* enum: TxDPCPU0 */ 8326 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 8327 /* enum: TxDPCPU1 */ 8328 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 8329 /* enum: RxDPCPU1 (Medford only) */ 8330 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 8331 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of 8332 * DPCPU_RX0) 8333 */ 8334 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 8335 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of 8336 * DPCPU_TX0) 8337 */ 8338 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 8339 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 8340 * initialised to zero 8341 */ 8342 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 8343 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 8344 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 8345 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 8346 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 8347 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 8348 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 8349 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 8350 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 8351 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 8352 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 8353 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 8354 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 8355 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 8356 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 8357 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 8358 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 8359 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 8360 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 8361 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 8362 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 8363 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 8364 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 8365 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 8366 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 8367 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 8368 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 8369 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 8370 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 8371 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 8372 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 8373 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 8374 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 8375 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 8376 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 8377 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 8378 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 8379 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 8380 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 8381 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 8382 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 8383 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 8384 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 8385 /* Register data to write. Only valid in write/write-read. */ 8386 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 8387 /* Register address. */ 8388 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 8389 8390 /* MC_CMD_DPCPU_RPC_OUT msgresponse */ 8391 #define MC_CMD_DPCPU_RPC_OUT_LEN 36 8392 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 8393 /* DATA */ 8394 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 8395 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 8396 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 8397 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 8398 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 8399 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 8400 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 8401 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 8402 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 8403 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 8404 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 8405 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 8406 8407 8408 /***********************************/ 8409 /* MC_CMD_TRIGGER_INTERRUPT 8410 * Trigger an interrupt by prodding the BIU. 8411 */ 8412 #define MC_CMD_TRIGGER_INTERRUPT 0xe3 8413 8414 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8415 8416 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ 8417 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 8418 /* Interrupt level relative to base for function. */ 8419 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 8420 8421 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 8422 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 8423 8424 8425 /***********************************/ 8426 /* MC_CMD_SHMBOOT_OP 8427 * Special operations to support (for now) shmboot. 8428 */ 8429 #define MC_CMD_SHMBOOT_OP 0xe6 8430 8431 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8432 8433 /* MC_CMD_SHMBOOT_OP_IN msgrequest */ 8434 #define MC_CMD_SHMBOOT_OP_IN_LEN 4 8435 /* Identifies the operation to perform */ 8436 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 8437 /* enum: Copy slave_data section to the slave core. (Greenport only) */ 8438 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 8439 8440 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */ 8441 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0 8442 8443 8444 /***********************************/ 8445 /* MC_CMD_CAP_BLK_READ 8446 * Read multiple 64bit words from capture block memory 8447 */ 8448 #define MC_CMD_CAP_BLK_READ 0xe7 8449 8450 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8451 8452 /* MC_CMD_CAP_BLK_READ_IN msgrequest */ 8453 #define MC_CMD_CAP_BLK_READ_IN_LEN 12 8454 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 8455 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 8456 #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 8457 8458 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */ 8459 #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 8460 #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 8461 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) 8462 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 8463 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 8464 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 8465 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 8466 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 8467 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 8468 8469 8470 /***********************************/ 8471 /* MC_CMD_DUMP_DO 8472 * Take a dump of the DUT state 8473 */ 8474 #define MC_CMD_DUMP_DO 0xe8 8475 8476 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8477 8478 /* MC_CMD_DUMP_DO_IN msgrequest */ 8479 #define MC_CMD_DUMP_DO_IN_LEN 52 8480 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 8481 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 8482 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ 8483 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ 8484 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 8485 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ 8486 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ 8487 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ 8488 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ 8489 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 8490 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 8491 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 8492 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 8493 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 8494 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ 8495 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 8496 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 8497 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ 8498 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 8499 /* enum: The uart port this command was received over (if using a uart 8500 * transport) 8501 */ 8502 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff 8503 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 8504 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 8505 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ 8506 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ 8507 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 8508 /* Enum values, see field(s): */ 8509 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 8510 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 8511 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 8512 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 8513 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 8514 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 8515 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 8516 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 8517 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 8518 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 8519 8520 /* MC_CMD_DUMP_DO_OUT msgresponse */ 8521 #define MC_CMD_DUMP_DO_OUT_LEN 4 8522 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 8523 8524 8525 /***********************************/ 8526 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED 8527 * Configure unsolicited dumps 8528 */ 8529 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 8530 8531 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8532 8533 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ 8534 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 8535 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 8536 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 8537 /* Enum values, see field(s): */ 8538 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ 8539 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 8540 /* Enum values, see field(s): */ 8541 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 8542 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 8543 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 8544 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 8545 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 8546 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 8547 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 8548 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 8549 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 8550 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 8551 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 8552 /* Enum values, see field(s): */ 8553 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ 8554 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 8555 /* Enum values, see field(s): */ 8556 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 8557 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 8558 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 8559 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 8560 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 8561 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 8562 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 8563 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 8564 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 8565 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 8566 8567 8568 /***********************************/ 8569 /* MC_CMD_SET_PSU 8570 * Adjusts power supply parameters. This is a warranty-voiding operation. 8571 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 8572 * the parameter is out of range. 8573 */ 8574 #define MC_CMD_SET_PSU 0xea 8575 8576 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8577 8578 /* MC_CMD_SET_PSU_IN msgrequest */ 8579 #define MC_CMD_SET_PSU_IN_LEN 12 8580 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 8581 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 8582 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 8583 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 8584 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 8585 /* desired value, eg voltage in mV */ 8586 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 8587 8588 /* MC_CMD_SET_PSU_OUT msgresponse */ 8589 #define MC_CMD_SET_PSU_OUT_LEN 0 8590 8591 8592 /***********************************/ 8593 /* MC_CMD_GET_FUNCTION_INFO 8594 * Get function information. PF and VF number. 8595 */ 8596 #define MC_CMD_GET_FUNCTION_INFO 0xec 8597 8598 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8599 8600 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ 8601 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 8602 8603 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ 8604 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 8605 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 8606 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 8607 8608 8609 /***********************************/ 8610 /* MC_CMD_ENABLE_OFFLINE_BIST 8611 * Enters offline BIST mode. All queues are torn down, chip enters quiescent 8612 * mode, calling function gets exclusive MCDI ownership. The only way out is 8613 * reboot. 8614 */ 8615 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed 8616 8617 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8618 8619 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 8620 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 8621 8622 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ 8623 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 8624 8625 8626 /***********************************/ 8627 /* MC_CMD_UART_SEND_DATA 8628 * Send checksummed[sic] block of data over the uart. Response is a placeholder 8629 * should we wish to make this reliable; currently requests are fire-and- 8630 * forget. 8631 */ 8632 #define MC_CMD_UART_SEND_DATA 0xee 8633 8634 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8635 8636 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */ 8637 #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 8638 #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 8639 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) 8640 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ 8641 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 8642 /* Offset at which to write the data */ 8643 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 8644 /* Length of data */ 8645 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 8646 /* Reserved for future use */ 8647 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 8648 #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 8649 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 8650 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 8651 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 8652 8653 /* MC_CMD_UART_SEND_DATA_IN msgresponse */ 8654 #define MC_CMD_UART_SEND_DATA_IN_LEN 0 8655 8656 8657 /***********************************/ 8658 /* MC_CMD_UART_RECV_DATA 8659 * Request checksummed[sic] block of data over the uart. Only a placeholder, 8660 * subject to change and not currently implemented. 8661 */ 8662 #define MC_CMD_UART_RECV_DATA 0xef 8663 8664 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8665 8666 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */ 8667 #define MC_CMD_UART_RECV_DATA_OUT_LEN 16 8668 /* CRC32 over OFFSET, LENGTH, RESERVED */ 8669 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 8670 /* Offset from which to read the data */ 8671 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 8672 /* Length of data */ 8673 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 8674 /* Reserved for future use */ 8675 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 8676 8677 /* MC_CMD_UART_RECV_DATA_IN msgresponse */ 8678 #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 8679 #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 8680 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) 8681 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ 8682 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 8683 /* Offset at which to write the data */ 8684 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 8685 /* Length of data */ 8686 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 8687 /* Reserved for future use */ 8688 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 8689 #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 8690 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 8691 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 8692 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 8693 8694 8695 /***********************************/ 8696 /* MC_CMD_READ_FUSES 8697 * Read data programmed into the device One-Time-Programmable (OTP) Fuses 8698 */ 8699 #define MC_CMD_READ_FUSES 0xf0 8700 8701 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8702 8703 /* MC_CMD_READ_FUSES_IN msgrequest */ 8704 #define MC_CMD_READ_FUSES_IN_LEN 8 8705 /* Offset in OTP to read */ 8706 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 8707 /* Length of data to read in bytes */ 8708 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 8709 8710 /* MC_CMD_READ_FUSES_OUT msgresponse */ 8711 #define MC_CMD_READ_FUSES_OUT_LENMIN 4 8712 #define MC_CMD_READ_FUSES_OUT_LENMAX 252 8713 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 8714 /* Length of returned OTP data in bytes */ 8715 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 8716 /* Returned data */ 8717 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 8718 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 8719 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 8720 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 8721 8722 8723 /***********************************/ 8724 /* MC_CMD_KR_TUNE 8725 * Get or set KR Serdes RXEQ and TX Driver settings 8726 */ 8727 #define MC_CMD_KR_TUNE 0xf1 8728 8729 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8730 8731 /* MC_CMD_KR_TUNE_IN msgrequest */ 8732 #define MC_CMD_KR_TUNE_IN_LENMIN 4 8733 #define MC_CMD_KR_TUNE_IN_LENMAX 252 8734 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) 8735 /* Requested operation */ 8736 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 8737 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 8738 /* enum: Get current RXEQ settings */ 8739 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 8740 /* enum: Override RXEQ settings */ 8741 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 8742 /* enum: Get current TX Driver settings */ 8743 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 8744 /* enum: Override TX Driver settings */ 8745 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 8746 /* enum: Force KR Serdes reset / recalibration */ 8747 #define MC_CMD_KR_TUNE_IN_RECAL 0x4 8748 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid 8749 * signal. 8750 */ 8751 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 8752 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The 8753 * caller should call this command repeatedly after starting eye plot, until no 8754 * more data is returned. 8755 */ 8756 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 8757 /* enum: Read Figure Of Merit (eye quality, higher is better). */ 8758 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7 8759 /* Align the arguments to 32 bits */ 8760 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 8761 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 8762 /* Arguments specific to the operation */ 8763 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 8764 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 8765 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 8766 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 8767 8768 /* MC_CMD_KR_TUNE_OUT msgresponse */ 8769 #define MC_CMD_KR_TUNE_OUT_LEN 0 8770 8771 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ 8772 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 8773 /* Requested operation */ 8774 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 8775 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 8776 /* Align the arguments to 32 bits */ 8777 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 8778 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 8779 8780 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ 8781 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 8782 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 8783 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 8784 /* RXEQ Parameter */ 8785 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 8786 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 8787 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 8788 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 8789 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 8790 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 8791 /* enum: Attenuation (0-15, TBD for Medford) */ 8792 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 8793 /* enum: CTLE Boost (0-15, TBD for Medford) */ 8794 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 8795 /* enum: Edge DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive, TBD 8796 * for Medford) 8797 */ 8798 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 8799 /* enum: Edge DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive, TBD for 8800 * Medford) 8801 */ 8802 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 8803 /* enum: Edge DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive, TBD for 8804 * Medford) 8805 */ 8806 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 8807 /* enum: Edge DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive, TBD for 8808 * Medford) 8809 */ 8810 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 8811 /* enum: Edge DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive, TBD for 8812 * Medford) 8813 */ 8814 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 8815 /* enum: Edge DFE DLEV (TBD for Medford) */ 8816 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 8817 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 8818 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 8819 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 8820 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 8821 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 8822 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 8823 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 8824 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 8825 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 8826 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 8827 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 8828 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 8829 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 8830 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 8831 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 8832 8833 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ 8834 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 8835 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 8836 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 8837 /* Requested operation */ 8838 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 8839 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 8840 /* Align the arguments to 32 bits */ 8841 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 8842 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 8843 /* RXEQ Parameter */ 8844 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 8845 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 8846 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 8847 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 8848 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 8849 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 8850 /* Enum values, see field(s): */ 8851 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ 8852 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 8853 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 8854 /* Enum values, see field(s): */ 8855 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 8856 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 8857 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 8858 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 8859 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 8860 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 8861 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 8862 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 8863 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 8864 8865 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ 8866 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 8867 8868 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ 8869 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 8870 /* Requested operation */ 8871 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 8872 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 8873 /* Align the arguments to 32 bits */ 8874 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 8875 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 8876 8877 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ 8878 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 8879 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 8880 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 8881 /* TXEQ Parameter */ 8882 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 8883 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 8884 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 8885 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 8886 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 8887 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 8888 /* enum: TX Amplitude */ 8889 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 8890 /* enum: De-Emphasis Tap1 Magnitude (0-7) */ 8891 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 8892 /* enum: De-Emphasis Tap1 Fine */ 8893 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 8894 /* enum: De-Emphasis Tap2 Magnitude (0-6) */ 8895 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 8896 /* enum: De-Emphasis Tap2 Fine */ 8897 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 8898 /* enum: Pre-Emphasis Magnitude */ 8899 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 8900 /* enum: Pre-Emphasis Fine */ 8901 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 8902 /* enum: TX Slew Rate Coarse control */ 8903 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 8904 /* enum: TX Slew Rate Fine control */ 8905 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 8906 /* enum: TX Termination Impedance control */ 8907 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 8908 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 8909 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 8910 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ 8911 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ 8912 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ 8913 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ 8914 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 8915 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 8916 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 8917 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 8918 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 8919 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 8920 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 8921 8922 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ 8923 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 8924 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 8925 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) 8926 /* Requested operation */ 8927 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 8928 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 8929 /* Align the arguments to 32 bits */ 8930 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 8931 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 8932 /* TXEQ Parameter */ 8933 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 8934 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 8935 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 8936 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 8937 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 8938 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 8939 /* Enum values, see field(s): */ 8940 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ 8941 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 8942 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 8943 /* Enum values, see field(s): */ 8944 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ 8945 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 8946 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 8947 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 8948 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 8949 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 8950 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 8951 8952 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ 8953 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 8954 8955 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ 8956 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 8957 /* Requested operation */ 8958 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 8959 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 8960 /* Align the arguments to 32 bits */ 8961 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 8962 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 8963 8964 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ 8965 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 8966 8967 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ 8968 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 8969 /* Requested operation */ 8970 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 8971 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 8972 /* Align the arguments to 32 bits */ 8973 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 8974 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 8975 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 8976 8977 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ 8978 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 8979 8980 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ 8981 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 8982 /* Requested operation */ 8983 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 8984 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 8985 /* Align the arguments to 32 bits */ 8986 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 8987 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 8988 8989 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 8990 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 8991 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 8992 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 8993 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 8994 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 8995 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 8996 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 8997 8998 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */ 8999 #define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8 9000 /* Requested operation */ 9001 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0 9002 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1 9003 /* Align the arguments to 32 bits */ 9004 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1 9005 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3 9006 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4 9007 9008 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */ 9009 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4 9010 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0 9011 9012 9013 /***********************************/ 9014 /* MC_CMD_PCIE_TUNE 9015 * Get or set PCIE Serdes RXEQ and TX Driver settings 9016 */ 9017 #define MC_CMD_PCIE_TUNE 0xf2 9018 9019 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9020 9021 /* MC_CMD_PCIE_TUNE_IN msgrequest */ 9022 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 9023 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 9024 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 9025 /* Requested operation */ 9026 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 9027 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 9028 /* enum: Get current RXEQ settings */ 9029 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 9030 /* enum: Override RXEQ settings */ 9031 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 9032 /* enum: Get current TX Driver settings */ 9033 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 9034 /* enum: Override TX Driver settings */ 9035 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 9036 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ 9037 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 9038 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The 9039 * caller should call this command repeatedly after starting eye plot, until no 9040 * more data is returned. 9041 */ 9042 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 9043 /* Align the arguments to 32 bits */ 9044 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 9045 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 9046 /* Arguments specific to the operation */ 9047 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 9048 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 9049 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 9050 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 9051 9052 /* MC_CMD_PCIE_TUNE_OUT msgresponse */ 9053 #define MC_CMD_PCIE_TUNE_OUT_LEN 0 9054 9055 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 9056 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 9057 /* Requested operation */ 9058 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 9059 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 9060 /* Align the arguments to 32 bits */ 9061 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 9062 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 9063 9064 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 9065 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 9066 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 9067 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 9068 /* RXEQ Parameter */ 9069 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 9070 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 9071 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 9072 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 9073 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 9074 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 9075 /* enum: Attenuation (0-15) */ 9076 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 9077 /* enum: CTLE Boost (0-15) */ 9078 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 9079 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 9080 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 9081 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 9082 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 9083 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 9084 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 9085 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 9086 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 9087 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 9088 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 9089 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 9090 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 4 9091 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 9092 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 9093 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 9094 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 9095 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 9096 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 9097 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 9098 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 9099 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x8 /* enum */ 9100 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 9101 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 12 9102 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 9103 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 9104 9105 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 9106 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 9107 /* Requested operation */ 9108 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 9109 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 9110 /* Align the arguments to 32 bits */ 9111 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 9112 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 9113 9114 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 9115 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 9116 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 9117 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 9118 /* RXEQ Parameter */ 9119 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 9120 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 9121 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 9122 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 9123 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 9124 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 9125 /* enum: TxMargin (PIPE) */ 9126 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 9127 /* enum: TxSwing (PIPE) */ 9128 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 9129 /* enum: De-emphasis coefficient C(-1) (PIPE) */ 9130 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 9131 /* enum: De-emphasis coefficient C(0) (PIPE) */ 9132 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 9133 /* enum: De-emphasis coefficient C(+1) (PIPE) */ 9134 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 9135 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 9136 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 9137 /* Enum values, see field(s): */ 9138 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 9139 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 9140 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 9141 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 9142 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 9143 9144 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ 9145 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 9146 /* Requested operation */ 9147 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 9148 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 9149 /* Align the arguments to 32 bits */ 9150 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 9151 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 9152 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 9153 9154 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ 9155 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 9156 9157 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ 9158 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 9159 /* Requested operation */ 9160 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 9161 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 9162 /* Align the arguments to 32 bits */ 9163 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 9164 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 9165 9166 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 9167 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 9168 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 9169 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 9170 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 9171 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 9172 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 9173 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 9174 9175 9176 /***********************************/ 9177 /* MC_CMD_LICENSING 9178 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 9179 */ 9180 #define MC_CMD_LICENSING 0xf3 9181 9182 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9183 9184 /* MC_CMD_LICENSING_IN msgrequest */ 9185 #define MC_CMD_LICENSING_IN_LEN 4 9186 /* identifies the type of operation requested */ 9187 #define MC_CMD_LICENSING_IN_OP_OFST 0 9188 /* enum: re-read and apply licenses after a license key partition update; note 9189 * that this operation returns a zero-length response 9190 */ 9191 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 9192 /* enum: report counts of installed licenses */ 9193 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 9194 9195 /* MC_CMD_LICENSING_OUT msgresponse */ 9196 #define MC_CMD_LICENSING_OUT_LEN 28 9197 /* count of application keys which are valid */ 9198 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 9199 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with 9200 * MC_CMD_FC_OP_LICENSE) 9201 */ 9202 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 9203 /* count of application keys which are invalid due to being blacklisted */ 9204 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 9205 /* count of application keys which are invalid due to being unverifiable */ 9206 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 9207 /* count of application keys which are invalid due to being for the wrong node 9208 */ 9209 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 9210 /* licensing state (for diagnostics; the exact meaning of the bits in this 9211 * field are private to the firmware) 9212 */ 9213 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 9214 /* licensing subsystem self-test report (for manftest) */ 9215 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 9216 /* enum: licensing subsystem self-test failed */ 9217 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 9218 /* enum: licensing subsystem self-test passed */ 9219 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 9220 9221 9222 /***********************************/ 9223 /* MC_CMD_MC2MC_PROXY 9224 * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 9225 * This will fail on a single-core system. 9226 */ 9227 #define MC_CMD_MC2MC_PROXY 0xf4 9228 9229 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9230 9231 /* MC_CMD_MC2MC_PROXY_IN msgrequest */ 9232 #define MC_CMD_MC2MC_PROXY_IN_LEN 0 9233 9234 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ 9235 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 9236 9237 9238 /***********************************/ 9239 /* MC_CMD_GET_LICENSED_APP_STATE 9240 * Query the state of an individual licensed application. (Note that the actual 9241 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation 9242 * or a reboot of the MC.) 9243 */ 9244 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 9245 9246 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9247 9248 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ 9249 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 9250 /* application ID to query (LICENSED_APP_ID_xxx) */ 9251 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 9252 9253 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ 9254 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 9255 /* state of this application */ 9256 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 9257 /* enum: no (or invalid) license is present for the application */ 9258 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 9259 /* enum: a valid license is present for the application */ 9260 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 9261 9262 9263 /***********************************/ 9264 /* MC_CMD_LICENSED_APP_OP 9265 * Perform an action for an individual licensed application. 9266 */ 9267 #define MC_CMD_LICENSED_APP_OP 0xf6 9268 9269 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9270 9271 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */ 9272 #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 9273 #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 9274 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) 9275 /* application ID */ 9276 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 9277 /* the type of operation requested */ 9278 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 9279 /* enum: validate application */ 9280 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 9281 /* enum: mask application */ 9282 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 9283 /* arguments specific to this particular operation */ 9284 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 9285 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 9286 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 9287 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 9288 9289 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ 9290 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 9291 #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 9292 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) 9293 /* result specific to this particular operation */ 9294 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 9295 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 9296 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 9297 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 9298 9299 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ 9300 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 9301 /* application ID */ 9302 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 9303 /* the type of operation requested */ 9304 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 9305 /* validation challenge */ 9306 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 9307 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 9308 9309 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ 9310 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 9311 /* feature expiry (time_t) */ 9312 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 9313 /* validation response */ 9314 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 9315 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 9316 9317 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ 9318 #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 9319 /* application ID */ 9320 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 9321 /* the type of operation requested */ 9322 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 9323 /* flag */ 9324 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 9325 9326 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ 9327 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 9328 9329 9330 /***********************************/ 9331 /* MC_CMD_SET_PORT_SNIFF_CONFIG 9332 * Configure RX port sniffing for the physical port associated with the calling 9333 * function. Only a privileged function may change the port sniffing 9334 * configuration. A copy of all traffic delivered to the host (non-promiscuous 9335 * mode) or all traffic arriving at the port (promiscuous mode) may be 9336 * delivered to a specific queue, or a set of queues with RSS. 9337 */ 9338 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 9339 9340 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9341 9342 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ 9343 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 9344 /* configuration flags */ 9345 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 9346 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 9347 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 9348 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 9349 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 9350 /* receive queue handle (for RSS mode, this is the base queue) */ 9351 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 9352 /* receive mode */ 9353 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 9354 /* enum: receive to just the specified queue */ 9355 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 9356 /* enum: receive to multiple queues using RSS context */ 9357 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 9358 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 9359 * that these handles should be considered opaque to the host, although a value 9360 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 9361 */ 9362 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 9363 9364 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ 9365 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 9366 9367 9368 /***********************************/ 9369 /* MC_CMD_GET_PORT_SNIFF_CONFIG 9370 * Obtain the current RX port sniffing configuration for the physical port 9371 * associated with the calling function. Only a privileged function may read 9372 * the configuration. 9373 */ 9374 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 9375 9376 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9377 9378 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ 9379 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 9380 9381 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ 9382 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 9383 /* configuration flags */ 9384 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 9385 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 9386 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 9387 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 9388 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 9389 /* receiving queue handle (for RSS mode, this is the base queue) */ 9390 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 9391 /* receive mode */ 9392 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 9393 /* enum: receiving to just the specified queue */ 9394 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 9395 /* enum: receiving to multiple queues using RSS context */ 9396 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 9397 /* RSS context (for RX_MODE_RSS) */ 9398 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 9399 9400 9401 /***********************************/ 9402 /* MC_CMD_SET_PARSER_DISP_CONFIG 9403 * Change configuration related to the parser-dispatcher subsystem. 9404 */ 9405 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9 9406 9407 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9408 9409 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */ 9410 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12 9411 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252 9412 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) 9413 /* the type of configuration setting to change */ 9414 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 9415 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible 9416 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.) 9417 */ 9418 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0 9419 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the 9420 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single 9421 * boolean.) 9422 */ 9423 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1 9424 /* handle for the entity to update: queue handle, EVB port ID, etc. depending 9425 * on the type of configuration setting being changed 9426 */ 9427 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 9428 /* new value: the details depend on the type of configuration setting being 9429 * changed 9430 */ 9431 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8 9432 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4 9433 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1 9434 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61 9435 9436 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ 9437 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 9438 9439 9440 /***********************************/ 9441 /* MC_CMD_GET_PARSER_DISP_CONFIG 9442 * Read configuration related to the parser-dispatcher subsystem. 9443 */ 9444 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa 9445 9446 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9447 9448 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ 9449 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 9450 /* the type of configuration setting to read */ 9451 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 9452 /* Enum values, see field(s): */ 9453 /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ 9454 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on 9455 * the type of configuration setting being read 9456 */ 9457 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 9458 9459 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ 9460 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 9461 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 9462 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) 9463 /* current value: the details depend on the type of configuration setting being 9464 * read 9465 */ 9466 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 9467 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 9468 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 9469 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 9470 9471 9472 /***********************************/ 9473 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG 9474 * Configure TX port sniffing for the physical port associated with the calling 9475 * function. Only a privileged function may change the port sniffing 9476 * configuration. A copy of all traffic transmitted through the port may be 9477 * delivered to a specific queue, or a set of queues with RSS. Note that these 9478 * packets are delivered with transmit timestamps in the packet prefix, not 9479 * receive timestamps, so it is likely that the queue(s) will need to be 9480 * dedicated as TX sniff receivers. 9481 */ 9482 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb 9483 9484 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9485 9486 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 9487 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 9488 /* configuration flags */ 9489 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 9490 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 9491 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 9492 /* receive queue handle (for RSS mode, this is the base queue) */ 9493 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 9494 /* receive mode */ 9495 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 9496 /* enum: receive to just the specified queue */ 9497 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 9498 /* enum: receive to multiple queues using RSS context */ 9499 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 9500 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 9501 * that these handles should be considered opaque to the host, although a value 9502 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 9503 */ 9504 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 9505 9506 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 9507 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 9508 9509 9510 /***********************************/ 9511 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG 9512 * Obtain the current TX port sniffing configuration for the physical port 9513 * associated with the calling function. Only a privileged function may read 9514 * the configuration. 9515 */ 9516 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc 9517 9518 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9519 9520 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 9521 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 9522 9523 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 9524 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 9525 /* configuration flags */ 9526 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 9527 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 9528 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 9529 /* receiving queue handle (for RSS mode, this is the base queue) */ 9530 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 9531 /* receive mode */ 9532 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 9533 /* enum: receiving to just the specified queue */ 9534 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 9535 /* enum: receiving to multiple queues using RSS context */ 9536 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 9537 /* RSS context (for RX_MODE_RSS) */ 9538 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 9539 9540 9541 /***********************************/ 9542 /* MC_CMD_RMON_STATS_RX_ERRORS 9543 * Per queue rx error stats. 9544 */ 9545 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe 9546 9547 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9548 9549 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ 9550 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 9551 /* The rx queue to get stats for. */ 9552 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 9553 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 9554 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 9555 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 9556 9557 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ 9558 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 9559 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 9560 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 9561 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 9562 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 9563 9564 9565 /***********************************/ 9566 /* MC_CMD_GET_PCIE_RESOURCE_INFO 9567 * Find out about available PCIE resources 9568 */ 9569 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd 9570 9571 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ 9572 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 9573 9574 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ 9575 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 9576 /* The maximum number of PFs the device can expose */ 9577 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 9578 /* The maximum number of VFs the device can expose in total */ 9579 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 9580 /* The maximum number of MSI-X vectors the device can provide in total */ 9581 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 9582 /* the number of MSI-X vectors the device will allocate by default to each PF 9583 */ 9584 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 9585 /* the number of MSI-X vectors the device will allocate by default to each VF 9586 */ 9587 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 9588 /* the maximum number of MSI-X vectors the device can allocate to any one PF */ 9589 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 9590 /* the maximum number of MSI-X vectors the device can allocate to any one VF */ 9591 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 9592 9593 9594 /***********************************/ 9595 /* MC_CMD_GET_PORT_MODES 9596 * Find out about available port modes 9597 */ 9598 #define MC_CMD_GET_PORT_MODES 0xff 9599 9600 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9601 9602 /* MC_CMD_GET_PORT_MODES_IN msgrequest */ 9603 #define MC_CMD_GET_PORT_MODES_IN_LEN 0 9604 9605 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */ 9606 #define MC_CMD_GET_PORT_MODES_OUT_LEN 12 9607 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */ 9608 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 9609 /* Default (canonical) board mode */ 9610 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 9611 /* Current board mode */ 9612 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 9613 9614 9615 /***********************************/ 9616 /* MC_CMD_READ_ATB 9617 * Sample voltages on the ATB 9618 */ 9619 #define MC_CMD_READ_ATB 0x100 9620 9621 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9622 9623 /* MC_CMD_READ_ATB_IN msgrequest */ 9624 #define MC_CMD_READ_ATB_IN_LEN 16 9625 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 9626 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ 9627 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ 9628 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ 9629 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 9630 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 9631 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 9632 9633 /* MC_CMD_READ_ATB_OUT msgresponse */ 9634 #define MC_CMD_READ_ATB_OUT_LEN 4 9635 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 9636 9637 9638 /***********************************/ 9639 /* MC_CMD_GET_WORKAROUNDS 9640 * Read the list of all implemented and all currently enabled workarounds. The 9641 * enums here must correspond with those in MC_CMD_WORKAROUND. 9642 */ 9643 #define MC_CMD_GET_WORKAROUNDS 0x59 9644 9645 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9646 9647 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ 9648 #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 9649 /* Each workaround is represented by a single bit according to the enums below. 9650 */ 9651 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 9652 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 9653 /* enum: Bug 17230 work around. */ 9654 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 9655 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 9656 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 9657 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 9658 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 9659 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 9660 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10 9661 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 9662 * - before adding code that queries this workaround, remember that there's 9663 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 9664 * and will hence (incorrectly) report that the bug doesn't exist. 9665 */ 9666 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20 9667 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */ 9668 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40 9669 9670 9671 /***********************************/ 9672 /* MC_CMD_PRIVILEGE_MASK 9673 * Read/set privileges of an arbitrary PCIe function 9674 */ 9675 #define MC_CMD_PRIVILEGE_MASK 0x5a 9676 9677 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9678 9679 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */ 9680 #define MC_CMD_PRIVILEGE_MASK_IN_LEN 8 9681 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF 9682 * 1,3 = 0x00030001 9683 */ 9684 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0 9685 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0 9686 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16 9687 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16 9688 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16 9689 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */ 9690 /* New privilege mask to be set. The mask will only be changed if the MSB is 9691 * set to 1. 9692 */ 9693 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4 9694 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */ 9695 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */ 9696 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ 9697 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ 9698 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ 9699 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 /* enum */ 9700 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ 9701 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ 9702 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ 9703 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ 9704 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ 9705 /* enum: Set this bit to indicate that a new privilege mask is to be set, 9706 * otherwise the command will only read the existing mask. 9707 */ 9708 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000 9709 9710 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */ 9711 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4 9712 /* For an admin function, always all the privileges are reported. */ 9713 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 9714 9715 9716 /***********************************/ 9717 /* MC_CMD_LINK_STATE_MODE 9718 * Read/set link state mode of a VF 9719 */ 9720 #define MC_CMD_LINK_STATE_MODE 0x5c 9721 9722 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9723 9724 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */ 9725 #define MC_CMD_LINK_STATE_MODE_IN_LEN 8 9726 /* The target function to have its link state mode read or set, must be a VF 9727 * e.g. VF 1,3 = 0x00030001 9728 */ 9729 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 9730 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 9731 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 9732 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 9733 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 9734 /* New link state mode to be set */ 9735 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 9736 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ 9737 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ 9738 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ 9739 /* enum: Use this value to just read the existing setting without modifying it. 9740 */ 9741 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff 9742 9743 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ 9744 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 9745 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 9746 9747 9748 /***********************************/ 9749 /* MC_CMD_GET_SNAPSHOT_LENGTH 9750 * Obtain the curent range of allowable values for the SNAPSHOT_LENGTH 9751 * parameter to MC_CMD_INIT_RXQ. 9752 */ 9753 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 9754 9755 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9756 9757 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ 9758 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 9759 9760 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ 9761 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 9762 /* Minimum acceptable snapshot length. */ 9763 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 9764 /* Maximum acceptable snapshot length. */ 9765 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 9766 9767 9768 /***********************************/ 9769 /* MC_CMD_FUSE_DIAGS 9770 * Additional fuse diagnostics 9771 */ 9772 #define MC_CMD_FUSE_DIAGS 0x102 9773 9774 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9775 9776 /* MC_CMD_FUSE_DIAGS_IN msgrequest */ 9777 #define MC_CMD_FUSE_DIAGS_IN_LEN 0 9778 9779 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */ 9780 #define MC_CMD_FUSE_DIAGS_OUT_LEN 48 9781 /* Total number of mismatched bits between pairs in area 0 */ 9782 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 9783 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ 9784 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 9785 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ 9786 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 9787 /* Checksum of data after logical OR of pairs in area 0 */ 9788 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 9789 /* Total number of mismatched bits between pairs in area 1 */ 9790 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 9791 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ 9792 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 9793 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ 9794 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 9795 /* Checksum of data after logical OR of pairs in area 1 */ 9796 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 9797 /* Total number of mismatched bits between pairs in area 2 */ 9798 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 9799 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ 9800 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 9801 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ 9802 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 9803 /* Checksum of data after logical OR of pairs in area 2 */ 9804 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 9805 9806 9807 /***********************************/ 9808 /* MC_CMD_PRIVILEGE_MODIFY 9809 * Modify the privileges of a set of PCIe functions. Note that this operation 9810 * only effects non-admin functions unless the admin privilege itself is 9811 * included in one of the masks provided. 9812 */ 9813 #define MC_CMD_PRIVILEGE_MODIFY 0x60 9814 9815 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9816 9817 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ 9818 #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 9819 /* The groups of functions to have their privilege masks modified. */ 9820 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 9821 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ 9822 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ 9823 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ 9824 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ 9825 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ 9826 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ 9827 /* For VFS_OF_PF specify the PF, for ONE specify the target function */ 9828 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 9829 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 9830 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 9831 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 9832 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 9833 /* Privileges to be added to the target functions. For privilege definitions 9834 * refer to the command MC_CMD_PRIVILEGE_MASK 9835 */ 9836 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 9837 /* Privileges to be removed from the target functions. For privilege 9838 * definitions refer to the command MC_CMD_PRIVILEGE_MASK 9839 */ 9840 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 9841 9842 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ 9843 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 9844 9845 9846 /***********************************/ 9847 /* MC_CMD_XPM_READ_BYTES 9848 * Read XPM memory 9849 */ 9850 #define MC_CMD_XPM_READ_BYTES 0x103 9851 9852 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9853 9854 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */ 9855 #define MC_CMD_XPM_READ_BYTES_IN_LEN 8 9856 /* Start address (byte) */ 9857 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 9858 /* Count (bytes) */ 9859 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 9860 9861 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ 9862 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 9863 #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 9864 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) 9865 /* Data */ 9866 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 9867 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 9868 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 9869 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 9870 9871 9872 /***********************************/ 9873 /* MC_CMD_XPM_WRITE_BYTES 9874 * Write XPM memory 9875 */ 9876 #define MC_CMD_XPM_WRITE_BYTES 0x104 9877 9878 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9879 9880 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ 9881 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 9882 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 9883 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) 9884 /* Start address (byte) */ 9885 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 9886 /* Count (bytes) */ 9887 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 9888 /* Data */ 9889 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 9890 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 9891 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 9892 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 9893 9894 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ 9895 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 9896 9897 9898 /***********************************/ 9899 /* MC_CMD_XPM_READ_SECTOR 9900 * Read XPM sector 9901 */ 9902 #define MC_CMD_XPM_READ_SECTOR 0x105 9903 9904 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9905 9906 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ 9907 #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 9908 /* Sector index */ 9909 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 9910 /* Sector size */ 9911 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 9912 9913 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ 9914 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 9915 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 9916 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) 9917 /* Sector type */ 9918 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 9919 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ 9920 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ 9921 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ 9922 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ 9923 /* Sector data */ 9924 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 9925 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 9926 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 9927 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 9928 9929 9930 /***********************************/ 9931 /* MC_CMD_XPM_WRITE_SECTOR 9932 * Write XPM sector 9933 */ 9934 #define MC_CMD_XPM_WRITE_SECTOR 0x106 9935 9936 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9937 9938 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ 9939 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 9940 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 9941 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) 9942 /* If writing fails due to an uncorrectable error, try up to RETRIES following 9943 * sectors (or until no more space available). If 0, only one write attempt is 9944 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair 9945 * mechanism. 9946 */ 9947 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 9948 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 9949 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 9950 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 9951 /* Sector type */ 9952 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 9953 /* Enum values, see field(s): */ 9954 /* MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ 9955 /* Sector size */ 9956 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 9957 /* Sector data */ 9958 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 9959 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 9960 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 9961 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 9962 9963 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ 9964 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 9965 /* New sector index */ 9966 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 9967 9968 9969 /***********************************/ 9970 /* MC_CMD_XPM_INVALIDATE_SECTOR 9971 * Invalidate XPM sector 9972 */ 9973 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 9974 9975 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9976 9977 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ 9978 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 9979 /* Sector index */ 9980 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 9981 9982 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ 9983 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 9984 9985 9986 /***********************************/ 9987 /* MC_CMD_XPM_BLANK_CHECK 9988 * Blank-check XPM memory and report bad locations 9989 */ 9990 #define MC_CMD_XPM_BLANK_CHECK 0x108 9991 9992 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9993 9994 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ 9995 #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 9996 /* Start address (byte) */ 9997 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 9998 /* Count (bytes) */ 9999 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 10000 10001 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ 10002 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 10003 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 10004 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) 10005 /* Total number of bad (non-blank) locations */ 10006 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 10007 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit 10008 * into MCDI response) 10009 */ 10010 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 10011 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 10012 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 10013 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 10014 10015 10016 /***********************************/ 10017 /* MC_CMD_XPM_REPAIR 10018 * Blank-check and repair XPM memory 10019 */ 10020 #define MC_CMD_XPM_REPAIR 0x109 10021 10022 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10023 10024 /* MC_CMD_XPM_REPAIR_IN msgrequest */ 10025 #define MC_CMD_XPM_REPAIR_IN_LEN 8 10026 /* Start address (byte) */ 10027 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 10028 /* Count (bytes) */ 10029 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 10030 10031 /* MC_CMD_XPM_REPAIR_OUT msgresponse */ 10032 #define MC_CMD_XPM_REPAIR_OUT_LEN 0 10033 10034 10035 /***********************************/ 10036 /* MC_CMD_XPM_DECODER_TEST 10037 * Test XPM memory address decoders for gross manufacturing defects. Can only 10038 * be performed on an unprogrammed part. 10039 */ 10040 #define MC_CMD_XPM_DECODER_TEST 0x10a 10041 10042 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10043 10044 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ 10045 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 10046 10047 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ 10048 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 10049 10050 10051 /***********************************/ 10052 /* MC_CMD_XPM_WRITE_TEST 10053 * XPM memory write test. Test XPM write logic for gross manufacturing defects 10054 * by writing to a dedicated test row. There are 16 locations in the test row 10055 * and the test can only be performed on locations that have not been 10056 * previously used (i.e. can be run at most 16 times). The test will pick the 10057 * first available location to use, or fail with ENOSPC if none left. 10058 */ 10059 #define MC_CMD_XPM_WRITE_TEST 0x10b 10060 10061 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10062 10063 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ 10064 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 10065 10066 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ 10067 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 10068 10069 10070 #endif /* MCDI_PCOL_H */ 10071