1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2009-2013 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 11 #ifndef MCDI_PCOL_H 12 #define MCDI_PCOL_H 13 14 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 15 /* Power-on reset state */ 16 #define MC_FW_STATE_POR (1) 17 /* If this is set in MC_RESET_STATE_REG then it should be 18 * possible to jump into IMEM without loading code from flash. */ 19 #define MC_FW_WARM_BOOT_OK (2) 20 /* The MC main image has started to boot. */ 21 #define MC_FW_STATE_BOOTING (4) 22 /* The Scheduler has started. */ 23 #define MC_FW_STATE_SCHED (8) 24 /* If this is set in MC_RESET_STATE_REG then it should be 25 * possible to jump into IMEM without loading code from flash. 26 * Unlike a warm boot, assume DMEM has been reloaded, so that 27 * the MC persistent data must be reinitialised. */ 28 #define MC_FW_TEPID_BOOT_OK (16) 29 /* We have entered the main firmware via recovery mode. This 30 * means that MC persistent data must be reinitialised, but that 31 * we shouldn't touch PCIe config. */ 32 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) 33 /* BIST state has been initialized */ 34 #define MC_FW_BIST_INIT_OK (128) 35 36 /* Siena MC shared memmory offsets */ 37 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 38 #define MC_SMEM_P0_DOORBELL_OFST 0x000 39 #define MC_SMEM_P1_DOORBELL_OFST 0x004 40 /* The rest of these are firmware-defined */ 41 #define MC_SMEM_P0_PDU_OFST 0x008 42 #define MC_SMEM_P1_PDU_OFST 0x108 43 #define MC_SMEM_PDU_LEN 0x100 44 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 45 #define MC_SMEM_P0_STATUS_OFST 0x7f8 46 #define MC_SMEM_P1_STATUS_OFST 0x7fc 47 48 /* Values to be written to the per-port status dword in shared 49 * memory on reboot and assert */ 50 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 51 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 52 53 /* Check whether an mcfw version (in host order) belongs to a bootloader */ 54 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) 55 56 /* The current version of the MCDI protocol. 57 * 58 * Note that the ROM burnt into the card only talks V0, so at the very 59 * least every driver must support version 0 and MCDI_PCOL_VERSION 60 */ 61 #define MCDI_PCOL_VERSION 2 62 63 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 64 65 /* MCDI version 1 66 * 67 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 68 * structure, filled in by the client. 69 * 70 * 0 7 8 16 20 22 23 24 31 71 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 72 * | | | 73 * | | \--- Response 74 * | \------- Error 75 * \------------------------------ Resync (always set) 76 * 77 * The client writes it's request into MC shared memory, and rings the 78 * doorbell. Each request is completed by either by the MC writting 79 * back into shared memory, or by writting out an event. 80 * 81 * All MCDI commands support completion by shared memory response. Each 82 * request may also contain additional data (accounted for by HEADER.LEN), 83 * and some response's may also contain additional data (again, accounted 84 * for by HEADER.LEN). 85 * 86 * Some MCDI commands support completion by event, in which any associated 87 * response data is included in the event. 88 * 89 * The protocol requires one response to be delivered for every request, a 90 * request should not be sent unless the response for the previous request 91 * has been received (either by polling shared memory, or by receiving 92 * an event). 93 */ 94 95 /** Request/Response structure */ 96 #define MCDI_HEADER_OFST 0 97 #define MCDI_HEADER_CODE_LBN 0 98 #define MCDI_HEADER_CODE_WIDTH 7 99 #define MCDI_HEADER_RESYNC_LBN 7 100 #define MCDI_HEADER_RESYNC_WIDTH 1 101 #define MCDI_HEADER_DATALEN_LBN 8 102 #define MCDI_HEADER_DATALEN_WIDTH 8 103 #define MCDI_HEADER_SEQ_LBN 16 104 #define MCDI_HEADER_SEQ_WIDTH 4 105 #define MCDI_HEADER_RSVD_LBN 20 106 #define MCDI_HEADER_RSVD_WIDTH 1 107 #define MCDI_HEADER_NOT_EPOCH_LBN 21 108 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 109 #define MCDI_HEADER_ERROR_LBN 22 110 #define MCDI_HEADER_ERROR_WIDTH 1 111 #define MCDI_HEADER_RESPONSE_LBN 23 112 #define MCDI_HEADER_RESPONSE_WIDTH 1 113 #define MCDI_HEADER_XFLAGS_LBN 24 114 #define MCDI_HEADER_XFLAGS_WIDTH 8 115 /* Request response using event */ 116 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 117 118 /* Maximum number of payload bytes */ 119 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc 120 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 121 122 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 123 124 125 /* The MC can generate events for two reasons: 126 * - To complete a shared memory request if XFLAGS_EVREQ was set 127 * - As a notification (link state, i2c event), controlled 128 * via MC_CMD_LOG_CTRL 129 * 130 * Both events share a common structure: 131 * 132 * 0 32 33 36 44 52 60 133 * | Data | Cont | Level | Src | Code | Rsvd | 134 * | 135 * \ There is another event pending in this notification 136 * 137 * If Code==CMDDONE, then the fields are further interpreted as: 138 * 139 * - LEVEL==INFO Command succeeded 140 * - LEVEL==ERR Command failed 141 * 142 * 0 8 16 24 32 143 * | Seq | Datalen | Errno | Rsvd | 144 * 145 * These fields are taken directly out of the standard MCDI header, i.e., 146 * LEVEL==ERR, Datalen == 0 => Reboot 147 * 148 * Events can be squirted out of the UART (using LOG_CTRL) without a 149 * MCDI header. An event can be distinguished from a MCDI response by 150 * examining the first byte which is 0xc0. This corresponds to the 151 * non-existent MCDI command MC_CMD_DEBUG_LOG. 152 * 153 * 0 7 8 154 * | command | Resync | = 0xc0 155 * 156 * Since the event is written in big-endian byte order, this works 157 * providing bits 56-63 of the event are 0xc0. 158 * 159 * 56 60 63 160 * | Rsvd | Code | = 0xc0 161 * 162 * Which means for convenience the event code is 0xc for all MC 163 * generated events. 164 */ 165 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 166 167 168 /* Operation not permitted. */ 169 #define MC_CMD_ERR_EPERM 1 170 /* Non-existent command target */ 171 #define MC_CMD_ERR_ENOENT 2 172 /* assert() has killed the MC */ 173 #define MC_CMD_ERR_EINTR 4 174 /* I/O failure */ 175 #define MC_CMD_ERR_EIO 5 176 /* Already exists */ 177 #define MC_CMD_ERR_EEXIST 6 178 /* Try again */ 179 #define MC_CMD_ERR_EAGAIN 11 180 /* Out of memory */ 181 #define MC_CMD_ERR_ENOMEM 12 182 /* Caller does not hold required locks */ 183 #define MC_CMD_ERR_EACCES 13 184 /* Resource is currently unavailable (e.g. lock contention) */ 185 #define MC_CMD_ERR_EBUSY 16 186 /* No such device */ 187 #define MC_CMD_ERR_ENODEV 19 188 /* Invalid argument to target */ 189 #define MC_CMD_ERR_EINVAL 22 190 /* Broken pipe */ 191 #define MC_CMD_ERR_EPIPE 32 192 /* Read-only */ 193 #define MC_CMD_ERR_EROFS 30 194 /* Out of range */ 195 #define MC_CMD_ERR_ERANGE 34 196 /* Non-recursive resource is already acquired */ 197 #define MC_CMD_ERR_EDEADLK 35 198 /* Operation not implemented */ 199 #define MC_CMD_ERR_ENOSYS 38 200 /* Operation timed out */ 201 #define MC_CMD_ERR_ETIME 62 202 /* Link has been severed */ 203 #define MC_CMD_ERR_ENOLINK 67 204 /* Protocol error */ 205 #define MC_CMD_ERR_EPROTO 71 206 /* Operation not supported */ 207 #define MC_CMD_ERR_ENOTSUP 95 208 /* Address not available */ 209 #define MC_CMD_ERR_EADDRNOTAVAIL 99 210 /* Not connected */ 211 #define MC_CMD_ERR_ENOTCONN 107 212 /* Operation already in progress */ 213 #define MC_CMD_ERR_EALREADY 114 214 215 /* Resource allocation failed. */ 216 #define MC_CMD_ERR_ALLOC_FAIL 0x1000 217 /* V-adaptor not found. */ 218 #define MC_CMD_ERR_NO_VADAPTOR 0x1001 219 /* EVB port not found. */ 220 #define MC_CMD_ERR_NO_EVB_PORT 0x1002 221 /* V-switch not found. */ 222 #define MC_CMD_ERR_NO_VSWITCH 0x1003 223 /* Too many VLAN tags. */ 224 #define MC_CMD_ERR_VLAN_LIMIT 0x1004 225 /* Bad PCI function number. */ 226 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 227 /* Invalid VLAN mode. */ 228 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 229 /* Invalid v-switch type. */ 230 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 231 /* Invalid v-port type. */ 232 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 233 /* MAC address exists. */ 234 #define MC_CMD_ERR_MAC_EXIST 0x1009 235 /* Slave core not present */ 236 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 237 /* The datapath is disabled. */ 238 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b 239 /* The requesting client is not a function */ 240 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c 241 /* The requested operation might require the 242 command to be passed between MCs, and the 243 transport doesn't support that. Should 244 only ever been seen over the UART. */ 245 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d 246 /* VLAN tag(s) exists */ 247 #define MC_CMD_ERR_VLAN_EXIST 0x100e 248 /* No MAC address assigned to an EVB port */ 249 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f 250 /* Notifies the driver that the request has been relayed 251 * to an admin function for authorization. The driver should 252 * wait for a PROXY_RESPONSE event and then resend its request. 253 * This error code is followed by a 32-bit handle that 254 * helps matching it with the respective PROXY_RESPONSE event. */ 255 #define MC_CMD_ERR_PROXY_PENDING 0x1010 256 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 257 /* The request cannot be passed for authorization because 258 * another request from the same function is currently being 259 * authorized. The drvier should try again later. */ 260 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 261 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function 262 * that has enabled proxying or BLOCK_INDEX points to a function that 263 * doesn't await an authorization. */ 264 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 265 /* This code is currently only used internally in FW. Its meaning is that 266 * an operation failed due to lack of SR-IOV privilege. 267 * Normally it is translated to EPERM by send_cmd_err(), 268 * but it may also be used to trigger some special mechanism 269 * for handling such case, e.g. to relay the failed request 270 * to a designated admin function for authorization. */ 271 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013 272 /* Workaround 26807 could not be turned on/off because some functions 273 * have already installed filters. See the comment at 274 * MC_CMD_WORKAROUND_BUG26807. */ 275 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 276 /* The clock whose frequency you've attempted to set set 277 * doesn't exist on this NIC */ 278 #define MC_CMD_ERR_NO_CLOCK 0x1015 279 /* Returned by MC_CMD_TESTASSERT if the action that should 280 * have caused an assertion failed to do so. */ 281 #define MC_CMD_ERR_UNREACHABLE 0x1016 282 283 #define MC_CMD_ERR_CODE_OFST 0 284 285 /* We define 8 "escape" commands to allow 286 for command number space extension */ 287 288 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 289 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 290 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 291 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 292 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 293 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 294 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 295 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 296 297 /* Vectors in the boot ROM */ 298 /* Point to the copycode entry point. */ 299 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) 300 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) 301 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4) 302 /* Points to the recovery mode entry point. */ 303 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) 304 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) 305 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4) 306 307 /* The command set exported by the boot ROM (MCDI v0) */ 308 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 309 (1 << MC_CMD_READ32) | \ 310 (1 << MC_CMD_WRITE32) | \ 311 (1 << MC_CMD_COPYCODE) | \ 312 (1 << MC_CMD_GET_VERSION), \ 313 0, 0, 0 } 314 315 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 316 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 317 318 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 319 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 320 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 321 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 322 323 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 324 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 325 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 326 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 327 328 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 329 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 330 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 331 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 332 333 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default 334 * stack ID (which must be in the range 1-255) along with an EVB port ID. 335 */ 336 #define EVB_STACK_ID(n) (((n) & 0xff) << 16) 337 338 339 /* Version 2 adds an optional argument to error returns: the errno value 340 * may be followed by the (0-based) number of the first argument that 341 * could not be processed. 342 */ 343 #define MC_CMD_ERR_ARG_OFST 4 344 345 /* No space */ 346 #define MC_CMD_ERR_ENOSPC 28 347 348 /* MCDI_EVENT structuredef */ 349 #define MCDI_EVENT_LEN 8 350 #define MCDI_EVENT_CONT_LBN 32 351 #define MCDI_EVENT_CONT_WIDTH 1 352 #define MCDI_EVENT_LEVEL_LBN 33 353 #define MCDI_EVENT_LEVEL_WIDTH 3 354 /* enum: Info. */ 355 #define MCDI_EVENT_LEVEL_INFO 0x0 356 /* enum: Warning. */ 357 #define MCDI_EVENT_LEVEL_WARN 0x1 358 /* enum: Error. */ 359 #define MCDI_EVENT_LEVEL_ERR 0x2 360 /* enum: Fatal. */ 361 #define MCDI_EVENT_LEVEL_FATAL 0x3 362 #define MCDI_EVENT_DATA_OFST 0 363 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 364 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 365 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 366 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 367 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 368 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 369 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 370 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 371 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 372 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 373 /* enum: 100Mbs */ 374 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 375 /* enum: 1Gbs */ 376 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 377 /* enum: 10Gbs */ 378 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 379 /* enum: 40Gbs */ 380 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 381 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 382 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 383 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 384 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 385 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 386 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 387 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 388 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 389 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 390 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 391 #define MCDI_EVENT_FWALERT_DATA_LBN 8 392 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 393 #define MCDI_EVENT_FWALERT_REASON_LBN 0 394 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 395 /* enum: SRAM Access. */ 396 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 397 #define MCDI_EVENT_FLR_VF_LBN 0 398 #define MCDI_EVENT_FLR_VF_WIDTH 8 399 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 400 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 401 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 402 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 403 /* enum: Descriptor loader reported failure */ 404 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 405 /* enum: Descriptor ring empty and no EOP seen for packet */ 406 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 407 /* enum: Overlength packet */ 408 #define MCDI_EVENT_TX_ERR_2BIG 0x3 409 /* enum: Malformed option descriptor */ 410 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 411 /* enum: Option descriptor part way through a packet */ 412 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 413 /* enum: DMA or PIO data access error */ 414 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 415 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 416 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 417 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 418 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 419 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 420 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 421 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 422 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 423 /* enum: PLL lost lock */ 424 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 425 /* enum: Filter overflow (PDMA) */ 426 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 427 /* enum: FIFO overflow (FPGA) */ 428 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 429 /* enum: Merge queue overflow */ 430 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 431 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 432 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 433 /* enum: AOE failed to load - no valid image? */ 434 #define MCDI_EVENT_AOE_NO_LOAD 0x1 435 /* enum: AOE FC reported an exception */ 436 #define MCDI_EVENT_AOE_FC_ASSERT 0x2 437 /* enum: AOE FC watchdogged */ 438 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 439 /* enum: AOE FC failed to start */ 440 #define MCDI_EVENT_AOE_FC_NO_START 0x4 441 /* enum: Generic AOE fault - likely to have been reported via other means too 442 * but intended for use by aoex driver. 443 */ 444 #define MCDI_EVENT_AOE_FAULT 0x5 445 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ 446 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 447 /* enum: AOE loaded successfully */ 448 #define MCDI_EVENT_AOE_LOAD 0x7 449 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ 450 #define MCDI_EVENT_AOE_DMA 0x8 451 /* enum: AOE byteblaster connected/disconnected (Connection status in 452 * AOE_ERR_DATA) 453 */ 454 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 455 /* enum: DDR ECC status update */ 456 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa 457 /* enum: PTP status update */ 458 #define MCDI_EVENT_AOE_PTP_STATUS 0xb 459 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 460 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 461 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 462 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 463 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 464 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 465 #define MCDI_EVENT_RX_ERR_INFO_LBN 16 466 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 467 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 468 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 469 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 470 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 471 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 472 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 473 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 474 #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 475 /* enum: MUM failed to load - no valid image? */ 476 #define MCDI_EVENT_MUM_NO_LOAD 0x1 477 /* enum: MUM f/w reported an exception */ 478 #define MCDI_EVENT_MUM_ASSERT 0x2 479 /* enum: MUM not kicking watchdog */ 480 #define MCDI_EVENT_MUM_WATCHDOG 0x3 481 #define MCDI_EVENT_MUM_ERR_DATA_LBN 8 482 #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 483 #define MCDI_EVENT_DATA_LBN 0 484 #define MCDI_EVENT_DATA_WIDTH 32 485 #define MCDI_EVENT_SRC_LBN 36 486 #define MCDI_EVENT_SRC_WIDTH 8 487 #define MCDI_EVENT_EV_CODE_LBN 60 488 #define MCDI_EVENT_EV_CODE_WIDTH 4 489 #define MCDI_EVENT_CODE_LBN 44 490 #define MCDI_EVENT_CODE_WIDTH 8 491 /* enum: Event generated by host software */ 492 #define MCDI_EVENT_SW_EVENT 0x0 493 /* enum: Bad assert. */ 494 #define MCDI_EVENT_CODE_BADSSERT 0x1 495 /* enum: PM Notice. */ 496 #define MCDI_EVENT_CODE_PMNOTICE 0x2 497 /* enum: Command done. */ 498 #define MCDI_EVENT_CODE_CMDDONE 0x3 499 /* enum: Link change. */ 500 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 501 /* enum: Sensor Event. */ 502 #define MCDI_EVENT_CODE_SENSOREVT 0x5 503 /* enum: Schedule error. */ 504 #define MCDI_EVENT_CODE_SCHEDERR 0x6 505 /* enum: Reboot. */ 506 #define MCDI_EVENT_CODE_REBOOT 0x7 507 /* enum: Mac stats DMA. */ 508 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 509 /* enum: Firmware alert. */ 510 #define MCDI_EVENT_CODE_FWALERT 0x9 511 /* enum: Function level reset. */ 512 #define MCDI_EVENT_CODE_FLR 0xa 513 /* enum: Transmit error */ 514 #define MCDI_EVENT_CODE_TX_ERR 0xb 515 /* enum: Tx flush has completed */ 516 #define MCDI_EVENT_CODE_TX_FLUSH 0xc 517 /* enum: PTP packet received timestamp */ 518 #define MCDI_EVENT_CODE_PTP_RX 0xd 519 /* enum: PTP NIC failure */ 520 #define MCDI_EVENT_CODE_PTP_FAULT 0xe 521 /* enum: PTP PPS event */ 522 #define MCDI_EVENT_CODE_PTP_PPS 0xf 523 /* enum: Rx flush has completed */ 524 #define MCDI_EVENT_CODE_RX_FLUSH 0x10 525 /* enum: Receive error */ 526 #define MCDI_EVENT_CODE_RX_ERR 0x11 527 /* enum: AOE fault */ 528 #define MCDI_EVENT_CODE_AOE 0x12 529 /* enum: Network port calibration failed (VCAL). */ 530 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 531 /* enum: HW PPS event */ 532 #define MCDI_EVENT_CODE_HW_PPS 0x14 533 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and 534 * a different format) 535 */ 536 #define MCDI_EVENT_CODE_MC_REBOOT 0x15 537 /* enum: the MC has detected a parity error */ 538 #define MCDI_EVENT_CODE_PAR_ERR 0x16 539 /* enum: the MC has detected a correctable error */ 540 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 541 /* enum: the MC has detected an uncorrectable error */ 542 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 543 /* enum: The MC has entered offline BIST mode */ 544 #define MCDI_EVENT_CODE_MC_BIST 0x19 545 /* enum: PTP tick event providing current NIC time */ 546 #define MCDI_EVENT_CODE_PTP_TIME 0x1a 547 /* enum: MUM fault */ 548 #define MCDI_EVENT_CODE_MUM 0x1b 549 /* enum: notify the designated PF of a new authorization request */ 550 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c 551 /* enum: notify a function that awaits an authorization that its request has 552 * been processed and it may now resend the command 553 */ 554 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d 555 /* enum: Artificial event generated by host and posted via MC for test 556 * purposes. 557 */ 558 #define MCDI_EVENT_CODE_TESTGEN 0xfa 559 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 560 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 561 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 562 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 563 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 564 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 565 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 566 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 567 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 568 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 569 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 570 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 571 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 572 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 573 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 574 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of 575 * timestamp 576 */ 577 #define MCDI_EVENT_PTP_SECONDS_OFST 0 578 #define MCDI_EVENT_PTP_SECONDS_LBN 0 579 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 580 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of 581 * timestamp 582 */ 583 #define MCDI_EVENT_PTP_MAJOR_OFST 0 584 #define MCDI_EVENT_PTP_MAJOR_LBN 0 585 #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 586 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field 587 * of timestamp 588 */ 589 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 590 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 591 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 592 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of 593 * timestamp 594 */ 595 #define MCDI_EVENT_PTP_MINOR_OFST 0 596 #define MCDI_EVENT_PTP_MINOR_LBN 0 597 #define MCDI_EVENT_PTP_MINOR_WIDTH 32 598 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet 599 */ 600 #define MCDI_EVENT_PTP_UUID_OFST 0 601 #define MCDI_EVENT_PTP_UUID_LBN 0 602 #define MCDI_EVENT_PTP_UUID_WIDTH 32 603 #define MCDI_EVENT_RX_ERR_DATA_OFST 0 604 #define MCDI_EVENT_RX_ERR_DATA_LBN 0 605 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 606 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 607 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 608 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 609 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 610 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 611 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 612 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 613 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 614 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 615 /* For CODE_PTP_TIME events, the major value of the PTP clock */ 616 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 617 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 618 #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 619 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ 620 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 621 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 622 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 623 * whether the NIC clock has ever been set 624 */ 625 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 626 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 627 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 628 * whether the NIC and System clocks are in sync 629 */ 630 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 631 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 632 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of 633 * the minor value of the PTP clock 634 */ 635 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 636 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 637 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 638 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 639 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 640 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 641 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 642 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 643 /* Zero means that the request has been completed or authorized, and the driver 644 * should resend it. A non-zero value means that the authorization has been 645 * denied, and gives the reason. Typically it will be EPERM. 646 */ 647 #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 648 #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 649 650 /* FCDI_EVENT structuredef */ 651 #define FCDI_EVENT_LEN 8 652 #define FCDI_EVENT_CONT_LBN 32 653 #define FCDI_EVENT_CONT_WIDTH 1 654 #define FCDI_EVENT_LEVEL_LBN 33 655 #define FCDI_EVENT_LEVEL_WIDTH 3 656 /* enum: Info. */ 657 #define FCDI_EVENT_LEVEL_INFO 0x0 658 /* enum: Warning. */ 659 #define FCDI_EVENT_LEVEL_WARN 0x1 660 /* enum: Error. */ 661 #define FCDI_EVENT_LEVEL_ERR 0x2 662 /* enum: Fatal. */ 663 #define FCDI_EVENT_LEVEL_FATAL 0x3 664 #define FCDI_EVENT_DATA_OFST 0 665 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 666 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 667 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 668 #define FCDI_EVENT_LINK_UP 0x1 /* enum */ 669 #define FCDI_EVENT_DATA_LBN 0 670 #define FCDI_EVENT_DATA_WIDTH 32 671 #define FCDI_EVENT_SRC_LBN 36 672 #define FCDI_EVENT_SRC_WIDTH 8 673 #define FCDI_EVENT_EV_CODE_LBN 60 674 #define FCDI_EVENT_EV_CODE_WIDTH 4 675 #define FCDI_EVENT_CODE_LBN 44 676 #define FCDI_EVENT_CODE_WIDTH 8 677 /* enum: The FC was rebooted. */ 678 #define FCDI_EVENT_CODE_REBOOT 0x1 679 /* enum: Bad assert. */ 680 #define FCDI_EVENT_CODE_ASSERT 0x2 681 /* enum: DDR3 test result. */ 682 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 683 /* enum: Link status. */ 684 #define FCDI_EVENT_CODE_LINK_STATE 0x4 685 /* enum: A timed read is ready to be serviced. */ 686 #define FCDI_EVENT_CODE_TIMED_READ 0x5 687 /* enum: One or more PPS IN events */ 688 #define FCDI_EVENT_CODE_PPS_IN 0x6 689 /* enum: Tick event from PTP clock */ 690 #define FCDI_EVENT_CODE_PTP_TICK 0x7 691 /* enum: ECC error counters */ 692 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 693 /* enum: Current status of PTP */ 694 #define FCDI_EVENT_CODE_PTP_STATUS 0x9 695 /* enum: Port id config to map MC-FC port idx */ 696 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa 697 /* enum: Boot result or error code */ 698 #define FCDI_EVENT_CODE_BOOT_RESULT 0xb 699 #define FCDI_EVENT_REBOOT_SRC_LBN 36 700 #define FCDI_EVENT_REBOOT_SRC_WIDTH 8 701 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */ 702 #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */ 703 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 704 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 705 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 706 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 707 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 708 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 709 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 710 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 711 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 712 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 713 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 714 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 715 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 716 #define FCDI_EVENT_PTP_STATE_OFST 0 717 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ 718 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ 719 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ 720 #define FCDI_EVENT_PTP_STATE_LBN 0 721 #define FCDI_EVENT_PTP_STATE_WIDTH 32 722 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 723 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 724 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 725 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 726 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 727 /* Index of MC port being referred to */ 728 #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 729 #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 730 /* FC Port index that matches the MC port index in SRC */ 731 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 732 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 733 #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 734 #define FCDI_EVENT_BOOT_RESULT_OFST 0 735 /* Enum values, see field(s): */ 736 /* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */ 737 #define FCDI_EVENT_BOOT_RESULT_LBN 0 738 #define FCDI_EVENT_BOOT_RESULT_WIDTH 32 739 740 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events 741 * to the MC. Note that this structure | is overlayed over a normal FCDI event 742 * such that bits 32-63 containing | event code, level, source etc remain the 743 * same. In this case the data | field of the header is defined to be the 744 * number of timestamps 745 */ 746 #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 747 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 748 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) 749 /* Number of timestamps following */ 750 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 751 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 752 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 753 /* Seconds field of a timestamp record */ 754 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 755 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 756 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 757 /* Nanoseconds field of a timestamp record */ 758 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 759 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 760 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 761 /* Timestamp records comprising the event */ 762 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 763 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 764 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 765 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 766 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 767 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 768 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 769 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 770 771 /* MUM_EVENT structuredef */ 772 #define MUM_EVENT_LEN 8 773 #define MUM_EVENT_CONT_LBN 32 774 #define MUM_EVENT_CONT_WIDTH 1 775 #define MUM_EVENT_LEVEL_LBN 33 776 #define MUM_EVENT_LEVEL_WIDTH 3 777 /* enum: Info. */ 778 #define MUM_EVENT_LEVEL_INFO 0x0 779 /* enum: Warning. */ 780 #define MUM_EVENT_LEVEL_WARN 0x1 781 /* enum: Error. */ 782 #define MUM_EVENT_LEVEL_ERR 0x2 783 /* enum: Fatal. */ 784 #define MUM_EVENT_LEVEL_FATAL 0x3 785 #define MUM_EVENT_DATA_OFST 0 786 #define MUM_EVENT_SENSOR_ID_LBN 0 787 #define MUM_EVENT_SENSOR_ID_WIDTH 8 788 /* Enum values, see field(s): */ 789 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 790 #define MUM_EVENT_SENSOR_STATE_LBN 8 791 #define MUM_EVENT_SENSOR_STATE_WIDTH 8 792 #define MUM_EVENT_PORT_PHY_READY_LBN 0 793 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1 794 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 795 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 796 #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 797 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 798 #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 799 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 800 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 801 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 802 #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 803 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 804 #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 805 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 806 #define MUM_EVENT_DATA_LBN 0 807 #define MUM_EVENT_DATA_WIDTH 32 808 #define MUM_EVENT_SRC_LBN 36 809 #define MUM_EVENT_SRC_WIDTH 8 810 #define MUM_EVENT_EV_CODE_LBN 60 811 #define MUM_EVENT_EV_CODE_WIDTH 4 812 #define MUM_EVENT_CODE_LBN 44 813 #define MUM_EVENT_CODE_WIDTH 8 814 /* enum: The MUM was rebooted. */ 815 #define MUM_EVENT_CODE_REBOOT 0x1 816 /* enum: Bad assert. */ 817 #define MUM_EVENT_CODE_ASSERT 0x2 818 /* enum: Sensor failure. */ 819 #define MUM_EVENT_CODE_SENSOR 0x3 820 /* enum: Link fault has been asserted, or has cleared. */ 821 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 822 #define MUM_EVENT_SENSOR_DATA_OFST 0 823 #define MUM_EVENT_SENSOR_DATA_LBN 0 824 #define MUM_EVENT_SENSOR_DATA_WIDTH 32 825 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 826 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 827 #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 828 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 829 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 830 #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 831 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0 832 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0 833 #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 834 #define MUM_EVENT_PORT_PHY_TECH_OFST 0 835 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ 836 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ 837 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ 838 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ 839 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ 840 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ 841 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ 842 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ 843 #define MUM_EVENT_PORT_PHY_TECH_LBN 0 844 #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 845 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 846 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 847 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ 848 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ 849 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ 850 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ 851 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ 852 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 853 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 854 855 856 /***********************************/ 857 /* MC_CMD_READ32 858 * Read multiple 32byte words from MC memory. 859 */ 860 #define MC_CMD_READ32 0x1 861 862 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 863 864 /* MC_CMD_READ32_IN msgrequest */ 865 #define MC_CMD_READ32_IN_LEN 8 866 #define MC_CMD_READ32_IN_ADDR_OFST 0 867 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 868 869 /* MC_CMD_READ32_OUT msgresponse */ 870 #define MC_CMD_READ32_OUT_LENMIN 4 871 #define MC_CMD_READ32_OUT_LENMAX 252 872 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 873 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 874 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 875 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 876 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 877 878 879 /***********************************/ 880 /* MC_CMD_WRITE32 881 * Write multiple 32byte words to MC memory. 882 */ 883 #define MC_CMD_WRITE32 0x2 884 885 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 886 887 /* MC_CMD_WRITE32_IN msgrequest */ 888 #define MC_CMD_WRITE32_IN_LENMIN 8 889 #define MC_CMD_WRITE32_IN_LENMAX 252 890 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 891 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 892 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 893 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 894 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 895 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 896 897 /* MC_CMD_WRITE32_OUT msgresponse */ 898 #define MC_CMD_WRITE32_OUT_LEN 0 899 900 901 /***********************************/ 902 /* MC_CMD_COPYCODE 903 * Copy MC code between two locations and jump. 904 */ 905 #define MC_CMD_COPYCODE 0x3 906 907 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN 908 909 /* MC_CMD_COPYCODE_IN msgrequest */ 910 #define MC_CMD_COPYCODE_IN_LEN 16 911 /* Source address 912 * 913 * The main image should be entered via a copy of a single word from and to a 914 * magic address, which controls various aspects of the boot. The magic address 915 * is a bitfield, with each bit as documented below. 916 */ 917 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 918 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ 919 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 920 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and 921 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) 922 */ 923 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 924 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, 925 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see 926 * below) 927 */ 928 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 929 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 930 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 931 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 932 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 933 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 934 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 935 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 936 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 937 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 938 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 939 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6 940 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1 941 /* Destination address */ 942 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 943 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 944 /* Address of where to jump after copy. */ 945 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 946 /* enum: Control should return to the caller rather than jumping */ 947 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 948 949 /* MC_CMD_COPYCODE_OUT msgresponse */ 950 #define MC_CMD_COPYCODE_OUT_LEN 0 951 952 953 /***********************************/ 954 /* MC_CMD_SET_FUNC 955 * Select function for function-specific commands. 956 */ 957 #define MC_CMD_SET_FUNC 0x4 958 959 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 960 961 /* MC_CMD_SET_FUNC_IN msgrequest */ 962 #define MC_CMD_SET_FUNC_IN_LEN 4 963 /* Set function */ 964 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 965 966 /* MC_CMD_SET_FUNC_OUT msgresponse */ 967 #define MC_CMD_SET_FUNC_OUT_LEN 0 968 969 970 /***********************************/ 971 /* MC_CMD_GET_BOOT_STATUS 972 * Get the instruction address from which the MC booted. 973 */ 974 #define MC_CMD_GET_BOOT_STATUS 0x5 975 976 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 977 978 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 979 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 980 981 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 982 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 983 /* ?? */ 984 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 985 /* enum: indicates that the MC wasn't flash booted */ 986 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef 987 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 988 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 989 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 990 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 991 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 992 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 993 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 994 995 996 /***********************************/ 997 /* MC_CMD_GET_ASSERTS 998 * Get (and optionally clear) the current assertion status. Only 999 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other 1000 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS 1001 */ 1002 #define MC_CMD_GET_ASSERTS 0x6 1003 1004 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1005 1006 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 1007 #define MC_CMD_GET_ASSERTS_IN_LEN 4 1008 /* Set to clear assertion */ 1009 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 1010 1011 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 1012 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 1013 /* Assertion status flag. */ 1014 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 1015 /* enum: No assertions have failed. */ 1016 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 1017 /* enum: A system-level assertion has failed. */ 1018 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 1019 /* enum: A thread-level assertion has failed. */ 1020 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 1021 /* enum: The system was reset by the watchdog. */ 1022 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 1023 /* enum: An illegal address trap stopped the system (huntington and later) */ 1024 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 1025 /* Failing PC value */ 1026 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 1027 /* Saved GP regs */ 1028 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 1029 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 1030 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 1031 /* enum: A magic value hinting that the value in this register at the time of 1032 * the failure has likely been lost. 1033 */ 1034 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 1035 /* Failing thread address */ 1036 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 1037 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 1038 1039 1040 /***********************************/ 1041 /* MC_CMD_LOG_CTRL 1042 * Configure the output stream for log events such as link state changes, 1043 * sensor notifications and MCDI completions 1044 */ 1045 #define MC_CMD_LOG_CTRL 0x7 1046 1047 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1048 1049 /* MC_CMD_LOG_CTRL_IN msgrequest */ 1050 #define MC_CMD_LOG_CTRL_IN_LEN 8 1051 /* Log destination */ 1052 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 1053 /* enum: UART. */ 1054 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 1055 /* enum: Event queue. */ 1056 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 1057 /* Legacy argument. Must be zero. */ 1058 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 1059 1060 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 1061 #define MC_CMD_LOG_CTRL_OUT_LEN 0 1062 1063 1064 /***********************************/ 1065 /* MC_CMD_GET_VERSION 1066 * Get version information about the MC firmware. 1067 */ 1068 #define MC_CMD_GET_VERSION 0x8 1069 1070 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1071 1072 /* MC_CMD_GET_VERSION_IN msgrequest */ 1073 #define MC_CMD_GET_VERSION_IN_LEN 0 1074 1075 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ 1076 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 1077 /* placeholder, set to 0 */ 1078 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 1079 1080 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ 1081 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 1082 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 1083 /* enum: Reserved version number to indicate "any" version. */ 1084 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 1085 /* enum: Bootrom version value for Siena. */ 1086 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 1087 /* enum: Bootrom version value for Huntington. */ 1088 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 1089 1090 /* MC_CMD_GET_VERSION_OUT msgresponse */ 1091 #define MC_CMD_GET_VERSION_OUT_LEN 32 1092 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1093 /* Enum values, see field(s): */ 1094 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1095 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 1096 /* 128bit mask of functions supported by the current firmware */ 1097 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 1098 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 1099 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 1100 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 1101 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 1102 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 1103 1104 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 1105 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 1106 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1107 /* Enum values, see field(s): */ 1108 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1109 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 1110 /* 128bit mask of functions supported by the current firmware */ 1111 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 1112 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 1113 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 1114 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 1115 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 1116 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 1117 /* extra info */ 1118 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 1119 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 1120 1121 1122 /***********************************/ 1123 /* MC_CMD_PTP 1124 * Perform PTP operation 1125 */ 1126 #define MC_CMD_PTP 0xb 1127 1128 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1129 1130 /* MC_CMD_PTP_IN msgrequest */ 1131 #define MC_CMD_PTP_IN_LEN 1 1132 /* PTP operation code */ 1133 #define MC_CMD_PTP_IN_OP_OFST 0 1134 #define MC_CMD_PTP_IN_OP_LEN 1 1135 /* enum: Enable PTP packet timestamping operation. */ 1136 #define MC_CMD_PTP_OP_ENABLE 0x1 1137 /* enum: Disable PTP packet timestamping operation. */ 1138 #define MC_CMD_PTP_OP_DISABLE 0x2 1139 /* enum: Send a PTP packet. */ 1140 #define MC_CMD_PTP_OP_TRANSMIT 0x3 1141 /* enum: Read the current NIC time. */ 1142 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 1143 /* enum: Get the current PTP status. */ 1144 #define MC_CMD_PTP_OP_STATUS 0x5 1145 /* enum: Adjust the PTP NIC's time. */ 1146 #define MC_CMD_PTP_OP_ADJUST 0x6 1147 /* enum: Synchronize host and NIC time. */ 1148 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 1149 /* enum: Basic manufacturing tests. */ 1150 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 1151 /* enum: Packet based manufacturing tests. */ 1152 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 1153 /* enum: Reset some of the PTP related statistics */ 1154 #define MC_CMD_PTP_OP_RESET_STATS 0xa 1155 /* enum: Debug operations to MC. */ 1156 #define MC_CMD_PTP_OP_DEBUG 0xb 1157 /* enum: Read an FPGA register */ 1158 #define MC_CMD_PTP_OP_FPGAREAD 0xc 1159 /* enum: Write an FPGA register */ 1160 #define MC_CMD_PTP_OP_FPGAWRITE 0xd 1161 /* enum: Apply an offset to the NIC clock */ 1162 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe 1163 /* enum: Change Apply an offset to the NIC clock */ 1164 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf 1165 /* enum: Set the MC packet filter VLAN tags for received PTP packets */ 1166 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 1167 /* enum: Set the MC packet filter UUID for received PTP packets */ 1168 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 1169 /* enum: Set the MC packet filter Domain for received PTP packets */ 1170 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 1171 /* enum: Set the clock source */ 1172 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 1173 /* enum: Reset value of Timer Reg. */ 1174 #define MC_CMD_PTP_OP_RST_CLK 0x14 1175 /* enum: Enable the forwarding of PPS events to the host */ 1176 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 1177 /* enum: Get the time format used by this NIC for PTP operations */ 1178 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 1179 /* enum: Get the clock attributes. NOTE- extended version of 1180 * MC_CMD_PTP_OP_GET_TIME_FORMAT 1181 */ 1182 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 1183 /* enum: Get corrections that should be applied to the various different 1184 * timestamps 1185 */ 1186 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 1187 /* enum: Subscribe to receive periodic time events indicating the current NIC 1188 * time 1189 */ 1190 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 1191 /* enum: Unsubscribe to stop receiving time events */ 1192 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 1193 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS 1194 * input on the same NIC. 1195 */ 1196 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a 1197 /* enum: Set the PTP sync status. Status is used by firmware to report to event 1198 * subscribers. 1199 */ 1200 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b 1201 /* enum: Above this for future use. */ 1202 #define MC_CMD_PTP_OP_MAX 0x1c 1203 1204 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 1205 #define MC_CMD_PTP_IN_ENABLE_LEN 16 1206 #define MC_CMD_PTP_IN_CMD_OFST 0 1207 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 1208 /* Event queue for PTP events */ 1209 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 1210 /* PTP timestamping mode */ 1211 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 1212 /* enum: PTP, version 1 */ 1213 #define MC_CMD_PTP_MODE_V1 0x0 1214 /* enum: PTP, version 1, with VLAN headers - deprecated */ 1215 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 1216 /* enum: PTP, version 2 */ 1217 #define MC_CMD_PTP_MODE_V2 0x2 1218 /* enum: PTP, version 2, with VLAN headers - deprecated */ 1219 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 1220 /* enum: PTP, version 2, with improved UUID filtering */ 1221 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 1222 /* enum: FCoE (seconds and microseconds) */ 1223 #define MC_CMD_PTP_MODE_FCOE 0x5 1224 1225 /* MC_CMD_PTP_IN_DISABLE msgrequest */ 1226 #define MC_CMD_PTP_IN_DISABLE_LEN 8 1227 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1228 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1229 1230 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 1231 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 1232 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 1233 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 1234 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1235 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1236 /* Transmit packet length */ 1237 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 1238 /* Transmit packet data */ 1239 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 1240 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 1241 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 1242 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 1243 1244 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 1245 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 1246 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1247 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1248 1249 /* MC_CMD_PTP_IN_STATUS msgrequest */ 1250 #define MC_CMD_PTP_IN_STATUS_LEN 8 1251 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1252 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1253 1254 /* MC_CMD_PTP_IN_ADJUST msgrequest */ 1255 #define MC_CMD_PTP_IN_ADJUST_LEN 24 1256 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1257 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1258 /* Frequency adjustment 40 bit fixed point ns */ 1259 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 1260 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 1261 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 1262 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 1263 /* enum: Number of fractional bits in frequency adjustment */ 1264 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 1265 /* Time adjustment in seconds */ 1266 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 1267 /* Time adjustment major value */ 1268 #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 1269 /* Time adjustment in nanoseconds */ 1270 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 1271 /* Time adjustment minor value */ 1272 #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 1273 1274 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 1275 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 1276 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1277 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1278 /* Number of time readings to capture */ 1279 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 1280 /* Host address in which to write "synchronization started" indication (64 1281 * bits) 1282 */ 1283 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 1284 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 1285 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 1286 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 1287 1288 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 1289 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 1290 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1291 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1292 1293 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 1294 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 1295 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1296 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1297 /* Enable or disable packet testing */ 1298 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 1299 1300 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ 1301 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 1302 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1303 /* Reset PTP statistics */ 1304 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1305 1306 /* MC_CMD_PTP_IN_DEBUG msgrequest */ 1307 #define MC_CMD_PTP_IN_DEBUG_LEN 12 1308 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1309 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1310 /* Debug operations */ 1311 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 1312 1313 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ 1314 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 1315 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1316 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1317 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 1318 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 1319 1320 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ 1321 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 1322 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 1323 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) 1324 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1325 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1326 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 1327 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 1328 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 1329 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 1330 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 1331 1332 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ 1333 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 1334 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1335 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1336 /* Time adjustment in seconds */ 1337 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 1338 /* Time adjustment major value */ 1339 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 1340 /* Time adjustment in nanoseconds */ 1341 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 1342 /* Time adjustment minor value */ 1343 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 1344 1345 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ 1346 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 1347 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1348 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1349 /* Frequency adjustment 40 bit fixed point ns */ 1350 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 1351 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 1352 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 1353 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 1354 /* enum: Number of fractional bits in frequency adjustment */ 1355 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ 1356 1357 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ 1358 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 1359 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1360 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1361 /* Number of VLAN tags, 0 if not VLAN */ 1362 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 1363 /* Set of VLAN tags to filter against */ 1364 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 1365 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 1366 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 1367 1368 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ 1369 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 1370 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1371 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1372 /* 1 to enable UUID filtering, 0 to disable */ 1373 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 1374 /* UUID to filter against */ 1375 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 1376 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 1377 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 1378 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 1379 1380 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ 1381 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 1382 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1383 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1384 /* 1 to enable Domain filtering, 0 to disable */ 1385 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 1386 /* Domain number to filter against */ 1387 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 1388 1389 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ 1390 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 1391 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1392 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1393 /* Set the clock source. */ 1394 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 1395 /* enum: Internal. */ 1396 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 1397 /* enum: External. */ 1398 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 1399 1400 /* MC_CMD_PTP_IN_RST_CLK msgrequest */ 1401 #define MC_CMD_PTP_IN_RST_CLK_LEN 8 1402 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1403 /* Reset value of Timer Reg. */ 1404 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1405 1406 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ 1407 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 1408 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1409 /* Enable or disable */ 1410 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 1411 /* enum: Enable */ 1412 #define MC_CMD_PTP_ENABLE_PPS 0x0 1413 /* enum: Disable */ 1414 #define MC_CMD_PTP_DISABLE_PPS 0x1 1415 /* Queue id to send events back */ 1416 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 1417 1418 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ 1419 #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 1420 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1421 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1422 1423 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ 1424 #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 1425 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1426 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1427 1428 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ 1429 #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 1430 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1431 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1432 1433 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ 1434 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 1435 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1436 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1437 /* Original field containing queue ID. Now extended to include flags. */ 1438 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 1439 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0 1440 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16 1441 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31 1442 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1 1443 1444 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ 1445 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 1446 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1447 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1448 /* Unsubscribe options */ 1449 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 1450 /* enum: Unsubscribe a single queue */ 1451 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 1452 /* enum: Unsubscribe all queues */ 1453 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 1454 /* Event queue ID */ 1455 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 1456 1457 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ 1458 #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 1459 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1460 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1461 /* 1 to enable PPS test mode, 0 to disable and return result. */ 1462 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 1463 1464 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ 1465 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 1466 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1467 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1468 /* NIC - Host System Clock Synchronization status */ 1469 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 1470 /* enum: Host System clock and NIC clock are not in sync */ 1471 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 1472 /* enum: Host System clock and NIC clock are synchronized */ 1473 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 1474 /* If synchronized, number of seconds until clocks should be considered to be 1475 * no longer in sync. 1476 */ 1477 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 1478 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 1479 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 1480 1481 /* MC_CMD_PTP_OUT msgresponse */ 1482 #define MC_CMD_PTP_OUT_LEN 0 1483 1484 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 1485 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 1486 /* Value of seconds timestamp */ 1487 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 1488 /* Timestamp major value */ 1489 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 1490 /* Value of nanoseconds timestamp */ 1491 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 1492 /* Timestamp minor value */ 1493 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 1494 1495 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ 1496 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 1497 1498 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ 1499 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 1500 1501 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 1502 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 1503 /* Value of seconds timestamp */ 1504 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 1505 /* Timestamp major value */ 1506 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 1507 /* Value of nanoseconds timestamp */ 1508 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 1509 /* Timestamp minor value */ 1510 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 1511 1512 /* MC_CMD_PTP_OUT_STATUS msgresponse */ 1513 #define MC_CMD_PTP_OUT_STATUS_LEN 64 1514 /* Frequency of NIC's hardware clock */ 1515 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 1516 /* Number of packets transmitted and timestamped */ 1517 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 1518 /* Number of packets received and timestamped */ 1519 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 1520 /* Number of packets timestamped by the FPGA */ 1521 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 1522 /* Number of packets filter matched */ 1523 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 1524 /* Number of packets not filter matched */ 1525 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 1526 /* Number of PPS overflows (noise on input?) */ 1527 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 1528 /* Number of PPS bad periods */ 1529 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 1530 /* Minimum period of PPS pulse in nanoseconds */ 1531 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 1532 /* Maximum period of PPS pulse in nanoseconds */ 1533 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 1534 /* Last period of PPS pulse in nanoseconds */ 1535 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 1536 /* Mean period of PPS pulse in nanoseconds */ 1537 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 1538 /* Minimum offset of PPS pulse in nanoseconds (signed) */ 1539 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 1540 /* Maximum offset of PPS pulse in nanoseconds (signed) */ 1541 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 1542 /* Last offset of PPS pulse in nanoseconds (signed) */ 1543 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 1544 /* Mean offset of PPS pulse in nanoseconds (signed) */ 1545 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 1546 1547 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 1548 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 1549 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 1550 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 1551 /* A set of host and NIC times */ 1552 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 1553 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 1554 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 1555 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 1556 /* Host time immediately before NIC's hardware clock read */ 1557 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 1558 /* Value of seconds timestamp */ 1559 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 1560 /* Timestamp major value */ 1561 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 1562 /* Value of nanoseconds timestamp */ 1563 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 1564 /* Timestamp minor value */ 1565 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 1566 /* Host time immediately after NIC's hardware clock read */ 1567 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 1568 /* Number of nanoseconds waited after reading NIC's hardware clock */ 1569 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 1570 1571 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 1572 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 1573 /* Results of testing */ 1574 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 1575 /* enum: Successful test */ 1576 #define MC_CMD_PTP_MANF_SUCCESS 0x0 1577 /* enum: FPGA load failed */ 1578 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 1579 /* enum: FPGA version invalid */ 1580 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 1581 /* enum: FPGA registers incorrect */ 1582 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 1583 /* enum: Oscillator possibly not working? */ 1584 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 1585 /* enum: Timestamps not increasing */ 1586 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 1587 /* enum: Mismatched packet count */ 1588 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 1589 /* enum: Mismatched packet count (Siena filter and FPGA) */ 1590 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 1591 /* enum: Not enough packets to perform timestamp check */ 1592 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 1593 /* enum: Timestamp trigger GPIO not working */ 1594 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 1595 /* enum: Insufficient PPS events to perform checks */ 1596 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa 1597 /* enum: PPS time event period not sufficiently close to 1s. */ 1598 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb 1599 /* enum: PPS time event nS reading not sufficiently close to zero. */ 1600 #define MC_CMD_PTP_MANF_PPS_NS 0xc 1601 /* enum: PTP peripheral registers incorrect */ 1602 #define MC_CMD_PTP_MANF_REGISTERS 0xd 1603 /* enum: Failed to read time from PTP peripheral */ 1604 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe 1605 /* Presence of external oscillator */ 1606 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 1607 1608 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 1609 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 1610 /* Results of testing */ 1611 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 1612 /* Number of packets received by FPGA */ 1613 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 1614 /* Number of packets received by Siena filters */ 1615 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 1616 1617 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ 1618 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 1619 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 1620 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) 1621 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 1622 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 1623 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 1624 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 1625 1626 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ 1627 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 1628 /* Time format required/used by for this NIC. Applies to all PTP MCDI 1629 * operations that pass times between the host and firmware. If this operation 1630 * is not supported (older firmware) a format of seconds and nanoseconds should 1631 * be assumed. 1632 */ 1633 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 1634 /* enum: Times are in seconds and nanoseconds */ 1635 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 1636 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 1637 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 1638 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 1639 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 1640 1641 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ 1642 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 1643 /* Time format required/used by for this NIC. Applies to all PTP MCDI 1644 * operations that pass times between the host and firmware. If this operation 1645 * is not supported (older firmware) a format of seconds and nanoseconds should 1646 * be assumed. 1647 */ 1648 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 1649 /* enum: Times are in seconds and nanoseconds */ 1650 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 1651 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 1652 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 1653 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 1654 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 1655 /* Minimum acceptable value for a corrected synchronization timeset. When 1656 * comparing host and NIC clock times, the MC returns a set of samples that 1657 * contain the host start and end time, the MC time when the host start was 1658 * detected and the time the MC waited between reading the time and detecting 1659 * the host end. The corrected sync window is the difference between the host 1660 * end and start times minus the time that the MC waited for host end. 1661 */ 1662 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 1663 /* Various PTP capabilities */ 1664 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 1665 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 1666 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 1667 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1 1668 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1 1669 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 1670 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 1671 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 1672 1673 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ 1674 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 1675 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 1676 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 1677 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 1678 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 1679 /* Uncorrected error on PPS output in NIC clock format */ 1680 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 1681 /* Uncorrected error on PPS input in NIC clock format */ 1682 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 1683 1684 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ 1685 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 1686 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 1687 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 1688 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 1689 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 1690 /* Uncorrected error on PPS output in NIC clock format */ 1691 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 1692 /* Uncorrected error on PPS input in NIC clock format */ 1693 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 1694 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ 1695 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 1696 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */ 1697 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 1698 1699 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ 1700 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 1701 /* Results of testing */ 1702 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 1703 /* Enum values, see field(s): */ 1704 /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ 1705 1706 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ 1707 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 1708 1709 1710 /***********************************/ 1711 /* MC_CMD_CSR_READ32 1712 * Read 32bit words from the indirect memory map. 1713 */ 1714 #define MC_CMD_CSR_READ32 0xc 1715 1716 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1717 1718 /* MC_CMD_CSR_READ32_IN msgrequest */ 1719 #define MC_CMD_CSR_READ32_IN_LEN 12 1720 /* Address */ 1721 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 1722 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 1723 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 1724 1725 /* MC_CMD_CSR_READ32_OUT msgresponse */ 1726 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 1727 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 1728 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 1729 /* The last dword is the status, not a value read */ 1730 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 1731 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 1732 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 1733 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 1734 1735 1736 /***********************************/ 1737 /* MC_CMD_CSR_WRITE32 1738 * Write 32bit dwords to the indirect memory map. 1739 */ 1740 #define MC_CMD_CSR_WRITE32 0xd 1741 1742 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1743 1744 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 1745 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 1746 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 1747 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 1748 /* Address */ 1749 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 1750 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 1751 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 1752 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 1753 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 1754 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 1755 1756 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 1757 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 1758 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 1759 1760 1761 /***********************************/ 1762 /* MC_CMD_HP 1763 * These commands are used for HP related features. They are grouped under one 1764 * MCDI command to avoid creating too many MCDI commands. 1765 */ 1766 #define MC_CMD_HP 0x54 1767 1768 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1769 1770 /* MC_CMD_HP_IN msgrequest */ 1771 #define MC_CMD_HP_IN_LEN 16 1772 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 1773 * the specified address with the specified interval.When address is NULL, 1774 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 1775 * state / 2: (debug) Show temperature reported by one of the supported 1776 * sensors. 1777 */ 1778 #define MC_CMD_HP_IN_SUBCMD_OFST 0 1779 /* enum: OCSD (Option Card Sensor Data) sub-command. */ 1780 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 1781 /* enum: Last known valid HP sub-command. */ 1782 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 1783 /* The address to the array of sensor fields. (Or NULL to use a sub-command.) 1784 */ 1785 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 1786 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 1787 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 1788 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 1789 /* The requested update interval, in seconds. (Or the sub-command if ADDR is 1790 * NULL.) 1791 */ 1792 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 1793 1794 /* MC_CMD_HP_OUT msgresponse */ 1795 #define MC_CMD_HP_OUT_LEN 4 1796 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 1797 /* enum: OCSD stopped for this card. */ 1798 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 1799 /* enum: OCSD was successfully started with the address provided. */ 1800 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 1801 /* enum: OCSD was already started for this card. */ 1802 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 1803 1804 1805 /***********************************/ 1806 /* MC_CMD_STACKINFO 1807 * Get stack information. 1808 */ 1809 #define MC_CMD_STACKINFO 0xf 1810 1811 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1812 1813 /* MC_CMD_STACKINFO_IN msgrequest */ 1814 #define MC_CMD_STACKINFO_IN_LEN 0 1815 1816 /* MC_CMD_STACKINFO_OUT msgresponse */ 1817 #define MC_CMD_STACKINFO_OUT_LENMIN 12 1818 #define MC_CMD_STACKINFO_OUT_LENMAX 252 1819 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 1820 /* (thread ptr, stack size, free space) for each thread in system */ 1821 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 1822 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 1823 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 1824 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 1825 1826 1827 /***********************************/ 1828 /* MC_CMD_MDIO_READ 1829 * MDIO register read. 1830 */ 1831 #define MC_CMD_MDIO_READ 0x10 1832 1833 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1834 1835 /* MC_CMD_MDIO_READ_IN msgrequest */ 1836 #define MC_CMD_MDIO_READ_IN_LEN 16 1837 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 1838 * external devices. 1839 */ 1840 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 1841 /* enum: Internal. */ 1842 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 1843 /* enum: External. */ 1844 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 1845 /* Port address */ 1846 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 1847 /* Device Address or clause 22. */ 1848 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 1849 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 1850 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 1851 */ 1852 #define MC_CMD_MDIO_CLAUSE22 0x20 1853 /* Address */ 1854 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 1855 1856 /* MC_CMD_MDIO_READ_OUT msgresponse */ 1857 #define MC_CMD_MDIO_READ_OUT_LEN 8 1858 /* Value */ 1859 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 1860 /* Status the MDIO commands return the raw status bits from the MDIO block. A 1861 * "good" transaction should have the DONE bit set and all other bits clear. 1862 */ 1863 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 1864 /* enum: Good. */ 1865 #define MC_CMD_MDIO_STATUS_GOOD 0x8 1866 1867 1868 /***********************************/ 1869 /* MC_CMD_MDIO_WRITE 1870 * MDIO register write. 1871 */ 1872 #define MC_CMD_MDIO_WRITE 0x11 1873 1874 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1875 1876 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 1877 #define MC_CMD_MDIO_WRITE_IN_LEN 20 1878 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 1879 * external devices. 1880 */ 1881 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 1882 /* enum: Internal. */ 1883 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 1884 /* enum: External. */ 1885 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 1886 /* Port address */ 1887 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 1888 /* Device Address or clause 22. */ 1889 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 1890 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 1891 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 1892 */ 1893 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 1894 /* Address */ 1895 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 1896 /* Value */ 1897 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 1898 1899 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 1900 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 1901 /* Status; the MDIO commands return the raw status bits from the MDIO block. A 1902 * "good" transaction should have the DONE bit set and all other bits clear. 1903 */ 1904 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 1905 /* enum: Good. */ 1906 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 1907 1908 1909 /***********************************/ 1910 /* MC_CMD_DBI_WRITE 1911 * Write DBI register(s). 1912 */ 1913 #define MC_CMD_DBI_WRITE 0x12 1914 1915 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1916 1917 /* MC_CMD_DBI_WRITE_IN msgrequest */ 1918 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 1919 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 1920 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 1921 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 1922 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 1923 */ 1924 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 1925 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 1926 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 1927 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 1928 1929 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 1930 #define MC_CMD_DBI_WRITE_OUT_LEN 0 1931 1932 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 1933 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 1934 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 1935 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 1936 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 1937 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 1938 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 1939 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 1940 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 1941 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 1942 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 1943 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 1944 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 1945 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 1946 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 1947 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 1948 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 1949 1950 1951 /***********************************/ 1952 /* MC_CMD_PORT_READ32 1953 * Read a 32-bit register from the indirect port register map. The port to 1954 * access is implied by the Shared memory channel used. 1955 */ 1956 #define MC_CMD_PORT_READ32 0x14 1957 1958 /* MC_CMD_PORT_READ32_IN msgrequest */ 1959 #define MC_CMD_PORT_READ32_IN_LEN 4 1960 /* Address */ 1961 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 1962 1963 /* MC_CMD_PORT_READ32_OUT msgresponse */ 1964 #define MC_CMD_PORT_READ32_OUT_LEN 8 1965 /* Value */ 1966 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 1967 /* Status */ 1968 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 1969 1970 1971 /***********************************/ 1972 /* MC_CMD_PORT_WRITE32 1973 * Write a 32-bit register to the indirect port register map. The port to 1974 * access is implied by the Shared memory channel used. 1975 */ 1976 #define MC_CMD_PORT_WRITE32 0x15 1977 1978 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 1979 #define MC_CMD_PORT_WRITE32_IN_LEN 8 1980 /* Address */ 1981 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 1982 /* Value */ 1983 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 1984 1985 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 1986 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 1987 /* Status */ 1988 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 1989 1990 1991 /***********************************/ 1992 /* MC_CMD_PORT_READ128 1993 * Read a 128-bit register from the indirect port register map. The port to 1994 * access is implied by the Shared memory channel used. 1995 */ 1996 #define MC_CMD_PORT_READ128 0x16 1997 1998 /* MC_CMD_PORT_READ128_IN msgrequest */ 1999 #define MC_CMD_PORT_READ128_IN_LEN 4 2000 /* Address */ 2001 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 2002 2003 /* MC_CMD_PORT_READ128_OUT msgresponse */ 2004 #define MC_CMD_PORT_READ128_OUT_LEN 20 2005 /* Value */ 2006 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 2007 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 2008 /* Status */ 2009 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 2010 2011 2012 /***********************************/ 2013 /* MC_CMD_PORT_WRITE128 2014 * Write a 128-bit register to the indirect port register map. The port to 2015 * access is implied by the Shared memory channel used. 2016 */ 2017 #define MC_CMD_PORT_WRITE128 0x17 2018 2019 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 2020 #define MC_CMD_PORT_WRITE128_IN_LEN 20 2021 /* Address */ 2022 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 2023 /* Value */ 2024 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 2025 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 2026 2027 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 2028 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 2029 /* Status */ 2030 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 2031 2032 /* MC_CMD_CAPABILITIES structuredef */ 2033 #define MC_CMD_CAPABILITIES_LEN 4 2034 /* Small buf table. */ 2035 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 2036 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 2037 /* Turbo mode (for Maranello). */ 2038 #define MC_CMD_CAPABILITIES_TURBO_LBN 1 2039 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 2040 /* Turbo mode active (for Maranello). */ 2041 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 2042 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 2043 /* PTP offload. */ 2044 #define MC_CMD_CAPABILITIES_PTP_LBN 3 2045 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 2046 /* AOE mode. */ 2047 #define MC_CMD_CAPABILITIES_AOE_LBN 4 2048 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 2049 /* AOE mode active. */ 2050 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 2051 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 2052 /* AOE mode active. */ 2053 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 2054 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 2055 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 2056 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 2057 2058 2059 /***********************************/ 2060 /* MC_CMD_GET_BOARD_CFG 2061 * Returns the MC firmware configuration structure. 2062 */ 2063 #define MC_CMD_GET_BOARD_CFG 0x18 2064 2065 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2066 2067 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 2068 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 2069 2070 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 2071 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 2072 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 2073 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 2074 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 2075 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 2076 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 2077 /* See MC_CMD_CAPABILITIES */ 2078 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 2079 /* See MC_CMD_CAPABILITIES */ 2080 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 2081 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 2082 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 2083 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 2084 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 2085 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 2086 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 2087 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 2088 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 2089 /* This field contains a 16-bit value for each of the types of NVRAM area. The 2090 * values are defined in the firmware/mc/platform/.c file for a specific board 2091 * type, but otherwise have no meaning to the MC; they are used by the driver 2092 * to manage selection of appropriate firmware updates. 2093 */ 2094 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 2095 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 2096 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 2097 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 2098 2099 2100 /***********************************/ 2101 /* MC_CMD_DBI_READX 2102 * Read DBI register(s) -- extended functionality 2103 */ 2104 #define MC_CMD_DBI_READX 0x19 2105 2106 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2107 2108 /* MC_CMD_DBI_READX_IN msgrequest */ 2109 #define MC_CMD_DBI_READX_IN_LENMIN 8 2110 #define MC_CMD_DBI_READX_IN_LENMAX 248 2111 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 2112 /* Each Read op consists of an address (offset 0), VF/CS2) */ 2113 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 2114 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 2115 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 2116 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 2117 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 2118 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 2119 2120 /* MC_CMD_DBI_READX_OUT msgresponse */ 2121 #define MC_CMD_DBI_READX_OUT_LENMIN 4 2122 #define MC_CMD_DBI_READX_OUT_LENMAX 252 2123 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 2124 /* Value */ 2125 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 2126 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 2127 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 2128 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 2129 2130 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 2131 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 2132 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 2133 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 2134 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 2135 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 2136 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 2137 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 2138 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 2139 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 2140 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 2141 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 2142 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 2143 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 2144 2145 2146 /***********************************/ 2147 /* MC_CMD_SET_RAND_SEED 2148 * Set the 16byte seed for the MC pseudo-random generator. 2149 */ 2150 #define MC_CMD_SET_RAND_SEED 0x1a 2151 2152 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2153 2154 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 2155 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 2156 /* Seed value. */ 2157 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 2158 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 2159 2160 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 2161 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 2162 2163 2164 /***********************************/ 2165 /* MC_CMD_LTSSM_HIST 2166 * Retrieve the history of the LTSSM, if the build supports it. 2167 */ 2168 #define MC_CMD_LTSSM_HIST 0x1b 2169 2170 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 2171 #define MC_CMD_LTSSM_HIST_IN_LEN 0 2172 2173 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 2174 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 2175 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 2176 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 2177 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 2178 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 2179 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 2180 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 2181 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 2182 2183 2184 /***********************************/ 2185 /* MC_CMD_DRV_ATTACH 2186 * Inform MCPU that this port is managed on the host (i.e. driver active). For 2187 * Huntington, also request the preferred datapath firmware to use if possible 2188 * (it may not be possible for this request to be fulfilled; the driver must 2189 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which 2190 * features are actually available). The FIRMWARE_ID field is ignored by older 2191 * platforms. 2192 */ 2193 #define MC_CMD_DRV_ATTACH 0x1c 2194 2195 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2196 2197 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 2198 #define MC_CMD_DRV_ATTACH_IN_LEN 12 2199 /* new state to set if UPDATE=1 */ 2200 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 2201 #define MC_CMD_DRV_ATTACH_LBN 0 2202 #define MC_CMD_DRV_ATTACH_WIDTH 1 2203 #define MC_CMD_DRV_PREBOOT_LBN 1 2204 #define MC_CMD_DRV_PREBOOT_WIDTH 1 2205 /* 1 to set new state, or 0 to just report the existing state */ 2206 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 2207 /* preferred datapath firmware (for Huntington; ignored for Siena) */ 2208 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 2209 /* enum: Prefer to use full featured firmware */ 2210 #define MC_CMD_FW_FULL_FEATURED 0x0 2211 /* enum: Prefer to use firmware with fewer features but lower latency */ 2212 #define MC_CMD_FW_LOW_LATENCY 0x1 2213 /* enum: Prefer to use firmware for SolarCapture packed stream mode */ 2214 #define MC_CMD_FW_PACKED_STREAM 0x2 2215 /* enum: Prefer to use firmware with fewer features and simpler TX event 2216 * batching but higher TX packet rate 2217 */ 2218 #define MC_CMD_FW_HIGH_TX_RATE 0x3 2219 /* enum: Reserved value */ 2220 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 2221 /* enum: Prefer to use firmware with additional "rules engine" filtering 2222 * support 2223 */ 2224 #define MC_CMD_FW_RULES_ENGINE 0x5 2225 /* enum: Only this option is allowed for non-admin functions */ 2226 #define MC_CMD_FW_DONT_CARE 0xffffffff 2227 2228 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 2229 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 2230 /* previous or existing state, see the bitmask at NEW_STATE */ 2231 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 2232 2233 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ 2234 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 2235 /* previous or existing state, see the bitmask at NEW_STATE */ 2236 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 2237 /* Flags associated with this function */ 2238 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 2239 /* enum: Labels the lowest-numbered function visible to the OS */ 2240 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 2241 /* enum: The function can control the link state of the physical port it is 2242 * bound to. 2243 */ 2244 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 2245 /* enum: The function can perform privileged operations */ 2246 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 2247 /* enum: The function does not have an active port associated with it. The port 2248 * refers to the Sorrento external FPGA port. 2249 */ 2250 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3 2251 2252 2253 /***********************************/ 2254 /* MC_CMD_SHMUART 2255 * Route UART output to circular buffer in shared memory instead. 2256 */ 2257 #define MC_CMD_SHMUART 0x1f 2258 2259 /* MC_CMD_SHMUART_IN msgrequest */ 2260 #define MC_CMD_SHMUART_IN_LEN 4 2261 /* ??? */ 2262 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 2263 2264 /* MC_CMD_SHMUART_OUT msgresponse */ 2265 #define MC_CMD_SHMUART_OUT_LEN 0 2266 2267 2268 /***********************************/ 2269 /* MC_CMD_PORT_RESET 2270 * Generic per-port reset. There is no equivalent for per-board reset. Locks 2271 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - 2272 * use MC_CMD_ENTITY_RESET instead. 2273 */ 2274 #define MC_CMD_PORT_RESET 0x20 2275 2276 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2277 2278 /* MC_CMD_PORT_RESET_IN msgrequest */ 2279 #define MC_CMD_PORT_RESET_IN_LEN 0 2280 2281 /* MC_CMD_PORT_RESET_OUT msgresponse */ 2282 #define MC_CMD_PORT_RESET_OUT_LEN 0 2283 2284 2285 /***********************************/ 2286 /* MC_CMD_ENTITY_RESET 2287 * Generic per-resource reset. There is no equivalent for per-board reset. 2288 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an 2289 * extended version of the deprecated MC_CMD_PORT_RESET with added fields. 2290 */ 2291 #define MC_CMD_ENTITY_RESET 0x20 2292 /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ 2293 2294 /* MC_CMD_ENTITY_RESET_IN msgrequest */ 2295 #define MC_CMD_ENTITY_RESET_IN_LEN 4 2296 /* Optional flags field. Omitting this will perform a "legacy" reset action 2297 * (TBD). 2298 */ 2299 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 2300 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 2301 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 2302 2303 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 2304 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 2305 2306 2307 /***********************************/ 2308 /* MC_CMD_PCIE_CREDITS 2309 * Read instantaneous and minimum flow control thresholds. 2310 */ 2311 #define MC_CMD_PCIE_CREDITS 0x21 2312 2313 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 2314 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 2315 /* poll period. 0 is disabled */ 2316 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 2317 /* wipe statistics */ 2318 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 2319 2320 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 2321 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 2322 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 2323 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 2324 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 2325 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 2326 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 2327 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 2328 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 2329 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 2330 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 2331 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 2332 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 2333 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 2334 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 2335 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 2336 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 2337 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 2338 2339 2340 /***********************************/ 2341 /* MC_CMD_RXD_MONITOR 2342 * Get histogram of RX queue fill level. 2343 */ 2344 #define MC_CMD_RXD_MONITOR 0x22 2345 2346 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 2347 #define MC_CMD_RXD_MONITOR_IN_LEN 12 2348 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 2349 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 2350 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 2351 2352 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 2353 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 2354 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 2355 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 2356 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 2357 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 2358 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 2359 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 2360 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 2361 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 2362 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 2363 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 2364 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 2365 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 2366 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 2367 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 2368 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 2369 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 2370 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 2371 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 2372 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 2373 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 2374 2375 2376 /***********************************/ 2377 /* MC_CMD_PUTS 2378 * Copy the given ASCII string out onto UART and/or out of the network port. 2379 */ 2380 #define MC_CMD_PUTS 0x23 2381 2382 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2383 2384 /* MC_CMD_PUTS_IN msgrequest */ 2385 #define MC_CMD_PUTS_IN_LENMIN 13 2386 #define MC_CMD_PUTS_IN_LENMAX 252 2387 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 2388 #define MC_CMD_PUTS_IN_DEST_OFST 0 2389 #define MC_CMD_PUTS_IN_UART_LBN 0 2390 #define MC_CMD_PUTS_IN_UART_WIDTH 1 2391 #define MC_CMD_PUTS_IN_PORT_LBN 1 2392 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 2393 #define MC_CMD_PUTS_IN_DHOST_OFST 4 2394 #define MC_CMD_PUTS_IN_DHOST_LEN 6 2395 #define MC_CMD_PUTS_IN_STRING_OFST 12 2396 #define MC_CMD_PUTS_IN_STRING_LEN 1 2397 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 2398 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 2399 2400 /* MC_CMD_PUTS_OUT msgresponse */ 2401 #define MC_CMD_PUTS_OUT_LEN 0 2402 2403 2404 /***********************************/ 2405 /* MC_CMD_GET_PHY_CFG 2406 * Report PHY configuration. This guarantees to succeed even if the PHY is in a 2407 * 'zombie' state. Locks required: None 2408 */ 2409 #define MC_CMD_GET_PHY_CFG 0x24 2410 2411 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2412 2413 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 2414 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 2415 2416 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 2417 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 2418 /* flags */ 2419 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 2420 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 2421 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 2422 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 2423 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 2424 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 2425 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 2426 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 2427 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 2428 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 2429 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 2430 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 2431 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 2432 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 2433 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 2434 /* ?? */ 2435 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 2436 /* Bitmask of supported capabilities */ 2437 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 2438 #define MC_CMD_PHY_CAP_10HDX_LBN 1 2439 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 2440 #define MC_CMD_PHY_CAP_10FDX_LBN 2 2441 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 2442 #define MC_CMD_PHY_CAP_100HDX_LBN 3 2443 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 2444 #define MC_CMD_PHY_CAP_100FDX_LBN 4 2445 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 2446 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 2447 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 2448 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 2449 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 2450 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 2451 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 2452 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 2453 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 2454 #define MC_CMD_PHY_CAP_ASYM_LBN 9 2455 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 2456 #define MC_CMD_PHY_CAP_AN_LBN 10 2457 #define MC_CMD_PHY_CAP_AN_WIDTH 1 2458 #define MC_CMD_PHY_CAP_40000FDX_LBN 11 2459 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 2460 #define MC_CMD_PHY_CAP_DDM_LBN 12 2461 #define MC_CMD_PHY_CAP_DDM_WIDTH 1 2462 /* ?? */ 2463 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 2464 /* ?? */ 2465 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 2466 /* ?? */ 2467 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 2468 /* ?? */ 2469 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 2470 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 2471 /* ?? */ 2472 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 2473 /* enum: Xaui. */ 2474 #define MC_CMD_MEDIA_XAUI 0x1 2475 /* enum: CX4. */ 2476 #define MC_CMD_MEDIA_CX4 0x2 2477 /* enum: KX4. */ 2478 #define MC_CMD_MEDIA_KX4 0x3 2479 /* enum: XFP Far. */ 2480 #define MC_CMD_MEDIA_XFP 0x4 2481 /* enum: SFP+. */ 2482 #define MC_CMD_MEDIA_SFP_PLUS 0x5 2483 /* enum: 10GBaseT. */ 2484 #define MC_CMD_MEDIA_BASE_T 0x6 2485 /* enum: QSFP+. */ 2486 #define MC_CMD_MEDIA_QSFP_PLUS 0x7 2487 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 2488 /* enum: Native clause 22 */ 2489 #define MC_CMD_MMD_CLAUSE22 0x0 2490 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 2491 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 2492 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 2493 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 2494 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 2495 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 2496 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 2497 /* enum: Clause22 proxied over clause45 by PHY. */ 2498 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d 2499 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 2500 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 2501 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 2502 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 2503 2504 2505 /***********************************/ 2506 /* MC_CMD_START_BIST 2507 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST 2508 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 2509 */ 2510 #define MC_CMD_START_BIST 0x25 2511 2512 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2513 2514 /* MC_CMD_START_BIST_IN msgrequest */ 2515 #define MC_CMD_START_BIST_IN_LEN 4 2516 /* Type of test. */ 2517 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 2518 /* enum: Run the PHY's short cable BIST. */ 2519 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 2520 /* enum: Run the PHY's long cable BIST. */ 2521 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 2522 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ 2523 #define MC_CMD_BPX_SERDES_BIST 0x3 2524 /* enum: Run the MC loopback tests. */ 2525 #define MC_CMD_MC_LOOPBACK_BIST 0x4 2526 /* enum: Run the PHY's standard BIST. */ 2527 #define MC_CMD_PHY_BIST 0x5 2528 /* enum: Run MC RAM test. */ 2529 #define MC_CMD_MC_MEM_BIST 0x6 2530 /* enum: Run Port RAM test. */ 2531 #define MC_CMD_PORT_MEM_BIST 0x7 2532 /* enum: Run register test. */ 2533 #define MC_CMD_REG_BIST 0x8 2534 2535 /* MC_CMD_START_BIST_OUT msgresponse */ 2536 #define MC_CMD_START_BIST_OUT_LEN 0 2537 2538 2539 /***********************************/ 2540 /* MC_CMD_POLL_BIST 2541 * Poll for BIST completion. Returns a single status code, and optionally some 2542 * PHY specific bist output. The driver should only consume the BIST output 2543 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't 2544 * successfully parse the BIST output, it should still respect the pass/Fail in 2545 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, 2546 * EACCES (if PHY_LOCK is not held). 2547 */ 2548 #define MC_CMD_POLL_BIST 0x26 2549 2550 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2551 2552 /* MC_CMD_POLL_BIST_IN msgrequest */ 2553 #define MC_CMD_POLL_BIST_IN_LEN 0 2554 2555 /* MC_CMD_POLL_BIST_OUT msgresponse */ 2556 #define MC_CMD_POLL_BIST_OUT_LEN 8 2557 /* result */ 2558 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 2559 /* enum: Running. */ 2560 #define MC_CMD_POLL_BIST_RUNNING 0x1 2561 /* enum: Passed. */ 2562 #define MC_CMD_POLL_BIST_PASSED 0x2 2563 /* enum: Failed. */ 2564 #define MC_CMD_POLL_BIST_FAILED 0x3 2565 /* enum: Timed-out. */ 2566 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 2567 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 2568 2569 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 2570 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 2571 /* result */ 2572 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 2573 /* Enum values, see field(s): */ 2574 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 2575 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 2576 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 2577 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 2578 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 2579 /* Status of each channel A */ 2580 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 2581 /* enum: Ok. */ 2582 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 2583 /* enum: Open. */ 2584 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 2585 /* enum: Intra-pair short. */ 2586 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 2587 /* enum: Inter-pair short. */ 2588 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 2589 /* enum: Busy. */ 2590 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 2591 /* Status of each channel B */ 2592 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 2593 /* Enum values, see field(s): */ 2594 /* CABLE_STATUS_A */ 2595 /* Status of each channel C */ 2596 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 2597 /* Enum values, see field(s): */ 2598 /* CABLE_STATUS_A */ 2599 /* Status of each channel D */ 2600 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 2601 /* Enum values, see field(s): */ 2602 /* CABLE_STATUS_A */ 2603 2604 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 2605 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 2606 /* result */ 2607 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 2608 /* Enum values, see field(s): */ 2609 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 2610 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 2611 /* enum: Complete. */ 2612 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 2613 /* enum: Bus switch off I2C write. */ 2614 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 2615 /* enum: Bus switch off I2C no access IO exp. */ 2616 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 2617 /* enum: Bus switch off I2C no access module. */ 2618 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 2619 /* enum: IO exp I2C configure. */ 2620 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 2621 /* enum: Bus switch I2C no cross talk. */ 2622 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 2623 /* enum: Module presence. */ 2624 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 2625 /* enum: Module ID I2C access. */ 2626 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 2627 /* enum: Module ID sane value. */ 2628 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 2629 2630 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ 2631 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 2632 /* result */ 2633 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 2634 /* Enum values, see field(s): */ 2635 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 2636 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 2637 /* enum: Test has completed. */ 2638 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 2639 /* enum: RAM test - walk ones. */ 2640 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 2641 /* enum: RAM test - walk zeros. */ 2642 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 2643 /* enum: RAM test - walking inversions zeros/ones. */ 2644 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 2645 /* enum: RAM test - walking inversions checkerboard. */ 2646 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 2647 /* enum: Register test - set / clear individual bits. */ 2648 #define MC_CMD_POLL_BIST_MEM_REG 0x5 2649 /* enum: ECC error detected. */ 2650 #define MC_CMD_POLL_BIST_MEM_ECC 0x6 2651 /* Failure address, only valid if result is POLL_BIST_FAILED */ 2652 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 2653 /* Bus or address space to which the failure address corresponds */ 2654 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 2655 /* enum: MC MIPS bus. */ 2656 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 2657 /* enum: CSR IREG bus. */ 2658 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 2659 /* enum: RX0 DPCPU bus. */ 2660 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 2661 /* enum: TX0 DPCPU bus. */ 2662 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 2663 /* enum: TX1 DPCPU bus. */ 2664 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 2665 /* enum: RX0 DICPU bus. */ 2666 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 2667 /* enum: TX DICPU bus. */ 2668 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 2669 /* enum: RX1 DPCPU bus. */ 2670 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7 2671 /* enum: RX1 DICPU bus. */ 2672 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8 2673 /* Pattern written to RAM / register */ 2674 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 2675 /* Actual value read from RAM / register */ 2676 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 2677 /* ECC error mask */ 2678 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 2679 /* ECC parity error mask */ 2680 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 2681 /* ECC fatal error mask */ 2682 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 2683 2684 2685 /***********************************/ 2686 /* MC_CMD_FLUSH_RX_QUEUES 2687 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 2688 * flushes should be initiated via this MCDI operation, rather than via 2689 * directly writing FLUSH_CMD. 2690 * 2691 * The flush is completed (either done/fail) asynchronously (after this command 2692 * returns). The driver must still wait for flush done/failure events as usual. 2693 */ 2694 #define MC_CMD_FLUSH_RX_QUEUES 0x27 2695 2696 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 2697 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 2698 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 2699 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 2700 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 2701 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 2702 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 2703 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 2704 2705 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 2706 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 2707 2708 2709 /***********************************/ 2710 /* MC_CMD_GET_LOOPBACK_MODES 2711 * Returns a bitmask of loopback modes available at each speed. 2712 */ 2713 #define MC_CMD_GET_LOOPBACK_MODES 0x28 2714 2715 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2716 2717 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 2718 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 2719 2720 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 2721 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 2722 /* Supported loopbacks. */ 2723 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 2724 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 2725 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 2726 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 2727 /* enum: None. */ 2728 #define MC_CMD_LOOPBACK_NONE 0x0 2729 /* enum: Data. */ 2730 #define MC_CMD_LOOPBACK_DATA 0x1 2731 /* enum: GMAC. */ 2732 #define MC_CMD_LOOPBACK_GMAC 0x2 2733 /* enum: XGMII. */ 2734 #define MC_CMD_LOOPBACK_XGMII 0x3 2735 /* enum: XGXS. */ 2736 #define MC_CMD_LOOPBACK_XGXS 0x4 2737 /* enum: XAUI. */ 2738 #define MC_CMD_LOOPBACK_XAUI 0x5 2739 /* enum: GMII. */ 2740 #define MC_CMD_LOOPBACK_GMII 0x6 2741 /* enum: SGMII. */ 2742 #define MC_CMD_LOOPBACK_SGMII 0x7 2743 /* enum: XGBR. */ 2744 #define MC_CMD_LOOPBACK_XGBR 0x8 2745 /* enum: XFI. */ 2746 #define MC_CMD_LOOPBACK_XFI 0x9 2747 /* enum: XAUI Far. */ 2748 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa 2749 /* enum: GMII Far. */ 2750 #define MC_CMD_LOOPBACK_GMII_FAR 0xb 2751 /* enum: SGMII Far. */ 2752 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc 2753 /* enum: XFI Far. */ 2754 #define MC_CMD_LOOPBACK_XFI_FAR 0xd 2755 /* enum: GPhy. */ 2756 #define MC_CMD_LOOPBACK_GPHY 0xe 2757 /* enum: PhyXS. */ 2758 #define MC_CMD_LOOPBACK_PHYXS 0xf 2759 /* enum: PCS. */ 2760 #define MC_CMD_LOOPBACK_PCS 0x10 2761 /* enum: PMA-PMD. */ 2762 #define MC_CMD_LOOPBACK_PMAPMD 0x11 2763 /* enum: Cross-Port. */ 2764 #define MC_CMD_LOOPBACK_XPORT 0x12 2765 /* enum: XGMII-Wireside. */ 2766 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 2767 /* enum: XAUI Wireside. */ 2768 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 2769 /* enum: XAUI Wireside Far. */ 2770 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 2771 /* enum: XAUI Wireside near. */ 2772 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 2773 /* enum: GMII Wireside. */ 2774 #define MC_CMD_LOOPBACK_GMII_WS 0x17 2775 /* enum: XFI Wireside. */ 2776 #define MC_CMD_LOOPBACK_XFI_WS 0x18 2777 /* enum: XFI Wireside Far. */ 2778 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 2779 /* enum: PhyXS Wireside. */ 2780 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a 2781 /* enum: PMA lanes MAC-Serdes. */ 2782 #define MC_CMD_LOOPBACK_PMA_INT 0x1b 2783 /* enum: KR Serdes Parallel (Encoder). */ 2784 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c 2785 /* enum: KR Serdes Serial. */ 2786 #define MC_CMD_LOOPBACK_SD_FAR 0x1d 2787 /* enum: PMA lanes MAC-Serdes Wireside. */ 2788 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e 2789 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 2790 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f 2791 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 2792 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 2793 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 2794 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 2795 /* enum: KR Serdes Serial Wireside. */ 2796 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 2797 /* enum: Near side of AOE Siena side port */ 2798 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 2799 /* enum: Medford Wireside datapath loopback */ 2800 #define MC_CMD_LOOPBACK_DATA_WS 0x24 2801 /* enum: Force link up without setting up any physical loopback (snapper use 2802 * only) 2803 */ 2804 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 2805 /* Supported loopbacks. */ 2806 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 2807 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 2808 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 2809 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 2810 /* Enum values, see field(s): */ 2811 /* 100M */ 2812 /* Supported loopbacks. */ 2813 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 2814 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 2815 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 2816 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 2817 /* Enum values, see field(s): */ 2818 /* 100M */ 2819 /* Supported loopbacks. */ 2820 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 2821 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 2822 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 2823 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 2824 /* Enum values, see field(s): */ 2825 /* 100M */ 2826 /* Supported loopbacks. */ 2827 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 2828 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 2829 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 2830 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 2831 /* Enum values, see field(s): */ 2832 /* 100M */ 2833 2834 2835 /***********************************/ 2836 /* MC_CMD_GET_LINK 2837 * Read the unified MAC/PHY link state. Locks required: None Return code: 0, 2838 * ETIME. 2839 */ 2840 #define MC_CMD_GET_LINK 0x29 2841 2842 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2843 2844 /* MC_CMD_GET_LINK_IN msgrequest */ 2845 #define MC_CMD_GET_LINK_IN_LEN 0 2846 2847 /* MC_CMD_GET_LINK_OUT msgresponse */ 2848 #define MC_CMD_GET_LINK_OUT_LEN 28 2849 /* near-side advertised capabilities */ 2850 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 2851 /* link-partner advertised capabilities */ 2852 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 2853 /* Autonegotiated speed in mbit/s. The link may still be down even if this 2854 * reads non-zero. 2855 */ 2856 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 2857 /* Current loopback setting. */ 2858 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 2859 /* Enum values, see field(s): */ 2860 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 2861 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 2862 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 2863 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 2864 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 2865 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 2866 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 2867 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 2868 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 2869 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 2870 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 2871 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 2872 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 2873 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 2874 /* This returns the negotiated flow control value. */ 2875 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 2876 /* Enum values, see field(s): */ 2877 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 2878 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 2879 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 2880 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 2881 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 2882 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 2883 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 2884 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 2885 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 2886 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 2887 2888 2889 /***********************************/ 2890 /* MC_CMD_SET_LINK 2891 * Write the unified MAC/PHY link configuration. Locks required: None. Return 2892 * code: 0, EINVAL, ETIME 2893 */ 2894 #define MC_CMD_SET_LINK 0x2a 2895 2896 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK 2897 2898 /* MC_CMD_SET_LINK_IN msgrequest */ 2899 #define MC_CMD_SET_LINK_IN_LEN 16 2900 /* ??? */ 2901 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 2902 /* Flags */ 2903 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 2904 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 2905 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 2906 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 2907 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 2908 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 2909 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 2910 /* Loopback mode. */ 2911 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 2912 /* Enum values, see field(s): */ 2913 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 2914 /* A loopback speed of "0" is supported, and means (choose any available 2915 * speed). 2916 */ 2917 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 2918 2919 /* MC_CMD_SET_LINK_OUT msgresponse */ 2920 #define MC_CMD_SET_LINK_OUT_LEN 0 2921 2922 2923 /***********************************/ 2924 /* MC_CMD_SET_ID_LED 2925 * Set identification LED state. Locks required: None. Return code: 0, EINVAL 2926 */ 2927 #define MC_CMD_SET_ID_LED 0x2b 2928 2929 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK 2930 2931 /* MC_CMD_SET_ID_LED_IN msgrequest */ 2932 #define MC_CMD_SET_ID_LED_IN_LEN 4 2933 /* Set LED state. */ 2934 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 2935 #define MC_CMD_LED_OFF 0x0 /* enum */ 2936 #define MC_CMD_LED_ON 0x1 /* enum */ 2937 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 2938 2939 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 2940 #define MC_CMD_SET_ID_LED_OUT_LEN 0 2941 2942 2943 /***********************************/ 2944 /* MC_CMD_SET_MAC 2945 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL 2946 */ 2947 #define MC_CMD_SET_MAC 0x2c 2948 2949 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2950 2951 /* MC_CMD_SET_MAC_IN msgrequest */ 2952 #define MC_CMD_SET_MAC_IN_LEN 28 2953 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 2954 * EtherII, VLAN, bug16011 padding). 2955 */ 2956 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 2957 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 2958 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 2959 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 2960 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 2961 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 2962 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 2963 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 2964 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 2965 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 2966 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 2967 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 2968 /* enum: Flow control is off. */ 2969 #define MC_CMD_FCNTL_OFF 0x0 2970 /* enum: Respond to flow control. */ 2971 #define MC_CMD_FCNTL_RESPOND 0x1 2972 /* enum: Respond to and Issue flow control. */ 2973 #define MC_CMD_FCNTL_BIDIR 0x2 2974 /* enum: Auto neg flow control. */ 2975 #define MC_CMD_FCNTL_AUTO 0x3 2976 /* enum: Priority flow control (eftest builds only). */ 2977 #define MC_CMD_FCNTL_QBB 0x4 2978 /* enum: Issue flow control. */ 2979 #define MC_CMD_FCNTL_GENERATE 0x5 2980 #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 2981 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 2982 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 2983 2984 /* MC_CMD_SET_MAC_EXT_IN msgrequest */ 2985 #define MC_CMD_SET_MAC_EXT_IN_LEN 32 2986 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 2987 * EtherII, VLAN, bug16011 padding). 2988 */ 2989 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0 2990 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4 2991 #define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8 2992 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8 2993 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8 2994 #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12 2995 #define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16 2996 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0 2997 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1 2998 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1 2999 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1 3000 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20 3001 /* enum: Flow control is off. */ 3002 /* MC_CMD_FCNTL_OFF 0x0 */ 3003 /* enum: Respond to flow control. */ 3004 /* MC_CMD_FCNTL_RESPOND 0x1 */ 3005 /* enum: Respond to and Issue flow control. */ 3006 /* MC_CMD_FCNTL_BIDIR 0x2 */ 3007 /* enum: Auto neg flow control. */ 3008 /* MC_CMD_FCNTL_AUTO 0x3 */ 3009 /* enum: Priority flow control (eftest builds only). */ 3010 /* MC_CMD_FCNTL_QBB 0x4 */ 3011 /* enum: Issue flow control. */ 3012 /* MC_CMD_FCNTL_GENERATE 0x5 */ 3013 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24 3014 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0 3015 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1 3016 /* Select which parameters to configure. A parameter will only be modified if 3017 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in 3018 * capabilities then this field is ignored (and all flags are assumed to be 3019 * set). 3020 */ 3021 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28 3022 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0 3023 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1 3024 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1 3025 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1 3026 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2 3027 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1 3028 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3 3029 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1 3030 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4 3031 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1 3032 3033 /* MC_CMD_SET_MAC_OUT msgresponse */ 3034 #define MC_CMD_SET_MAC_OUT_LEN 0 3035 3036 /* MC_CMD_SET_MAC_V2_OUT msgresponse */ 3037 #define MC_CMD_SET_MAC_V2_OUT_LEN 4 3038 /* MTU as configured after processing the request. See comment at 3039 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL 3040 * to 0. 3041 */ 3042 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0 3043 3044 3045 /***********************************/ 3046 /* MC_CMD_PHY_STATS 3047 * Get generic PHY statistics. This call returns the statistics for a generic 3048 * PHY in a sparse array (indexed by the enumerate). Each value is represented 3049 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the 3050 * statistics may be read from the message response. If DMA_ADDR != 0, then the 3051 * statistics are dmad to that (page-aligned location). Locks required: None. 3052 * Returns: 0, ETIME 3053 */ 3054 #define MC_CMD_PHY_STATS 0x2d 3055 3056 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK 3057 3058 /* MC_CMD_PHY_STATS_IN msgrequest */ 3059 #define MC_CMD_PHY_STATS_IN_LEN 8 3060 /* ??? */ 3061 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 3062 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 3063 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 3064 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 3065 3066 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 3067 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 3068 3069 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 3070 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 3071 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 3072 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 3073 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 3074 /* enum: OUI. */ 3075 #define MC_CMD_OUI 0x0 3076 /* enum: PMA-PMD Link Up. */ 3077 #define MC_CMD_PMA_PMD_LINK_UP 0x1 3078 /* enum: PMA-PMD RX Fault. */ 3079 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 3080 /* enum: PMA-PMD TX Fault. */ 3081 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 3082 /* enum: PMA-PMD Signal */ 3083 #define MC_CMD_PMA_PMD_SIGNAL 0x4 3084 /* enum: PMA-PMD SNR A. */ 3085 #define MC_CMD_PMA_PMD_SNR_A 0x5 3086 /* enum: PMA-PMD SNR B. */ 3087 #define MC_CMD_PMA_PMD_SNR_B 0x6 3088 /* enum: PMA-PMD SNR C. */ 3089 #define MC_CMD_PMA_PMD_SNR_C 0x7 3090 /* enum: PMA-PMD SNR D. */ 3091 #define MC_CMD_PMA_PMD_SNR_D 0x8 3092 /* enum: PCS Link Up. */ 3093 #define MC_CMD_PCS_LINK_UP 0x9 3094 /* enum: PCS RX Fault. */ 3095 #define MC_CMD_PCS_RX_FAULT 0xa 3096 /* enum: PCS TX Fault. */ 3097 #define MC_CMD_PCS_TX_FAULT 0xb 3098 /* enum: PCS BER. */ 3099 #define MC_CMD_PCS_BER 0xc 3100 /* enum: PCS Block Errors. */ 3101 #define MC_CMD_PCS_BLOCK_ERRORS 0xd 3102 /* enum: PhyXS Link Up. */ 3103 #define MC_CMD_PHYXS_LINK_UP 0xe 3104 /* enum: PhyXS RX Fault. */ 3105 #define MC_CMD_PHYXS_RX_FAULT 0xf 3106 /* enum: PhyXS TX Fault. */ 3107 #define MC_CMD_PHYXS_TX_FAULT 0x10 3108 /* enum: PhyXS Align. */ 3109 #define MC_CMD_PHYXS_ALIGN 0x11 3110 /* enum: PhyXS Sync. */ 3111 #define MC_CMD_PHYXS_SYNC 0x12 3112 /* enum: AN link-up. */ 3113 #define MC_CMD_AN_LINK_UP 0x13 3114 /* enum: AN Complete. */ 3115 #define MC_CMD_AN_COMPLETE 0x14 3116 /* enum: AN 10GBaseT Status. */ 3117 #define MC_CMD_AN_10GBT_STATUS 0x15 3118 /* enum: Clause 22 Link-Up. */ 3119 #define MC_CMD_CL22_LINK_UP 0x16 3120 /* enum: (Last entry) */ 3121 #define MC_CMD_PHY_NSTATS 0x17 3122 3123 3124 /***********************************/ 3125 /* MC_CMD_MAC_STATS 3126 * Get generic MAC statistics. This call returns unified statistics maintained 3127 * by the MC as it switches between the GMAC and XMAC. The MC will write out 3128 * all supported stats. The driver should zero initialise the buffer to 3129 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is 3130 * performed, and the statistics may be read from the message response. If 3131 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). 3132 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no 3133 * effect. Returns: 0, ETIME 3134 */ 3135 #define MC_CMD_MAC_STATS 0x2e 3136 3137 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3138 3139 /* MC_CMD_MAC_STATS_IN msgrequest */ 3140 #define MC_CMD_MAC_STATS_IN_LEN 20 3141 /* ??? */ 3142 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 3143 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 3144 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 3145 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 3146 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 3147 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 3148 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 3149 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 3150 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 3151 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 3152 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 3153 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 3154 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 3155 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 3156 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 3157 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 3158 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 3159 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 3160 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 3161 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 3162 /* port id so vadapter stats can be provided */ 3163 #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 3164 3165 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 3166 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 3167 3168 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 3169 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 3170 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 3171 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 3172 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 3173 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 3174 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 3175 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 3176 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ 3177 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 3178 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 3179 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 3180 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 3181 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 3182 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 3183 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 3184 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 3185 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 3186 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 3187 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 3188 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 3189 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 3190 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 3191 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 3192 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 3193 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 3194 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 3195 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 3196 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 3197 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 3198 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 3199 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 3200 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 3201 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 3202 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 3203 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 3204 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 3205 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 3206 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 3207 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 3208 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 3209 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 3210 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 3211 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 3212 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 3213 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 3214 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 3215 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 3216 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 3217 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 3218 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 3219 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 3220 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 3221 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 3222 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 3223 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 3224 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 3225 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 3226 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 3227 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 3228 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 3229 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 3230 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 3231 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 3232 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 3233 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 3234 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 3235 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 3236 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3237 * capability only. 3238 */ 3239 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c 3240 /* enum: PM discard_bb_overflow counter. Valid for EF10 with 3241 * PM_AND_RXDP_COUNTERS capability only. 3242 */ 3243 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d 3244 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3245 * capability only. 3246 */ 3247 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e 3248 /* enum: PM discard_vfifo_full counter. Valid for EF10 with 3249 * PM_AND_RXDP_COUNTERS capability only. 3250 */ 3251 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f 3252 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3253 * capability only. 3254 */ 3255 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40 3256 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3257 * capability only. 3258 */ 3259 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41 3260 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 3261 * capability only. 3262 */ 3263 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 3264 /* enum: RXDP counter: Number of packets dropped due to the queue being 3265 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 3266 */ 3267 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 3268 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 3269 * with PM_AND_RXDP_COUNTERS capability only. 3270 */ 3271 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 3272 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with 3273 * PM_AND_RXDP_COUNTERS capability only. 3274 */ 3275 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 3276 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed. 3277 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 3278 */ 3279 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 3280 /* enum: RXDP counter: Number of times the DPCPU waited for an existing 3281 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 3282 */ 3283 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 3284 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */ 3285 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */ 3286 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */ 3287 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */ 3288 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */ 3289 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */ 3290 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */ 3291 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */ 3292 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */ 3293 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */ 3294 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */ 3295 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */ 3296 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */ 3297 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */ 3298 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */ 3299 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */ 3300 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */ 3301 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */ 3302 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */ 3303 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */ 3304 /* enum: Start of GMAC stats buffer space, for Siena only. */ 3305 #define MC_CMD_GMAC_DMABUF_START 0x40 3306 /* enum: End of GMAC stats buffer space, for Siena only. */ 3307 #define MC_CMD_GMAC_DMABUF_END 0x5f 3308 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ 3309 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 3310 3311 3312 /***********************************/ 3313 /* MC_CMD_SRIOV 3314 * to be documented 3315 */ 3316 #define MC_CMD_SRIOV 0x30 3317 3318 /* MC_CMD_SRIOV_IN msgrequest */ 3319 #define MC_CMD_SRIOV_IN_LEN 12 3320 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 3321 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 3322 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 3323 3324 /* MC_CMD_SRIOV_OUT msgresponse */ 3325 #define MC_CMD_SRIOV_OUT_LEN 8 3326 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 3327 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 3328 3329 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 3330 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 3331 /* this is only used for the first record */ 3332 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 3333 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 3334 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 3335 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 3336 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 3337 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 3338 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 3339 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 3340 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 3341 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 3342 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 3343 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 3344 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 3345 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 3346 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 3347 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 3348 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 3349 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 3350 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 3351 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 3352 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 3353 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 3354 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 3355 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 3356 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 3357 3358 3359 /***********************************/ 3360 /* MC_CMD_MEMCPY 3361 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 3362 * embedded directly in the command. 3363 * 3364 * A common pattern is for a client to use generation counts to signal a dma 3365 * update of a datastructure. To facilitate this, this MCDI operation can 3366 * contain multiple requests which are executed in strict order. Requests take 3367 * the form of duplicating the entire MCDI request continuously (including the 3368 * requests record, which is ignored in all but the first structure) 3369 * 3370 * The source data can either come from a DMA from the host, or it can be 3371 * embedded within the request directly, thereby eliminating a DMA read. To 3372 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 3373 * ADDR_LO=offset, and inserts the data at %offset from the start of the 3374 * payload. It's the callers responsibility to ensure that the embedded data 3375 * doesn't overlap the records. 3376 * 3377 * Returns: 0, EINVAL (invalid RID) 3378 */ 3379 #define MC_CMD_MEMCPY 0x31 3380 3381 /* MC_CMD_MEMCPY_IN msgrequest */ 3382 #define MC_CMD_MEMCPY_IN_LENMIN 32 3383 #define MC_CMD_MEMCPY_IN_LENMAX 224 3384 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 3385 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 3386 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 3387 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 3388 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 3389 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 3390 3391 /* MC_CMD_MEMCPY_OUT msgresponse */ 3392 #define MC_CMD_MEMCPY_OUT_LEN 0 3393 3394 3395 /***********************************/ 3396 /* MC_CMD_WOL_FILTER_SET 3397 * Set a WoL filter. 3398 */ 3399 #define MC_CMD_WOL_FILTER_SET 0x32 3400 3401 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK 3402 3403 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 3404 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 3405 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 3406 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 3407 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 3408 /* A type value of 1 is unused. */ 3409 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 3410 /* enum: Magic */ 3411 #define MC_CMD_WOL_TYPE_MAGIC 0x0 3412 /* enum: MS Windows Magic */ 3413 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 3414 /* enum: IPv4 Syn */ 3415 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 3416 /* enum: IPv6 Syn */ 3417 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 3418 /* enum: Bitmap */ 3419 #define MC_CMD_WOL_TYPE_BITMAP 0x5 3420 /* enum: Link */ 3421 #define MC_CMD_WOL_TYPE_LINK 0x6 3422 /* enum: (Above this for future use) */ 3423 #define MC_CMD_WOL_TYPE_MAX 0x7 3424 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 3425 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 3426 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 3427 3428 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 3429 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 3430 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3431 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3432 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 3433 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 3434 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 3435 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 3436 3437 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 3438 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 3439 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3440 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3441 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 3442 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 3443 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 3444 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 3445 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 3446 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 3447 3448 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 3449 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 3450 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3451 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3452 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 3453 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 3454 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 3455 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 3456 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 3457 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 3458 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 3459 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 3460 3461 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 3462 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 3463 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3464 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3465 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 3466 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 3467 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 3468 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 3469 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 3470 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 3471 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 3472 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 3473 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 3474 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 3475 3476 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 3477 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 3478 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3479 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3480 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 3481 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 3482 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 3483 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 3484 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 3485 3486 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 3487 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 3488 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 3489 3490 3491 /***********************************/ 3492 /* MC_CMD_WOL_FILTER_REMOVE 3493 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS 3494 */ 3495 #define MC_CMD_WOL_FILTER_REMOVE 0x33 3496 3497 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK 3498 3499 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 3500 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 3501 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 3502 3503 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 3504 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 3505 3506 3507 /***********************************/ 3508 /* MC_CMD_WOL_FILTER_RESET 3509 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, 3510 * ENOSYS 3511 */ 3512 #define MC_CMD_WOL_FILTER_RESET 0x34 3513 3514 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK 3515 3516 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 3517 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 3518 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 3519 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 3520 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 3521 3522 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 3523 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 3524 3525 3526 /***********************************/ 3527 /* MC_CMD_SET_MCAST_HASH 3528 * Set the MCAST hash value without otherwise reconfiguring the MAC 3529 */ 3530 #define MC_CMD_SET_MCAST_HASH 0x35 3531 3532 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 3533 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 3534 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 3535 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 3536 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 3537 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 3538 3539 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 3540 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 3541 3542 3543 /***********************************/ 3544 /* MC_CMD_NVRAM_TYPES 3545 * Return bitfield indicating available types of virtual NVRAM partitions. 3546 * Locks required: none. Returns: 0 3547 */ 3548 #define MC_CMD_NVRAM_TYPES 0x36 3549 3550 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3551 3552 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 3553 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 3554 3555 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 3556 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 3557 /* Bit mask of supported types. */ 3558 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 3559 /* enum: Disabled callisto. */ 3560 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 3561 /* enum: MC firmware. */ 3562 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 3563 /* enum: MC backup firmware. */ 3564 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 3565 /* enum: Static configuration Port0. */ 3566 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 3567 /* enum: Static configuration Port1. */ 3568 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 3569 /* enum: Dynamic configuration Port0. */ 3570 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 3571 /* enum: Dynamic configuration Port1. */ 3572 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 3573 /* enum: Expansion Rom. */ 3574 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 3575 /* enum: Expansion Rom Configuration Port0. */ 3576 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 3577 /* enum: Expansion Rom Configuration Port1. */ 3578 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 3579 /* enum: Phy Configuration Port0. */ 3580 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa 3581 /* enum: Phy Configuration Port1. */ 3582 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb 3583 /* enum: Log. */ 3584 #define MC_CMD_NVRAM_TYPE_LOG 0xc 3585 /* enum: FPGA image. */ 3586 #define MC_CMD_NVRAM_TYPE_FPGA 0xd 3587 /* enum: FPGA backup image */ 3588 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe 3589 /* enum: FC firmware. */ 3590 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf 3591 /* enum: FC backup firmware. */ 3592 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 3593 /* enum: CPLD image. */ 3594 #define MC_CMD_NVRAM_TYPE_CPLD 0x11 3595 /* enum: Licensing information. */ 3596 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 3597 /* enum: FC Log. */ 3598 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 3599 /* enum: Additional flash on FPGA. */ 3600 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 3601 3602 3603 /***********************************/ 3604 /* MC_CMD_NVRAM_INFO 3605 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, 3606 * EINVAL (bad type). 3607 */ 3608 #define MC_CMD_NVRAM_INFO 0x37 3609 3610 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3611 3612 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 3613 #define MC_CMD_NVRAM_INFO_IN_LEN 4 3614 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 3615 /* Enum values, see field(s): */ 3616 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3617 3618 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 3619 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 3620 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 3621 /* Enum values, see field(s): */ 3622 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3623 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 3624 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 3625 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 3626 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 3627 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 3628 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 3629 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 3630 #define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6 3631 #define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1 3632 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 3633 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 3634 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 3635 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 3636 3637 /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */ 3638 #define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28 3639 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0 3640 /* Enum values, see field(s): */ 3641 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3642 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4 3643 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8 3644 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12 3645 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0 3646 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1 3647 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1 3648 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1 3649 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7 3650 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1 3651 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16 3652 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20 3653 /* Writes must be multiples of this size. Added to support the MUM on Sorrento. 3654 */ 3655 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24 3656 3657 3658 /***********************************/ 3659 /* MC_CMD_NVRAM_UPDATE_START 3660 * Start a group of update operations on a virtual NVRAM partition. Locks 3661 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if 3662 * PHY_LOCK required and not held). 3663 */ 3664 #define MC_CMD_NVRAM_UPDATE_START 0x38 3665 3666 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3667 3668 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request. 3669 * Use NVRAM_UPDATE_START_V2_IN in new code 3670 */ 3671 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 3672 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 3673 /* Enum values, see field(s): */ 3674 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3675 3676 /* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START 3677 * request with additional flags indicating version of command in use. See 3678 * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use 3679 * paired up with NVRAM_UPDATE_FINISH_V2_IN. 3680 */ 3681 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8 3682 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0 3683 /* Enum values, see field(s): */ 3684 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3685 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4 3686 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 3687 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 3688 3689 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 3690 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 3691 3692 3693 /***********************************/ 3694 /* MC_CMD_NVRAM_READ 3695 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if 3696 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 3697 * PHY_LOCK required and not held) 3698 */ 3699 #define MC_CMD_NVRAM_READ 0x39 3700 3701 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3702 3703 /* MC_CMD_NVRAM_READ_IN msgrequest */ 3704 #define MC_CMD_NVRAM_READ_IN_LEN 12 3705 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 3706 /* Enum values, see field(s): */ 3707 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3708 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 3709 /* amount to read in bytes */ 3710 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 3711 3712 /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ 3713 #define MC_CMD_NVRAM_READ_IN_V2_LEN 16 3714 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 3715 /* Enum values, see field(s): */ 3716 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3717 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 3718 /* amount to read in bytes */ 3719 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 3720 /* Optional control info. If a partition is stored with an A/B versioning 3721 * scheme (i.e. in more than one physical partition in NVRAM) the host can set 3722 * this to control which underlying physical partition is used to read data 3723 * from. This allows it to perform a read-modify-write-verify with the write 3724 * lock continuously held by calling NVRAM_UPDATE_START, reading the old 3725 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then 3726 * verifying by reading with MODE=TARGET_BACKUP. 3727 */ 3728 #define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 3729 /* enum: Same as omitting MODE: caller sees data in current partition unless it 3730 * holds the write lock in which case it sees data in the partition it is 3731 * updating. 3732 */ 3733 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0 3734 /* enum: Read from the current partition of an A/B pair, even if holding the 3735 * write lock. 3736 */ 3737 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1 3738 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B 3739 * pair 3740 */ 3741 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2 3742 3743 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 3744 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 3745 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 3746 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 3747 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 3748 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 3749 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 3750 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 3751 3752 3753 /***********************************/ 3754 /* MC_CMD_NVRAM_WRITE 3755 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if 3756 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 3757 * PHY_LOCK required and not held) 3758 */ 3759 #define MC_CMD_NVRAM_WRITE 0x3a 3760 3761 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3762 3763 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 3764 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 3765 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 3766 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 3767 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 3768 /* Enum values, see field(s): */ 3769 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3770 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 3771 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 3772 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 3773 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 3774 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 3775 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 3776 3777 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 3778 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 3779 3780 3781 /***********************************/ 3782 /* MC_CMD_NVRAM_ERASE 3783 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if 3784 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 3785 * PHY_LOCK required and not held) 3786 */ 3787 #define MC_CMD_NVRAM_ERASE 0x3b 3788 3789 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3790 3791 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 3792 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 3793 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 3794 /* Enum values, see field(s): */ 3795 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3796 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 3797 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 3798 3799 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 3800 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 3801 3802 3803 /***********************************/ 3804 /* MC_CMD_NVRAM_UPDATE_FINISH 3805 * Finish a group of update operations on a virtual NVRAM partition. Locks 3806 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad 3807 * type/offset/length), EACCES (if PHY_LOCK required and not held) 3808 */ 3809 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 3810 3811 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3812 3813 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH 3814 * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code 3815 */ 3816 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 3817 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 3818 /* Enum values, see field(s): */ 3819 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3820 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 3821 3822 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH 3823 * request with additional flags indicating version of NVRAM_UPDATE commands in 3824 * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended 3825 * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN. 3826 */ 3827 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12 3828 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0 3829 /* Enum values, see field(s): */ 3830 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3831 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4 3832 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8 3833 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 3834 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 3835 3836 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH 3837 * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code 3838 */ 3839 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 3840 3841 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse: 3842 * 3843 * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure 3844 * firmware validation where applicable back to the host. 3845 * 3846 * Medford only: For signed firmware images, such as those for medford, the MC 3847 * firmware verifies the signature before marking the firmware image as valid. 3848 * This process takes a few seconds to complete. So is likely to take more than 3849 * the MCDI timeout. Hence signature verification is initiated when 3850 * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the 3851 * MCDI command returns immediately with error code EAGAIN. Subsequent 3852 * NVRAM_UPDATE_FINISH_V2_IN requests also return EAGAIN if the verification is 3853 * in progress. Once the verification has completed, this response payload 3854 * includes the results of the signature verification. Note that the nvram lock 3855 * in firmware is only released after the verification has completed and the 3856 * host has read back the result code from firmware. 3857 */ 3858 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4 3859 /* Result of nvram update completion processing */ 3860 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0 3861 /* enum: Verify succeeded without any errors. */ 3862 #define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1 3863 /* enum: CMS format verification failed due to an internal error. */ 3864 #define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2 3865 /* enum: Invalid CMS format in image metadata. */ 3866 #define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3 3867 /* enum: Message digest verification failed due to an internal error. */ 3868 #define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4 3869 /* enum: Error in message digest calculated over the reflash-header, payload 3870 * and reflash-trailer. 3871 */ 3872 #define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5 3873 /* enum: Signature verification failed due to an internal error. */ 3874 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6 3875 /* enum: There are no valid signatures in the image. */ 3876 #define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7 3877 /* enum: Trusted approvers verification failed due to an internal error. */ 3878 #define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8 3879 /* enum: The Trusted approver's list is empty. */ 3880 #define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9 3881 /* enum: Signature chain verification failed due to an internal error. */ 3882 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa 3883 /* enum: The signers of the signatures in the image are not listed in the 3884 * Trusted approver's list. 3885 */ 3886 #define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb 3887 3888 3889 /***********************************/ 3890 /* MC_CMD_REBOOT 3891 * Reboot the MC. 3892 * 3893 * The AFTER_ASSERTION flag is intended to be used when the driver notices an 3894 * assertion failure (at which point it is expected to perform a complete tear 3895 * down and reinitialise), to allow both ports to reset the MC once in an 3896 * atomic fashion. 3897 * 3898 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 3899 * which means that they will automatically reboot out of the assertion 3900 * handler, so this is in practise an optional operation. It is still 3901 * recommended that drivers execute this to support custom firmwares with 3902 * REBOOT_ON_ASSERT=0. 3903 * 3904 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, 3905 * DATALEN=0 3906 */ 3907 #define MC_CMD_REBOOT 0x3d 3908 3909 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3910 3911 /* MC_CMD_REBOOT_IN msgrequest */ 3912 #define MC_CMD_REBOOT_IN_LEN 4 3913 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 3914 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 3915 3916 /* MC_CMD_REBOOT_OUT msgresponse */ 3917 #define MC_CMD_REBOOT_OUT_LEN 0 3918 3919 3920 /***********************************/ 3921 /* MC_CMD_SCHEDINFO 3922 * Request scheduler info. Locks required: NONE. Returns: An array of 3923 * (timeslice,maximum overrun), one for each thread, in ascending order of 3924 * thread address. 3925 */ 3926 #define MC_CMD_SCHEDINFO 0x3e 3927 3928 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3929 3930 /* MC_CMD_SCHEDINFO_IN msgrequest */ 3931 #define MC_CMD_SCHEDINFO_IN_LEN 0 3932 3933 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 3934 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 3935 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 3936 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 3937 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 3938 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 3939 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 3940 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 3941 3942 3943 /***********************************/ 3944 /* MC_CMD_REBOOT_MODE 3945 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 3946 * mode to the specified value. Returns the old mode. 3947 */ 3948 #define MC_CMD_REBOOT_MODE 0x3f 3949 3950 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3951 3952 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 3953 #define MC_CMD_REBOOT_MODE_IN_LEN 4 3954 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 3955 /* enum: Normal. */ 3956 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 3957 /* enum: Power-on Reset. */ 3958 #define MC_CMD_REBOOT_MODE_POR 0x2 3959 /* enum: Snapper. */ 3960 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 3961 /* enum: snapper fake POR */ 3962 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 3963 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 3964 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 3965 3966 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 3967 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 3968 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 3969 3970 3971 /***********************************/ 3972 /* MC_CMD_SENSOR_INFO 3973 * Returns information about every available sensor. 3974 * 3975 * Each sensor has a single (16bit) value, and a corresponding state. The 3976 * mapping between value and state is nominally determined by the MC, but may 3977 * be implemented using up to 2 ranges per sensor. 3978 * 3979 * This call returns a mask (32bit) of the sensors that are supported by this 3980 * platform, then an array of sensor information structures, in order of sensor 3981 * type (but without gaps for unimplemented sensors). Each structure defines 3982 * the ranges for the corresponding sensor. An unused range is indicated by 3983 * equal limit values. If one range is used, a value outside that range results 3984 * in STATE_FATAL. If two ranges are used, a value outside the second range 3985 * results in STATE_FATAL while a value outside the first and inside the second 3986 * range results in STATE_WARNING. 3987 * 3988 * Sensor masks and sensor information arrays are organised into pages. For 3989 * backward compatibility, older host software can only use sensors in page 0. 3990 * Bit 32 in the sensor mask was previously unused, and is no reserved for use 3991 * as the next page flag. 3992 * 3993 * If the request does not contain a PAGE value then firmware will only return 3994 * page 0 of sensor information, with bit 31 in the sensor mask cleared. 3995 * 3996 * If the request contains a PAGE value then firmware responds with the sensor 3997 * mask and sensor information array for that page of sensors. In this case bit 3998 * 31 in the mask is set if another page exists. 3999 * 4000 * Locks required: None Returns: 0 4001 */ 4002 #define MC_CMD_SENSOR_INFO 0x41 4003 4004 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4005 4006 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 4007 #define MC_CMD_SENSOR_INFO_IN_LEN 0 4008 4009 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ 4010 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 4011 /* Which page of sensors to report. 4012 * 4013 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 4014 * 4015 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 4016 */ 4017 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 4018 4019 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 4020 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 4021 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 4022 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 4023 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 4024 /* enum: Controller temperature: degC */ 4025 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 4026 /* enum: Phy common temperature: degC */ 4027 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 4028 /* enum: Controller cooling: bool */ 4029 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 4030 /* enum: Phy 0 temperature: degC */ 4031 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 4032 /* enum: Phy 0 cooling: bool */ 4033 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 4034 /* enum: Phy 1 temperature: degC */ 4035 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 4036 /* enum: Phy 1 cooling: bool */ 4037 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 4038 /* enum: 1.0v power: mV */ 4039 #define MC_CMD_SENSOR_IN_1V0 0x7 4040 /* enum: 1.2v power: mV */ 4041 #define MC_CMD_SENSOR_IN_1V2 0x8 4042 /* enum: 1.8v power: mV */ 4043 #define MC_CMD_SENSOR_IN_1V8 0x9 4044 /* enum: 2.5v power: mV */ 4045 #define MC_CMD_SENSOR_IN_2V5 0xa 4046 /* enum: 3.3v power: mV */ 4047 #define MC_CMD_SENSOR_IN_3V3 0xb 4048 /* enum: 12v power: mV */ 4049 #define MC_CMD_SENSOR_IN_12V0 0xc 4050 /* enum: 1.2v analogue power: mV */ 4051 #define MC_CMD_SENSOR_IN_1V2A 0xd 4052 /* enum: reference voltage: mV */ 4053 #define MC_CMD_SENSOR_IN_VREF 0xe 4054 /* enum: AOE FPGA power: mV */ 4055 #define MC_CMD_SENSOR_OUT_VAOE 0xf 4056 /* enum: AOE FPGA temperature: degC */ 4057 #define MC_CMD_SENSOR_AOE_TEMP 0x10 4058 /* enum: AOE FPGA PSU temperature: degC */ 4059 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 4060 /* enum: AOE PSU temperature: degC */ 4061 #define MC_CMD_SENSOR_PSU_TEMP 0x12 4062 /* enum: Fan 0 speed: RPM */ 4063 #define MC_CMD_SENSOR_FAN_0 0x13 4064 /* enum: Fan 1 speed: RPM */ 4065 #define MC_CMD_SENSOR_FAN_1 0x14 4066 /* enum: Fan 2 speed: RPM */ 4067 #define MC_CMD_SENSOR_FAN_2 0x15 4068 /* enum: Fan 3 speed: RPM */ 4069 #define MC_CMD_SENSOR_FAN_3 0x16 4070 /* enum: Fan 4 speed: RPM */ 4071 #define MC_CMD_SENSOR_FAN_4 0x17 4072 /* enum: AOE FPGA input power: mV */ 4073 #define MC_CMD_SENSOR_IN_VAOE 0x18 4074 /* enum: AOE FPGA current: mA */ 4075 #define MC_CMD_SENSOR_OUT_IAOE 0x19 4076 /* enum: AOE FPGA input current: mA */ 4077 #define MC_CMD_SENSOR_IN_IAOE 0x1a 4078 /* enum: NIC power consumption: W */ 4079 #define MC_CMD_SENSOR_NIC_POWER 0x1b 4080 /* enum: 0.9v power voltage: mV */ 4081 #define MC_CMD_SENSOR_IN_0V9 0x1c 4082 /* enum: 0.9v power current: mA */ 4083 #define MC_CMD_SENSOR_IN_I0V9 0x1d 4084 /* enum: 1.2v power current: mA */ 4085 #define MC_CMD_SENSOR_IN_I1V2 0x1e 4086 /* enum: Not a sensor: reserved for the next page flag */ 4087 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f 4088 /* enum: 0.9v power voltage (at ADC): mV */ 4089 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 4090 /* enum: Controller temperature 2: degC */ 4091 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 4092 /* enum: Voltage regulator internal temperature: degC */ 4093 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 4094 /* enum: 0.9V voltage regulator temperature: degC */ 4095 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 4096 /* enum: 1.2V voltage regulator temperature: degC */ 4097 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 4098 /* enum: controller internal temperature sensor voltage (internal ADC): mV */ 4099 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 4100 /* enum: controller internal temperature (internal ADC): degC */ 4101 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 4102 /* enum: controller internal temperature sensor voltage (external ADC): mV */ 4103 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 4104 /* enum: controller internal temperature (external ADC): degC */ 4105 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 4106 /* enum: ambient temperature: degC */ 4107 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 4108 /* enum: air flow: bool */ 4109 #define MC_CMD_SENSOR_AIRFLOW 0x2a 4110 /* enum: voltage between VSS08D and VSS08D at CSR: mV */ 4111 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b 4112 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ 4113 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c 4114 /* enum: Hotpoint temperature: degC */ 4115 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d 4116 /* enum: Port 0 PHY power switch over-current: bool */ 4117 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e 4118 /* enum: Port 1 PHY power switch over-current: bool */ 4119 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f 4120 /* enum: Mop-up microcontroller reference voltage (millivolts) */ 4121 #define MC_CMD_SENSOR_MUM_VCC 0x30 4122 /* enum: 0.9v power phase A voltage: mV */ 4123 #define MC_CMD_SENSOR_IN_0V9_A 0x31 4124 /* enum: 0.9v power phase A current: mA */ 4125 #define MC_CMD_SENSOR_IN_I0V9_A 0x32 4126 /* enum: 0.9V voltage regulator phase A temperature: degC */ 4127 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 4128 /* enum: 0.9v power phase B voltage: mV */ 4129 #define MC_CMD_SENSOR_IN_0V9_B 0x34 4130 /* enum: 0.9v power phase B current: mA */ 4131 #define MC_CMD_SENSOR_IN_I0V9_B 0x35 4132 /* enum: 0.9V voltage regulator phase B temperature: degC */ 4133 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 4134 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ 4135 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 4136 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */ 4137 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 4138 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ 4139 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 4140 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */ 4141 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a 4142 /* enum: CCOM RTS temperature: degC */ 4143 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b 4144 /* enum: Not a sensor: reserved for the next page flag */ 4145 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f 4146 /* enum: controller internal temperature sensor voltage on master core 4147 * (internal ADC): mV 4148 */ 4149 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 4150 /* enum: controller internal temperature on master core (internal ADC): degC */ 4151 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 4152 /* enum: controller internal temperature sensor voltage on master core 4153 * (external ADC): mV 4154 */ 4155 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 4156 /* enum: controller internal temperature on master core (external ADC): degC */ 4157 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 4158 /* enum: controller internal temperature on slave core sensor voltage (internal 4159 * ADC): mV 4160 */ 4161 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 4162 /* enum: controller internal temperature on slave core (internal ADC): degC */ 4163 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 4164 /* enum: controller internal temperature on slave core sensor voltage (external 4165 * ADC): mV 4166 */ 4167 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 4168 /* enum: controller internal temperature on slave core (external ADC): degC */ 4169 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 4170 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */ 4171 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49 4172 /* enum: Temperature of SODIMM 0 (if installed): degC */ 4173 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a 4174 /* enum: Temperature of SODIMM 1 (if installed): degC */ 4175 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b 4176 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ 4177 #define MC_CMD_SENSOR_PHY0_VCC 0x4c 4178 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ 4179 #define MC_CMD_SENSOR_PHY1_VCC 0x4d 4180 /* enum: Controller die temperature (TDIODE): degC */ 4181 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e 4182 /* enum: Board temperature (front): degC */ 4183 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f 4184 /* enum: Board temperature (back): degC */ 4185 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50 4186 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 4187 #define MC_CMD_SENSOR_ENTRY_OFST 4 4188 #define MC_CMD_SENSOR_ENTRY_LEN 8 4189 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 4190 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 4191 #define MC_CMD_SENSOR_ENTRY_MINNUM 0 4192 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 4193 4194 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ 4195 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 4196 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 4197 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) 4198 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 4199 /* Enum values, see field(s): */ 4200 /* MC_CMD_SENSOR_INFO_OUT */ 4201 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 4202 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 4203 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 4204 /* MC_CMD_SENSOR_ENTRY_OFST 4 */ 4205 /* MC_CMD_SENSOR_ENTRY_LEN 8 */ 4206 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ 4207 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ 4208 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ 4209 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ 4210 4211 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 4212 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 4213 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 4214 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 4215 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 4216 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 4217 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 4218 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 4219 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 4220 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 4221 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 4222 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 4223 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 4224 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 4225 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 4226 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 4227 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 4228 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 4229 4230 4231 /***********************************/ 4232 /* MC_CMD_READ_SENSORS 4233 * Returns the current reading from each sensor. DMAs an array of sensor 4234 * readings, in order of sensor type (but without gaps for unimplemented 4235 * sensors), into host memory. Each array element is a 4236 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. 4237 * 4238 * If the request does not contain the LENGTH field then only sensors 0 to 30 4239 * are reported, to avoid DMA buffer overflow in older host software. If the 4240 * sensor reading require more space than the LENGTH allows, then return 4241 * EINVAL. 4242 * 4243 * The MC will send a SENSOREVT event every time any sensor changes state. The 4244 * driver is responsible for ensuring that it doesn't miss any events. The 4245 * board will function normally if all sensors are in STATE_OK or 4246 * STATE_WARNING. Otherwise the board should not be expected to function. 4247 */ 4248 #define MC_CMD_READ_SENSORS 0x42 4249 4250 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4251 4252 /* MC_CMD_READ_SENSORS_IN msgrequest */ 4253 #define MC_CMD_READ_SENSORS_IN_LEN 8 4254 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 4255 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 4256 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 4257 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 4258 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 4259 4260 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ 4261 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 4262 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 4263 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 4264 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 4265 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 4266 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 4267 /* Size in bytes of host buffer. */ 4268 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 4269 4270 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 4271 #define MC_CMD_READ_SENSORS_OUT_LEN 0 4272 4273 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ 4274 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 4275 4276 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 4277 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 4278 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 4279 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 4280 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 4281 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 4282 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 4283 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 4284 /* enum: Ok. */ 4285 #define MC_CMD_SENSOR_STATE_OK 0x0 4286 /* enum: Breached warning threshold. */ 4287 #define MC_CMD_SENSOR_STATE_WARNING 0x1 4288 /* enum: Breached fatal threshold. */ 4289 #define MC_CMD_SENSOR_STATE_FATAL 0x2 4290 /* enum: Fault with sensor. */ 4291 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 4292 /* enum: Sensor is working but does not currently have a reading. */ 4293 #define MC_CMD_SENSOR_STATE_NO_READING 0x4 4294 /* enum: Sensor initialisation failed. */ 4295 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5 4296 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 4297 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 4298 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 4299 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 4300 /* Enum values, see field(s): */ 4301 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 4302 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 4303 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 4304 4305 4306 /***********************************/ 4307 /* MC_CMD_GET_PHY_STATE 4308 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot 4309 * (e.g. due to missing or corrupted firmware). Locks required: None. Return 4310 * code: 0 4311 */ 4312 #define MC_CMD_GET_PHY_STATE 0x43 4313 4314 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4315 4316 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 4317 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 4318 4319 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 4320 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 4321 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 4322 /* enum: Ok. */ 4323 #define MC_CMD_PHY_STATE_OK 0x1 4324 /* enum: Faulty. */ 4325 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 4326 4327 4328 /***********************************/ 4329 /* MC_CMD_SETUP_8021QBB 4330 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 4331 * disable 802.Qbb for a given priority. 4332 */ 4333 #define MC_CMD_SETUP_8021QBB 0x44 4334 4335 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 4336 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 4337 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 4338 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 4339 4340 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 4341 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 4342 4343 4344 /***********************************/ 4345 /* MC_CMD_WOL_FILTER_GET 4346 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS 4347 */ 4348 #define MC_CMD_WOL_FILTER_GET 0x45 4349 4350 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK 4351 4352 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 4353 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 4354 4355 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 4356 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 4357 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 4358 4359 4360 /***********************************/ 4361 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 4362 * Add a protocol offload to NIC for lights-out state. Locks required: None. 4363 * Returns: 0, ENOSYS 4364 */ 4365 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 4366 4367 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK 4368 4369 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 4370 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 4371 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 4372 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 4373 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 4374 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 4375 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 4376 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 4377 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 4378 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 4379 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 4380 4381 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 4382 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 4383 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 4384 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 4385 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 4386 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 4387 4388 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 4389 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 4390 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 4391 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 4392 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 4393 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 4394 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 4395 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 4396 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 4397 4398 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 4399 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 4400 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 4401 4402 4403 /***********************************/ 4404 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 4405 * Remove a protocol offload from NIC for lights-out state. Locks required: 4406 * None. Returns: 0, ENOSYS 4407 */ 4408 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 4409 4410 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK 4411 4412 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 4413 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 4414 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 4415 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 4416 4417 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 4418 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 4419 4420 4421 /***********************************/ 4422 /* MC_CMD_MAC_RESET_RESTORE 4423 * Restore MAC after block reset. Locks required: None. Returns: 0. 4424 */ 4425 #define MC_CMD_MAC_RESET_RESTORE 0x48 4426 4427 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 4428 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 4429 4430 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 4431 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 4432 4433 4434 /***********************************/ 4435 /* MC_CMD_TESTASSERT 4436 * Deliberately trigger an assert-detonation in the firmware for testing 4437 * purposes (i.e. to allow tests that the driver copes gracefully). Locks 4438 * required: None Returns: 0 4439 */ 4440 #define MC_CMD_TESTASSERT 0x49 4441 4442 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4443 4444 /* MC_CMD_TESTASSERT_IN msgrequest */ 4445 #define MC_CMD_TESTASSERT_IN_LEN 0 4446 4447 /* MC_CMD_TESTASSERT_OUT msgresponse */ 4448 #define MC_CMD_TESTASSERT_OUT_LEN 0 4449 4450 /* MC_CMD_TESTASSERT_V2_IN msgrequest */ 4451 #define MC_CMD_TESTASSERT_V2_IN_LEN 4 4452 /* How to provoke the assertion */ 4453 #define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0 4454 /* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless 4455 * you're testing firmware, this is what you want. 4456 */ 4457 #define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0 4458 /* enum: Assert using assert(0); */ 4459 #define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1 4460 /* enum: Deliberately trigger a watchdog */ 4461 #define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2 4462 /* enum: Deliberately trigger a trap by loading from an invalid address */ 4463 #define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3 4464 /* enum: Deliberately trigger a trap by storing to an invalid address */ 4465 #define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4 4466 /* enum: Jump to an invalid address */ 4467 #define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5 4468 4469 /* MC_CMD_TESTASSERT_V2_OUT msgresponse */ 4470 #define MC_CMD_TESTASSERT_V2_OUT_LEN 0 4471 4472 4473 /***********************************/ 4474 /* MC_CMD_WORKAROUND 4475 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't 4476 * understand the given workaround number - which should not be treated as a 4477 * hard error by client code. This op does not imply any semantics about each 4478 * workaround, that's between the driver and the mcfw on a per-workaround 4479 * basis. Locks required: None. Returns: 0, EINVAL . 4480 */ 4481 #define MC_CMD_WORKAROUND 0x4a 4482 4483 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4484 4485 /* MC_CMD_WORKAROUND_IN msgrequest */ 4486 #define MC_CMD_WORKAROUND_IN_LEN 8 4487 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ 4488 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 4489 /* enum: Bug 17230 work around. */ 4490 #define MC_CMD_WORKAROUND_BUG17230 0x1 4491 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 4492 #define MC_CMD_WORKAROUND_BUG35388 0x2 4493 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 4494 #define MC_CMD_WORKAROUND_BUG35017 0x3 4495 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 4496 #define MC_CMD_WORKAROUND_BUG41750 0x4 4497 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 4498 * - before adding code that queries this workaround, remember that there's 4499 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 4500 * and will hence (incorrectly) report that the bug doesn't exist. 4501 */ 4502 #define MC_CMD_WORKAROUND_BUG42008 0x5 4503 /* enum: Bug 26807 features present in firmware (multicast filter chaining) 4504 * This feature cannot be turned on/off while there are any filters already 4505 * present. The behaviour in such case depends on the acting client's privilege 4506 * level. If the client has the admin privilege, then all functions that have 4507 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise 4508 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT. 4509 */ 4510 #define MC_CMD_WORKAROUND_BUG26807 0x6 4511 /* enum: Bug 61265 work around (broken EVQ TMR writes). */ 4512 #define MC_CMD_WORKAROUND_BUG61265 0x7 4513 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable 4514 * the workaround 4515 */ 4516 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 4517 4518 /* MC_CMD_WORKAROUND_OUT msgresponse */ 4519 #define MC_CMD_WORKAROUND_OUT_LEN 0 4520 4521 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used 4522 * when (TYPE == MC_CMD_WORKAROUND_BUG26807) 4523 */ 4524 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 4525 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 4526 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 4527 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 4528 4529 4530 /***********************************/ 4531 /* MC_CMD_GET_PHY_MEDIA_INFO 4532 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 4533 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG 4534 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the 4535 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 4536 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. 4537 * Anything else: currently undefined. Locks required: None. Return code: 0. 4538 */ 4539 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 4540 4541 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4542 4543 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 4544 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 4545 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 4546 4547 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 4548 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 4549 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 4550 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 4551 /* in bytes */ 4552 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 4553 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 4554 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 4555 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 4556 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 4557 4558 4559 /***********************************/ 4560 /* MC_CMD_NVRAM_TEST 4561 * Test a particular NVRAM partition for valid contents (where "valid" depends 4562 * on the type of partition). 4563 */ 4564 #define MC_CMD_NVRAM_TEST 0x4c 4565 4566 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4567 4568 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 4569 #define MC_CMD_NVRAM_TEST_IN_LEN 4 4570 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 4571 /* Enum values, see field(s): */ 4572 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4573 4574 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 4575 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 4576 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 4577 /* enum: Passed. */ 4578 #define MC_CMD_NVRAM_TEST_PASS 0x0 4579 /* enum: Failed. */ 4580 #define MC_CMD_NVRAM_TEST_FAIL 0x1 4581 /* enum: Not supported. */ 4582 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 4583 4584 4585 /***********************************/ 4586 /* MC_CMD_MRSFP_TWEAK 4587 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 4588 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 4589 * they are configured first. Locks required: None. Return code: 0, EINVAL. 4590 */ 4591 #define MC_CMD_MRSFP_TWEAK 0x4d 4592 4593 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 4594 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 4595 /* 0-6 low->high de-emph. */ 4596 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 4597 /* 0-8 low->high ref.V */ 4598 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 4599 /* 0-8 0-8 low->high boost */ 4600 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 4601 /* 0-8 low->high ref.V */ 4602 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 4603 4604 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 4605 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 4606 4607 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 4608 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 4609 /* input bits */ 4610 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 4611 /* output bits */ 4612 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 4613 /* direction */ 4614 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 4615 /* enum: Out. */ 4616 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 4617 /* enum: In. */ 4618 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 4619 4620 4621 /***********************************/ 4622 /* MC_CMD_SENSOR_SET_LIMS 4623 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 4624 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 4625 * of range. 4626 */ 4627 #define MC_CMD_SENSOR_SET_LIMS 0x4e 4628 4629 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4630 4631 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 4632 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 4633 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 4634 /* Enum values, see field(s): */ 4635 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 4636 /* interpretation is is sensor-specific. */ 4637 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 4638 /* interpretation is is sensor-specific. */ 4639 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 4640 /* interpretation is is sensor-specific. */ 4641 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 4642 /* interpretation is is sensor-specific. */ 4643 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 4644 4645 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 4646 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 4647 4648 4649 /***********************************/ 4650 /* MC_CMD_GET_RESOURCE_LIMITS 4651 */ 4652 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 4653 4654 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 4655 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 4656 4657 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 4658 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 4659 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 4660 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 4661 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 4662 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 4663 4664 4665 /***********************************/ 4666 /* MC_CMD_NVRAM_PARTITIONS 4667 * Reads the list of available virtual NVRAM partition types. Locks required: 4668 * none. Returns: 0, EINVAL (bad type). 4669 */ 4670 #define MC_CMD_NVRAM_PARTITIONS 0x51 4671 4672 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4673 4674 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ 4675 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 4676 4677 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ 4678 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 4679 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 4680 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) 4681 /* total number of partitions */ 4682 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 4683 /* type ID code for each of NUM_PARTITIONS partitions */ 4684 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 4685 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 4686 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 4687 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 4688 4689 4690 /***********************************/ 4691 /* MC_CMD_NVRAM_METADATA 4692 * Reads soft metadata for a virtual NVRAM partition type. Locks required: 4693 * none. Returns: 0, EINVAL (bad type). 4694 */ 4695 #define MC_CMD_NVRAM_METADATA 0x52 4696 4697 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4698 4699 /* MC_CMD_NVRAM_METADATA_IN msgrequest */ 4700 #define MC_CMD_NVRAM_METADATA_IN_LEN 4 4701 /* Partition type ID code */ 4702 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 4703 4704 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ 4705 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 4706 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 4707 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) 4708 /* Partition type ID code */ 4709 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 4710 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 4711 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 4712 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 4713 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 4714 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 4715 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 4716 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 4717 /* Subtype ID code for content of this partition */ 4718 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 4719 /* 1st component of W.X.Y.Z version number for content of this partition */ 4720 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 4721 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 4722 /* 2nd component of W.X.Y.Z version number for content of this partition */ 4723 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 4724 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 4725 /* 3rd component of W.X.Y.Z version number for content of this partition */ 4726 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 4727 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 4728 /* 4th component of W.X.Y.Z version number for content of this partition */ 4729 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 4730 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 4731 /* Zero-terminated string describing the content of this partition */ 4732 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 4733 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 4734 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 4735 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 4736 4737 4738 /***********************************/ 4739 /* MC_CMD_GET_MAC_ADDRESSES 4740 * Returns the base MAC, count and stride for the requesting function 4741 */ 4742 #define MC_CMD_GET_MAC_ADDRESSES 0x55 4743 4744 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4745 4746 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ 4747 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 4748 4749 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ 4750 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 4751 /* Base MAC address */ 4752 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 4753 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 4754 /* Padding */ 4755 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 4756 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 4757 /* Number of allocated MAC addresses */ 4758 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 4759 /* Spacing of allocated MAC addresses */ 4760 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 4761 4762 4763 /***********************************/ 4764 /* MC_CMD_CLP 4765 * Perform a CLP related operation 4766 */ 4767 #define MC_CMD_CLP 0x56 4768 4769 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4770 4771 /* MC_CMD_CLP_IN msgrequest */ 4772 #define MC_CMD_CLP_IN_LEN 4 4773 /* Sub operation */ 4774 #define MC_CMD_CLP_IN_OP_OFST 0 4775 /* enum: Return to factory default settings */ 4776 #define MC_CMD_CLP_OP_DEFAULT 0x1 4777 /* enum: Set MAC address */ 4778 #define MC_CMD_CLP_OP_SET_MAC 0x2 4779 /* enum: Get MAC address */ 4780 #define MC_CMD_CLP_OP_GET_MAC 0x3 4781 /* enum: Set UEFI/GPXE boot mode */ 4782 #define MC_CMD_CLP_OP_SET_BOOT 0x4 4783 /* enum: Get UEFI/GPXE boot mode */ 4784 #define MC_CMD_CLP_OP_GET_BOOT 0x5 4785 4786 /* MC_CMD_CLP_OUT msgresponse */ 4787 #define MC_CMD_CLP_OUT_LEN 0 4788 4789 /* MC_CMD_CLP_IN_DEFAULT msgrequest */ 4790 #define MC_CMD_CLP_IN_DEFAULT_LEN 4 4791 /* MC_CMD_CLP_IN_OP_OFST 0 */ 4792 4793 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ 4794 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 4795 4796 /* MC_CMD_CLP_IN_SET_MAC msgrequest */ 4797 #define MC_CMD_CLP_IN_SET_MAC_LEN 12 4798 /* MC_CMD_CLP_IN_OP_OFST 0 */ 4799 /* MAC address assigned to port */ 4800 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 4801 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 4802 /* Padding */ 4803 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 4804 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 4805 4806 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ 4807 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 4808 4809 /* MC_CMD_CLP_IN_GET_MAC msgrequest */ 4810 #define MC_CMD_CLP_IN_GET_MAC_LEN 4 4811 /* MC_CMD_CLP_IN_OP_OFST 0 */ 4812 4813 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ 4814 #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 4815 /* MAC address assigned to port */ 4816 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 4817 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 4818 /* Padding */ 4819 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 4820 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 4821 4822 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ 4823 #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 4824 /* MC_CMD_CLP_IN_OP_OFST 0 */ 4825 /* Boot flag */ 4826 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 4827 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 4828 4829 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ 4830 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 4831 4832 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ 4833 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 4834 /* MC_CMD_CLP_IN_OP_OFST 0 */ 4835 4836 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ 4837 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 4838 /* Boot flag */ 4839 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 4840 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 4841 /* Padding */ 4842 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 4843 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 4844 4845 4846 /***********************************/ 4847 /* MC_CMD_MUM 4848 * Perform a MUM operation 4849 */ 4850 #define MC_CMD_MUM 0x57 4851 4852 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4853 4854 /* MC_CMD_MUM_IN msgrequest */ 4855 #define MC_CMD_MUM_IN_LEN 4 4856 #define MC_CMD_MUM_IN_OP_HDR_OFST 0 4857 #define MC_CMD_MUM_IN_OP_LBN 0 4858 #define MC_CMD_MUM_IN_OP_WIDTH 8 4859 /* enum: NULL MCDI command to MUM */ 4860 #define MC_CMD_MUM_OP_NULL 0x1 4861 /* enum: Get MUM version */ 4862 #define MC_CMD_MUM_OP_GET_VERSION 0x2 4863 /* enum: Issue raw I2C command to MUM */ 4864 #define MC_CMD_MUM_OP_RAW_CMD 0x3 4865 /* enum: Read from registers on devices connected to MUM. */ 4866 #define MC_CMD_MUM_OP_READ 0x4 4867 /* enum: Write to registers on devices connected to MUM. */ 4868 #define MC_CMD_MUM_OP_WRITE 0x5 4869 /* enum: Control UART logging. */ 4870 #define MC_CMD_MUM_OP_LOG 0x6 4871 /* enum: Operations on MUM GPIO lines */ 4872 #define MC_CMD_MUM_OP_GPIO 0x7 4873 /* enum: Get sensor readings from MUM */ 4874 #define MC_CMD_MUM_OP_READ_SENSORS 0x8 4875 /* enum: Initiate clock programming on the MUM */ 4876 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 4877 /* enum: Initiate FPGA load from flash on the MUM */ 4878 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa 4879 /* enum: Request sensor reading from MUM ADC resulting from earlier request via 4880 * MUM ATB 4881 */ 4882 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb 4883 /* enum: Send commands relating to the QSFP ports via the MUM for PHY 4884 * operations 4885 */ 4886 #define MC_CMD_MUM_OP_QSFP 0xc 4887 /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage 4888 * level) from MUM 4889 */ 4890 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd 4891 4892 /* MC_CMD_MUM_IN_NULL msgrequest */ 4893 #define MC_CMD_MUM_IN_NULL_LEN 4 4894 /* MUM cmd header */ 4895 #define MC_CMD_MUM_IN_CMD_OFST 0 4896 4897 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */ 4898 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4 4899 /* MUM cmd header */ 4900 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4901 4902 /* MC_CMD_MUM_IN_READ msgrequest */ 4903 #define MC_CMD_MUM_IN_READ_LEN 16 4904 /* MUM cmd header */ 4905 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4906 /* ID of (device connected to MUM) to read from registers of */ 4907 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 4908 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 4909 #define MC_CMD_MUM_DEV_HITTITE 0x1 4910 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ 4911 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 4912 /* 32-bit address to read from */ 4913 #define MC_CMD_MUM_IN_READ_ADDR_OFST 8 4914 /* Number of words to read. */ 4915 #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 4916 4917 /* MC_CMD_MUM_IN_WRITE msgrequest */ 4918 #define MC_CMD_MUM_IN_WRITE_LENMIN 16 4919 #define MC_CMD_MUM_IN_WRITE_LENMAX 252 4920 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) 4921 /* MUM cmd header */ 4922 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4923 /* ID of (device connected to MUM) to write to registers of */ 4924 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 4925 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 4926 /* MC_CMD_MUM_DEV_HITTITE 0x1 */ 4927 /* 32-bit address to write to */ 4928 #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 4929 /* Words to write */ 4930 #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 4931 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 4932 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 4933 #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 4934 4935 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */ 4936 #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 4937 #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 4938 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) 4939 /* MUM cmd header */ 4940 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4941 /* MUM I2C cmd code */ 4942 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 4943 /* Number of bytes to write */ 4944 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 4945 /* Number of bytes to read */ 4946 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 4947 /* Bytes to write */ 4948 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 4949 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 4950 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 4951 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 4952 4953 /* MC_CMD_MUM_IN_LOG msgrequest */ 4954 #define MC_CMD_MUM_IN_LOG_LEN 8 4955 /* MUM cmd header */ 4956 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4957 #define MC_CMD_MUM_IN_LOG_OP_OFST 4 4958 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ 4959 4960 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ 4961 #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 4962 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4963 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ 4964 /* Enable/disable debug output to UART */ 4965 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 4966 4967 /* MC_CMD_MUM_IN_GPIO msgrequest */ 4968 #define MC_CMD_MUM_IN_GPIO_LEN 8 4969 /* MUM cmd header */ 4970 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4971 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 4972 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 4973 #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 4974 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ 4975 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ 4976 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ 4977 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ 4978 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ 4979 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ 4980 4981 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ 4982 #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 4983 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4984 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 4985 4986 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ 4987 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 4988 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4989 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 4990 /* The first 32-bit word to be written to the GPIO OUT register. */ 4991 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 4992 /* The second 32-bit word to be written to the GPIO OUT register. */ 4993 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 4994 4995 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ 4996 #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 4997 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 4998 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 4999 5000 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ 5001 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 5002 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5003 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 5004 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ 5005 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 5006 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ 5007 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 5008 5009 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ 5010 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 5011 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5012 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 5013 5014 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */ 5015 #define MC_CMD_MUM_IN_GPIO_OP_LEN 8 5016 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5017 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 5018 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 5019 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 5020 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ 5021 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ 5022 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ 5023 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ 5024 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 5025 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 5026 5027 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ 5028 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 5029 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5030 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 5031 5032 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ 5033 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 5034 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5035 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 5036 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 5037 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 5038 5039 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ 5040 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 5041 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5042 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 5043 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 5044 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 5045 5046 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ 5047 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 5048 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5049 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 5050 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 5051 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 5052 5053 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ 5054 #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 5055 /* MUM cmd header */ 5056 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5057 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 5058 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 5059 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 5060 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 5061 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 5062 5063 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ 5064 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 5065 /* MUM cmd header */ 5066 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5067 /* Bit-mask of clocks to be programmed */ 5068 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 5069 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ 5070 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ 5071 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ 5072 /* Control flags for clock programming */ 5073 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 5074 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 5075 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 5076 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1 5077 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1 5078 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2 5079 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1 5080 5081 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ 5082 #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 5083 /* MUM cmd header */ 5084 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5085 /* Enable/Disable FPGA config from flash */ 5086 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 5087 5088 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ 5089 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 5090 /* MUM cmd header */ 5091 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5092 5093 /* MC_CMD_MUM_IN_QSFP msgrequest */ 5094 #define MC_CMD_MUM_IN_QSFP_LEN 12 5095 /* MUM cmd header */ 5096 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5097 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 5098 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 5099 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 5100 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ 5101 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ 5102 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ 5103 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ 5104 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ 5105 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ 5106 #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 5107 5108 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ 5109 #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 5110 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5111 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 5112 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 5113 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 5114 5115 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ 5116 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 5117 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5118 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 5119 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 5120 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 5121 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 5122 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 5123 5124 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ 5125 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 5126 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5127 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 5128 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 5129 5130 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ 5131 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 5132 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5133 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 5134 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 5135 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 5136 5137 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ 5138 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 5139 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5140 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 5141 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 5142 5143 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ 5144 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 5145 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5146 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 5147 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 5148 5149 /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */ 5150 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4 5151 /* MUM cmd header */ 5152 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5153 5154 /* MC_CMD_MUM_OUT msgresponse */ 5155 #define MC_CMD_MUM_OUT_LEN 0 5156 5157 /* MC_CMD_MUM_OUT_NULL msgresponse */ 5158 #define MC_CMD_MUM_OUT_NULL_LEN 0 5159 5160 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ 5161 #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 5162 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 5163 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 5164 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 5165 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 5166 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 5167 5168 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ 5169 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 5170 #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 5171 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) 5172 /* returned data */ 5173 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 5174 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 5175 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 5176 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 5177 5178 /* MC_CMD_MUM_OUT_READ msgresponse */ 5179 #define MC_CMD_MUM_OUT_READ_LENMIN 4 5180 #define MC_CMD_MUM_OUT_READ_LENMAX 252 5181 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) 5182 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 5183 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 5184 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 5185 #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 5186 5187 /* MC_CMD_MUM_OUT_WRITE msgresponse */ 5188 #define MC_CMD_MUM_OUT_WRITE_LEN 0 5189 5190 /* MC_CMD_MUM_OUT_LOG msgresponse */ 5191 #define MC_CMD_MUM_OUT_LOG_LEN 0 5192 5193 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ 5194 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 5195 5196 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ 5197 #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 5198 /* The first 32-bit word read from the GPIO IN register. */ 5199 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 5200 /* The second 32-bit word read from the GPIO IN register. */ 5201 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 5202 5203 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ 5204 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 5205 5206 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ 5207 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 5208 /* The first 32-bit word read from the GPIO OUT register. */ 5209 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 5210 /* The second 32-bit word read from the GPIO OUT register. */ 5211 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 5212 5213 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ 5214 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 5215 5216 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ 5217 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 5218 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 5219 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 5220 5221 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ 5222 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 5223 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 5224 5225 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ 5226 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 5227 5228 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ 5229 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 5230 5231 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ 5232 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 5233 5234 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ 5235 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 5236 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 5237 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) 5238 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 5239 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 5240 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 5241 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 5242 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 5243 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 5244 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 5245 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 5246 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 5247 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 5248 5249 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ 5250 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 5251 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 5252 5253 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ 5254 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 5255 5256 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ 5257 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 5258 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 5259 5260 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ 5261 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 5262 5263 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ 5264 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 5265 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 5266 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 5267 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 5268 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 5269 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 5270 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 5271 5272 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ 5273 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 5274 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 5275 5276 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ 5277 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 5278 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 5279 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) 5280 /* in bytes */ 5281 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 5282 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 5283 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 5284 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 5285 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 5286 5287 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ 5288 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 5289 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 5290 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 5291 5292 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ 5293 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 5294 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 5295 5296 /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */ 5297 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24 5298 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248 5299 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) 5300 /* Discrete (soldered) DDR resistor strap info */ 5301 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0 5302 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0 5303 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16 5304 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16 5305 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16 5306 /* Number of SODIMM info records */ 5307 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4 5308 /* Array of SODIMM info records */ 5309 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8 5310 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8 5311 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8 5312 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12 5313 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2 5314 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30 5315 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0 5316 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8 5317 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */ 5318 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0 5319 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */ 5320 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1 5321 /* enum: Total number of SODIMM banks */ 5322 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2 5323 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8 5324 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8 5325 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16 5326 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4 5327 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20 5328 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4 5329 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */ 5330 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */ 5331 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */ 5332 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */ 5333 /* enum: Values 5-15 are reserved for future usage */ 5334 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4 5335 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24 5336 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8 5337 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32 5338 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16 5339 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48 5340 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4 5341 /* enum: No module present */ 5342 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0 5343 /* enum: Module present supported and powered on */ 5344 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1 5345 /* enum: Module present but bad type */ 5346 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2 5347 /* enum: Module present but incompatible voltage */ 5348 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3 5349 /* enum: Module present but unknown SPD */ 5350 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4 5351 /* enum: Module present but slot cannot support it */ 5352 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5 5353 /* enum: Modules may or may not be present, but cannot establish contact by I2C 5354 */ 5355 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6 5356 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52 5357 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12 5358 5359 /* MC_CMD_RESOURCE_SPECIFIER enum */ 5360 /* enum: Any */ 5361 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff 5362 /* enum: None */ 5363 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe 5364 5365 /* EVB_PORT_ID structuredef */ 5366 #define EVB_PORT_ID_LEN 4 5367 #define EVB_PORT_ID_PORT_ID_OFST 0 5368 /* enum: An invalid port handle. */ 5369 #define EVB_PORT_ID_NULL 0x0 5370 /* enum: The port assigned to this function.. */ 5371 #define EVB_PORT_ID_ASSIGNED 0x1000000 5372 /* enum: External network port 0 */ 5373 #define EVB_PORT_ID_MAC0 0x2000000 5374 /* enum: External network port 1 */ 5375 #define EVB_PORT_ID_MAC1 0x2000001 5376 /* enum: External network port 2 */ 5377 #define EVB_PORT_ID_MAC2 0x2000002 5378 /* enum: External network port 3 */ 5379 #define EVB_PORT_ID_MAC3 0x2000003 5380 #define EVB_PORT_ID_PORT_ID_LBN 0 5381 #define EVB_PORT_ID_PORT_ID_WIDTH 32 5382 5383 /* EVB_VLAN_TAG structuredef */ 5384 #define EVB_VLAN_TAG_LEN 2 5385 /* The VLAN tag value */ 5386 #define EVB_VLAN_TAG_VLAN_ID_LBN 0 5387 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 5388 #define EVB_VLAN_TAG_MODE_LBN 12 5389 #define EVB_VLAN_TAG_MODE_WIDTH 4 5390 /* enum: Insert the VLAN. */ 5391 #define EVB_VLAN_TAG_INSERT 0x0 5392 /* enum: Replace the VLAN if already present. */ 5393 #define EVB_VLAN_TAG_REPLACE 0x1 5394 5395 /* BUFTBL_ENTRY structuredef */ 5396 #define BUFTBL_ENTRY_LEN 12 5397 /* the owner ID */ 5398 #define BUFTBL_ENTRY_OID_OFST 0 5399 #define BUFTBL_ENTRY_OID_LEN 2 5400 #define BUFTBL_ENTRY_OID_LBN 0 5401 #define BUFTBL_ENTRY_OID_WIDTH 16 5402 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 5403 #define BUFTBL_ENTRY_PGSZ_OFST 2 5404 #define BUFTBL_ENTRY_PGSZ_LEN 2 5405 #define BUFTBL_ENTRY_PGSZ_LBN 16 5406 #define BUFTBL_ENTRY_PGSZ_WIDTH 16 5407 /* the raw 64-bit address field from the SMC, not adjusted for page size */ 5408 #define BUFTBL_ENTRY_RAWADDR_OFST 4 5409 #define BUFTBL_ENTRY_RAWADDR_LEN 8 5410 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 5411 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 5412 #define BUFTBL_ENTRY_RAWADDR_LBN 32 5413 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 5414 5415 /* NVRAM_PARTITION_TYPE structuredef */ 5416 #define NVRAM_PARTITION_TYPE_LEN 2 5417 #define NVRAM_PARTITION_TYPE_ID_OFST 0 5418 #define NVRAM_PARTITION_TYPE_ID_LEN 2 5419 /* enum: Primary MC firmware partition */ 5420 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 5421 /* enum: Secondary MC firmware partition */ 5422 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 5423 /* enum: Expansion ROM partition */ 5424 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 5425 /* enum: Static configuration TLV partition */ 5426 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 5427 /* enum: Dynamic configuration TLV partition */ 5428 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 5429 /* enum: Expansion ROM configuration data for port 0 */ 5430 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 5431 /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */ 5432 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600 5433 /* enum: Expansion ROM configuration data for port 1 */ 5434 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 5435 /* enum: Expansion ROM configuration data for port 2 */ 5436 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 5437 /* enum: Expansion ROM configuration data for port 3 */ 5438 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 5439 /* enum: Non-volatile log output partition */ 5440 #define NVRAM_PARTITION_TYPE_LOG 0x700 5441 /* enum: Non-volatile log output of second core on dual-core device */ 5442 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701 5443 /* enum: Device state dump output partition */ 5444 #define NVRAM_PARTITION_TYPE_DUMP 0x800 5445 /* enum: Application license key storage partition */ 5446 #define NVRAM_PARTITION_TYPE_LICENSE 0x900 5447 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ 5448 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 5449 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ 5450 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff 5451 /* enum: Primary FPGA partition */ 5452 #define NVRAM_PARTITION_TYPE_FPGA 0xb00 5453 /* enum: Secondary FPGA partition */ 5454 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01 5455 /* enum: FC firmware partition */ 5456 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02 5457 /* enum: FC License partition */ 5458 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03 5459 /* enum: Non-volatile log output partition for FC */ 5460 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04 5461 /* enum: MUM firmware partition */ 5462 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00 5463 /* enum: MUM Non-volatile log output partition. */ 5464 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01 5465 /* enum: MUM Application table partition. */ 5466 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02 5467 /* enum: MUM boot rom partition. */ 5468 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03 5469 /* enum: MUM production signatures & calibration rom partition. */ 5470 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04 5471 /* enum: MUM user signatures & calibration rom partition. */ 5472 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 5473 /* enum: MUM fuses and lockbits partition. */ 5474 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 5475 /* enum: UEFI expansion ROM if separate from PXE */ 5476 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00 5477 /* enum: Spare partition 0 */ 5478 #define NVRAM_PARTITION_TYPE_SPARE_0 0x1000 5479 /* enum: Used for XIP code of shmbooted images */ 5480 #define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100 5481 /* enum: Spare partition 2 */ 5482 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200 5483 /* enum: Manufacturing partition. Used during manufacture to pass information 5484 * between XJTAG and Manftest. 5485 */ 5486 #define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300 5487 /* enum: Spare partition 4 */ 5488 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400 5489 /* enum: Spare partition 5 */ 5490 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500 5491 /* enum: Start of reserved value range (firmware may use for any purpose) */ 5492 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 5493 /* enum: End of reserved value range (firmware may use for any purpose) */ 5494 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd 5495 /* enum: Recovery partition map (provided if real map is missing or corrupt) */ 5496 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe 5497 /* enum: Partition map (real map as stored in flash) */ 5498 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff 5499 #define NVRAM_PARTITION_TYPE_ID_LBN 0 5500 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 5501 5502 /* LICENSED_APP_ID structuredef */ 5503 #define LICENSED_APP_ID_LEN 4 5504 #define LICENSED_APP_ID_ID_OFST 0 5505 /* enum: OpenOnload */ 5506 #define LICENSED_APP_ID_ONLOAD 0x1 5507 /* enum: PTP timestamping */ 5508 #define LICENSED_APP_ID_PTP 0x2 5509 /* enum: SolarCapture Pro */ 5510 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 5511 /* enum: SolarSecure filter engine */ 5512 #define LICENSED_APP_ID_SOLARSECURE 0x8 5513 /* enum: Performance monitor */ 5514 #define LICENSED_APP_ID_PERF_MONITOR 0x10 5515 /* enum: SolarCapture Live */ 5516 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20 5517 /* enum: Capture SolarSystem */ 5518 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40 5519 /* enum: Network Access Control */ 5520 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80 5521 /* enum: TCP Direct */ 5522 #define LICENSED_APP_ID_TCP_DIRECT 0x100 5523 /* enum: Low Latency */ 5524 #define LICENSED_APP_ID_LOW_LATENCY 0x200 5525 /* enum: SolarCapture Tap */ 5526 #define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400 5527 /* enum: Capture SolarSystem 40G */ 5528 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800 5529 #define LICENSED_APP_ID_ID_LBN 0 5530 #define LICENSED_APP_ID_ID_WIDTH 32 5531 5532 /* LICENSED_FEATURES structuredef */ 5533 #define LICENSED_FEATURES_LEN 8 5534 /* Bitmask of licensed firmware features */ 5535 #define LICENSED_FEATURES_MASK_OFST 0 5536 #define LICENSED_FEATURES_MASK_LEN 8 5537 #define LICENSED_FEATURES_MASK_LO_OFST 0 5538 #define LICENSED_FEATURES_MASK_HI_OFST 4 5539 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0 5540 #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1 5541 #define LICENSED_FEATURES_PIO_LBN 1 5542 #define LICENSED_FEATURES_PIO_WIDTH 1 5543 #define LICENSED_FEATURES_EVQ_TIMER_LBN 2 5544 #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1 5545 #define LICENSED_FEATURES_CLOCK_LBN 3 5546 #define LICENSED_FEATURES_CLOCK_WIDTH 1 5547 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4 5548 #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1 5549 #define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5 5550 #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1 5551 #define LICENSED_FEATURES_RX_SNIFF_LBN 6 5552 #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1 5553 #define LICENSED_FEATURES_TX_SNIFF_LBN 7 5554 #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1 5555 #define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8 5556 #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1 5557 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9 5558 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 5559 #define LICENSED_FEATURES_MASK_LBN 0 5560 #define LICENSED_FEATURES_MASK_WIDTH 64 5561 5562 /* LICENSED_V3_APPS structuredef */ 5563 #define LICENSED_V3_APPS_LEN 8 5564 /* Bitmask of licensed applications */ 5565 #define LICENSED_V3_APPS_MASK_OFST 0 5566 #define LICENSED_V3_APPS_MASK_LEN 8 5567 #define LICENSED_V3_APPS_MASK_LO_OFST 0 5568 #define LICENSED_V3_APPS_MASK_HI_OFST 4 5569 #define LICENSED_V3_APPS_ONLOAD_LBN 0 5570 #define LICENSED_V3_APPS_ONLOAD_WIDTH 1 5571 #define LICENSED_V3_APPS_PTP_LBN 1 5572 #define LICENSED_V3_APPS_PTP_WIDTH 1 5573 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2 5574 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1 5575 #define LICENSED_V3_APPS_SOLARSECURE_LBN 3 5576 #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1 5577 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4 5578 #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1 5579 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5 5580 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1 5581 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6 5582 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1 5583 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7 5584 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1 5585 #define LICENSED_V3_APPS_TCP_DIRECT_LBN 8 5586 #define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1 5587 #define LICENSED_V3_APPS_LOW_LATENCY_LBN 9 5588 #define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1 5589 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10 5590 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1 5591 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11 5592 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1 5593 #define LICENSED_V3_APPS_MASK_LBN 0 5594 #define LICENSED_V3_APPS_MASK_WIDTH 64 5595 5596 /* LICENSED_V3_FEATURES structuredef */ 5597 #define LICENSED_V3_FEATURES_LEN 8 5598 /* Bitmask of licensed firmware features */ 5599 #define LICENSED_V3_FEATURES_MASK_OFST 0 5600 #define LICENSED_V3_FEATURES_MASK_LEN 8 5601 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0 5602 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4 5603 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0 5604 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1 5605 #define LICENSED_V3_FEATURES_PIO_LBN 1 5606 #define LICENSED_V3_FEATURES_PIO_WIDTH 1 5607 #define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2 5608 #define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1 5609 #define LICENSED_V3_FEATURES_CLOCK_LBN 3 5610 #define LICENSED_V3_FEATURES_CLOCK_WIDTH 1 5611 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4 5612 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1 5613 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5 5614 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1 5615 #define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6 5616 #define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1 5617 #define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7 5618 #define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1 5619 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8 5620 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1 5621 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9 5622 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 5623 #define LICENSED_V3_FEATURES_MASK_LBN 0 5624 #define LICENSED_V3_FEATURES_MASK_WIDTH 64 5625 5626 /* TX_TIMESTAMP_EVENT structuredef */ 5627 #define TX_TIMESTAMP_EVENT_LEN 6 5628 /* lower 16 bits of timestamp data */ 5629 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 5630 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 5631 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 5632 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 5633 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp 5634 */ 5635 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 5636 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 5637 /* enum: This is a TX completion event, not a timestamp */ 5638 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 5639 /* enum: This is the low part of a TX timestamp event */ 5640 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 5641 /* enum: This is the high part of a TX timestamp event */ 5642 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 5643 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 5644 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 5645 /* upper 16 bits of timestamp data */ 5646 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 5647 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 5648 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 5649 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16 5650 5651 /* RSS_MODE structuredef */ 5652 #define RSS_MODE_LEN 1 5653 /* The RSS mode for a particular packet type is a value from 0 - 15 which can 5654 * be considered as 4 bits selecting which fields are included in the hash. (A 5655 * value 0 effectively disables RSS spreading for the packet type.) The YAML 5656 * generation tools require this structure to be a whole number of bytes wide, 5657 * but only 4 bits are relevant. 5658 */ 5659 #define RSS_MODE_HASH_SELECTOR_OFST 0 5660 #define RSS_MODE_HASH_SELECTOR_LEN 1 5661 #define RSS_MODE_HASH_SRC_ADDR_LBN 0 5662 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 5663 #define RSS_MODE_HASH_DST_ADDR_LBN 1 5664 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1 5665 #define RSS_MODE_HASH_SRC_PORT_LBN 2 5666 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1 5667 #define RSS_MODE_HASH_DST_PORT_LBN 3 5668 #define RSS_MODE_HASH_DST_PORT_WIDTH 1 5669 #define RSS_MODE_HASH_SELECTOR_LBN 0 5670 #define RSS_MODE_HASH_SELECTOR_WIDTH 8 5671 5672 5673 /***********************************/ 5674 /* MC_CMD_READ_REGS 5675 * Get a dump of the MCPU registers 5676 */ 5677 #define MC_CMD_READ_REGS 0x50 5678 5679 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5680 5681 /* MC_CMD_READ_REGS_IN msgrequest */ 5682 #define MC_CMD_READ_REGS_IN_LEN 0 5683 5684 /* MC_CMD_READ_REGS_OUT msgresponse */ 5685 #define MC_CMD_READ_REGS_OUT_LEN 308 5686 /* Whether the corresponding register entry contains a valid value */ 5687 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 5688 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 5689 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 5690 * fir, fp) 5691 */ 5692 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 5693 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 5694 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 5695 5696 5697 /***********************************/ 5698 /* MC_CMD_INIT_EVQ 5699 * Set up an event queue according to the supplied parameters. The IN arguments 5700 * end with an address for each 4k of host memory required to back the EVQ. 5701 */ 5702 #define MC_CMD_INIT_EVQ 0x80 5703 5704 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5705 5706 /* MC_CMD_INIT_EVQ_IN msgrequest */ 5707 #define MC_CMD_INIT_EVQ_IN_LENMIN 44 5708 #define MC_CMD_INIT_EVQ_IN_LENMAX 548 5709 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) 5710 /* Size, in entries */ 5711 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 5712 /* Desired instance. Must be set to a specific instance, which is a function 5713 * local queue index. 5714 */ 5715 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 5716 /* The initial timer value. The load value is ignored if the timer mode is DIS. 5717 */ 5718 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 5719 /* The reload value is ignored in one-shot modes */ 5720 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 5721 /* tbd */ 5722 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 5723 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 5724 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 5725 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 5726 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 5727 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 5728 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 5729 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 5730 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 5731 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 5732 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 5733 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 5734 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 5735 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6 5736 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1 5737 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 5738 /* enum: Disabled */ 5739 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 5740 /* enum: Immediate */ 5741 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 5742 /* enum: Triggered */ 5743 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 5744 /* enum: Hold-off */ 5745 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 5746 /* Target EVQ for wakeups if in wakeup mode. */ 5747 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 5748 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 5749 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 5750 * purposes. 5751 */ 5752 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 5753 /* Event Counter Mode. */ 5754 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 5755 /* enum: Disabled */ 5756 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 5757 /* enum: Disabled */ 5758 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 5759 /* enum: Disabled */ 5760 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 5761 /* enum: Disabled */ 5762 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 5763 /* Event queue packet count threshold. */ 5764 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 5765 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 5766 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 5767 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 5768 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 5769 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 5770 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 5771 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 5772 5773 /* MC_CMD_INIT_EVQ_OUT msgresponse */ 5774 #define MC_CMD_INIT_EVQ_OUT_LEN 4 5775 /* Only valid if INTRFLAG was true */ 5776 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 5777 5778 /* MC_CMD_INIT_EVQ_V2_IN msgrequest */ 5779 #define MC_CMD_INIT_EVQ_V2_IN_LENMIN 44 5780 #define MC_CMD_INIT_EVQ_V2_IN_LENMAX 548 5781 #define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num)) 5782 /* Size, in entries */ 5783 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0 5784 /* Desired instance. Must be set to a specific instance, which is a function 5785 * local queue index. 5786 */ 5787 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4 5788 /* The initial timer value. The load value is ignored if the timer mode is DIS. 5789 */ 5790 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8 5791 /* The reload value is ignored in one-shot modes */ 5792 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12 5793 /* tbd */ 5794 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16 5795 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0 5796 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1 5797 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1 5798 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1 5799 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2 5800 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1 5801 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3 5802 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1 5803 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4 5804 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1 5805 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5 5806 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1 5807 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6 5808 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1 5809 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7 5810 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4 5811 /* enum: All initialisation flags specified by host. */ 5812 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0 5813 /* enum: MEDFORD only. Certain initialisation flags specified by host may be 5814 * over-ridden by firmware based on licenses and firmware variant in order to 5815 * provide the lowest latency achievable. See 5816 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 5817 */ 5818 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1 5819 /* enum: MEDFORD only. Certain initialisation flags specified by host may be 5820 * over-ridden by firmware based on licenses and firmware variant in order to 5821 * provide the best throughput achievable. See 5822 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 5823 */ 5824 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2 5825 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by 5826 * firmware based on licenses and firmware variant. See 5827 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 5828 */ 5829 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3 5830 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20 5831 /* enum: Disabled */ 5832 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0 5833 /* enum: Immediate */ 5834 #define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1 5835 /* enum: Triggered */ 5836 #define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2 5837 /* enum: Hold-off */ 5838 #define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3 5839 /* Target EVQ for wakeups if in wakeup mode. */ 5840 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24 5841 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 5842 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 5843 * purposes. 5844 */ 5845 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24 5846 /* Event Counter Mode. */ 5847 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28 5848 /* enum: Disabled */ 5849 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0 5850 /* enum: Disabled */ 5851 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1 5852 /* enum: Disabled */ 5853 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2 5854 /* enum: Disabled */ 5855 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3 5856 /* Event queue packet count threshold. */ 5857 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32 5858 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 5859 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36 5860 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8 5861 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36 5862 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40 5863 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1 5864 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64 5865 5866 /* MC_CMD_INIT_EVQ_V2_OUT msgresponse */ 5867 #define MC_CMD_INIT_EVQ_V2_OUT_LEN 8 5868 /* Only valid if INTRFLAG was true */ 5869 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0 5870 /* Actual configuration applied on the card */ 5871 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4 5872 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0 5873 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1 5874 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1 5875 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1 5876 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2 5877 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1 5878 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3 5879 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1 5880 5881 /* QUEUE_CRC_MODE structuredef */ 5882 #define QUEUE_CRC_MODE_LEN 1 5883 #define QUEUE_CRC_MODE_MODE_LBN 0 5884 #define QUEUE_CRC_MODE_MODE_WIDTH 4 5885 /* enum: No CRC. */ 5886 #define QUEUE_CRC_MODE_NONE 0x0 5887 /* enum: CRC Fiber channel over ethernet. */ 5888 #define QUEUE_CRC_MODE_FCOE 0x1 5889 /* enum: CRC (digest) iSCSI header only. */ 5890 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 5891 /* enum: CRC (digest) iSCSI header and payload. */ 5892 #define QUEUE_CRC_MODE_ISCSI 0x3 5893 /* enum: CRC Fiber channel over IP over ethernet. */ 5894 #define QUEUE_CRC_MODE_FCOIPOE 0x4 5895 /* enum: CRC MPA. */ 5896 #define QUEUE_CRC_MODE_MPA 0x5 5897 #define QUEUE_CRC_MODE_SPARE_LBN 4 5898 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 5899 5900 5901 /***********************************/ 5902 /* MC_CMD_INIT_RXQ 5903 * set up a receive queue according to the supplied parameters. The IN 5904 * arguments end with an address for each 4k of host memory required to back 5905 * the RXQ. 5906 */ 5907 #define MC_CMD_INIT_RXQ 0x81 5908 5909 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5910 5911 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version 5912 * in new code. 5913 */ 5914 #define MC_CMD_INIT_RXQ_IN_LENMIN 36 5915 #define MC_CMD_INIT_RXQ_IN_LENMAX 252 5916 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) 5917 /* Size, in entries */ 5918 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 5919 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 5920 */ 5921 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 5922 /* The value to put in the event data. Check hardware spec. for valid range. */ 5923 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 5924 /* Desired instance. Must be set to a specific instance, which is a function 5925 * local queue index. 5926 */ 5927 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 5928 /* There will be more flags here. */ 5929 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 5930 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 5931 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 5932 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 5933 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 5934 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 5935 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 5936 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 5937 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 5938 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 5939 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 5940 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 5941 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 5942 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 5943 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 5944 #define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10 5945 #define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1 5946 /* Owner ID to use if in buffer mode (zero if physical) */ 5947 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 5948 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 5949 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 5950 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 5951 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 5952 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 5953 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 5954 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 5955 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 5956 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 5957 5958 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode 5959 * flags 5960 */ 5961 #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 5962 /* Size, in entries */ 5963 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 5964 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 5965 */ 5966 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 5967 /* The value to put in the event data. Check hardware spec. for valid range. */ 5968 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 5969 /* Desired instance. Must be set to a specific instance, which is a function 5970 * local queue index. 5971 */ 5972 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 5973 /* There will be more flags here. */ 5974 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 5975 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 5976 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 5977 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 5978 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 5979 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 5980 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 5981 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 5982 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 5983 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 5984 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 5985 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 5986 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 5987 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 5988 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 5989 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 5990 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 5991 /* enum: One packet per descriptor (for normal networking) */ 5992 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 5993 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 5994 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 5995 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 5996 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 5997 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 5998 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 5999 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ 6000 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ 6001 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ 6002 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ 6003 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ 6004 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 6005 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 6006 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19 6007 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 6008 /* Owner ID to use if in buffer mode (zero if physical) */ 6009 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 6010 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 6011 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 6012 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 6013 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 6014 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 6015 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 6016 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 6017 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 6018 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 6019 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 6020 6021 /* MC_CMD_INIT_RXQ_OUT msgresponse */ 6022 #define MC_CMD_INIT_RXQ_OUT_LEN 0 6023 6024 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */ 6025 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0 6026 6027 6028 /***********************************/ 6029 /* MC_CMD_INIT_TXQ 6030 */ 6031 #define MC_CMD_INIT_TXQ 0x82 6032 6033 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6034 6035 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version 6036 * in new code. 6037 */ 6038 #define MC_CMD_INIT_TXQ_IN_LENMIN 36 6039 #define MC_CMD_INIT_TXQ_IN_LENMAX 252 6040 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) 6041 /* Size, in entries */ 6042 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 6043 /* The EVQ to send events to. This is an index originally specified to 6044 * INIT_EVQ. 6045 */ 6046 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 6047 /* The value to put in the event data. Check hardware spec. for valid range. */ 6048 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 6049 /* Desired instance. Must be set to a specific instance, which is a function 6050 * local queue index. 6051 */ 6052 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 6053 /* There will be more flags here. */ 6054 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 6055 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 6056 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 6057 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 6058 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 6059 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 6060 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 6061 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 6062 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 6063 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 6064 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 6065 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 6066 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 6067 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 6068 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 6069 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 6070 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 6071 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 6072 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 6073 /* Owner ID to use if in buffer mode (zero if physical) */ 6074 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 6075 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 6076 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 6077 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 6078 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 6079 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 6080 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 6081 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 6082 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 6083 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 6084 6085 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode 6086 * flags 6087 */ 6088 #define MC_CMD_INIT_TXQ_EXT_IN_LEN 544 6089 /* Size, in entries */ 6090 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0 6091 /* The EVQ to send events to. This is an index originally specified to 6092 * INIT_EVQ. 6093 */ 6094 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4 6095 /* The value to put in the event data. Check hardware spec. for valid range. */ 6096 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8 6097 /* Desired instance. Must be set to a specific instance, which is a function 6098 * local queue index. 6099 */ 6100 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12 6101 /* There will be more flags here. */ 6102 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16 6103 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 6104 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 6105 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1 6106 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1 6107 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2 6108 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 6109 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3 6110 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 6111 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4 6112 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4 6113 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8 6114 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 6115 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9 6116 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1 6117 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 6118 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 6119 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 6120 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 6121 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12 6122 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1 6123 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13 6124 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1 6125 /* Owner ID to use if in buffer mode (zero if physical) */ 6126 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 6127 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 6128 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24 6129 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 6130 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28 6131 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8 6132 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28 6133 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32 6134 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1 6135 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64 6136 /* Flags related to Qbb flow control mode. */ 6137 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540 6138 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0 6139 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1 6140 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1 6141 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3 6142 6143 /* MC_CMD_INIT_TXQ_OUT msgresponse */ 6144 #define MC_CMD_INIT_TXQ_OUT_LEN 0 6145 6146 6147 /***********************************/ 6148 /* MC_CMD_FINI_EVQ 6149 * Teardown an EVQ. 6150 * 6151 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first 6152 * or the operation will fail with EBUSY 6153 */ 6154 #define MC_CMD_FINI_EVQ 0x83 6155 6156 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6157 6158 /* MC_CMD_FINI_EVQ_IN msgrequest */ 6159 #define MC_CMD_FINI_EVQ_IN_LEN 4 6160 /* Instance of EVQ to destroy. Should be the same instance as that previously 6161 * passed to INIT_EVQ 6162 */ 6163 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 6164 6165 /* MC_CMD_FINI_EVQ_OUT msgresponse */ 6166 #define MC_CMD_FINI_EVQ_OUT_LEN 0 6167 6168 6169 /***********************************/ 6170 /* MC_CMD_FINI_RXQ 6171 * Teardown a RXQ. 6172 */ 6173 #define MC_CMD_FINI_RXQ 0x84 6174 6175 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6176 6177 /* MC_CMD_FINI_RXQ_IN msgrequest */ 6178 #define MC_CMD_FINI_RXQ_IN_LEN 4 6179 /* Instance of RXQ to destroy */ 6180 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 6181 6182 /* MC_CMD_FINI_RXQ_OUT msgresponse */ 6183 #define MC_CMD_FINI_RXQ_OUT_LEN 0 6184 6185 6186 /***********************************/ 6187 /* MC_CMD_FINI_TXQ 6188 * Teardown a TXQ. 6189 */ 6190 #define MC_CMD_FINI_TXQ 0x85 6191 6192 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6193 6194 /* MC_CMD_FINI_TXQ_IN msgrequest */ 6195 #define MC_CMD_FINI_TXQ_IN_LEN 4 6196 /* Instance of TXQ to destroy */ 6197 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 6198 6199 /* MC_CMD_FINI_TXQ_OUT msgresponse */ 6200 #define MC_CMD_FINI_TXQ_OUT_LEN 0 6201 6202 6203 /***********************************/ 6204 /* MC_CMD_DRIVER_EVENT 6205 * Generate an event on an EVQ belonging to the function issuing the command. 6206 */ 6207 #define MC_CMD_DRIVER_EVENT 0x86 6208 6209 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6210 6211 /* MC_CMD_DRIVER_EVENT_IN msgrequest */ 6212 #define MC_CMD_DRIVER_EVENT_IN_LEN 12 6213 /* Handle of target EVQ */ 6214 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 6215 /* Bits 0 - 63 of event */ 6216 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 6217 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 6218 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 6219 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 6220 6221 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ 6222 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 6223 6224 6225 /***********************************/ 6226 /* MC_CMD_PROXY_CMD 6227 * Execute an arbitrary MCDI command on behalf of a different function, subject 6228 * to security restrictions. The command to be proxied follows immediately 6229 * afterward in the host buffer (or on the UART). This command supercedes 6230 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. 6231 */ 6232 #define MC_CMD_PROXY_CMD 0x5b 6233 6234 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6235 6236 /* MC_CMD_PROXY_CMD_IN msgrequest */ 6237 #define MC_CMD_PROXY_CMD_IN_LEN 4 6238 /* The handle of the target function. */ 6239 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 6240 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 6241 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 6242 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 6243 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 6244 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ 6245 6246 /* MC_CMD_PROXY_CMD_OUT msgresponse */ 6247 #define MC_CMD_PROXY_CMD_OUT_LEN 0 6248 6249 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to 6250 * manage proxied requests 6251 */ 6252 #define MC_PROXY_STATUS_BUFFER_LEN 16 6253 /* Handle allocated by the firmware for this proxy transaction */ 6254 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 6255 /* enum: An invalid handle. */ 6256 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 6257 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 6258 #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 6259 /* The requesting physical function number */ 6260 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4 6261 #define MC_PROXY_STATUS_BUFFER_PF_LEN 2 6262 #define MC_PROXY_STATUS_BUFFER_PF_LBN 32 6263 #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 6264 /* The requesting virtual function number. Set to VF_NULL if the target is a 6265 * PF. 6266 */ 6267 #define MC_PROXY_STATUS_BUFFER_VF_OFST 6 6268 #define MC_PROXY_STATUS_BUFFER_VF_LEN 2 6269 #define MC_PROXY_STATUS_BUFFER_VF_LBN 48 6270 #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 6271 /* The target function RID. */ 6272 #define MC_PROXY_STATUS_BUFFER_RID_OFST 8 6273 #define MC_PROXY_STATUS_BUFFER_RID_LEN 2 6274 #define MC_PROXY_STATUS_BUFFER_RID_LBN 64 6275 #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 6276 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ 6277 #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 6278 #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 6279 #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 6280 #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 6281 /* If a request is authorized rather than carried out by the host, this is the 6282 * elevated privilege mask granted to the requesting function. 6283 */ 6284 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 6285 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 6286 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 6287 6288 6289 /***********************************/ 6290 /* MC_CMD_PROXY_CONFIGURE 6291 * Enable/disable authorization of MCDI requests from unprivileged functions by 6292 * a designated admin function 6293 */ 6294 #define MC_CMD_PROXY_CONFIGURE 0x58 6295 6296 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6297 6298 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ 6299 #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 6300 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 6301 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 6302 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 6303 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 6304 * of blocks, each of the size REQUEST_BLOCK_SIZE. 6305 */ 6306 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 6307 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 6308 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 6309 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 6310 /* Must be a power of 2 */ 6311 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 6312 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 6313 * of blocks, each of the size REPLY_BLOCK_SIZE. 6314 */ 6315 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 6316 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 6317 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 6318 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 6319 /* Must be a power of 2 */ 6320 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 6321 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 6322 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 6323 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 6324 */ 6325 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 6326 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 6327 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 6328 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 6329 /* Must be a power of 2, or zero if this buffer is not provided */ 6330 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 6331 /* Applies to all three buffers */ 6332 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 6333 /* A bit mask defining which MCDI operations may be proxied */ 6334 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 6335 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 6336 6337 /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */ 6338 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112 6339 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0 6340 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0 6341 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1 6342 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 6343 * of blocks, each of the size REQUEST_BLOCK_SIZE. 6344 */ 6345 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4 6346 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8 6347 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4 6348 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8 6349 /* Must be a power of 2 */ 6350 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12 6351 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 6352 * of blocks, each of the size REPLY_BLOCK_SIZE. 6353 */ 6354 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16 6355 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8 6356 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16 6357 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20 6358 /* Must be a power of 2 */ 6359 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24 6360 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 6361 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 6362 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 6363 */ 6364 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28 6365 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8 6366 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28 6367 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32 6368 /* Must be a power of 2, or zero if this buffer is not provided */ 6369 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36 6370 /* Applies to all three buffers */ 6371 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40 6372 /* A bit mask defining which MCDI operations may be proxied */ 6373 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44 6374 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64 6375 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108 6376 6377 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ 6378 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 6379 6380 6381 /***********************************/ 6382 /* MC_CMD_PROXY_COMPLETE 6383 * Tells FW that a requested proxy operation has either been completed (by 6384 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the 6385 * function that enabled proxying/authorization (by using 6386 * MC_CMD_PROXY_CONFIGURE). 6387 */ 6388 #define MC_CMD_PROXY_COMPLETE 0x5f 6389 6390 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6391 6392 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */ 6393 #define MC_CMD_PROXY_COMPLETE_IN_LEN 12 6394 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 6395 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 6396 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply 6397 * is stored in the REPLY_BUFF. 6398 */ 6399 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 6400 /* enum: The operation has been authorized. The originating function may now 6401 * try again. 6402 */ 6403 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 6404 /* enum: The operation has been declined. */ 6405 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 6406 /* enum: The authorization failed because the relevant application did not 6407 * respond in time. 6408 */ 6409 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 6410 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 6411 6412 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ 6413 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 6414 6415 6416 /***********************************/ 6417 /* MC_CMD_ALLOC_BUFTBL_CHUNK 6418 * Allocate a set of buffer table entries using the specified owner ID. This 6419 * operation allocates the required buffer table entries (and fails if it 6420 * cannot do so). The buffer table entries will initially be zeroed. 6421 */ 6422 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 6423 6424 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 6425 6426 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 6427 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 6428 /* Owner ID to use */ 6429 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 6430 /* Size of buffer table pages to use, in bytes (note that only a few values are 6431 * legal on any specific hardware). 6432 */ 6433 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 6434 6435 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 6436 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 6437 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 6438 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 6439 /* Buffer table IDs for use in DMA descriptors. */ 6440 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 6441 6442 6443 /***********************************/ 6444 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES 6445 * Reprogram a set of buffer table entries in the specified chunk. 6446 */ 6447 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 6448 6449 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 6450 6451 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 6452 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 6453 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 6454 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 6455 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 6456 /* ID */ 6457 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 6458 /* Num entries */ 6459 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 6460 /* Buffer table entry address */ 6461 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 6462 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 6463 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 6464 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 6465 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 6466 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 6467 6468 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 6469 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 6470 6471 6472 /***********************************/ 6473 /* MC_CMD_FREE_BUFTBL_CHUNK 6474 */ 6475 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 6476 6477 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 6478 6479 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 6480 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 6481 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 6482 6483 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 6484 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 6485 6486 /* PORT_CONFIG_ENTRY structuredef */ 6487 #define PORT_CONFIG_ENTRY_LEN 16 6488 /* External port number (label) */ 6489 #define PORT_CONFIG_ENTRY_EXT_NUMBER_OFST 0 6490 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LEN 1 6491 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LBN 0 6492 #define PORT_CONFIG_ENTRY_EXT_NUMBER_WIDTH 8 6493 /* Port core location */ 6494 #define PORT_CONFIG_ENTRY_CORE_OFST 1 6495 #define PORT_CONFIG_ENTRY_CORE_LEN 1 6496 #define PORT_CONFIG_ENTRY_STANDALONE 0x0 /* enum */ 6497 #define PORT_CONFIG_ENTRY_MASTER 0x1 /* enum */ 6498 #define PORT_CONFIG_ENTRY_SLAVE 0x2 /* enum */ 6499 #define PORT_CONFIG_ENTRY_CORE_LBN 8 6500 #define PORT_CONFIG_ENTRY_CORE_WIDTH 8 6501 /* Internal number (HW resource) relative to the core */ 6502 #define PORT_CONFIG_ENTRY_INT_NUMBER_OFST 2 6503 #define PORT_CONFIG_ENTRY_INT_NUMBER_LEN 1 6504 #define PORT_CONFIG_ENTRY_INT_NUMBER_LBN 16 6505 #define PORT_CONFIG_ENTRY_INT_NUMBER_WIDTH 8 6506 /* Reserved */ 6507 #define PORT_CONFIG_ENTRY_RSVD_OFST 3 6508 #define PORT_CONFIG_ENTRY_RSVD_LEN 1 6509 #define PORT_CONFIG_ENTRY_RSVD_LBN 24 6510 #define PORT_CONFIG_ENTRY_RSVD_WIDTH 8 6511 /* Bitmask of KR lanes used by the port */ 6512 #define PORT_CONFIG_ENTRY_LANES_OFST 4 6513 #define PORT_CONFIG_ENTRY_LANES_LBN 32 6514 #define PORT_CONFIG_ENTRY_LANES_WIDTH 32 6515 /* Port capabilities (MC_CMD_PHY_CAP_*) */ 6516 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_OFST 8 6517 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_LBN 64 6518 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_WIDTH 32 6519 /* Reserved (align to 16 bytes) */ 6520 #define PORT_CONFIG_ENTRY_RSVD2_OFST 12 6521 #define PORT_CONFIG_ENTRY_RSVD2_LBN 96 6522 #define PORT_CONFIG_ENTRY_RSVD2_WIDTH 32 6523 6524 6525 /***********************************/ 6526 /* MC_CMD_FILTER_OP 6527 * Multiplexed MCDI call for filter operations 6528 */ 6529 #define MC_CMD_FILTER_OP 0x8a 6530 6531 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6532 6533 /* MC_CMD_FILTER_OP_IN msgrequest */ 6534 #define MC_CMD_FILTER_OP_IN_LEN 108 6535 /* identifies the type of operation requested */ 6536 #define MC_CMD_FILTER_OP_IN_OP_OFST 0 6537 /* enum: single-recipient filter insert */ 6538 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 6539 /* enum: single-recipient filter remove */ 6540 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 6541 /* enum: multi-recipient filter subscribe */ 6542 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 6543 /* enum: multi-recipient filter unsubscribe */ 6544 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 6545 /* enum: replace one recipient with another (warning - the filter handle may 6546 * change) 6547 */ 6548 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 6549 /* filter handle (for remove / unsubscribe operations) */ 6550 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 6551 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 6552 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 6553 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 6554 /* The port ID associated with the v-adaptor which should contain this filter. 6555 */ 6556 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 6557 /* fields to include in match criteria */ 6558 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 6559 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 6560 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 6561 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 6562 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 6563 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 6564 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 6565 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 6566 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 6567 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 6568 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 6569 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 6570 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 6571 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 6572 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 6573 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 6574 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 6575 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 6576 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 6577 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 6578 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 6579 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 6580 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 6581 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 6582 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 6583 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 6584 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 6585 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 6586 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 6587 /* receive destination */ 6588 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 6589 /* enum: drop packets */ 6590 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 6591 /* enum: receive to host */ 6592 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 6593 /* enum: receive to MC */ 6594 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 6595 /* enum: loop back to TXDP 0 */ 6596 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 6597 /* enum: loop back to TXDP 1 */ 6598 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 6599 /* receive queue handle (for multiple queue modes, this is the base queue) */ 6600 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 6601 /* receive mode */ 6602 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 6603 /* enum: receive to just the specified queue */ 6604 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 6605 /* enum: receive to multiple queues using RSS context */ 6606 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 6607 /* enum: receive to multiple queues using .1p mapping */ 6608 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 6609 /* enum: install a filter entry that will never match; for test purposes only 6610 */ 6611 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 6612 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 6613 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 6614 * MC_CMD_DOT1P_MAPPING_ALLOC. 6615 */ 6616 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 6617 /* transmit domain (reserved; set to 0) */ 6618 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 6619 /* transmit destination (either set the MAC and/or PM bits for explicit 6620 * control, or set this field to TX_DEST_DEFAULT for sensible default 6621 * behaviour) 6622 */ 6623 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 6624 /* enum: request default behaviour (based on filter type) */ 6625 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff 6626 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 6627 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 6628 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 6629 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 6630 /* source MAC address to match (as bytes in network order) */ 6631 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 6632 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 6633 /* source port to match (as bytes in network order) */ 6634 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 6635 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 6636 /* destination MAC address to match (as bytes in network order) */ 6637 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 6638 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 6639 /* destination port to match (as bytes in network order) */ 6640 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 6641 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 6642 /* Ethernet type to match (as bytes in network order) */ 6643 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 6644 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 6645 /* Inner VLAN tag to match (as bytes in network order) */ 6646 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 6647 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 6648 /* Outer VLAN tag to match (as bytes in network order) */ 6649 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 6650 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 6651 /* IP protocol to match (in low byte; set high byte to 0) */ 6652 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 6653 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 6654 /* Firmware defined register 0 to match (reserved; set to 0) */ 6655 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 6656 /* Firmware defined register 1 to match (reserved; set to 0) */ 6657 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 6658 /* source IP address to match (as bytes in network order; set last 12 bytes to 6659 * 0 for IPv4 address) 6660 */ 6661 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 6662 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 6663 /* destination IP address to match (as bytes in network order; set last 12 6664 * bytes to 0 for IPv4 address) 6665 */ 6666 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 6667 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 6668 6669 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to 6670 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is 6671 * supported on Medford only). 6672 */ 6673 #define MC_CMD_FILTER_OP_EXT_IN_LEN 172 6674 /* identifies the type of operation requested */ 6675 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 6676 /* Enum values, see field(s): */ 6677 /* MC_CMD_FILTER_OP_IN/OP */ 6678 /* filter handle (for remove / unsubscribe operations) */ 6679 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 6680 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 6681 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 6682 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 6683 /* The port ID associated with the v-adaptor which should contain this filter. 6684 */ 6685 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 6686 /* fields to include in match criteria */ 6687 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 6688 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 6689 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 6690 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 6691 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 6692 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 6693 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 6694 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 6695 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 6696 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 6697 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 6698 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 6699 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 6700 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 6701 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 6702 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 6703 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 6704 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 6705 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 6706 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 6707 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 6708 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 6709 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 6710 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 6711 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 6712 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 6713 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 6714 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 6715 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 6716 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 6717 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 6718 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 6719 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 6720 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 6721 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 6722 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 6723 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 6724 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 6725 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 6726 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 6727 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 6728 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 6729 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 6730 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 6731 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 6732 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 6733 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 6734 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 6735 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 6736 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 6737 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 6738 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 6739 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 6740 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 6741 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 6742 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 6743 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 6744 /* receive destination */ 6745 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 6746 /* enum: drop packets */ 6747 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 6748 /* enum: receive to host */ 6749 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 6750 /* enum: receive to MC */ 6751 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 6752 /* enum: loop back to TXDP 0 */ 6753 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 6754 /* enum: loop back to TXDP 1 */ 6755 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 6756 /* receive queue handle (for multiple queue modes, this is the base queue) */ 6757 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 6758 /* receive mode */ 6759 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 6760 /* enum: receive to just the specified queue */ 6761 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 6762 /* enum: receive to multiple queues using RSS context */ 6763 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 6764 /* enum: receive to multiple queues using .1p mapping */ 6765 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 6766 /* enum: install a filter entry that will never match; for test purposes only 6767 */ 6768 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 6769 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 6770 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 6771 * MC_CMD_DOT1P_MAPPING_ALLOC. 6772 */ 6773 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 6774 /* transmit domain (reserved; set to 0) */ 6775 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 6776 /* transmit destination (either set the MAC and/or PM bits for explicit 6777 * control, or set this field to TX_DEST_DEFAULT for sensible default 6778 * behaviour) 6779 */ 6780 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 6781 /* enum: request default behaviour (based on filter type) */ 6782 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff 6783 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 6784 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 6785 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 6786 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 6787 /* source MAC address to match (as bytes in network order) */ 6788 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 6789 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 6790 /* source port to match (as bytes in network order) */ 6791 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 6792 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 6793 /* destination MAC address to match (as bytes in network order) */ 6794 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 6795 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 6796 /* destination port to match (as bytes in network order) */ 6797 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 6798 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 6799 /* Ethernet type to match (as bytes in network order) */ 6800 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 6801 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 6802 /* Inner VLAN tag to match (as bytes in network order) */ 6803 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 6804 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 6805 /* Outer VLAN tag to match (as bytes in network order) */ 6806 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 6807 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 6808 /* IP protocol to match (in low byte; set high byte to 0) */ 6809 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 6810 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 6811 /* Firmware defined register 0 to match (reserved; set to 0) */ 6812 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 6813 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 6814 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 6815 * VXLAN/NVGRE, or 1 for Geneve) 6816 */ 6817 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 6818 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 6819 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 6820 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 6821 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 6822 /* enum: Match VXLAN traffic with this VNI */ 6823 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 6824 /* enum: Match Geneve traffic with this VNI */ 6825 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 6826 /* enum: Reserved for experimental development use */ 6827 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe 6828 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 6829 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 6830 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 6831 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 6832 /* enum: Match NVGRE traffic with this VSID */ 6833 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 6834 /* source IP address to match (as bytes in network order; set last 12 bytes to 6835 * 0 for IPv4 address) 6836 */ 6837 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 6838 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 6839 /* destination IP address to match (as bytes in network order; set last 12 6840 * bytes to 0 for IPv4 address) 6841 */ 6842 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 6843 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 6844 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 6845 * order) 6846 */ 6847 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 6848 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 6849 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 6850 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 6851 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 6852 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 6853 * network order) 6854 */ 6855 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 6856 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 6857 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network 6858 * order) 6859 */ 6860 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 6861 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 6862 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 6863 */ 6864 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 6865 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 6866 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 6867 */ 6868 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 6869 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 6870 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 6871 */ 6872 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 6873 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 6874 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 6875 * 0) 6876 */ 6877 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 6878 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 6879 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 6880 * to 0) 6881 */ 6882 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 6883 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 6884 * to 0) 6885 */ 6886 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 6887 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 6888 * order; set last 12 bytes to 0 for IPv4 address) 6889 */ 6890 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 6891 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 6892 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 6893 * order; set last 12 bytes to 0 for IPv4 address) 6894 */ 6895 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 6896 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16 6897 6898 /* MC_CMD_FILTER_OP_OUT msgresponse */ 6899 #define MC_CMD_FILTER_OP_OUT_LEN 12 6900 /* identifies the type of operation requested */ 6901 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 6902 /* Enum values, see field(s): */ 6903 /* MC_CMD_FILTER_OP_IN/OP */ 6904 /* Returned filter handle (for insert / subscribe operations). Note that these 6905 * handles should be considered opaque to the host, although a value of 6906 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 6907 */ 6908 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 6909 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 6910 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 6911 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 6912 /* enum: guaranteed invalid filter handle (low 32 bits) */ 6913 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff 6914 /* enum: guaranteed invalid filter handle (high 32 bits) */ 6915 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff 6916 6917 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ 6918 #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 6919 /* identifies the type of operation requested */ 6920 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 6921 /* Enum values, see field(s): */ 6922 /* MC_CMD_FILTER_OP_EXT_IN/OP */ 6923 /* Returned filter handle (for insert / subscribe operations). Note that these 6924 * handles should be considered opaque to the host, although a value of 6925 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 6926 */ 6927 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 6928 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 6929 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 6930 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 6931 /* Enum values, see field(s): */ 6932 /* MC_CMD_FILTER_OP_OUT/HANDLE */ 6933 6934 6935 /***********************************/ 6936 /* MC_CMD_GET_PARSER_DISP_INFO 6937 * Get information related to the parser-dispatcher subsystem 6938 */ 6939 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 6940 6941 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6942 6943 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ 6944 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 6945 /* identifies the type of operation requested */ 6946 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 6947 /* enum: read the list of supported RX filter matches */ 6948 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 6949 /* enum: read flags indicating restrictions on filter insertion for the calling 6950 * client 6951 */ 6952 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 6953 /* enum: read properties relating to security rules (Medford-only; for use by 6954 * SolarSecure apps, not directly by drivers. See SF-114946-SW.) 6955 */ 6956 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3 6957 /* enum: read the list of supported RX filter matches for VXLAN/NVGRE 6958 * encapsulated frames, which follow a different match sequence to normal 6959 * frames (Medford only) 6960 */ 6961 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4 6962 6963 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 6964 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 6965 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 6966 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) 6967 /* identifies the type of operation requested */ 6968 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 6969 /* Enum values, see field(s): */ 6970 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 6971 /* number of supported match types */ 6972 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 6973 /* array of supported match types (valid MATCH_FIELDS values for 6974 * MC_CMD_FILTER_OP) sorted in decreasing priority order 6975 */ 6976 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 6977 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 6978 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 6979 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 6980 6981 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */ 6982 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8 6983 /* identifies the type of operation requested */ 6984 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0 6985 /* Enum values, see field(s): */ 6986 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 6987 /* bitfield of filter insertion restrictions */ 6988 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4 6989 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 6990 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 6991 6992 6993 /***********************************/ 6994 /* MC_CMD_PARSER_DISP_RW 6995 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. 6996 * Please note that this interface is only of use to debug tools which have 6997 * knowledge of firmware and hardware data structures; nothing here is intended 6998 * for use by normal driver code. 6999 */ 7000 #define MC_CMD_PARSER_DISP_RW 0xe5 7001 7002 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7003 7004 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 7005 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 7006 /* identifies the target of the operation */ 7007 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 7008 /* enum: RX dispatcher CPU */ 7009 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 7010 /* enum: TX dispatcher CPU */ 7011 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 7012 /* enum: Lookup engine (with original metadata format) */ 7013 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 7014 /* enum: Lookup engine (with requested metadata format) */ 7015 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 7016 /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */ 7017 #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0 7018 /* enum: RX1 dispatcher CPU (only valid for Medford) */ 7019 #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4 7020 /* enum: Miscellaneous other state (only valid for Medford) */ 7021 #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5 7022 /* identifies the type of operation requested */ 7023 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 7024 /* enum: read a word of DICPU DMEM or a LUE entry */ 7025 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 7026 /* enum: write a word of DICPU DMEM or a LUE entry */ 7027 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 7028 /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ 7029 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 7030 /* data memory address (DICPU targets) or LUE index (LUE targets) */ 7031 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 7032 /* selector (for MISC_STATE target) */ 7033 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8 7034 /* enum: Port to datapath mapping */ 7035 #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1 7036 /* value to write (for DMEM writes) */ 7037 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 7038 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 7039 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 7040 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 7041 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 7042 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ 7043 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 7044 /* value to write (for LUE writes) */ 7045 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 7046 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 7047 7048 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 7049 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 7050 /* value read (for DMEM reads) */ 7051 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 7052 /* value read (for LUE reads) */ 7053 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 7054 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 7055 /* up to 8 32-bit words of additional soft state from the LUE manager (the 7056 * exact content is firmware-dependent and intended only for debug use) 7057 */ 7058 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 7059 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 7060 /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */ 7061 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0 7062 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4 7063 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4 7064 #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ 7065 #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ 7066 7067 7068 /***********************************/ 7069 /* MC_CMD_GET_PF_COUNT 7070 * Get number of PFs on the device. 7071 */ 7072 #define MC_CMD_GET_PF_COUNT 0xb6 7073 7074 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7075 7076 /* MC_CMD_GET_PF_COUNT_IN msgrequest */ 7077 #define MC_CMD_GET_PF_COUNT_IN_LEN 0 7078 7079 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 7080 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 7081 /* Identifies the number of PFs on the device. */ 7082 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 7083 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 7084 7085 7086 /***********************************/ 7087 /* MC_CMD_SET_PF_COUNT 7088 * Set number of PFs on the device. 7089 */ 7090 #define MC_CMD_SET_PF_COUNT 0xb7 7091 7092 /* MC_CMD_SET_PF_COUNT_IN msgrequest */ 7093 #define MC_CMD_SET_PF_COUNT_IN_LEN 4 7094 /* New number of PFs on the device. */ 7095 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 7096 7097 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 7098 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 7099 7100 7101 /***********************************/ 7102 /* MC_CMD_GET_PORT_ASSIGNMENT 7103 * Get port assignment for current PCI function. 7104 */ 7105 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 7106 7107 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7108 7109 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 7110 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 7111 7112 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 7113 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 7114 /* Identifies the port assignment for this function. */ 7115 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 7116 7117 7118 /***********************************/ 7119 /* MC_CMD_SET_PORT_ASSIGNMENT 7120 * Set port assignment for current PCI function. 7121 */ 7122 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 7123 7124 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7125 7126 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 7127 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 7128 /* Identifies the port assignment for this function. */ 7129 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 7130 7131 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 7132 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 7133 7134 7135 /***********************************/ 7136 /* MC_CMD_ALLOC_VIS 7137 * Allocate VIs for current PCI function. 7138 */ 7139 #define MC_CMD_ALLOC_VIS 0x8b 7140 7141 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7142 7143 /* MC_CMD_ALLOC_VIS_IN msgrequest */ 7144 #define MC_CMD_ALLOC_VIS_IN_LEN 8 7145 /* The minimum number of VIs that is acceptable */ 7146 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 7147 /* The maximum number of VIs that would be useful */ 7148 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 7149 7150 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. 7151 * Use extended version in new code. 7152 */ 7153 #define MC_CMD_ALLOC_VIS_OUT_LEN 8 7154 /* The number of VIs allocated on this function */ 7155 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 7156 /* The base absolute VI number allocated to this function. Required to 7157 * correctly interpret wakeup events. 7158 */ 7159 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 7160 7161 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ 7162 #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 7163 /* The number of VIs allocated on this function */ 7164 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 7165 /* The base absolute VI number allocated to this function. Required to 7166 * correctly interpret wakeup events. 7167 */ 7168 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 7169 /* Function's port vi_shift value (always 0 on Huntington) */ 7170 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 7171 7172 7173 /***********************************/ 7174 /* MC_CMD_FREE_VIS 7175 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, 7176 * but not freed. 7177 */ 7178 #define MC_CMD_FREE_VIS 0x8c 7179 7180 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7181 7182 /* MC_CMD_FREE_VIS_IN msgrequest */ 7183 #define MC_CMD_FREE_VIS_IN_LEN 0 7184 7185 /* MC_CMD_FREE_VIS_OUT msgresponse */ 7186 #define MC_CMD_FREE_VIS_OUT_LEN 0 7187 7188 7189 /***********************************/ 7190 /* MC_CMD_GET_SRIOV_CFG 7191 * Get SRIOV config for this PF. 7192 */ 7193 #define MC_CMD_GET_SRIOV_CFG 0xba 7194 7195 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7196 7197 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 7198 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 7199 7200 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 7201 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 7202 /* Number of VFs currently enabled. */ 7203 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 7204 /* Max number of VFs before sriov stride and offset may need to be changed. */ 7205 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 7206 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 7207 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 7208 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 7209 /* RID offset of first VF from PF. */ 7210 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 7211 /* RID offset of each subsequent VF from the previous. */ 7212 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 7213 7214 7215 /***********************************/ 7216 /* MC_CMD_SET_SRIOV_CFG 7217 * Set SRIOV config for this PF. 7218 */ 7219 #define MC_CMD_SET_SRIOV_CFG 0xbb 7220 7221 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7222 7223 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 7224 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 7225 /* Number of VFs currently enabled. */ 7226 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 7227 /* Max number of VFs before sriov stride and offset may need to be changed. */ 7228 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 7229 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 7230 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 7231 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 7232 /* RID offset of first VF from PF, or 0 for no change, or 7233 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 7234 */ 7235 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 7236 /* RID offset of each subsequent VF from the previous, 0 for no change, or 7237 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 7238 */ 7239 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 7240 7241 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 7242 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 7243 7244 7245 /***********************************/ 7246 /* MC_CMD_GET_VI_ALLOC_INFO 7247 * Get information about number of VI's and base VI number allocated to this 7248 * function. 7249 */ 7250 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d 7251 7252 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7253 7254 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 7255 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 7256 7257 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 7258 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 7259 /* The number of VIs allocated on this function */ 7260 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 7261 /* The base absolute VI number allocated to this function. Required to 7262 * correctly interpret wakeup events. 7263 */ 7264 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 7265 /* Function's port vi_shift value (always 0 on Huntington) */ 7266 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 7267 7268 7269 /***********************************/ 7270 /* MC_CMD_DUMP_VI_STATE 7271 * For CmdClient use. Dump pertinent information on a specific absolute VI. 7272 */ 7273 #define MC_CMD_DUMP_VI_STATE 0x8e 7274 7275 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7276 7277 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 7278 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 7279 /* The VI number to query. */ 7280 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 7281 7282 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 7283 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 7284 /* The PF part of the function owning this VI. */ 7285 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 7286 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 7287 /* The VF part of the function owning this VI. */ 7288 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 7289 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 7290 /* Base of VIs allocated to this function. */ 7291 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 7292 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 7293 /* Count of VIs allocated to the owner function. */ 7294 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 7295 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 7296 /* Base interrupt vector allocated to this function. */ 7297 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 7298 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 7299 /* Number of interrupt vectors allocated to this function. */ 7300 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 7301 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 7302 /* Raw evq ptr table data. */ 7303 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 7304 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 7305 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 7306 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 7307 /* Raw evq timer table data. */ 7308 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 7309 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 7310 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 7311 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 7312 /* Combined metadata field. */ 7313 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 7314 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 7315 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 7316 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 7317 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 7318 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 7319 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 7320 /* TXDPCPU raw table data for queue. */ 7321 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 7322 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 7323 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 7324 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 7325 /* TXDPCPU raw table data for queue. */ 7326 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 7327 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 7328 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 7329 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 7330 /* TXDPCPU raw table data for queue. */ 7331 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 7332 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 7333 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 7334 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 7335 /* Combined metadata field. */ 7336 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 7337 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 7338 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 7339 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 7340 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 7341 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 7342 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 7343 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 7344 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 7345 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 7346 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 7347 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 7348 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 7349 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 7350 /* RXDPCPU raw table data for queue. */ 7351 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 7352 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 7353 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 7354 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 7355 /* RXDPCPU raw table data for queue. */ 7356 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 7357 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 7358 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 7359 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 7360 /* Reserved, currently 0. */ 7361 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 7362 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 7363 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 7364 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 7365 /* Combined metadata field. */ 7366 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 7367 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 7368 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 7369 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 7370 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 7371 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 7372 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 7373 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 7374 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 7375 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 7376 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 7377 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 7378 7379 7380 /***********************************/ 7381 /* MC_CMD_ALLOC_PIOBUF 7382 * Allocate a push I/O buffer for later use with a tx queue. 7383 */ 7384 #define MC_CMD_ALLOC_PIOBUF 0x8f 7385 7386 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 7387 7388 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 7389 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 7390 7391 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 7392 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 7393 /* Handle for allocated push I/O buffer. */ 7394 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 7395 7396 7397 /***********************************/ 7398 /* MC_CMD_FREE_PIOBUF 7399 * Free a push I/O buffer. 7400 */ 7401 #define MC_CMD_FREE_PIOBUF 0x90 7402 7403 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 7404 7405 /* MC_CMD_FREE_PIOBUF_IN msgrequest */ 7406 #define MC_CMD_FREE_PIOBUF_IN_LEN 4 7407 /* Handle for allocated push I/O buffer. */ 7408 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 7409 7410 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 7411 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 7412 7413 7414 /***********************************/ 7415 /* MC_CMD_GET_VI_TLP_PROCESSING 7416 * Get TLP steering and ordering information for a VI. 7417 */ 7418 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 7419 7420 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7421 7422 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 7423 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 7424 /* VI number to get information for. */ 7425 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 7426 7427 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 7428 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 7429 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 7430 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 7431 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 7432 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 7433 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 7434 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 7435 /* Use Relaxed ordering model for TLPs on this VI. */ 7436 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 7437 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 7438 /* Use ID based ordering for TLPs on this VI. */ 7439 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 7440 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 7441 /* Set no snoop bit for TLPs on this VI. */ 7442 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 7443 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 7444 /* Enable TPH for TLPs on this VI. */ 7445 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 7446 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 7447 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 7448 7449 7450 /***********************************/ 7451 /* MC_CMD_SET_VI_TLP_PROCESSING 7452 * Set TLP steering and ordering information for a VI. 7453 */ 7454 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 7455 7456 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7457 7458 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 7459 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 7460 /* VI number to set information for. */ 7461 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 7462 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 7463 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 7464 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 7465 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 7466 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 7467 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 7468 /* Use Relaxed ordering model for TLPs on this VI. */ 7469 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 7470 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 7471 /* Use ID based ordering for TLPs on this VI. */ 7472 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 7473 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 7474 /* Set the no snoop bit for TLPs on this VI. */ 7475 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 7476 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 7477 /* Enable TPH for TLPs on this VI. */ 7478 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 7479 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 7480 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 7481 7482 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 7483 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 7484 7485 7486 /***********************************/ 7487 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS 7488 * Get global PCIe steering and transaction processing configuration. 7489 */ 7490 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 7491 7492 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7493 7494 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 7495 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 7496 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 7497 /* enum: MISC. */ 7498 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 7499 /* enum: IDO. */ 7500 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 7501 /* enum: RO. */ 7502 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 7503 /* enum: TPH Type. */ 7504 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 7505 7506 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 7507 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 7508 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 7509 /* Enum values, see field(s): */ 7510 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 7511 /* Amalgamated TLP info word. */ 7512 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 7513 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 7514 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 7515 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 7516 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 7517 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 7518 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 7519 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 7520 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 7521 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 7522 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 7523 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 7524 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 7525 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 7526 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 7527 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 7528 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 7529 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 7530 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 7531 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 7532 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 7533 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 7534 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 7535 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 7536 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 7537 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 7538 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 7539 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 7540 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 7541 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 7542 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 7543 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 7544 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 7545 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 7546 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 7547 7548 7549 /***********************************/ 7550 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS 7551 * Set global PCIe steering and transaction processing configuration. 7552 */ 7553 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 7554 7555 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7556 7557 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 7558 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 7559 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 7560 /* Enum values, see field(s): */ 7561 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 7562 /* Amalgamated TLP info word. */ 7563 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 7564 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 7565 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 7566 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 7567 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 7568 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 7569 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 7570 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 7571 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 7572 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 7573 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 7574 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 7575 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 7576 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 7577 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 7578 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 7579 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 7580 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 7581 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 7582 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 7583 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 7584 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 7585 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 7586 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 7587 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 7588 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 7589 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 7590 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 7591 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 7592 7593 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 7594 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 7595 7596 7597 /***********************************/ 7598 /* MC_CMD_SATELLITE_DOWNLOAD 7599 * Download a new set of images to the satellite CPUs from the host. 7600 */ 7601 #define MC_CMD_SATELLITE_DOWNLOAD 0x91 7602 7603 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7604 7605 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 7606 * are subtle, and so downloads must proceed in a number of phases. 7607 * 7608 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 7609 * 7610 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 7611 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 7612 * be a checksum (a simple 32-bit sum) of the transferred data. An individual 7613 * download may be aborted using CHUNK_ID_ABORT. 7614 * 7615 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 7616 * similar to PHASE_IMEMS. 7617 * 7618 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 7619 * 7620 * After any error (a requested abort is not considered to be an error) the 7621 * sequence must be restarted from PHASE_RESET. 7622 */ 7623 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 7624 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 7625 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 7626 /* Download phase. (Note: the IDLE phase is used internally and is never valid 7627 * in a command from the host.) 7628 */ 7629 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 7630 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 7631 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 7632 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 7633 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 7634 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 7635 /* Target for download. (These match the blob numbers defined in 7636 * mc_flash_layout.h.) 7637 */ 7638 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 7639 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7640 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 7641 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7642 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 7643 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7644 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 7645 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7646 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 7647 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7648 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 7649 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7650 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 7651 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7652 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 7653 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7654 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 7655 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7656 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 7657 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7658 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 7659 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7660 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 7661 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 7662 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 7663 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 7664 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 7665 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 7666 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 7667 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 7668 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 7669 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 7670 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 7671 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 7672 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 7673 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 7674 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 7675 /* enum: Last chunk, containing checksum rather than data */ 7676 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 7677 /* enum: Abort download of this item */ 7678 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 7679 /* Length of this chunk in bytes */ 7680 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 7681 /* Data for this chunk */ 7682 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 7683 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 7684 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 7685 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 7686 7687 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 7688 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 7689 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 7690 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 7691 /* Extra status information */ 7692 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 7693 /* enum: Code download OK, completed. */ 7694 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 7695 /* enum: Code download aborted as requested. */ 7696 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 7697 /* enum: Code download OK so far, send next chunk. */ 7698 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 7699 /* enum: Download phases out of sequence */ 7700 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 7701 /* enum: Bad target for this phase */ 7702 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 7703 /* enum: Chunk ID out of sequence */ 7704 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 7705 /* enum: Chunk length zero or too large */ 7706 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 7707 /* enum: Checksum was incorrect */ 7708 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 7709 7710 7711 /***********************************/ 7712 /* MC_CMD_GET_CAPABILITIES 7713 * Get device capabilities. 7714 * 7715 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 7716 * reference inherent device capabilities as opposed to current NVRAM config. 7717 */ 7718 #define MC_CMD_GET_CAPABILITIES 0xbe 7719 7720 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7721 7722 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ 7723 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 7724 7725 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ 7726 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 7727 /* First word of flags. */ 7728 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 7729 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3 7730 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1 7731 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4 7732 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1 7733 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5 7734 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1 7735 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 7736 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 7737 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7 7738 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 7739 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8 7740 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 7741 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9 7742 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1 7743 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 7744 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 7745 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 7746 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 7747 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 7748 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 7749 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 7750 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 7751 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14 7752 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1 7753 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 7754 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 7755 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16 7756 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1 7757 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17 7758 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1 7759 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18 7760 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1 7761 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 7762 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 7763 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 7764 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 7765 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 7766 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 7767 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 7768 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 7769 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 7770 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 7771 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 7772 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 7773 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 7774 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 7775 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 7776 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 7777 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 7778 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 7779 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28 7780 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1 7781 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 7782 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 7783 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30 7784 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1 7785 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31 7786 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1 7787 /* RxDPCPU firmware id. */ 7788 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 7789 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 7790 /* enum: Standard RXDP firmware */ 7791 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 7792 /* enum: Low latency RXDP firmware */ 7793 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 7794 /* enum: Packed stream RXDP firmware */ 7795 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2 7796 /* enum: BIST RXDP firmware */ 7797 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a 7798 /* enum: RXDP Test firmware image 1 */ 7799 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 7800 /* enum: RXDP Test firmware image 2 */ 7801 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 7802 /* enum: RXDP Test firmware image 3 */ 7803 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 7804 /* enum: RXDP Test firmware image 4 */ 7805 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 7806 /* enum: RXDP Test firmware image 5 */ 7807 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 7808 /* enum: RXDP Test firmware image 6 */ 7809 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 7810 /* enum: RXDP Test firmware image 7 */ 7811 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 7812 /* enum: RXDP Test firmware image 8 */ 7813 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 7814 /* enum: RXDP Test firmware image 9 */ 7815 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 7816 /* TxDPCPU firmware id. */ 7817 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 7818 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 7819 /* enum: Standard TXDP firmware */ 7820 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 7821 /* enum: Low latency TXDP firmware */ 7822 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 7823 /* enum: High packet rate TXDP firmware */ 7824 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3 7825 /* enum: BIST TXDP firmware */ 7826 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d 7827 /* enum: TXDP Test firmware image 1 */ 7828 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 7829 /* enum: TXDP Test firmware image 2 */ 7830 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 7831 /* enum: TXDP CSR bus test firmware */ 7832 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103 7833 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 7834 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 7835 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 7836 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 7837 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 7838 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 7839 /* enum: reserved value - do not use (may indicate alternative interpretation 7840 * of REV field in future) 7841 */ 7842 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0 7843 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 7844 * development only) 7845 */ 7846 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 7847 /* enum: RX PD firmware with approximately Siena-compatible behaviour 7848 * (Huntington development only) 7849 */ 7850 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 7851 /* enum: Virtual switching (full feature) RX PD production firmware */ 7852 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 7853 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 7854 * (Huntington development only) 7855 */ 7856 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 7857 /* enum: Low latency RX PD production firmware */ 7858 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 7859 /* enum: Packed stream RX PD production firmware */ 7860 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 7861 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 7862 * tests (Medford development only) 7863 */ 7864 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 7865 /* enum: Rules engine RX PD production firmware */ 7866 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 7867 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 7868 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 7869 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 7870 * encapsulations (Medford development only) 7871 */ 7872 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 7873 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 7874 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 7875 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 7876 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 7877 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 7878 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 7879 /* enum: reserved value - do not use (may indicate alternative interpretation 7880 * of REV field in future) 7881 */ 7882 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0 7883 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 7884 * development only) 7885 */ 7886 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 7887 /* enum: TX PD firmware with approximately Siena-compatible behaviour 7888 * (Huntington development only) 7889 */ 7890 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 7891 /* enum: Virtual switching (full feature) TX PD production firmware */ 7892 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 7893 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 7894 * (Huntington development only) 7895 */ 7896 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 7897 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 7898 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 7899 * tests (Medford development only) 7900 */ 7901 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 7902 /* enum: Rules engine TX PD production firmware */ 7903 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 7904 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 7905 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 7906 /* Hardware capabilities of NIC */ 7907 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 7908 /* Licensed capabilities */ 7909 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 7910 7911 /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */ 7912 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0 7913 7914 /* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */ 7915 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72 7916 /* First word of flags. */ 7917 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0 7918 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3 7919 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1 7920 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4 7921 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1 7922 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5 7923 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1 7924 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 7925 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 7926 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7 7927 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 7928 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8 7929 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 7930 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9 7931 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1 7932 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 7933 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 7934 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 7935 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 7936 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 7937 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 7938 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13 7939 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 7940 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14 7941 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1 7942 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 7943 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 7944 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16 7945 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1 7946 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17 7947 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1 7948 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18 7949 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1 7950 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19 7951 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1 7952 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20 7953 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1 7954 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21 7955 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1 7956 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22 7957 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1 7958 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23 7959 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1 7960 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24 7961 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1 7962 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25 7963 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1 7964 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26 7965 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1 7966 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27 7967 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 7968 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28 7969 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1 7970 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 7971 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 7972 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30 7973 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1 7974 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31 7975 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1 7976 /* RxDPCPU firmware id. */ 7977 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4 7978 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2 7979 /* enum: Standard RXDP firmware */ 7980 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0 7981 /* enum: Low latency RXDP firmware */ 7982 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1 7983 /* enum: Packed stream RXDP firmware */ 7984 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2 7985 /* enum: BIST RXDP firmware */ 7986 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a 7987 /* enum: RXDP Test firmware image 1 */ 7988 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 7989 /* enum: RXDP Test firmware image 2 */ 7990 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 7991 /* enum: RXDP Test firmware image 3 */ 7992 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 7993 /* enum: RXDP Test firmware image 4 */ 7994 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 7995 /* enum: RXDP Test firmware image 5 */ 7996 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105 7997 /* enum: RXDP Test firmware image 6 */ 7998 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 7999 /* enum: RXDP Test firmware image 7 */ 8000 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 8001 /* enum: RXDP Test firmware image 8 */ 8002 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 8003 /* enum: RXDP Test firmware image 9 */ 8004 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 8005 /* TxDPCPU firmware id. */ 8006 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6 8007 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2 8008 /* enum: Standard TXDP firmware */ 8009 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0 8010 /* enum: Low latency TXDP firmware */ 8011 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1 8012 /* enum: High packet rate TXDP firmware */ 8013 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3 8014 /* enum: BIST TXDP firmware */ 8015 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d 8016 /* enum: TXDP Test firmware image 1 */ 8017 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 8018 /* enum: TXDP Test firmware image 2 */ 8019 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 8020 /* enum: TXDP CSR bus test firmware */ 8021 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103 8022 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8 8023 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2 8024 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0 8025 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12 8026 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12 8027 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 8028 /* enum: reserved value - do not use (may indicate alternative interpretation 8029 * of REV field in future) 8030 */ 8031 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0 8032 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 8033 * development only) 8034 */ 8035 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 8036 /* enum: RX PD firmware with approximately Siena-compatible behaviour 8037 * (Huntington development only) 8038 */ 8039 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 8040 /* enum: Virtual switching (full feature) RX PD production firmware */ 8041 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3 8042 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 8043 * (Huntington development only) 8044 */ 8045 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 8046 /* enum: Low latency RX PD production firmware */ 8047 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 8048 /* enum: Packed stream RX PD production firmware */ 8049 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 8050 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 8051 * tests (Medford development only) 8052 */ 8053 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 8054 /* enum: Rules engine RX PD production firmware */ 8055 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 8056 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 8057 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 8058 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 8059 * encapsulations (Medford development only) 8060 */ 8061 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 8062 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10 8063 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2 8064 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0 8065 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12 8066 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12 8067 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 8068 /* enum: reserved value - do not use (may indicate alternative interpretation 8069 * of REV field in future) 8070 */ 8071 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0 8072 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 8073 * development only) 8074 */ 8075 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 8076 /* enum: TX PD firmware with approximately Siena-compatible behaviour 8077 * (Huntington development only) 8078 */ 8079 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 8080 /* enum: Virtual switching (full feature) TX PD production firmware */ 8081 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3 8082 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 8083 * (Huntington development only) 8084 */ 8085 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 8086 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 8087 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 8088 * tests (Medford development only) 8089 */ 8090 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 8091 /* enum: Rules engine TX PD production firmware */ 8092 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 8093 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 8094 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 8095 /* Hardware capabilities of NIC */ 8096 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12 8097 /* Licensed capabilities */ 8098 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16 8099 /* Second word of flags. Not present on older firmware (check the length). */ 8100 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20 8101 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0 8102 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1 8103 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1 8104 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1 8105 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2 8106 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1 8107 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3 8108 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1 8109 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4 8110 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1 8111 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5 8112 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 8113 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 8114 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 8115 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7 8116 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1 8117 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8 8118 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 8119 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9 8120 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1 8121 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10 8122 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1 8123 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11 8124 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1 8125 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 8126 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 8127 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 8128 * on older firmware (check the length). 8129 */ 8130 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 8131 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 8132 /* One byte per PF containing the number of the external port assigned to this 8133 * PF, indexed by PF number. Special values indicate that a PF is either not 8134 * present or not assigned. 8135 */ 8136 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 8137 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 8138 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 8139 /* enum: The caller is not permitted to access information on this PF. */ 8140 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff 8141 /* enum: PF does not exist. */ 8142 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe 8143 /* enum: PF does exist but is not assigned to any external port. */ 8144 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd 8145 /* enum: This value indicates that PF is assigned, but it cannot be expressed 8146 * in this field. It is intended for a possible future situation where a more 8147 * complex scheme of PFs to ports mapping is being used. The future driver 8148 * should look for a new field supporting the new scheme. The current/old 8149 * driver should treat this value as PF_NOT_ASSIGNED. 8150 */ 8151 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 8152 /* One byte per PF containing the number of its VFs, indexed by PF number. A 8153 * special value indicates that a PF is not present. 8154 */ 8155 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42 8156 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1 8157 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16 8158 /* enum: The caller is not permitted to access information on this PF. */ 8159 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */ 8160 /* enum: PF does not exist. */ 8161 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */ 8162 /* Number of VIs available for each external port */ 8163 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58 8164 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2 8165 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4 8166 /* Size of RX descriptor cache expressed as binary logarithm The actual size 8167 * equals (2 ^ RX_DESC_CACHE_SIZE) 8168 */ 8169 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66 8170 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1 8171 /* Size of TX descriptor cache expressed as binary logarithm The actual size 8172 * equals (2 ^ TX_DESC_CACHE_SIZE) 8173 */ 8174 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67 8175 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1 8176 /* Total number of available PIO buffers */ 8177 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68 8178 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2 8179 /* Size of a single PIO buffer */ 8180 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70 8181 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2 8182 8183 /* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */ 8184 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 73 8185 /* First word of flags. */ 8186 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0 8187 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3 8188 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1 8189 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4 8190 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1 8191 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5 8192 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1 8193 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 8194 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 8195 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7 8196 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 8197 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8 8198 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 8199 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9 8200 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1 8201 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 8202 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 8203 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 8204 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 8205 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 8206 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 8207 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13 8208 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 8209 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14 8210 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1 8211 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 8212 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 8213 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16 8214 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1 8215 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17 8216 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1 8217 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18 8218 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1 8219 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19 8220 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1 8221 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20 8222 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1 8223 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21 8224 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1 8225 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22 8226 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1 8227 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23 8228 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1 8229 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24 8230 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1 8231 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25 8232 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1 8233 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26 8234 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1 8235 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27 8236 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 8237 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28 8238 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1 8239 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 8240 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 8241 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30 8242 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1 8243 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31 8244 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1 8245 /* RxDPCPU firmware id. */ 8246 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4 8247 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2 8248 /* enum: Standard RXDP firmware */ 8249 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0 8250 /* enum: Low latency RXDP firmware */ 8251 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1 8252 /* enum: Packed stream RXDP firmware */ 8253 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2 8254 /* enum: BIST RXDP firmware */ 8255 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a 8256 /* enum: RXDP Test firmware image 1 */ 8257 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 8258 /* enum: RXDP Test firmware image 2 */ 8259 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 8260 /* enum: RXDP Test firmware image 3 */ 8261 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 8262 /* enum: RXDP Test firmware image 4 */ 8263 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 8264 /* enum: RXDP Test firmware image 5 */ 8265 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105 8266 /* enum: RXDP Test firmware image 6 */ 8267 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 8268 /* enum: RXDP Test firmware image 7 */ 8269 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 8270 /* enum: RXDP Test firmware image 8 */ 8271 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 8272 /* enum: RXDP Test firmware image 9 */ 8273 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 8274 /* TxDPCPU firmware id. */ 8275 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6 8276 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2 8277 /* enum: Standard TXDP firmware */ 8278 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0 8279 /* enum: Low latency TXDP firmware */ 8280 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1 8281 /* enum: High packet rate TXDP firmware */ 8282 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3 8283 /* enum: BIST TXDP firmware */ 8284 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d 8285 /* enum: TXDP Test firmware image 1 */ 8286 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 8287 /* enum: TXDP Test firmware image 2 */ 8288 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 8289 /* enum: TXDP CSR bus test firmware */ 8290 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103 8291 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8 8292 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2 8293 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0 8294 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12 8295 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12 8296 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 8297 /* enum: reserved value - do not use (may indicate alternative interpretation 8298 * of REV field in future) 8299 */ 8300 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0 8301 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 8302 * development only) 8303 */ 8304 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 8305 /* enum: RX PD firmware with approximately Siena-compatible behaviour 8306 * (Huntington development only) 8307 */ 8308 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 8309 /* enum: Virtual switching (full feature) RX PD production firmware */ 8310 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3 8311 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 8312 * (Huntington development only) 8313 */ 8314 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 8315 /* enum: Low latency RX PD production firmware */ 8316 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 8317 /* enum: Packed stream RX PD production firmware */ 8318 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 8319 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 8320 * tests (Medford development only) 8321 */ 8322 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 8323 /* enum: Rules engine RX PD production firmware */ 8324 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 8325 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 8326 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 8327 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 8328 * encapsulations (Medford development only) 8329 */ 8330 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 8331 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10 8332 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2 8333 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0 8334 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12 8335 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12 8336 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 8337 /* enum: reserved value - do not use (may indicate alternative interpretation 8338 * of REV field in future) 8339 */ 8340 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0 8341 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 8342 * development only) 8343 */ 8344 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 8345 /* enum: TX PD firmware with approximately Siena-compatible behaviour 8346 * (Huntington development only) 8347 */ 8348 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 8349 /* enum: Virtual switching (full feature) TX PD production firmware */ 8350 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3 8351 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 8352 * (Huntington development only) 8353 */ 8354 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 8355 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 8356 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 8357 * tests (Medford development only) 8358 */ 8359 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 8360 /* enum: Rules engine TX PD production firmware */ 8361 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 8362 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 8363 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 8364 /* Hardware capabilities of NIC */ 8365 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12 8366 /* Licensed capabilities */ 8367 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16 8368 /* Second word of flags. Not present on older firmware (check the length). */ 8369 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20 8370 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0 8371 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1 8372 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1 8373 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1 8374 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2 8375 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1 8376 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3 8377 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1 8378 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4 8379 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1 8380 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5 8381 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 8382 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 8383 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 8384 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7 8385 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1 8386 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8 8387 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 8388 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9 8389 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1 8390 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10 8391 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1 8392 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11 8393 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1 8394 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 8395 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 8396 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 8397 * on older firmware (check the length). 8398 */ 8399 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 8400 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 8401 /* One byte per PF containing the number of the external port assigned to this 8402 * PF, indexed by PF number. Special values indicate that a PF is either not 8403 * present or not assigned. 8404 */ 8405 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 8406 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 8407 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 8408 /* enum: The caller is not permitted to access information on this PF. */ 8409 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff 8410 /* enum: PF does not exist. */ 8411 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe 8412 /* enum: PF does exist but is not assigned to any external port. */ 8413 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd 8414 /* enum: This value indicates that PF is assigned, but it cannot be expressed 8415 * in this field. It is intended for a possible future situation where a more 8416 * complex scheme of PFs to ports mapping is being used. The future driver 8417 * should look for a new field supporting the new scheme. The current/old 8418 * driver should treat this value as PF_NOT_ASSIGNED. 8419 */ 8420 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 8421 /* One byte per PF containing the number of its VFs, indexed by PF number. A 8422 * special value indicates that a PF is not present. 8423 */ 8424 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42 8425 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1 8426 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16 8427 /* enum: The caller is not permitted to access information on this PF. */ 8428 /* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */ 8429 /* enum: PF does not exist. */ 8430 /* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */ 8431 /* Number of VIs available for each external port */ 8432 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58 8433 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2 8434 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4 8435 /* Size of RX descriptor cache expressed as binary logarithm The actual size 8436 * equals (2 ^ RX_DESC_CACHE_SIZE) 8437 */ 8438 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66 8439 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1 8440 /* Size of TX descriptor cache expressed as binary logarithm The actual size 8441 * equals (2 ^ TX_DESC_CACHE_SIZE) 8442 */ 8443 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67 8444 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1 8445 /* Total number of available PIO buffers */ 8446 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68 8447 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2 8448 /* Size of a single PIO buffer */ 8449 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70 8450 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2 8451 /* On chips later than Medford the amount of address space assigned to each VI 8452 * is configurable. This is a global setting that the driver must query to 8453 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 8454 * with 8k VI windows. 8455 */ 8456 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72 8457 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1 8458 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 8459 * CTPIO is not mapped. 8460 */ 8461 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0 8462 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 8463 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1 8464 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 8465 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2 8466 8467 8468 /***********************************/ 8469 /* MC_CMD_V2_EXTN 8470 * Encapsulation for a v2 extended command 8471 */ 8472 #define MC_CMD_V2_EXTN 0x7f 8473 8474 /* MC_CMD_V2_EXTN_IN msgrequest */ 8475 #define MC_CMD_V2_EXTN_IN_LEN 4 8476 /* the extended command number */ 8477 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 8478 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 8479 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 8480 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 8481 /* the actual length of the encapsulated command (which is not in the v1 8482 * header) 8483 */ 8484 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 8485 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 8486 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 8487 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 8488 8489 8490 /***********************************/ 8491 /* MC_CMD_TCM_BUCKET_ALLOC 8492 * Allocate a pacer bucket (for qau rp or a snapper test) 8493 */ 8494 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 8495 8496 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8497 8498 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 8499 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 8500 8501 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 8502 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 8503 /* the bucket id */ 8504 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 8505 8506 8507 /***********************************/ 8508 /* MC_CMD_TCM_BUCKET_FREE 8509 * Free a pacer bucket 8510 */ 8511 #define MC_CMD_TCM_BUCKET_FREE 0xb3 8512 8513 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8514 8515 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 8516 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 8517 /* the bucket id */ 8518 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 8519 8520 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 8521 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 8522 8523 8524 /***********************************/ 8525 /* MC_CMD_TCM_BUCKET_INIT 8526 * Initialise pacer bucket with a given rate 8527 */ 8528 #define MC_CMD_TCM_BUCKET_INIT 0xb4 8529 8530 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8531 8532 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 8533 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 8534 /* the bucket id */ 8535 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 8536 /* the rate in mbps */ 8537 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 8538 8539 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ 8540 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 8541 /* the bucket id */ 8542 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 8543 /* the rate in mbps */ 8544 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 8545 /* the desired maximum fill level */ 8546 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 8547 8548 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 8549 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 8550 8551 8552 /***********************************/ 8553 /* MC_CMD_TCM_TXQ_INIT 8554 * Initialise txq in pacer with given options or set options 8555 */ 8556 #define MC_CMD_TCM_TXQ_INIT 0xb5 8557 8558 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8559 8560 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 8561 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 8562 /* the txq id */ 8563 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 8564 /* the static priority associated with the txq */ 8565 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 8566 /* bitmask of the priority queues this txq is inserted into when inserted. */ 8567 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 8568 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 8569 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 8570 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 8571 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 8572 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 8573 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 8574 /* the reaction point (RP) bucket */ 8575 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 8576 /* an already reserved bucket (typically set to bucket associated with outer 8577 * vswitch) 8578 */ 8579 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 8580 /* an already reserved bucket (typically set to bucket associated with inner 8581 * vswitch) 8582 */ 8583 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 8584 /* the min bucket (typically for ETS/minimum bandwidth) */ 8585 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 8586 8587 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ 8588 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 8589 /* the txq id */ 8590 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 8591 /* the static priority associated with the txq */ 8592 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 8593 /* bitmask of the priority queues this txq is inserted into when inserted. */ 8594 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 8595 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 8596 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 8597 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 8598 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 8599 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 8600 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 8601 /* the reaction point (RP) bucket */ 8602 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 8603 /* an already reserved bucket (typically set to bucket associated with outer 8604 * vswitch) 8605 */ 8606 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 8607 /* an already reserved bucket (typically set to bucket associated with inner 8608 * vswitch) 8609 */ 8610 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 8611 /* the min bucket (typically for ETS/minimum bandwidth) */ 8612 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 8613 /* the static priority associated with the txq */ 8614 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 8615 8616 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 8617 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 8618 8619 8620 /***********************************/ 8621 /* MC_CMD_LINK_PIOBUF 8622 * Link a push I/O buffer to a TxQ 8623 */ 8624 #define MC_CMD_LINK_PIOBUF 0x92 8625 8626 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8627 8628 /* MC_CMD_LINK_PIOBUF_IN msgrequest */ 8629 #define MC_CMD_LINK_PIOBUF_IN_LEN 8 8630 /* Handle for allocated push I/O buffer. */ 8631 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 8632 /* Function Local Instance (VI) number. */ 8633 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 8634 8635 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ 8636 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 8637 8638 8639 /***********************************/ 8640 /* MC_CMD_UNLINK_PIOBUF 8641 * Unlink a push I/O buffer from a TxQ 8642 */ 8643 #define MC_CMD_UNLINK_PIOBUF 0x93 8644 8645 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8646 8647 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ 8648 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 8649 /* Function Local Instance (VI) number. */ 8650 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 8651 8652 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ 8653 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 8654 8655 8656 /***********************************/ 8657 /* MC_CMD_VSWITCH_ALLOC 8658 * allocate and initialise a v-switch. 8659 */ 8660 #define MC_CMD_VSWITCH_ALLOC 0x94 8661 8662 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8663 8664 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ 8665 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 8666 /* The port to connect to the v-switch's upstream port. */ 8667 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 8668 /* The type of v-switch to create. */ 8669 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 8670 /* enum: VLAN */ 8671 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 8672 /* enum: VEB */ 8673 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 8674 /* enum: VEPA (obsolete) */ 8675 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 8676 /* enum: MUX */ 8677 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4 8678 /* enum: Snapper specific; semantics TBD */ 8679 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5 8680 /* Flags controlling v-port creation */ 8681 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 8682 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 8683 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 8684 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators, 8685 * this must be one or greated, and the attached v-ports must have exactly this 8686 * number of tags. For other v-switch types, this must be zero of greater, and 8687 * is an upper limit on the number of VLAN tags for attached v-ports. An error 8688 * will be returned if existing configuration means we can't support attached 8689 * v-ports with this number of tags. 8690 */ 8691 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 8692 8693 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ 8694 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 8695 8696 8697 /***********************************/ 8698 /* MC_CMD_VSWITCH_FREE 8699 * de-allocate a v-switch. 8700 */ 8701 #define MC_CMD_VSWITCH_FREE 0x95 8702 8703 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8704 8705 /* MC_CMD_VSWITCH_FREE_IN msgrequest */ 8706 #define MC_CMD_VSWITCH_FREE_IN_LEN 4 8707 /* The port to which the v-switch is connected. */ 8708 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 8709 8710 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 8711 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 8712 8713 8714 /***********************************/ 8715 /* MC_CMD_VSWITCH_QUERY 8716 * read some config of v-switch. For now this command is an empty placeholder. 8717 * It may be used to check if a v-switch is connected to a given EVB port (if 8718 * not, then the command returns ENOENT). 8719 */ 8720 #define MC_CMD_VSWITCH_QUERY 0x63 8721 8722 #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8723 8724 /* MC_CMD_VSWITCH_QUERY_IN msgrequest */ 8725 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4 8726 /* The port to which the v-switch is connected. */ 8727 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 8728 8729 /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */ 8730 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0 8731 8732 8733 /***********************************/ 8734 /* MC_CMD_VPORT_ALLOC 8735 * allocate a v-port. 8736 */ 8737 #define MC_CMD_VPORT_ALLOC 0x96 8738 8739 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8740 8741 /* MC_CMD_VPORT_ALLOC_IN msgrequest */ 8742 #define MC_CMD_VPORT_ALLOC_IN_LEN 20 8743 /* The port to which the v-switch is connected. */ 8744 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 8745 /* The type of the new v-port. */ 8746 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 8747 /* enum: VLAN (obsolete) */ 8748 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 8749 /* enum: VEB (obsolete) */ 8750 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 8751 /* enum: VEPA (obsolete) */ 8752 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 8753 /* enum: A normal v-port receives packets which match a specified MAC and/or 8754 * VLAN. 8755 */ 8756 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 8757 /* enum: An expansion v-port packets traffic which don't match any other 8758 * v-port. 8759 */ 8760 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 8761 /* enum: An test v-port receives packets which match any filters installed by 8762 * its downstream components. 8763 */ 8764 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 8765 /* Flags controlling v-port creation */ 8766 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 8767 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 8768 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 8769 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1 8770 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1 8771 /* The number of VLAN tags to insert/remove. An error will be returned if 8772 * incompatible with the number of VLAN tags specified for the upstream 8773 * v-switch. 8774 */ 8775 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 8776 /* The actual VLAN tags to insert/remove */ 8777 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 8778 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 8779 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 8780 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 8781 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 8782 8783 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ 8784 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 8785 /* The handle of the new v-port */ 8786 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 8787 8788 8789 /***********************************/ 8790 /* MC_CMD_VPORT_FREE 8791 * de-allocate a v-port. 8792 */ 8793 #define MC_CMD_VPORT_FREE 0x97 8794 8795 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8796 8797 /* MC_CMD_VPORT_FREE_IN msgrequest */ 8798 #define MC_CMD_VPORT_FREE_IN_LEN 4 8799 /* The handle of the v-port */ 8800 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 8801 8802 /* MC_CMD_VPORT_FREE_OUT msgresponse */ 8803 #define MC_CMD_VPORT_FREE_OUT_LEN 0 8804 8805 8806 /***********************************/ 8807 /* MC_CMD_VADAPTOR_ALLOC 8808 * allocate a v-adaptor. 8809 */ 8810 #define MC_CMD_VADAPTOR_ALLOC 0x98 8811 8812 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8813 8814 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ 8815 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 8816 /* The port to connect to the v-adaptor's port. */ 8817 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 8818 /* Flags controlling v-adaptor creation */ 8819 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 8820 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 8821 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 8822 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1 8823 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 8824 /* The number of VLAN tags to strip on receive */ 8825 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 8826 /* The number of VLAN tags to transparently insert/remove. */ 8827 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 8828 /* The actual VLAN tags to insert/remove */ 8829 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 8830 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 8831 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 8832 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 8833 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 8834 /* The MAC address to assign to this v-adaptor */ 8835 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 8836 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 8837 /* enum: Derive the MAC address from the upstream port */ 8838 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 8839 8840 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ 8841 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 8842 8843 8844 /***********************************/ 8845 /* MC_CMD_VADAPTOR_FREE 8846 * de-allocate a v-adaptor. 8847 */ 8848 #define MC_CMD_VADAPTOR_FREE 0x99 8849 8850 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8851 8852 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ 8853 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 8854 /* The port to which the v-adaptor is connected. */ 8855 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 8856 8857 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ 8858 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 8859 8860 8861 /***********************************/ 8862 /* MC_CMD_VADAPTOR_SET_MAC 8863 * assign a new MAC address to a v-adaptor. 8864 */ 8865 #define MC_CMD_VADAPTOR_SET_MAC 0x5d 8866 8867 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8868 8869 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ 8870 #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 8871 /* The port to which the v-adaptor is connected. */ 8872 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 8873 /* The new MAC address to assign to this v-adaptor */ 8874 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 8875 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 8876 8877 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ 8878 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 8879 8880 8881 /***********************************/ 8882 /* MC_CMD_VADAPTOR_GET_MAC 8883 * read the MAC address assigned to a v-adaptor. 8884 */ 8885 #define MC_CMD_VADAPTOR_GET_MAC 0x5e 8886 8887 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8888 8889 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ 8890 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 8891 /* The port to which the v-adaptor is connected. */ 8892 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 8893 8894 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ 8895 #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 8896 /* The MAC address assigned to this v-adaptor */ 8897 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 8898 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 8899 8900 8901 /***********************************/ 8902 /* MC_CMD_VADAPTOR_QUERY 8903 * read some config of v-adaptor. 8904 */ 8905 #define MC_CMD_VADAPTOR_QUERY 0x61 8906 8907 #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8908 8909 /* MC_CMD_VADAPTOR_QUERY_IN msgrequest */ 8910 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4 8911 /* The port to which the v-adaptor is connected. */ 8912 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 8913 8914 /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */ 8915 #define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12 8916 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 8917 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0 8918 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */ 8919 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4 8920 /* The number of VLAN tags that may still be added */ 8921 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8 8922 8923 8924 /***********************************/ 8925 /* MC_CMD_EVB_PORT_ASSIGN 8926 * assign a port to a PCI function. 8927 */ 8928 #define MC_CMD_EVB_PORT_ASSIGN 0x9a 8929 8930 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8931 8932 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ 8933 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 8934 /* The port to assign. */ 8935 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 8936 /* The target function to modify. */ 8937 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 8938 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 8939 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 8940 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 8941 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 8942 8943 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 8944 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 8945 8946 8947 /***********************************/ 8948 /* MC_CMD_RDWR_A64_REGIONS 8949 * Assign the 64 bit region addresses. 8950 */ 8951 #define MC_CMD_RDWR_A64_REGIONS 0x9b 8952 8953 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8954 8955 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 8956 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 8957 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 8958 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 8959 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 8960 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 8961 /* Write enable bits 0-3, set to write, clear to read. */ 8962 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 8963 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 8964 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 8965 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 8966 8967 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 8968 * regardless of state of write bits in the request. 8969 */ 8970 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 8971 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 8972 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 8973 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 8974 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 8975 8976 8977 /***********************************/ 8978 /* MC_CMD_ONLOAD_STACK_ALLOC 8979 * Allocate an Onload stack ID. 8980 */ 8981 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 8982 8983 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8984 8985 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 8986 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 8987 /* The handle of the owning upstream port */ 8988 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 8989 8990 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 8991 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 8992 /* The handle of the new Onload stack */ 8993 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 8994 8995 8996 /***********************************/ 8997 /* MC_CMD_ONLOAD_STACK_FREE 8998 * Free an Onload stack ID. 8999 */ 9000 #define MC_CMD_ONLOAD_STACK_FREE 0x9d 9001 9002 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9003 9004 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 9005 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 9006 /* The handle of the Onload stack */ 9007 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 9008 9009 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 9010 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 9011 9012 9013 /***********************************/ 9014 /* MC_CMD_RSS_CONTEXT_ALLOC 9015 * Allocate an RSS context. 9016 */ 9017 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e 9018 9019 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9020 9021 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ 9022 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 9023 /* The handle of the owning upstream port */ 9024 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 9025 /* The type of context to allocate */ 9026 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 9027 /* enum: Allocate a context for exclusive use. The key and indirection table 9028 * must be explicitly configured. 9029 */ 9030 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 9031 /* enum: Allocate a context for shared use; this will spread across a range of 9032 * queues, but the key and indirection table are pre-configured and may not be 9033 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 9034 */ 9035 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 9036 /* Number of queues spanned by this context, in the range 1-64; valid offsets 9037 * in the indirection table will be in the range 0 to NUM_QUEUES-1. 9038 */ 9039 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 9040 9041 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ 9042 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 9043 /* The handle of the new RSS context. This should be considered opaque to the 9044 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 9045 * handle. 9046 */ 9047 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 9048 /* enum: guaranteed invalid RSS context handle value */ 9049 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff 9050 9051 9052 /***********************************/ 9053 /* MC_CMD_RSS_CONTEXT_FREE 9054 * Free an RSS context. 9055 */ 9056 #define MC_CMD_RSS_CONTEXT_FREE 0x9f 9057 9058 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9059 9060 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ 9061 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 9062 /* The handle of the RSS context */ 9063 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 9064 9065 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ 9066 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 9067 9068 9069 /***********************************/ 9070 /* MC_CMD_RSS_CONTEXT_SET_KEY 9071 * Set the Toeplitz hash key for an RSS context. 9072 */ 9073 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 9074 9075 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9076 9077 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ 9078 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 9079 /* The handle of the RSS context */ 9080 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 9081 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 9082 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 9083 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 9084 9085 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ 9086 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 9087 9088 9089 /***********************************/ 9090 /* MC_CMD_RSS_CONTEXT_GET_KEY 9091 * Get the Toeplitz hash key for an RSS context. 9092 */ 9093 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 9094 9095 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9096 9097 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ 9098 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 9099 /* The handle of the RSS context */ 9100 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 9101 9102 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ 9103 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 9104 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 9105 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 9106 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 9107 9108 9109 /***********************************/ 9110 /* MC_CMD_RSS_CONTEXT_SET_TABLE 9111 * Set the indirection table for an RSS context. 9112 */ 9113 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 9114 9115 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9116 9117 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ 9118 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 9119 /* The handle of the RSS context */ 9120 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 9121 /* The 128-byte indirection table (1 byte per entry) */ 9122 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 9123 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 9124 9125 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ 9126 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 9127 9128 9129 /***********************************/ 9130 /* MC_CMD_RSS_CONTEXT_GET_TABLE 9131 * Get the indirection table for an RSS context. 9132 */ 9133 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 9134 9135 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9136 9137 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ 9138 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 9139 /* The handle of the RSS context */ 9140 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 9141 9142 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ 9143 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 9144 /* The 128-byte indirection table (1 byte per entry) */ 9145 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 9146 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 9147 9148 9149 /***********************************/ 9150 /* MC_CMD_RSS_CONTEXT_SET_FLAGS 9151 * Set various control flags for an RSS context. 9152 */ 9153 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 9154 9155 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9156 9157 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ 9158 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 9159 /* The handle of the RSS context */ 9160 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 9161 /* Hash control flags. The _EN bits are always supported, but new modes are 9162 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES: 9163 * in this case, the MODE fields may be set to non-zero values, and will take 9164 * effect regardless of the settings of the _EN flags. See the RSS_MODE 9165 * structure for the meaning of the mode bits. Drivers must check the 9166 * capability before trying to set any _MODE fields, as older firmware will 9167 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In 9168 * the case where all the _MODE flags are zero, the _EN flags take effect, 9169 * providing backward compatibility for existing drivers. (Setting all _MODE 9170 * *and* all _EN flags to zero is valid, to disable RSS spreading for that 9171 * particular packet type.) 9172 */ 9173 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 9174 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 9175 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 9176 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 9177 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 9178 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 9179 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 9180 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 9181 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 9182 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4 9183 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4 9184 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8 9185 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4 9186 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12 9187 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4 9188 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16 9189 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4 9190 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20 9191 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4 9192 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24 9193 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4 9194 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28 9195 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4 9196 9197 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ 9198 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 9199 9200 9201 /***********************************/ 9202 /* MC_CMD_RSS_CONTEXT_GET_FLAGS 9203 * Get various control flags for an RSS context. 9204 */ 9205 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 9206 9207 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9208 9209 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ 9210 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 9211 /* The handle of the RSS context */ 9212 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 9213 9214 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ 9215 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 9216 /* Hash control flags. If all _MODE bits are zero (which will always be true 9217 * for older firmware which does not report the ADDITIONAL_RSS_MODES 9218 * capability), the _EN bits report the state. If any _MODE bits are non-zero 9219 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES) 9220 * then the _EN bits should be disregarded, although the _MODE flags are 9221 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS 9222 * context and in the case where the _EN flags were used in the SET. This 9223 * provides backward compatibility: old drivers will not be attempting to 9224 * derive any meaning from the _MODE bits (and can never set them to any value 9225 * not representable by the _EN bits); new drivers can always determine the 9226 * mode by looking only at the _MODE bits; the value returned by a GET can 9227 * always be used for a SET regardless of old/new driver vs. old/new firmware. 9228 */ 9229 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 9230 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 9231 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 9232 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 9233 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 9234 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 9235 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 9236 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 9237 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 9238 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4 9239 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4 9240 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8 9241 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4 9242 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12 9243 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4 9244 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16 9245 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4 9246 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20 9247 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4 9248 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24 9249 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4 9250 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 9251 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 9252 9253 9254 /***********************************/ 9255 /* MC_CMD_DOT1P_MAPPING_ALLOC 9256 * Allocate a .1p mapping. 9257 */ 9258 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 9259 9260 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9261 9262 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 9263 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 9264 /* The handle of the owning upstream port */ 9265 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 9266 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed 9267 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 9268 * referenced RSS contexts must span no more than this number. 9269 */ 9270 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 9271 9272 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 9273 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 9274 /* The handle of the new .1p mapping. This should be considered opaque to the 9275 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 9276 * handle. 9277 */ 9278 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 9279 /* enum: guaranteed invalid .1p mapping handle value */ 9280 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff 9281 9282 9283 /***********************************/ 9284 /* MC_CMD_DOT1P_MAPPING_FREE 9285 * Free a .1p mapping. 9286 */ 9287 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 9288 9289 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9290 9291 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 9292 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 9293 /* The handle of the .1p mapping */ 9294 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 9295 9296 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 9297 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 9298 9299 9300 /***********************************/ 9301 /* MC_CMD_DOT1P_MAPPING_SET_TABLE 9302 * Set the mapping table for a .1p mapping. 9303 */ 9304 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 9305 9306 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9307 9308 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 9309 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 9310 /* The handle of the .1p mapping */ 9311 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 9312 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 9313 * handle) 9314 */ 9315 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 9316 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 9317 9318 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 9319 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 9320 9321 9322 /***********************************/ 9323 /* MC_CMD_DOT1P_MAPPING_GET_TABLE 9324 * Get the mapping table for a .1p mapping. 9325 */ 9326 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 9327 9328 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9329 9330 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 9331 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 9332 /* The handle of the .1p mapping */ 9333 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 9334 9335 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 9336 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 9337 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 9338 * handle) 9339 */ 9340 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 9341 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 9342 9343 9344 /***********************************/ 9345 /* MC_CMD_GET_VECTOR_CFG 9346 * Get Interrupt Vector config for this PF. 9347 */ 9348 #define MC_CMD_GET_VECTOR_CFG 0xbf 9349 9350 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9351 9352 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 9353 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 9354 9355 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 9356 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 9357 /* Base absolute interrupt vector number. */ 9358 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 9359 /* Number of interrupt vectors allocate to this PF. */ 9360 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 9361 /* Number of interrupt vectors to allocate per VF. */ 9362 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 9363 9364 9365 /***********************************/ 9366 /* MC_CMD_SET_VECTOR_CFG 9367 * Set Interrupt Vector config for this PF. 9368 */ 9369 #define MC_CMD_SET_VECTOR_CFG 0xc0 9370 9371 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9372 9373 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 9374 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 9375 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 9376 * let the system find a suitable base. 9377 */ 9378 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 9379 /* Number of interrupt vectors allocate to this PF. */ 9380 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 9381 /* Number of interrupt vectors to allocate per VF. */ 9382 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 9383 9384 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 9385 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 9386 9387 9388 /***********************************/ 9389 /* MC_CMD_VPORT_ADD_MAC_ADDRESS 9390 * Add a MAC address to a v-port 9391 */ 9392 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 9393 9394 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9395 9396 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ 9397 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 9398 /* The handle of the v-port */ 9399 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 9400 /* MAC address to add */ 9401 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 9402 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 9403 9404 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ 9405 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 9406 9407 9408 /***********************************/ 9409 /* MC_CMD_VPORT_DEL_MAC_ADDRESS 9410 * Delete a MAC address from a v-port 9411 */ 9412 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 9413 9414 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9415 9416 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ 9417 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 9418 /* The handle of the v-port */ 9419 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 9420 /* MAC address to add */ 9421 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 9422 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 9423 9424 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ 9425 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 9426 9427 9428 /***********************************/ 9429 /* MC_CMD_VPORT_GET_MAC_ADDRESSES 9430 * Delete a MAC address from a v-port 9431 */ 9432 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa 9433 9434 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9435 9436 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ 9437 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 9438 /* The handle of the v-port */ 9439 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 9440 9441 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ 9442 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 9443 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 9444 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) 9445 /* The number of MAC addresses returned */ 9446 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 9447 /* Array of MAC addresses */ 9448 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 9449 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 9450 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 9451 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 9452 9453 9454 /***********************************/ 9455 /* MC_CMD_VPORT_RECONFIGURE 9456 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port 9457 * has already been passed to another function (v-port's user), then that 9458 * function will be reset before applying the changes. 9459 */ 9460 #define MC_CMD_VPORT_RECONFIGURE 0xeb 9461 9462 #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9463 9464 /* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */ 9465 #define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44 9466 /* The handle of the v-port */ 9467 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0 9468 /* Flags requesting what should be changed. */ 9469 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4 9470 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0 9471 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1 9472 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1 9473 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1 9474 /* The number of VLAN tags to insert/remove. An error will be returned if 9475 * incompatible with the number of VLAN tags specified for the upstream 9476 * v-switch. 9477 */ 9478 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8 9479 /* The actual VLAN tags to insert/remove */ 9480 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12 9481 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0 9482 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16 9483 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16 9484 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16 9485 /* The number of MAC addresses to add */ 9486 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16 9487 /* MAC addresses to add */ 9488 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20 9489 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6 9490 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4 9491 9492 /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */ 9493 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4 9494 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0 9495 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0 9496 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1 9497 9498 9499 /***********************************/ 9500 /* MC_CMD_EVB_PORT_QUERY 9501 * read some config of v-port. 9502 */ 9503 #define MC_CMD_EVB_PORT_QUERY 0x62 9504 9505 #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9506 9507 /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */ 9508 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4 9509 /* The handle of the v-port */ 9510 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0 9511 9512 /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */ 9513 #define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8 9514 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 9515 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0 9516 /* The number of VLAN tags that may be used on a v-adaptor connected to this 9517 * EVB port. 9518 */ 9519 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4 9520 9521 9522 /***********************************/ 9523 /* MC_CMD_DUMP_BUFTBL_ENTRIES 9524 * Dump buffer table entries, mainly for command client debug use. Dumps 9525 * absolute entries, and does not use chunk handles. All entries must be in 9526 * range, and used for q page mapping, Although the latter restriction may be 9527 * lifted in future. 9528 */ 9529 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 9530 9531 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9532 9533 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 9534 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 9535 /* Index of the first buffer table entry. */ 9536 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 9537 /* Number of buffer table entries to dump. */ 9538 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 9539 9540 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 9541 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 9542 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 9543 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 9544 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ 9545 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 9546 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 9547 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 9548 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 9549 9550 9551 /***********************************/ 9552 /* MC_CMD_SET_RXDP_CONFIG 9553 * Set global RXDP configuration settings 9554 */ 9555 #define MC_CMD_SET_RXDP_CONFIG 0xc1 9556 9557 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9558 9559 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 9560 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 9561 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 9562 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 9563 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 9564 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1 9565 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2 9566 /* enum: pad to 64 bytes */ 9567 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0 9568 /* enum: pad to 128 bytes (Medford only) */ 9569 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1 9570 /* enum: pad to 256 bytes (Medford only) */ 9571 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2 9572 9573 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 9574 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 9575 9576 9577 /***********************************/ 9578 /* MC_CMD_GET_RXDP_CONFIG 9579 * Get global RXDP configuration settings 9580 */ 9581 #define MC_CMD_GET_RXDP_CONFIG 0xc2 9582 9583 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9584 9585 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 9586 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 9587 9588 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 9589 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 9590 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 9591 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 9592 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 9593 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1 9594 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2 9595 /* Enum values, see field(s): */ 9596 /* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */ 9597 9598 9599 /***********************************/ 9600 /* MC_CMD_GET_CLOCK 9601 * Return the system and PDCPU clock frequencies. 9602 */ 9603 #define MC_CMD_GET_CLOCK 0xac 9604 9605 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9606 9607 /* MC_CMD_GET_CLOCK_IN msgrequest */ 9608 #define MC_CMD_GET_CLOCK_IN_LEN 0 9609 9610 /* MC_CMD_GET_CLOCK_OUT msgresponse */ 9611 #define MC_CMD_GET_CLOCK_OUT_LEN 8 9612 /* System frequency, MHz */ 9613 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 9614 /* DPCPU frequency, MHz */ 9615 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 9616 9617 9618 /***********************************/ 9619 /* MC_CMD_SET_CLOCK 9620 * Control the system and DPCPU clock frequencies. Changes are lost reboot. 9621 */ 9622 #define MC_CMD_SET_CLOCK 0xad 9623 9624 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9625 9626 /* MC_CMD_SET_CLOCK_IN msgrequest */ 9627 #define MC_CMD_SET_CLOCK_IN_LEN 28 9628 /* Requested frequency in MHz for system clock domain */ 9629 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 9630 /* enum: Leave the system clock domain frequency unchanged */ 9631 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 9632 /* Requested frequency in MHz for inter-core clock domain */ 9633 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 9634 /* enum: Leave the inter-core clock domain frequency unchanged */ 9635 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 9636 /* Requested frequency in MHz for DPCPU clock domain */ 9637 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 9638 /* enum: Leave the DPCPU clock domain frequency unchanged */ 9639 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 9640 /* Requested frequency in MHz for PCS clock domain */ 9641 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 9642 /* enum: Leave the PCS clock domain frequency unchanged */ 9643 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 9644 /* Requested frequency in MHz for MC clock domain */ 9645 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 9646 /* enum: Leave the MC clock domain frequency unchanged */ 9647 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 9648 /* Requested frequency in MHz for rmon clock domain */ 9649 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 9650 /* enum: Leave the rmon clock domain frequency unchanged */ 9651 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 9652 /* Requested frequency in MHz for vswitch clock domain */ 9653 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 9654 /* enum: Leave the vswitch clock domain frequency unchanged */ 9655 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 9656 9657 /* MC_CMD_SET_CLOCK_OUT msgresponse */ 9658 #define MC_CMD_SET_CLOCK_OUT_LEN 28 9659 /* Resulting system frequency in MHz */ 9660 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 9661 /* enum: The system clock domain doesn't exist */ 9662 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 9663 /* Resulting inter-core frequency in MHz */ 9664 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 9665 /* enum: The inter-core clock domain doesn't exist / isn't used */ 9666 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 9667 /* Resulting DPCPU frequency in MHz */ 9668 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 9669 /* enum: The dpcpu clock domain doesn't exist */ 9670 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 9671 /* Resulting PCS frequency in MHz */ 9672 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 9673 /* enum: The PCS clock domain doesn't exist / isn't controlled */ 9674 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 9675 /* Resulting MC frequency in MHz */ 9676 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 9677 /* enum: The MC clock domain doesn't exist / isn't controlled */ 9678 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 9679 /* Resulting rmon frequency in MHz */ 9680 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 9681 /* enum: The rmon clock domain doesn't exist / isn't controlled */ 9682 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 9683 /* Resulting vswitch frequency in MHz */ 9684 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 9685 /* enum: The vswitch clock domain doesn't exist / isn't controlled */ 9686 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 9687 9688 9689 /***********************************/ 9690 /* MC_CMD_DPCPU_RPC 9691 * Send an arbitrary DPCPU message. 9692 */ 9693 #define MC_CMD_DPCPU_RPC 0xae 9694 9695 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9696 9697 /* MC_CMD_DPCPU_RPC_IN msgrequest */ 9698 #define MC_CMD_DPCPU_RPC_IN_LEN 36 9699 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 9700 /* enum: RxDPCPU0 */ 9701 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 9702 /* enum: TxDPCPU0 */ 9703 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 9704 /* enum: TxDPCPU1 */ 9705 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 9706 /* enum: RxDPCPU1 (Medford only) */ 9707 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 9708 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of 9709 * DPCPU_RX0) 9710 */ 9711 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 9712 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of 9713 * DPCPU_TX0) 9714 */ 9715 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 9716 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 9717 * initialised to zero 9718 */ 9719 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 9720 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 9721 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 9722 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 9723 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 9724 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 9725 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 9726 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 9727 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 9728 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 9729 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 9730 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 9731 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 9732 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 9733 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 9734 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 9735 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 9736 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 9737 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 9738 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 9739 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 9740 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 9741 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 9742 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 9743 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 9744 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 9745 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 9746 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 9747 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 9748 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 9749 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 9750 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 9751 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 9752 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 9753 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 9754 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 9755 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 9756 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 9757 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 9758 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 9759 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 9760 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 9761 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 9762 /* Register data to write. Only valid in write/write-read. */ 9763 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 9764 /* Register address. */ 9765 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 9766 9767 /* MC_CMD_DPCPU_RPC_OUT msgresponse */ 9768 #define MC_CMD_DPCPU_RPC_OUT_LEN 36 9769 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 9770 /* DATA */ 9771 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 9772 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 9773 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 9774 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 9775 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 9776 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 9777 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 9778 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 9779 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 9780 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 9781 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 9782 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 9783 9784 9785 /***********************************/ 9786 /* MC_CMD_TRIGGER_INTERRUPT 9787 * Trigger an interrupt by prodding the BIU. 9788 */ 9789 #define MC_CMD_TRIGGER_INTERRUPT 0xe3 9790 9791 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9792 9793 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ 9794 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 9795 /* Interrupt level relative to base for function. */ 9796 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 9797 9798 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 9799 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 9800 9801 9802 /***********************************/ 9803 /* MC_CMD_SHMBOOT_OP 9804 * Special operations to support (for now) shmboot. 9805 */ 9806 #define MC_CMD_SHMBOOT_OP 0xe6 9807 9808 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9809 9810 /* MC_CMD_SHMBOOT_OP_IN msgrequest */ 9811 #define MC_CMD_SHMBOOT_OP_IN_LEN 4 9812 /* Identifies the operation to perform */ 9813 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 9814 /* enum: Copy slave_data section to the slave core. (Greenport only) */ 9815 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 9816 9817 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */ 9818 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0 9819 9820 9821 /***********************************/ 9822 /* MC_CMD_CAP_BLK_READ 9823 * Read multiple 64bit words from capture block memory 9824 */ 9825 #define MC_CMD_CAP_BLK_READ 0xe7 9826 9827 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9828 9829 /* MC_CMD_CAP_BLK_READ_IN msgrequest */ 9830 #define MC_CMD_CAP_BLK_READ_IN_LEN 12 9831 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 9832 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 9833 #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 9834 9835 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */ 9836 #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 9837 #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 9838 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) 9839 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 9840 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 9841 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 9842 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 9843 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 9844 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 9845 9846 9847 /***********************************/ 9848 /* MC_CMD_DUMP_DO 9849 * Take a dump of the DUT state 9850 */ 9851 #define MC_CMD_DUMP_DO 0xe8 9852 9853 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9854 9855 /* MC_CMD_DUMP_DO_IN msgrequest */ 9856 #define MC_CMD_DUMP_DO_IN_LEN 52 9857 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 9858 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 9859 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ 9860 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ 9861 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 9862 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ 9863 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ 9864 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ 9865 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ 9866 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 9867 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 9868 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 9869 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 9870 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 9871 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ 9872 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 9873 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 9874 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ 9875 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 9876 /* enum: The uart port this command was received over (if using a uart 9877 * transport) 9878 */ 9879 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff 9880 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 9881 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 9882 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ 9883 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ 9884 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 9885 /* Enum values, see field(s): */ 9886 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 9887 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 9888 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 9889 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 9890 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 9891 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 9892 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 9893 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 9894 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 9895 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 9896 9897 /* MC_CMD_DUMP_DO_OUT msgresponse */ 9898 #define MC_CMD_DUMP_DO_OUT_LEN 4 9899 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 9900 9901 9902 /***********************************/ 9903 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED 9904 * Configure unsolicited dumps 9905 */ 9906 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 9907 9908 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9909 9910 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ 9911 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 9912 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 9913 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 9914 /* Enum values, see field(s): */ 9915 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ 9916 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 9917 /* Enum values, see field(s): */ 9918 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 9919 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 9920 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 9921 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 9922 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 9923 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 9924 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 9925 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 9926 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 9927 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 9928 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 9929 /* Enum values, see field(s): */ 9930 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ 9931 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 9932 /* Enum values, see field(s): */ 9933 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 9934 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 9935 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 9936 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 9937 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 9938 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 9939 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 9940 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 9941 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 9942 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 9943 9944 9945 /***********************************/ 9946 /* MC_CMD_SET_PSU 9947 * Adjusts power supply parameters. This is a warranty-voiding operation. 9948 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 9949 * the parameter is out of range. 9950 */ 9951 #define MC_CMD_SET_PSU 0xea 9952 9953 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9954 9955 /* MC_CMD_SET_PSU_IN msgrequest */ 9956 #define MC_CMD_SET_PSU_IN_LEN 12 9957 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 9958 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 9959 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 9960 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 9961 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 9962 /* desired value, eg voltage in mV */ 9963 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 9964 9965 /* MC_CMD_SET_PSU_OUT msgresponse */ 9966 #define MC_CMD_SET_PSU_OUT_LEN 0 9967 9968 9969 /***********************************/ 9970 /* MC_CMD_GET_FUNCTION_INFO 9971 * Get function information. PF and VF number. 9972 */ 9973 #define MC_CMD_GET_FUNCTION_INFO 0xec 9974 9975 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9976 9977 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ 9978 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 9979 9980 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ 9981 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 9982 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 9983 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 9984 9985 9986 /***********************************/ 9987 /* MC_CMD_ENABLE_OFFLINE_BIST 9988 * Enters offline BIST mode. All queues are torn down, chip enters quiescent 9989 * mode, calling function gets exclusive MCDI ownership. The only way out is 9990 * reboot. 9991 */ 9992 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed 9993 9994 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9995 9996 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 9997 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 9998 9999 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ 10000 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 10001 10002 10003 /***********************************/ 10004 /* MC_CMD_UART_SEND_DATA 10005 * Send checksummed[sic] block of data over the uart. Response is a placeholder 10006 * should we wish to make this reliable; currently requests are fire-and- 10007 * forget. 10008 */ 10009 #define MC_CMD_UART_SEND_DATA 0xee 10010 10011 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10012 10013 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */ 10014 #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 10015 #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 10016 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) 10017 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ 10018 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 10019 /* Offset at which to write the data */ 10020 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 10021 /* Length of data */ 10022 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 10023 /* Reserved for future use */ 10024 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 10025 #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 10026 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 10027 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 10028 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 10029 10030 /* MC_CMD_UART_SEND_DATA_IN msgresponse */ 10031 #define MC_CMD_UART_SEND_DATA_IN_LEN 0 10032 10033 10034 /***********************************/ 10035 /* MC_CMD_UART_RECV_DATA 10036 * Request checksummed[sic] block of data over the uart. Only a placeholder, 10037 * subject to change and not currently implemented. 10038 */ 10039 #define MC_CMD_UART_RECV_DATA 0xef 10040 10041 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10042 10043 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */ 10044 #define MC_CMD_UART_RECV_DATA_OUT_LEN 16 10045 /* CRC32 over OFFSET, LENGTH, RESERVED */ 10046 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 10047 /* Offset from which to read the data */ 10048 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 10049 /* Length of data */ 10050 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 10051 /* Reserved for future use */ 10052 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 10053 10054 /* MC_CMD_UART_RECV_DATA_IN msgresponse */ 10055 #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 10056 #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 10057 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) 10058 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ 10059 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 10060 /* Offset at which to write the data */ 10061 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 10062 /* Length of data */ 10063 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 10064 /* Reserved for future use */ 10065 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 10066 #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 10067 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 10068 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 10069 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 10070 10071 10072 /***********************************/ 10073 /* MC_CMD_READ_FUSES 10074 * Read data programmed into the device One-Time-Programmable (OTP) Fuses 10075 */ 10076 #define MC_CMD_READ_FUSES 0xf0 10077 10078 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10079 10080 /* MC_CMD_READ_FUSES_IN msgrequest */ 10081 #define MC_CMD_READ_FUSES_IN_LEN 8 10082 /* Offset in OTP to read */ 10083 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 10084 /* Length of data to read in bytes */ 10085 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 10086 10087 /* MC_CMD_READ_FUSES_OUT msgresponse */ 10088 #define MC_CMD_READ_FUSES_OUT_LENMIN 4 10089 #define MC_CMD_READ_FUSES_OUT_LENMAX 252 10090 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 10091 /* Length of returned OTP data in bytes */ 10092 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 10093 /* Returned data */ 10094 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 10095 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 10096 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 10097 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 10098 10099 10100 /***********************************/ 10101 /* MC_CMD_KR_TUNE 10102 * Get or set KR Serdes RXEQ and TX Driver settings 10103 */ 10104 #define MC_CMD_KR_TUNE 0xf1 10105 10106 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10107 10108 /* MC_CMD_KR_TUNE_IN msgrequest */ 10109 #define MC_CMD_KR_TUNE_IN_LENMIN 4 10110 #define MC_CMD_KR_TUNE_IN_LENMAX 252 10111 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) 10112 /* Requested operation */ 10113 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 10114 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 10115 /* enum: Get current RXEQ settings */ 10116 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 10117 /* enum: Override RXEQ settings */ 10118 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 10119 /* enum: Get current TX Driver settings */ 10120 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 10121 /* enum: Override TX Driver settings */ 10122 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 10123 /* enum: Force KR Serdes reset / recalibration */ 10124 #define MC_CMD_KR_TUNE_IN_RECAL 0x4 10125 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid 10126 * signal. 10127 */ 10128 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 10129 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The 10130 * caller should call this command repeatedly after starting eye plot, until no 10131 * more data is returned. 10132 */ 10133 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 10134 /* enum: Read Figure Of Merit (eye quality, higher is better). */ 10135 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7 10136 /* Align the arguments to 32 bits */ 10137 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 10138 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 10139 /* Arguments specific to the operation */ 10140 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 10141 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 10142 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 10143 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 10144 10145 /* MC_CMD_KR_TUNE_OUT msgresponse */ 10146 #define MC_CMD_KR_TUNE_OUT_LEN 0 10147 10148 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ 10149 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 10150 /* Requested operation */ 10151 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 10152 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 10153 /* Align the arguments to 32 bits */ 10154 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 10155 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 10156 10157 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ 10158 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 10159 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 10160 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 10161 /* RXEQ Parameter */ 10162 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 10163 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 10164 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 10165 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 10166 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 10167 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 10168 /* enum: Attenuation (0-15, Huntington) */ 10169 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 10170 /* enum: CTLE Boost (0-15, Huntington) */ 10171 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 10172 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max 10173 * positive, Medford - 0-31) 10174 */ 10175 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 10176 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max 10177 * positive, Medford - 0-31) 10178 */ 10179 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 10180 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max 10181 * positive, Medford - 0-16) 10182 */ 10183 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 10184 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max 10185 * positive, Medford - 0-16) 10186 */ 10187 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 10188 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max 10189 * positive, Medford - 0-16) 10190 */ 10191 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 10192 /* enum: Edge DFE DLEV (0-128 for Medford) */ 10193 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 10194 /* enum: Variable Gain Amplifier (0-15, Medford) */ 10195 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8 10196 /* enum: CTLE EQ Capacitor (0-15, Medford) */ 10197 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 10198 /* enum: CTLE EQ Resistor (0-7, Medford) */ 10199 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 10200 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 10201 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 10202 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 10203 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 10204 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 10205 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 10206 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 10207 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 10208 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 10209 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 10210 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 10211 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 10212 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 10213 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 10214 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 10215 10216 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ 10217 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 10218 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 10219 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 10220 /* Requested operation */ 10221 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 10222 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 10223 /* Align the arguments to 32 bits */ 10224 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 10225 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 10226 /* RXEQ Parameter */ 10227 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 10228 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 10229 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 10230 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 10231 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 10232 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 10233 /* Enum values, see field(s): */ 10234 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ 10235 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 10236 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 10237 /* Enum values, see field(s): */ 10238 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 10239 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 10240 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 10241 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 10242 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 10243 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 10244 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 10245 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 10246 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 10247 10248 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ 10249 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 10250 10251 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ 10252 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 10253 /* Requested operation */ 10254 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 10255 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 10256 /* Align the arguments to 32 bits */ 10257 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 10258 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 10259 10260 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ 10261 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 10262 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 10263 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 10264 /* TXEQ Parameter */ 10265 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 10266 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 10267 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 10268 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 10269 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 10270 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 10271 /* enum: TX Amplitude (Huntington, Medford) */ 10272 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 10273 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */ 10274 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 10275 /* enum: De-Emphasis Tap1 Fine */ 10276 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 10277 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */ 10278 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 10279 /* enum: De-Emphasis Tap2 Fine (Huntington) */ 10280 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 10281 /* enum: Pre-Emphasis Magnitude (Huntington) */ 10282 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 10283 /* enum: Pre-Emphasis Fine (Huntington) */ 10284 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 10285 /* enum: TX Slew Rate Coarse control (Huntington) */ 10286 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 10287 /* enum: TX Slew Rate Fine control (Huntington) */ 10288 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 10289 /* enum: TX Termination Impedance control (Huntington) */ 10290 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 10291 /* enum: TX Amplitude Fine control (Medford) */ 10292 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa 10293 /* enum: Pre-shoot Tap (Medford) */ 10294 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb 10295 /* enum: De-emphasis Tap (Medford) */ 10296 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc 10297 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 10298 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 10299 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ 10300 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ 10301 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ 10302 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ 10303 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 10304 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 10305 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 10306 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 10307 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 10308 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 10309 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 10310 10311 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ 10312 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 10313 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 10314 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) 10315 /* Requested operation */ 10316 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 10317 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 10318 /* Align the arguments to 32 bits */ 10319 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 10320 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 10321 /* TXEQ Parameter */ 10322 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 10323 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 10324 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 10325 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 10326 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 10327 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 10328 /* Enum values, see field(s): */ 10329 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ 10330 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 10331 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 10332 /* Enum values, see field(s): */ 10333 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ 10334 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 10335 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 10336 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 10337 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 10338 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 10339 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 10340 10341 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ 10342 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 10343 10344 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ 10345 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 10346 /* Requested operation */ 10347 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 10348 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 10349 /* Align the arguments to 32 bits */ 10350 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 10351 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 10352 10353 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ 10354 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 10355 10356 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ 10357 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 10358 /* Requested operation */ 10359 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 10360 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 10361 /* Align the arguments to 32 bits */ 10362 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 10363 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 10364 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 10365 10366 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ 10367 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 10368 10369 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ 10370 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 10371 /* Requested operation */ 10372 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 10373 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 10374 /* Align the arguments to 32 bits */ 10375 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 10376 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 10377 10378 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 10379 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 10380 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 10381 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 10382 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 10383 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 10384 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 10385 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 10386 10387 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */ 10388 #define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8 10389 /* Requested operation */ 10390 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0 10391 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1 10392 /* Align the arguments to 32 bits */ 10393 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1 10394 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3 10395 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4 10396 10397 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */ 10398 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4 10399 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0 10400 10401 10402 /***********************************/ 10403 /* MC_CMD_PCIE_TUNE 10404 * Get or set PCIE Serdes RXEQ and TX Driver settings 10405 */ 10406 #define MC_CMD_PCIE_TUNE 0xf2 10407 10408 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10409 10410 /* MC_CMD_PCIE_TUNE_IN msgrequest */ 10411 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 10412 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 10413 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 10414 /* Requested operation */ 10415 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 10416 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 10417 /* enum: Get current RXEQ settings */ 10418 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 10419 /* enum: Override RXEQ settings */ 10420 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 10421 /* enum: Get current TX Driver settings */ 10422 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 10423 /* enum: Override TX Driver settings */ 10424 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 10425 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ 10426 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 10427 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The 10428 * caller should call this command repeatedly after starting eye plot, until no 10429 * more data is returned. 10430 */ 10431 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 10432 /* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */ 10433 #define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7 10434 /* Align the arguments to 32 bits */ 10435 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 10436 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 10437 /* Arguments specific to the operation */ 10438 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 10439 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 10440 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 10441 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 10442 10443 /* MC_CMD_PCIE_TUNE_OUT msgresponse */ 10444 #define MC_CMD_PCIE_TUNE_OUT_LEN 0 10445 10446 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 10447 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 10448 /* Requested operation */ 10449 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 10450 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 10451 /* Align the arguments to 32 bits */ 10452 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 10453 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 10454 10455 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 10456 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 10457 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 10458 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 10459 /* RXEQ Parameter */ 10460 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 10461 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 10462 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 10463 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 10464 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 10465 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 10466 /* enum: Attenuation (0-15) */ 10467 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 10468 /* enum: CTLE Boost (0-15) */ 10469 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 10470 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 10471 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 10472 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 10473 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 10474 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 10475 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 10476 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 10477 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 10478 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 10479 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 10480 /* enum: DFE DLev */ 10481 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7 10482 /* enum: Figure of Merit */ 10483 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8 10484 /* enum: CTLE EQ Capacitor (HF Gain) */ 10485 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 10486 /* enum: CTLE EQ Resistor (DC Gain) */ 10487 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 10488 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 10489 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5 10490 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 10491 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 10492 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 10493 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 10494 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 10495 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 10496 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 10497 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 10498 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */ 10499 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */ 10500 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */ 10501 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */ 10502 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */ 10503 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */ 10504 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */ 10505 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */ 10506 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */ 10507 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13 10508 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 10509 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14 10510 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10 10511 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 10512 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 10513 10514 /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */ 10515 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8 10516 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252 10517 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 10518 /* Requested operation */ 10519 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0 10520 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1 10521 /* Align the arguments to 32 bits */ 10522 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1 10523 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3 10524 /* RXEQ Parameter */ 10525 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4 10526 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4 10527 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 10528 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 10529 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 10530 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 10531 /* Enum values, see field(s): */ 10532 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */ 10533 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 10534 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5 10535 /* Enum values, see field(s): */ 10536 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 10537 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13 10538 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 10539 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14 10540 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2 10541 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 10542 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 10543 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 10544 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 10545 10546 /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */ 10547 #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0 10548 10549 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 10550 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 10551 /* Requested operation */ 10552 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 10553 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 10554 /* Align the arguments to 32 bits */ 10555 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 10556 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 10557 10558 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 10559 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 10560 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 10561 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 10562 /* RXEQ Parameter */ 10563 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 10564 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 10565 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 10566 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 10567 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 10568 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 10569 /* enum: TxMargin (PIPE) */ 10570 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 10571 /* enum: TxSwing (PIPE) */ 10572 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 10573 /* enum: De-emphasis coefficient C(-1) (PIPE) */ 10574 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 10575 /* enum: De-emphasis coefficient C(0) (PIPE) */ 10576 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 10577 /* enum: De-emphasis coefficient C(+1) (PIPE) */ 10578 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 10579 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 10580 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 10581 /* Enum values, see field(s): */ 10582 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 10583 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 10584 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 10585 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 10586 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 10587 10588 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ 10589 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 10590 /* Requested operation */ 10591 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 10592 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 10593 /* Align the arguments to 32 bits */ 10594 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 10595 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 10596 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 10597 10598 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ 10599 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 10600 10601 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ 10602 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 10603 /* Requested operation */ 10604 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 10605 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 10606 /* Align the arguments to 32 bits */ 10607 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 10608 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 10609 10610 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 10611 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 10612 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 10613 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 10614 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 10615 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 10616 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 10617 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 10618 10619 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN msgrequest */ 10620 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0 10621 10622 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT msgrequest */ 10623 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0 10624 10625 10626 /***********************************/ 10627 /* MC_CMD_LICENSING 10628 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 10629 * - not used for V3 licensing 10630 */ 10631 #define MC_CMD_LICENSING 0xf3 10632 10633 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10634 10635 /* MC_CMD_LICENSING_IN msgrequest */ 10636 #define MC_CMD_LICENSING_IN_LEN 4 10637 /* identifies the type of operation requested */ 10638 #define MC_CMD_LICENSING_IN_OP_OFST 0 10639 /* enum: re-read and apply licenses after a license key partition update; note 10640 * that this operation returns a zero-length response 10641 */ 10642 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 10643 /* enum: report counts of installed licenses */ 10644 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 10645 10646 /* MC_CMD_LICENSING_OUT msgresponse */ 10647 #define MC_CMD_LICENSING_OUT_LEN 28 10648 /* count of application keys which are valid */ 10649 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 10650 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with 10651 * MC_CMD_FC_OP_LICENSE) 10652 */ 10653 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 10654 /* count of application keys which are invalid due to being blacklisted */ 10655 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 10656 /* count of application keys which are invalid due to being unverifiable */ 10657 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 10658 /* count of application keys which are invalid due to being for the wrong node 10659 */ 10660 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 10661 /* licensing state (for diagnostics; the exact meaning of the bits in this 10662 * field are private to the firmware) 10663 */ 10664 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 10665 /* licensing subsystem self-test report (for manftest) */ 10666 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 10667 /* enum: licensing subsystem self-test failed */ 10668 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 10669 /* enum: licensing subsystem self-test passed */ 10670 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 10671 10672 10673 /***********************************/ 10674 /* MC_CMD_LICENSING_V3 10675 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 10676 * - V3 licensing (Medford) 10677 */ 10678 #define MC_CMD_LICENSING_V3 0xd0 10679 10680 #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10681 10682 /* MC_CMD_LICENSING_V3_IN msgrequest */ 10683 #define MC_CMD_LICENSING_V3_IN_LEN 4 10684 /* identifies the type of operation requested */ 10685 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0 10686 /* enum: re-read and apply licenses after a license key partition update; note 10687 * that this operation returns a zero-length response 10688 */ 10689 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0 10690 /* enum: report counts of installed licenses Returns EAGAIN if license 10691 * processing (updating) has been started but not yet completed. 10692 */ 10693 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1 10694 10695 /* MC_CMD_LICENSING_V3_OUT msgresponse */ 10696 #define MC_CMD_LICENSING_V3_OUT_LEN 88 10697 /* count of keys which are valid */ 10698 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0 10699 /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with 10700 * MC_CMD_FC_OP_LICENSE) 10701 */ 10702 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4 10703 /* count of keys which are invalid due to being unverifiable */ 10704 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8 10705 /* count of keys which are invalid due to being for the wrong node */ 10706 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12 10707 /* licensing state (for diagnostics; the exact meaning of the bits in this 10708 * field are private to the firmware) 10709 */ 10710 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16 10711 /* licensing subsystem self-test report (for manftest) */ 10712 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20 10713 /* enum: licensing subsystem self-test failed */ 10714 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0 10715 /* enum: licensing subsystem self-test passed */ 10716 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1 10717 /* bitmask of licensed applications */ 10718 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24 10719 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8 10720 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24 10721 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28 10722 /* reserved for future use */ 10723 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32 10724 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24 10725 /* bitmask of licensed features */ 10726 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56 10727 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8 10728 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56 10729 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60 10730 /* reserved for future use */ 10731 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64 10732 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24 10733 10734 10735 /***********************************/ 10736 /* MC_CMD_LICENSING_GET_ID_V3 10737 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license 10738 * partition - V3 licensing (Medford) 10739 */ 10740 #define MC_CMD_LICENSING_GET_ID_V3 0xd1 10741 10742 #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10743 10744 /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */ 10745 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0 10746 10747 /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */ 10748 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8 10749 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252 10750 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num)) 10751 /* type of license (eg 3) */ 10752 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0 10753 /* length of the license ID (in bytes) */ 10754 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4 10755 /* the unique license ID of the adapter */ 10756 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8 10757 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1 10758 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 10759 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 10760 10761 10762 /***********************************/ 10763 /* MC_CMD_MC2MC_PROXY 10764 * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 10765 * This will fail on a single-core system. 10766 */ 10767 #define MC_CMD_MC2MC_PROXY 0xf4 10768 10769 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10770 10771 /* MC_CMD_MC2MC_PROXY_IN msgrequest */ 10772 #define MC_CMD_MC2MC_PROXY_IN_LEN 0 10773 10774 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ 10775 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 10776 10777 10778 /***********************************/ 10779 /* MC_CMD_GET_LICENSED_APP_STATE 10780 * Query the state of an individual licensed application. (Note that the actual 10781 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation 10782 * or a reboot of the MC.) Not used for V3 licensing 10783 */ 10784 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 10785 10786 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10787 10788 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ 10789 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 10790 /* application ID to query (LICENSED_APP_ID_xxx) */ 10791 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 10792 10793 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ 10794 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 10795 /* state of this application */ 10796 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 10797 /* enum: no (or invalid) license is present for the application */ 10798 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 10799 /* enum: a valid license is present for the application */ 10800 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 10801 10802 10803 /***********************************/ 10804 /* MC_CMD_GET_LICENSED_V3_APP_STATE 10805 * Query the state of an individual licensed application. (Note that the actual 10806 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 10807 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 10808 */ 10809 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2 10810 10811 #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10812 10813 /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */ 10814 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8 10815 /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit 10816 * mask 10817 */ 10818 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0 10819 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8 10820 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0 10821 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4 10822 10823 /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */ 10824 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4 10825 /* state of this application */ 10826 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0 10827 /* enum: no (or invalid) license is present for the application */ 10828 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0 10829 /* enum: a valid license is present for the application */ 10830 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 10831 10832 10833 /***********************************/ 10834 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES 10835 * Query the state of an one or more licensed features. (Note that the actual 10836 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 10837 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 10838 */ 10839 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3 10840 10841 #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10842 10843 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */ 10844 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8 10845 /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or 10846 * more bits set 10847 */ 10848 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0 10849 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8 10850 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0 10851 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4 10852 10853 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */ 10854 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8 10855 /* states of these features - bit set for licensed, clear for not licensed */ 10856 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0 10857 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8 10858 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 10859 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 10860 10861 10862 /***********************************/ 10863 /* MC_CMD_LICENSED_APP_OP 10864 * Perform an action for an individual licensed application - not used for V3 10865 * licensing. 10866 */ 10867 #define MC_CMD_LICENSED_APP_OP 0xf6 10868 10869 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10870 10871 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */ 10872 #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 10873 #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 10874 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) 10875 /* application ID */ 10876 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 10877 /* the type of operation requested */ 10878 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 10879 /* enum: validate application */ 10880 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 10881 /* enum: mask application */ 10882 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 10883 /* arguments specific to this particular operation */ 10884 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 10885 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 10886 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 10887 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 10888 10889 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ 10890 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 10891 #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 10892 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) 10893 /* result specific to this particular operation */ 10894 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 10895 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 10896 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 10897 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 10898 10899 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ 10900 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 10901 /* application ID */ 10902 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 10903 /* the type of operation requested */ 10904 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 10905 /* validation challenge */ 10906 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 10907 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 10908 10909 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ 10910 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 10911 /* feature expiry (time_t) */ 10912 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 10913 /* validation response */ 10914 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 10915 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 10916 10917 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ 10918 #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 10919 /* application ID */ 10920 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 10921 /* the type of operation requested */ 10922 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 10923 /* flag */ 10924 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 10925 10926 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ 10927 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 10928 10929 10930 /***********************************/ 10931 /* MC_CMD_LICENSED_V3_VALIDATE_APP 10932 * Perform validation for an individual licensed application - V3 licensing 10933 * (Medford) 10934 */ 10935 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4 10936 10937 #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10938 10939 /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */ 10940 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 56 10941 /* challenge for validation (384 bits) */ 10942 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0 10943 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48 10944 /* application ID expressed as a single bit mask */ 10945 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48 10946 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8 10947 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48 10948 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52 10949 10950 /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */ 10951 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116 10952 /* validation response to challenge in the form of ECDSA signature consisting 10953 * of two 384-bit integers, r and s, in big-endian order. The signature signs a 10954 * SHA-384 digest of a message constructed from the concatenation of the input 10955 * message and the remaining fields of this output message, e.g. challenge[48 10956 * bytes] ... expiry_time[4 bytes] ... 10957 */ 10958 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0 10959 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96 10960 /* application expiry time */ 10961 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96 10962 /* application expiry units */ 10963 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100 10964 /* enum: expiry units are accounting units */ 10965 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0 10966 /* enum: expiry units are calendar days */ 10967 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1 10968 /* base MAC address of the NIC stored in NVRAM (note that this is a constant 10969 * value for a given NIC regardless which function is calling, effectively this 10970 * is PF0 base MAC address) 10971 */ 10972 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 104 10973 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 6 10974 /* MAC address of v-adaptor associated with the client. If no such v-adapator 10975 * exists, then the field is filled with 0xFF. 10976 */ 10977 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110 10978 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6 10979 10980 10981 /***********************************/ 10982 /* MC_CMD_LICENSED_V3_MASK_FEATURES 10983 * Mask features - V3 licensing (Medford) 10984 */ 10985 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5 10986 10987 #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10988 10989 /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */ 10990 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12 10991 /* mask to be applied to features to be changed */ 10992 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0 10993 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8 10994 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0 10995 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4 10996 /* whether to turn on or turn off the masked features */ 10997 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8 10998 /* enum: turn the features off */ 10999 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0 11000 /* enum: turn the features back on */ 11001 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1 11002 11003 /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ 11004 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 11005 11006 11007 /***********************************/ 11008 /* MC_CMD_LICENSING_V3_TEMPORARY 11009 * Perform operations to support installation of a single temporary license in 11010 * the adapter, in addition to those found in the licensing partition. See 11011 * SF-116124-SW for an overview of how this could be used. The license is 11012 * stored in MC persistent data and so will survive a MC reboot, but will be 11013 * erased when the adapter is power cycled 11014 */ 11015 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6 11016 11017 #define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11018 11019 /* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */ 11020 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4 11021 /* operation code */ 11022 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0 11023 /* enum: install a new license, overwriting any existing temporary license. 11024 * This is an asynchronous operation owing to the time taken to validate an 11025 * ECDSA license 11026 */ 11027 #define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0 11028 /* enum: clear the license immediately rather than waiting for the next power 11029 * cycle 11030 */ 11031 #define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1 11032 /* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET 11033 * operation 11034 */ 11035 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2 11036 11037 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */ 11038 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164 11039 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0 11040 /* ECDSA license and signature */ 11041 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4 11042 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160 11043 11044 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */ 11045 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4 11046 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0 11047 11048 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */ 11049 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4 11050 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0 11051 11052 /* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */ 11053 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12 11054 /* status code */ 11055 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0 11056 /* enum: finished validating and installing license */ 11057 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0 11058 /* enum: license validation and installation in progress */ 11059 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1 11060 /* enum: licensing error. More specific error messages are not provided to 11061 * avoid exposing details of the licensing system to the client 11062 */ 11063 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2 11064 /* bitmask of licensed features */ 11065 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4 11066 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8 11067 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4 11068 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8 11069 11070 11071 /***********************************/ 11072 /* MC_CMD_SET_PORT_SNIFF_CONFIG 11073 * Configure RX port sniffing for the physical port associated with the calling 11074 * function. Only a privileged function may change the port sniffing 11075 * configuration. A copy of all traffic delivered to the host (non-promiscuous 11076 * mode) or all traffic arriving at the port (promiscuous mode) may be 11077 * delivered to a specific queue, or a set of queues with RSS. 11078 */ 11079 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 11080 11081 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11082 11083 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ 11084 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 11085 /* configuration flags */ 11086 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 11087 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 11088 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 11089 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 11090 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 11091 /* receive queue handle (for RSS mode, this is the base queue) */ 11092 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 11093 /* receive mode */ 11094 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 11095 /* enum: receive to just the specified queue */ 11096 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 11097 /* enum: receive to multiple queues using RSS context */ 11098 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 11099 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 11100 * that these handles should be considered opaque to the host, although a value 11101 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 11102 */ 11103 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 11104 11105 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ 11106 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 11107 11108 11109 /***********************************/ 11110 /* MC_CMD_GET_PORT_SNIFF_CONFIG 11111 * Obtain the current RX port sniffing configuration for the physical port 11112 * associated with the calling function. Only a privileged function may read 11113 * the configuration. 11114 */ 11115 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 11116 11117 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11118 11119 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ 11120 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 11121 11122 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ 11123 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 11124 /* configuration flags */ 11125 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 11126 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 11127 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 11128 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 11129 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 11130 /* receiving queue handle (for RSS mode, this is the base queue) */ 11131 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 11132 /* receive mode */ 11133 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 11134 /* enum: receiving to just the specified queue */ 11135 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 11136 /* enum: receiving to multiple queues using RSS context */ 11137 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 11138 /* RSS context (for RX_MODE_RSS) */ 11139 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 11140 11141 11142 /***********************************/ 11143 /* MC_CMD_SET_PARSER_DISP_CONFIG 11144 * Change configuration related to the parser-dispatcher subsystem. 11145 */ 11146 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9 11147 11148 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11149 11150 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */ 11151 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12 11152 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252 11153 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) 11154 /* the type of configuration setting to change */ 11155 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 11156 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible 11157 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.) 11158 */ 11159 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0 11160 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the 11161 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single 11162 * boolean.) 11163 */ 11164 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1 11165 /* handle for the entity to update: queue handle, EVB port ID, etc. depending 11166 * on the type of configuration setting being changed 11167 */ 11168 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 11169 /* new value: the details depend on the type of configuration setting being 11170 * changed 11171 */ 11172 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8 11173 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4 11174 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1 11175 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61 11176 11177 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ 11178 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 11179 11180 11181 /***********************************/ 11182 /* MC_CMD_GET_PARSER_DISP_CONFIG 11183 * Read configuration related to the parser-dispatcher subsystem. 11184 */ 11185 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa 11186 11187 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11188 11189 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ 11190 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 11191 /* the type of configuration setting to read */ 11192 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 11193 /* Enum values, see field(s): */ 11194 /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ 11195 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on 11196 * the type of configuration setting being read 11197 */ 11198 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 11199 11200 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ 11201 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 11202 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 11203 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) 11204 /* current value: the details depend on the type of configuration setting being 11205 * read 11206 */ 11207 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 11208 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 11209 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 11210 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 11211 11212 11213 /***********************************/ 11214 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG 11215 * Configure TX port sniffing for the physical port associated with the calling 11216 * function. Only a privileged function may change the port sniffing 11217 * configuration. A copy of all traffic transmitted through the port may be 11218 * delivered to a specific queue, or a set of queues with RSS. Note that these 11219 * packets are delivered with transmit timestamps in the packet prefix, not 11220 * receive timestamps, so it is likely that the queue(s) will need to be 11221 * dedicated as TX sniff receivers. 11222 */ 11223 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb 11224 11225 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11226 11227 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 11228 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 11229 /* configuration flags */ 11230 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 11231 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 11232 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 11233 /* receive queue handle (for RSS mode, this is the base queue) */ 11234 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 11235 /* receive mode */ 11236 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 11237 /* enum: receive to just the specified queue */ 11238 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 11239 /* enum: receive to multiple queues using RSS context */ 11240 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 11241 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 11242 * that these handles should be considered opaque to the host, although a value 11243 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 11244 */ 11245 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 11246 11247 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 11248 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 11249 11250 11251 /***********************************/ 11252 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG 11253 * Obtain the current TX port sniffing configuration for the physical port 11254 * associated with the calling function. Only a privileged function may read 11255 * the configuration. 11256 */ 11257 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc 11258 11259 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11260 11261 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 11262 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 11263 11264 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 11265 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 11266 /* configuration flags */ 11267 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 11268 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 11269 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 11270 /* receiving queue handle (for RSS mode, this is the base queue) */ 11271 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 11272 /* receive mode */ 11273 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 11274 /* enum: receiving to just the specified queue */ 11275 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 11276 /* enum: receiving to multiple queues using RSS context */ 11277 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 11278 /* RSS context (for RX_MODE_RSS) */ 11279 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 11280 11281 11282 /***********************************/ 11283 /* MC_CMD_RMON_STATS_RX_ERRORS 11284 * Per queue rx error stats. 11285 */ 11286 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe 11287 11288 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11289 11290 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ 11291 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 11292 /* The rx queue to get stats for. */ 11293 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 11294 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 11295 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 11296 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 11297 11298 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ 11299 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 11300 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 11301 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 11302 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 11303 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 11304 11305 11306 /***********************************/ 11307 /* MC_CMD_GET_PCIE_RESOURCE_INFO 11308 * Find out about available PCIE resources 11309 */ 11310 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd 11311 11312 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ 11313 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 11314 11315 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ 11316 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 11317 /* The maximum number of PFs the device can expose */ 11318 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 11319 /* The maximum number of VFs the device can expose in total */ 11320 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 11321 /* The maximum number of MSI-X vectors the device can provide in total */ 11322 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 11323 /* the number of MSI-X vectors the device will allocate by default to each PF 11324 */ 11325 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 11326 /* the number of MSI-X vectors the device will allocate by default to each VF 11327 */ 11328 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 11329 /* the maximum number of MSI-X vectors the device can allocate to any one PF */ 11330 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 11331 /* the maximum number of MSI-X vectors the device can allocate to any one VF */ 11332 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 11333 11334 11335 /***********************************/ 11336 /* MC_CMD_GET_PORT_MODES 11337 * Find out about available port modes 11338 */ 11339 #define MC_CMD_GET_PORT_MODES 0xff 11340 11341 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11342 11343 /* MC_CMD_GET_PORT_MODES_IN msgrequest */ 11344 #define MC_CMD_GET_PORT_MODES_IN_LEN 0 11345 11346 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */ 11347 #define MC_CMD_GET_PORT_MODES_OUT_LEN 12 11348 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */ 11349 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 11350 /* Default (canonical) board mode */ 11351 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 11352 /* Current board mode */ 11353 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 11354 11355 11356 /***********************************/ 11357 /* MC_CMD_READ_ATB 11358 * Sample voltages on the ATB 11359 */ 11360 #define MC_CMD_READ_ATB 0x100 11361 11362 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11363 11364 /* MC_CMD_READ_ATB_IN msgrequest */ 11365 #define MC_CMD_READ_ATB_IN_LEN 16 11366 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 11367 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ 11368 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ 11369 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ 11370 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 11371 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 11372 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 11373 11374 /* MC_CMD_READ_ATB_OUT msgresponse */ 11375 #define MC_CMD_READ_ATB_OUT_LEN 4 11376 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 11377 11378 11379 /***********************************/ 11380 /* MC_CMD_GET_WORKAROUNDS 11381 * Read the list of all implemented and all currently enabled workarounds. The 11382 * enums here must correspond with those in MC_CMD_WORKAROUND. 11383 */ 11384 #define MC_CMD_GET_WORKAROUNDS 0x59 11385 11386 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11387 11388 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ 11389 #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 11390 /* Each workaround is represented by a single bit according to the enums below. 11391 */ 11392 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 11393 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 11394 /* enum: Bug 17230 work around. */ 11395 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 11396 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 11397 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 11398 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 11399 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 11400 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 11401 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10 11402 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 11403 * - before adding code that queries this workaround, remember that there's 11404 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 11405 * and will hence (incorrectly) report that the bug doesn't exist. 11406 */ 11407 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20 11408 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */ 11409 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40 11410 /* enum: Bug 61265 work around (broken EVQ TMR writes). */ 11411 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80 11412 11413 11414 /***********************************/ 11415 /* MC_CMD_PRIVILEGE_MASK 11416 * Read/set privileges of an arbitrary PCIe function 11417 */ 11418 #define MC_CMD_PRIVILEGE_MASK 0x5a 11419 11420 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11421 11422 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */ 11423 #define MC_CMD_PRIVILEGE_MASK_IN_LEN 8 11424 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF 11425 * 1,3 = 0x00030001 11426 */ 11427 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0 11428 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0 11429 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16 11430 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16 11431 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16 11432 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */ 11433 /* New privilege mask to be set. The mask will only be changed if the MSB is 11434 * set to 1. 11435 */ 11436 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4 11437 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */ 11438 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */ 11439 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ 11440 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ 11441 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ 11442 /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */ 11443 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 11444 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ 11445 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ 11446 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ 11447 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ 11448 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ 11449 /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC 11450 * adress. 11451 */ 11452 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800 11453 /* enum: Privilege that allows a Function to change the MAC address configured 11454 * in its associated vAdapter/vPort. 11455 */ 11456 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000 11457 /* enum: Privilege that allows a Function to install filters that specify VLANs 11458 * that are not in the permit list for the associated vPort. This privilege is 11459 * primarily to support ESX where vPorts are created that restrict traffic to 11460 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT. 11461 */ 11462 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000 11463 /* enum: Set this bit to indicate that a new privilege mask is to be set, 11464 * otherwise the command will only read the existing mask. 11465 */ 11466 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000 11467 11468 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */ 11469 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4 11470 /* For an admin function, always all the privileges are reported. */ 11471 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 11472 11473 11474 /***********************************/ 11475 /* MC_CMD_LINK_STATE_MODE 11476 * Read/set link state mode of a VF 11477 */ 11478 #define MC_CMD_LINK_STATE_MODE 0x5c 11479 11480 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11481 11482 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */ 11483 #define MC_CMD_LINK_STATE_MODE_IN_LEN 8 11484 /* The target function to have its link state mode read or set, must be a VF 11485 * e.g. VF 1,3 = 0x00030001 11486 */ 11487 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 11488 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 11489 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 11490 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 11491 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 11492 /* New link state mode to be set */ 11493 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 11494 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ 11495 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ 11496 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ 11497 /* enum: Use this value to just read the existing setting without modifying it. 11498 */ 11499 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff 11500 11501 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ 11502 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 11503 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 11504 11505 11506 /***********************************/ 11507 /* MC_CMD_GET_SNAPSHOT_LENGTH 11508 * Obtain the curent range of allowable values for the SNAPSHOT_LENGTH 11509 * parameter to MC_CMD_INIT_RXQ. 11510 */ 11511 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 11512 11513 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11514 11515 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ 11516 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 11517 11518 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ 11519 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 11520 /* Minimum acceptable snapshot length. */ 11521 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 11522 /* Maximum acceptable snapshot length. */ 11523 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 11524 11525 11526 /***********************************/ 11527 /* MC_CMD_FUSE_DIAGS 11528 * Additional fuse diagnostics 11529 */ 11530 #define MC_CMD_FUSE_DIAGS 0x102 11531 11532 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11533 11534 /* MC_CMD_FUSE_DIAGS_IN msgrequest */ 11535 #define MC_CMD_FUSE_DIAGS_IN_LEN 0 11536 11537 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */ 11538 #define MC_CMD_FUSE_DIAGS_OUT_LEN 48 11539 /* Total number of mismatched bits between pairs in area 0 */ 11540 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 11541 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ 11542 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 11543 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ 11544 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 11545 /* Checksum of data after logical OR of pairs in area 0 */ 11546 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 11547 /* Total number of mismatched bits between pairs in area 1 */ 11548 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 11549 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ 11550 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 11551 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ 11552 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 11553 /* Checksum of data after logical OR of pairs in area 1 */ 11554 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 11555 /* Total number of mismatched bits between pairs in area 2 */ 11556 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 11557 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ 11558 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 11559 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ 11560 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 11561 /* Checksum of data after logical OR of pairs in area 2 */ 11562 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 11563 11564 11565 /***********************************/ 11566 /* MC_CMD_PRIVILEGE_MODIFY 11567 * Modify the privileges of a set of PCIe functions. Note that this operation 11568 * only effects non-admin functions unless the admin privilege itself is 11569 * included in one of the masks provided. 11570 */ 11571 #define MC_CMD_PRIVILEGE_MODIFY 0x60 11572 11573 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11574 11575 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ 11576 #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 11577 /* The groups of functions to have their privilege masks modified. */ 11578 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 11579 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ 11580 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ 11581 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ 11582 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ 11583 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ 11584 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ 11585 /* For VFS_OF_PF specify the PF, for ONE specify the target function */ 11586 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 11587 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 11588 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 11589 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 11590 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 11591 /* Privileges to be added to the target functions. For privilege definitions 11592 * refer to the command MC_CMD_PRIVILEGE_MASK 11593 */ 11594 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 11595 /* Privileges to be removed from the target functions. For privilege 11596 * definitions refer to the command MC_CMD_PRIVILEGE_MASK 11597 */ 11598 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 11599 11600 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ 11601 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 11602 11603 11604 /***********************************/ 11605 /* MC_CMD_XPM_READ_BYTES 11606 * Read XPM memory 11607 */ 11608 #define MC_CMD_XPM_READ_BYTES 0x103 11609 11610 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11611 11612 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */ 11613 #define MC_CMD_XPM_READ_BYTES_IN_LEN 8 11614 /* Start address (byte) */ 11615 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 11616 /* Count (bytes) */ 11617 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 11618 11619 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ 11620 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 11621 #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 11622 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) 11623 /* Data */ 11624 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 11625 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 11626 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 11627 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 11628 11629 11630 /***********************************/ 11631 /* MC_CMD_XPM_WRITE_BYTES 11632 * Write XPM memory 11633 */ 11634 #define MC_CMD_XPM_WRITE_BYTES 0x104 11635 11636 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11637 11638 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ 11639 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 11640 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 11641 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) 11642 /* Start address (byte) */ 11643 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 11644 /* Count (bytes) */ 11645 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 11646 /* Data */ 11647 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 11648 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 11649 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 11650 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 11651 11652 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ 11653 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 11654 11655 11656 /***********************************/ 11657 /* MC_CMD_XPM_READ_SECTOR 11658 * Read XPM sector 11659 */ 11660 #define MC_CMD_XPM_READ_SECTOR 0x105 11661 11662 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11663 11664 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ 11665 #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 11666 /* Sector index */ 11667 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 11668 /* Sector size */ 11669 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 11670 11671 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ 11672 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 11673 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 11674 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) 11675 /* Sector type */ 11676 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 11677 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ 11678 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ 11679 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ 11680 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ 11681 /* Sector data */ 11682 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 11683 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 11684 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 11685 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 11686 11687 11688 /***********************************/ 11689 /* MC_CMD_XPM_WRITE_SECTOR 11690 * Write XPM sector 11691 */ 11692 #define MC_CMD_XPM_WRITE_SECTOR 0x106 11693 11694 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11695 11696 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ 11697 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 11698 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 11699 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) 11700 /* If writing fails due to an uncorrectable error, try up to RETRIES following 11701 * sectors (or until no more space available). If 0, only one write attempt is 11702 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair 11703 * mechanism. 11704 */ 11705 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 11706 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 11707 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 11708 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 11709 /* Sector type */ 11710 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 11711 /* Enum values, see field(s): */ 11712 /* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ 11713 /* Sector size */ 11714 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 11715 /* Sector data */ 11716 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 11717 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 11718 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 11719 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 11720 11721 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ 11722 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 11723 /* New sector index */ 11724 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 11725 11726 11727 /***********************************/ 11728 /* MC_CMD_XPM_INVALIDATE_SECTOR 11729 * Invalidate XPM sector 11730 */ 11731 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 11732 11733 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11734 11735 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ 11736 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 11737 /* Sector index */ 11738 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 11739 11740 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ 11741 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 11742 11743 11744 /***********************************/ 11745 /* MC_CMD_XPM_BLANK_CHECK 11746 * Blank-check XPM memory and report bad locations 11747 */ 11748 #define MC_CMD_XPM_BLANK_CHECK 0x108 11749 11750 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11751 11752 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ 11753 #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 11754 /* Start address (byte) */ 11755 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 11756 /* Count (bytes) */ 11757 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 11758 11759 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ 11760 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 11761 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 11762 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) 11763 /* Total number of bad (non-blank) locations */ 11764 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 11765 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit 11766 * into MCDI response) 11767 */ 11768 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 11769 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 11770 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 11771 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 11772 11773 11774 /***********************************/ 11775 /* MC_CMD_XPM_REPAIR 11776 * Blank-check and repair XPM memory 11777 */ 11778 #define MC_CMD_XPM_REPAIR 0x109 11779 11780 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11781 11782 /* MC_CMD_XPM_REPAIR_IN msgrequest */ 11783 #define MC_CMD_XPM_REPAIR_IN_LEN 8 11784 /* Start address (byte) */ 11785 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 11786 /* Count (bytes) */ 11787 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 11788 11789 /* MC_CMD_XPM_REPAIR_OUT msgresponse */ 11790 #define MC_CMD_XPM_REPAIR_OUT_LEN 0 11791 11792 11793 /***********************************/ 11794 /* MC_CMD_XPM_DECODER_TEST 11795 * Test XPM memory address decoders for gross manufacturing defects. Can only 11796 * be performed on an unprogrammed part. 11797 */ 11798 #define MC_CMD_XPM_DECODER_TEST 0x10a 11799 11800 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11801 11802 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ 11803 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 11804 11805 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ 11806 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 11807 11808 11809 /***********************************/ 11810 /* MC_CMD_XPM_WRITE_TEST 11811 * XPM memory write test. Test XPM write logic for gross manufacturing defects 11812 * by writing to a dedicated test row. There are 16 locations in the test row 11813 * and the test can only be performed on locations that have not been 11814 * previously used (i.e. can be run at most 16 times). The test will pick the 11815 * first available location to use, or fail with ENOSPC if none left. 11816 */ 11817 #define MC_CMD_XPM_WRITE_TEST 0x10b 11818 11819 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11820 11821 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ 11822 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 11823 11824 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ 11825 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 11826 11827 11828 /***********************************/ 11829 /* MC_CMD_EXEC_SIGNED 11830 * Check the CMAC of the contents of IMEM and DMEM against the value supplied 11831 * and if correct begin execution from the start of IMEM. The caller supplies a 11832 * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC 11833 * computation runs from the start of IMEM, and from the start of DMEM + 16k, 11834 * to match flash booting. The command will respond with EINVAL if the CMAC 11835 * does match, otherwise it will respond with success before it jumps to IMEM. 11836 */ 11837 #define MC_CMD_EXEC_SIGNED 0x10c 11838 11839 #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11840 11841 /* MC_CMD_EXEC_SIGNED_IN msgrequest */ 11842 #define MC_CMD_EXEC_SIGNED_IN_LEN 28 11843 /* the length of code to include in the CMAC */ 11844 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0 11845 /* the length of date to include in the CMAC */ 11846 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4 11847 /* the XPM sector containing the key to use */ 11848 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8 11849 /* the expected CMAC value */ 11850 #define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12 11851 #define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16 11852 11853 /* MC_CMD_EXEC_SIGNED_OUT msgresponse */ 11854 #define MC_CMD_EXEC_SIGNED_OUT_LEN 0 11855 11856 11857 /***********************************/ 11858 /* MC_CMD_PREPARE_SIGNED 11859 * Prepare to upload a signed image. This will scrub the specified length of 11860 * the data region, which must be at least as large as the DATALEN supplied to 11861 * MC_CMD_EXEC_SIGNED. 11862 */ 11863 #define MC_CMD_PREPARE_SIGNED 0x10d 11864 11865 #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11866 11867 /* MC_CMD_PREPARE_SIGNED_IN msgrequest */ 11868 #define MC_CMD_PREPARE_SIGNED_IN_LEN 4 11869 /* the length of data area to clear */ 11870 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0 11871 11872 /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */ 11873 #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0 11874 11875 11876 /***********************************/ 11877 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 11878 * Configure UDP ports for tunnel encapsulation hardware acceleration. The 11879 * parser-dispatcher will attempt to parse traffic on these ports as tunnel 11880 * encapsulation PDUs and filter them using the tunnel encapsulation filter 11881 * chain rather than the standard filter chain. Note that this command can 11882 * cause all functions to see a reset. (Available on Medford only.) 11883 */ 11884 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117 11885 11886 #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11887 11888 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */ 11889 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4 11890 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68 11891 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num)) 11892 /* Flags */ 11893 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0 11894 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2 11895 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0 11896 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1 11897 /* The number of entries in the ENTRIES array */ 11898 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2 11899 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2 11900 /* Entries defining the UDP port to protocol mapping, each laid out as a 11901 * TUNNEL_ENCAP_UDP_PORT_ENTRY 11902 */ 11903 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4 11904 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4 11905 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0 11906 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16 11907 11908 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */ 11909 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2 11910 /* Flags */ 11911 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0 11912 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2 11913 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0 11914 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1 11915 11916 11917 /***********************************/ 11918 /* MC_CMD_RX_BALANCING 11919 * Configure a port upconverter to distribute the packets on both RX engines. 11920 * Packets are distributed based on a table with the destination vFIFO. The 11921 * index of the table is a hash of source and destination of IPV4 and VLAN 11922 * priority. 11923 */ 11924 #define MC_CMD_RX_BALANCING 0x118 11925 11926 #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11927 11928 /* MC_CMD_RX_BALANCING_IN msgrequest */ 11929 #define MC_CMD_RX_BALANCING_IN_LEN 16 11930 /* The RX port whose upconverter table will be modified */ 11931 #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0 11932 /* The VLAN priority associated to the table index and vFIFO */ 11933 #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4 11934 /* The resulting bit of SRC^DST for indexing the table */ 11935 #define MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8 11936 /* The RX engine to which the vFIFO in the table entry will point to */ 11937 #define MC_CMD_RX_BALANCING_IN_ENG_OFST 12 11938 11939 /* MC_CMD_RX_BALANCING_OUT msgresponse */ 11940 #define MC_CMD_RX_BALANCING_OUT_LEN 0 11941 11942 11943 /***********************************/ 11944 /* MC_CMD_NVRAM_PRIVATE_APPEND 11945 * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST 11946 * if the tag is already present. 11947 */ 11948 #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c 11949 11950 #define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11951 11952 /* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */ 11953 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9 11954 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252 11955 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num)) 11956 /* The tag to be appended */ 11957 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0 11958 /* The length of the data */ 11959 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4 11960 /* The data to be contained in the TLV structure */ 11961 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8 11962 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1 11963 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1 11964 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244 11965 11966 /* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */ 11967 #define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0 11968 11969 11970 /***********************************/ 11971 /* MC_CMD_XPM_VERIFY_CONTENTS 11972 * Verify that the contents of the XPM memory is correct (Medford only). This 11973 * is used during manufacture to check that the XPM memory has been programmed 11974 * correctly at ATE. 11975 */ 11976 #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b 11977 11978 #define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11979 11980 /* MC_CMD_XPM_VERIFY_CONTENTS_IN msgrequest */ 11981 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4 11982 /* Data type to be checked */ 11983 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0 11984 11985 /* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */ 11986 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12 11987 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252 11988 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num)) 11989 /* Number of sectors found (test builds only) */ 11990 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0 11991 /* Number of bytes found (test builds only) */ 11992 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4 11993 /* Length of signature */ 11994 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8 11995 /* Signature */ 11996 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12 11997 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1 11998 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0 11999 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240 12000 12001 12002 /***********************************/ 12003 /* MC_CMD_SET_EVQ_TMR 12004 * Update the timer load, timer reload and timer mode values for a given EVQ. 12005 * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will 12006 * be rounded up to the granularity supported by the hardware, then truncated 12007 * to the range supported by the hardware. The resulting value after the 12008 * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS 12009 * and TMR_RELOAD_ACT_NS). 12010 */ 12011 #define MC_CMD_SET_EVQ_TMR 0x120 12012 12013 #define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12014 12015 /* MC_CMD_SET_EVQ_TMR_IN msgrequest */ 12016 #define MC_CMD_SET_EVQ_TMR_IN_LEN 16 12017 /* Function-relative queue instance */ 12018 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0 12019 /* Requested value for timer load (in nanoseconds) */ 12020 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4 12021 /* Requested value for timer reload (in nanoseconds) */ 12022 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8 12023 /* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */ 12024 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12 12025 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */ 12026 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */ 12027 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */ 12028 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */ 12029 12030 /* MC_CMD_SET_EVQ_TMR_OUT msgresponse */ 12031 #define MC_CMD_SET_EVQ_TMR_OUT_LEN 8 12032 /* Actual value for timer load (in nanoseconds) */ 12033 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0 12034 /* Actual value for timer reload (in nanoseconds) */ 12035 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4 12036 12037 12038 /***********************************/ 12039 /* MC_CMD_GET_EVQ_TMR_PROPERTIES 12040 * Query properties about the event queue timers. 12041 */ 12042 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122 12043 12044 #define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12045 12046 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */ 12047 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0 12048 12049 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */ 12050 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36 12051 /* Reserved for future use. */ 12052 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0 12053 /* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in 12054 * nanoseconds) for each increment of the timer load/reload count. The 12055 * requested duration of a timer is this value multiplied by the timer 12056 * load/reload count. 12057 */ 12058 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4 12059 /* For timers updated via writes to EVQ_TMR_REG, this is the maximum value 12060 * allowed for timer load/reload counts. 12061 */ 12062 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8 12063 /* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a 12064 * multiple of this step size will be rounded in an implementation defined 12065 * manner. 12066 */ 12067 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12 12068 /* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only 12069 * meaningful if MC_CMD_SET_EVQ_TMR is implemented. 12070 */ 12071 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16 12072 /* Timer durations requested via MCDI that are not a multiple of this step size 12073 * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented. 12074 */ 12075 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20 12076 /* For timers updated using the bug35388 workaround, this is the time interval 12077 * (in nanoseconds) for each increment of the timer load/reload count. The 12078 * requested duration of a timer is this value multiplied by the timer 12079 * load/reload count. This field is only meaningful if the bug35388 workaround 12080 * is enabled. 12081 */ 12082 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24 12083 /* For timers updated using the bug35388 workaround, this is the maximum value 12084 * allowed for timer load/reload counts. This field is only meaningful if the 12085 * bug35388 workaround is enabled. 12086 */ 12087 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28 12088 /* For timers updated using the bug35388 workaround, timer load/reload counts 12089 * not a multiple of this step size will be rounded in an implementation 12090 * defined manner. This field is only meaningful if the bug35388 workaround is 12091 * enabled. 12092 */ 12093 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32 12094 12095 12096 /***********************************/ 12097 /* MC_CMD_ALLOCATE_TX_VFIFO_CP 12098 * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the 12099 * non used switch buffers. 12100 */ 12101 #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d 12102 12103 #define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12104 12105 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */ 12106 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20 12107 /* Desired instance. Must be set to a specific instance, which is a function 12108 * local queue index. 12109 */ 12110 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0 12111 /* Will the common pool be used as TX_vFIFO_ULL (1) */ 12112 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4 12113 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */ 12114 /* enum: Using this interface without TX_vFIFO_ULL is not supported for now */ 12115 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0 12116 /* Number of buffers to reserve for the common pool */ 12117 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8 12118 /* TX datapath to which the Common Pool is connected to. */ 12119 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12 12120 /* enum: Extracts information from function */ 12121 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 12122 /* Network port or RX Engine to which the common pool connects. */ 12123 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16 12124 /* enum: Extracts information from function */ 12125 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */ 12126 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */ 12127 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */ 12128 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */ 12129 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */ 12130 /* enum: To enable Switch loopback with Rx engine 0 */ 12131 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4 12132 /* enum: To enable Switch loopback with Rx engine 1 */ 12133 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5 12134 12135 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 12136 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4 12137 /* ID of the common pool allocated */ 12138 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0 12139 12140 12141 /***********************************/ 12142 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 12143 * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the 12144 * previously allocated common pools. 12145 */ 12146 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e 12147 12148 #define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12149 12150 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */ 12151 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20 12152 /* Common pool previously allocated to which the new vFIFO will be associated 12153 */ 12154 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0 12155 /* Port or RX engine to associate the vFIFO egress */ 12156 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4 12157 /* enum: Extracts information from common pool */ 12158 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1 12159 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */ 12160 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */ 12161 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */ 12162 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */ 12163 /* enum: To enable Switch loopback with Rx engine 0 */ 12164 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4 12165 /* enum: To enable Switch loopback with Rx engine 1 */ 12166 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5 12167 /* Minimum number of buffers that the pool must have */ 12168 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8 12169 /* enum: Do not check the space available */ 12170 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0 12171 /* Will the vFIFO be used as TX_vFIFO_ULL */ 12172 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12 12173 /* Network priority of the vFIFO,if applicable */ 12174 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16 12175 /* enum: Search for the lowest unused priority */ 12176 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1 12177 12178 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */ 12179 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8 12180 /* Short vFIFO ID */ 12181 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0 12182 /* Network priority of the vFIFO */ 12183 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4 12184 12185 12186 /***********************************/ 12187 /* MC_CMD_TEARDOWN_TX_VFIFO_VF 12188 * This interface clears the configuration of the given vFIFO and leaves it 12189 * ready to be re-used. 12190 */ 12191 #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f 12192 12193 #define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12194 12195 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */ 12196 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4 12197 /* Short vFIFO ID */ 12198 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0 12199 12200 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */ 12201 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0 12202 12203 12204 /***********************************/ 12205 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP 12206 * This interface clears the configuration of the given common pool and leaves 12207 * it ready to be re-used. 12208 */ 12209 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121 12210 12211 #define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12212 12213 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */ 12214 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4 12215 /* Common pool ID given when pool allocated */ 12216 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0 12217 12218 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 12219 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0 12220 12221 12222 /***********************************/ 12223 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 12224 * This interface allows the host to find out how many common pool buffers are 12225 * not yet assigned. 12226 */ 12227 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124 12228 12229 #define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12230 12231 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */ 12232 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0 12233 12234 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT msgresponse */ 12235 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_LEN 8 12236 /* Available buffers for the ENG to NET vFIFOs. */ 12237 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0 12238 /* Available buffers for the ENG to ENG and NET to ENG vFIFOs. */ 12239 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4 12240 12241 12242 #endif /* MCDI_PCOL_H */ 12243