1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 /* Common definitions for all Efx net driver code */ 12 13 #ifndef EF4_NET_DRIVER_H 14 #define EF4_NET_DRIVER_H 15 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ethtool.h> 19 #include <linux/if_vlan.h> 20 #include <linux/timer.h> 21 #include <linux/mdio.h> 22 #include <linux/list.h> 23 #include <linux/pci.h> 24 #include <linux/device.h> 25 #include <linux/highmem.h> 26 #include <linux/workqueue.h> 27 #include <linux/mutex.h> 28 #include <linux/rwsem.h> 29 #include <linux/vmalloc.h> 30 #include <linux/i2c.h> 31 #include <linux/mtd/mtd.h> 32 #include <net/busy_poll.h> 33 34 #include "enum.h" 35 #include "bitfield.h" 36 #include "filter.h" 37 38 /************************************************************************** 39 * 40 * Build definitions 41 * 42 **************************************************************************/ 43 44 #define EF4_DRIVER_VERSION "4.1" 45 46 #ifdef DEBUG 47 #define EF4_BUG_ON_PARANOID(x) BUG_ON(x) 48 #define EF4_WARN_ON_PARANOID(x) WARN_ON(x) 49 #else 50 #define EF4_BUG_ON_PARANOID(x) do {} while (0) 51 #define EF4_WARN_ON_PARANOID(x) do {} while (0) 52 #endif 53 54 /************************************************************************** 55 * 56 * Efx data structures 57 * 58 **************************************************************************/ 59 60 #define EF4_MAX_CHANNELS 32U 61 #define EF4_MAX_RX_QUEUES EF4_MAX_CHANNELS 62 #define EF4_EXTRA_CHANNEL_IOV 0 63 #define EF4_EXTRA_CHANNEL_PTP 1 64 #define EF4_MAX_EXTRA_CHANNELS 2U 65 66 /* Checksum generation is a per-queue option in hardware, so each 67 * queue visible to the networking core is backed by two hardware TX 68 * queues. */ 69 #define EF4_MAX_TX_TC 2 70 #define EF4_MAX_CORE_TX_QUEUES (EF4_MAX_TX_TC * EF4_MAX_CHANNELS) 71 #define EF4_TXQ_TYPE_OFFLOAD 1 /* flag */ 72 #define EF4_TXQ_TYPE_HIGHPRI 2 /* flag */ 73 #define EF4_TXQ_TYPES 4 74 #define EF4_MAX_TX_QUEUES (EF4_TXQ_TYPES * EF4_MAX_CHANNELS) 75 76 /* Maximum possible MTU the driver supports */ 77 #define EF4_MAX_MTU (9 * 1024) 78 79 /* Minimum MTU, from RFC791 (IP) */ 80 #define EF4_MIN_MTU 68 81 82 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page, 83 * and should be a multiple of the cache line size. 84 */ 85 #define EF4_RX_USR_BUF_SIZE (2048 - 256) 86 87 /* If possible, we should ensure cache line alignment at start and end 88 * of every buffer. Otherwise, we just need to ensure 4-byte 89 * alignment of the network header. 90 */ 91 #if NET_IP_ALIGN == 0 92 #define EF4_RX_BUF_ALIGNMENT L1_CACHE_BYTES 93 #else 94 #define EF4_RX_BUF_ALIGNMENT 4 95 #endif 96 97 struct ef4_self_tests; 98 99 /** 100 * struct ef4_buffer - A general-purpose DMA buffer 101 * @addr: host base address of the buffer 102 * @dma_addr: DMA base address of the buffer 103 * @len: Buffer length, in bytes 104 * 105 * The NIC uses these buffers for its interrupt status registers and 106 * MAC stats dumps. 107 */ 108 struct ef4_buffer { 109 void *addr; 110 dma_addr_t dma_addr; 111 unsigned int len; 112 }; 113 114 /** 115 * struct ef4_special_buffer - DMA buffer entered into buffer table 116 * @buf: Standard &struct ef4_buffer 117 * @index: Buffer index within controller;s buffer table 118 * @entries: Number of buffer table entries 119 * 120 * The NIC has a buffer table that maps buffers of size %EF4_BUF_SIZE. 121 * Event and descriptor rings are addressed via one or more buffer 122 * table entries (and so can be physically non-contiguous, although we 123 * currently do not take advantage of that). On Falcon and Siena we 124 * have to take care of allocating and initialising the entries 125 * ourselves. On later hardware this is managed by the firmware and 126 * @index and @entries are left as 0. 127 */ 128 struct ef4_special_buffer { 129 struct ef4_buffer buf; 130 unsigned int index; 131 unsigned int entries; 132 }; 133 134 /** 135 * struct ef4_tx_buffer - buffer state for a TX descriptor 136 * @skb: When @flags & %EF4_TX_BUF_SKB, the associated socket buffer to be 137 * freed when descriptor completes 138 * @option: When @flags & %EF4_TX_BUF_OPTION, a NIC-specific option descriptor. 139 * @dma_addr: DMA address of the fragment. 140 * @flags: Flags for allocation and DMA mapping type 141 * @len: Length of this fragment. 142 * This field is zero when the queue slot is empty. 143 * @unmap_len: Length of this fragment to unmap 144 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping. 145 * Only valid if @unmap_len != 0. 146 */ 147 struct ef4_tx_buffer { 148 const struct sk_buff *skb; 149 union { 150 ef4_qword_t option; 151 dma_addr_t dma_addr; 152 }; 153 unsigned short flags; 154 unsigned short len; 155 unsigned short unmap_len; 156 unsigned short dma_offset; 157 }; 158 #define EF4_TX_BUF_CONT 1 /* not last descriptor of packet */ 159 #define EF4_TX_BUF_SKB 2 /* buffer is last part of skb */ 160 #define EF4_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */ 161 #define EF4_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */ 162 163 /** 164 * struct ef4_tx_queue - An Efx TX queue 165 * 166 * This is a ring buffer of TX fragments. 167 * Since the TX completion path always executes on the same 168 * CPU and the xmit path can operate on different CPUs, 169 * performance is increased by ensuring that the completion 170 * path and the xmit path operate on different cache lines. 171 * This is particularly important if the xmit path is always 172 * executing on one CPU which is different from the completion 173 * path. There is also a cache line for members which are 174 * read but not written on the fast path. 175 * 176 * @efx: The associated Efx NIC 177 * @queue: DMA queue number 178 * @channel: The associated channel 179 * @core_txq: The networking core TX queue structure 180 * @buffer: The software buffer ring 181 * @cb_page: Array of pages of copy buffers. Carved up according to 182 * %EF4_TX_CB_ORDER into %EF4_TX_CB_SIZE-sized chunks. 183 * @txd: The hardware descriptor ring 184 * @ptr_mask: The size of the ring minus 1. 185 * @initialised: Has hardware queue been initialised? 186 * @tx_min_size: Minimum transmit size for this queue. Depends on HW. 187 * @read_count: Current read pointer. 188 * This is the number of buffers that have been removed from both rings. 189 * @old_write_count: The value of @write_count when last checked. 190 * This is here for performance reasons. The xmit path will 191 * only get the up-to-date value of @write_count if this 192 * variable indicates that the queue is empty. This is to 193 * avoid cache-line ping-pong between the xmit path and the 194 * completion path. 195 * @merge_events: Number of TX merged completion events 196 * @insert_count: Current insert pointer 197 * This is the number of buffers that have been added to the 198 * software ring. 199 * @write_count: Current write pointer 200 * This is the number of buffers that have been added to the 201 * hardware ring. 202 * @old_read_count: The value of read_count when last checked. 203 * This is here for performance reasons. The xmit path will 204 * only get the up-to-date value of read_count if this 205 * variable indicates that the queue is full. This is to 206 * avoid cache-line ping-pong between the xmit path and the 207 * completion path. 208 * @pushes: Number of times the TX push feature has been used 209 * @xmit_more_available: Are any packets waiting to be pushed to the NIC 210 * @cb_packets: Number of times the TX copybreak feature has been used 211 * @empty_read_count: If the completion path has seen the queue as empty 212 * and the transmission path has not yet checked this, the value of 213 * @read_count bitwise-added to %EF4_EMPTY_COUNT_VALID; otherwise 0. 214 */ 215 struct ef4_tx_queue { 216 /* Members which don't change on the fast path */ 217 struct ef4_nic *efx ____cacheline_aligned_in_smp; 218 unsigned queue; 219 struct ef4_channel *channel; 220 struct netdev_queue *core_txq; 221 struct ef4_tx_buffer *buffer; 222 struct ef4_buffer *cb_page; 223 struct ef4_special_buffer txd; 224 unsigned int ptr_mask; 225 bool initialised; 226 unsigned int tx_min_size; 227 228 /* Function pointers used in the fast path. */ 229 int (*handle_tso)(struct ef4_tx_queue*, struct sk_buff*, bool *); 230 231 /* Members used mainly on the completion path */ 232 unsigned int read_count ____cacheline_aligned_in_smp; 233 unsigned int old_write_count; 234 unsigned int merge_events; 235 unsigned int bytes_compl; 236 unsigned int pkts_compl; 237 238 /* Members used only on the xmit path */ 239 unsigned int insert_count ____cacheline_aligned_in_smp; 240 unsigned int write_count; 241 unsigned int old_read_count; 242 unsigned int pushes; 243 bool xmit_more_available; 244 unsigned int cb_packets; 245 /* Statistics to supplement MAC stats */ 246 unsigned long tx_packets; 247 248 /* Members shared between paths and sometimes updated */ 249 unsigned int empty_read_count ____cacheline_aligned_in_smp; 250 #define EF4_EMPTY_COUNT_VALID 0x80000000 251 atomic_t flush_outstanding; 252 }; 253 254 #define EF4_TX_CB_ORDER 7 255 #define EF4_TX_CB_SIZE (1 << EF4_TX_CB_ORDER) - NET_IP_ALIGN 256 257 /** 258 * struct ef4_rx_buffer - An Efx RX data buffer 259 * @dma_addr: DMA base address of the buffer 260 * @page: The associated page buffer. 261 * Will be %NULL if the buffer slot is currently free. 262 * @page_offset: If pending: offset in @page of DMA base address. 263 * If completed: offset in @page of Ethernet header. 264 * @len: If pending: length for DMA descriptor. 265 * If completed: received length, excluding hash prefix. 266 * @flags: Flags for buffer and packet state. These are only set on the 267 * first buffer of a scattered packet. 268 */ 269 struct ef4_rx_buffer { 270 dma_addr_t dma_addr; 271 struct page *page; 272 u16 page_offset; 273 u16 len; 274 u16 flags; 275 }; 276 #define EF4_RX_BUF_LAST_IN_PAGE 0x0001 277 #define EF4_RX_PKT_CSUMMED 0x0002 278 #define EF4_RX_PKT_DISCARD 0x0004 279 #define EF4_RX_PKT_TCP 0x0040 280 #define EF4_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */ 281 282 /** 283 * struct ef4_rx_page_state - Page-based rx buffer state 284 * 285 * Inserted at the start of every page allocated for receive buffers. 286 * Used to facilitate sharing dma mappings between recycled rx buffers 287 * and those passed up to the kernel. 288 * 289 * @dma_addr: The dma address of this page. 290 */ 291 struct ef4_rx_page_state { 292 dma_addr_t dma_addr; 293 294 unsigned int __pad[0] ____cacheline_aligned; 295 }; 296 297 /** 298 * struct ef4_rx_queue - An Efx RX queue 299 * @efx: The associated Efx NIC 300 * @core_index: Index of network core RX queue. Will be >= 0 iff this 301 * is associated with a real RX queue. 302 * @buffer: The software buffer ring 303 * @rxd: The hardware descriptor ring 304 * @ptr_mask: The size of the ring minus 1. 305 * @refill_enabled: Enable refill whenever fill level is low 306 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as 307 * @rxq_flush_pending. 308 * @added_count: Number of buffers added to the receive queue. 309 * @notified_count: Number of buffers given to NIC (<= @added_count). 310 * @removed_count: Number of buffers removed from the receive queue. 311 * @scatter_n: Used by NIC specific receive code. 312 * @scatter_len: Used by NIC specific receive code. 313 * @page_ring: The ring to store DMA mapped pages for reuse. 314 * @page_add: Counter to calculate the write pointer for the recycle ring. 315 * @page_remove: Counter to calculate the read pointer for the recycle ring. 316 * @page_recycle_count: The number of pages that have been recycled. 317 * @page_recycle_failed: The number of pages that couldn't be recycled because 318 * the kernel still held a reference to them. 319 * @page_recycle_full: The number of pages that were released because the 320 * recycle ring was full. 321 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1. 322 * @max_fill: RX descriptor maximum fill level (<= ring size) 323 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill 324 * (<= @max_fill) 325 * @min_fill: RX descriptor minimum non-zero fill level. 326 * This records the minimum fill level observed when a ring 327 * refill was triggered. 328 * @recycle_count: RX buffer recycle counter. 329 * @slow_fill: Timer used to defer ef4_nic_generate_fill_event(). 330 */ 331 struct ef4_rx_queue { 332 struct ef4_nic *efx; 333 int core_index; 334 struct ef4_rx_buffer *buffer; 335 struct ef4_special_buffer rxd; 336 unsigned int ptr_mask; 337 bool refill_enabled; 338 bool flush_pending; 339 340 unsigned int added_count; 341 unsigned int notified_count; 342 unsigned int removed_count; 343 unsigned int scatter_n; 344 unsigned int scatter_len; 345 struct page **page_ring; 346 unsigned int page_add; 347 unsigned int page_remove; 348 unsigned int page_recycle_count; 349 unsigned int page_recycle_failed; 350 unsigned int page_recycle_full; 351 unsigned int page_ptr_mask; 352 unsigned int max_fill; 353 unsigned int fast_fill_trigger; 354 unsigned int min_fill; 355 unsigned int min_overfill; 356 unsigned int recycle_count; 357 struct timer_list slow_fill; 358 unsigned int slow_fill_count; 359 /* Statistics to supplement MAC stats */ 360 unsigned long rx_packets; 361 }; 362 363 /** 364 * struct ef4_channel - An Efx channel 365 * 366 * A channel comprises an event queue, at least one TX queue, at least 367 * one RX queue, and an associated tasklet for processing the event 368 * queue. 369 * 370 * @efx: Associated Efx NIC 371 * @channel: Channel instance number 372 * @type: Channel type definition 373 * @eventq_init: Event queue initialised flag 374 * @enabled: Channel enabled indicator 375 * @irq: IRQ number (MSI and MSI-X only) 376 * @irq_moderation_us: IRQ moderation value (in microseconds) 377 * @napi_dev: Net device used with NAPI 378 * @napi_str: NAPI control structure 379 * @state: state for NAPI vs busy polling 380 * @state_lock: lock protecting @state 381 * @eventq: Event queue buffer 382 * @eventq_mask: Event queue pointer mask 383 * @eventq_read_ptr: Event queue read pointer 384 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel 385 * @irq_count: Number of IRQs since last adaptive moderation decision 386 * @irq_mod_score: IRQ moderation score 387 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS, 388 * indexed by filter ID 389 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors 390 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors 391 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors 392 * @n_rx_mcast_mismatch: Count of unmatched multicast frames 393 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors 394 * @n_rx_overlength: Count of RX_OVERLENGTH errors 395 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun 396 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to 397 * lack of descriptors 398 * @n_rx_merge_events: Number of RX merged completion events 399 * @n_rx_merge_packets: Number of RX packets completed by merged events 400 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by 401 * __ef4_rx_packet(), or zero if there is none 402 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered 403 * by __ef4_rx_packet(), if @rx_pkt_n_frags != 0 404 * @rx_queue: RX queue for this channel 405 * @tx_queue: TX queues for this channel 406 */ 407 struct ef4_channel { 408 struct ef4_nic *efx; 409 int channel; 410 const struct ef4_channel_type *type; 411 bool eventq_init; 412 bool enabled; 413 int irq; 414 unsigned int irq_moderation_us; 415 struct net_device *napi_dev; 416 struct napi_struct napi_str; 417 #ifdef CONFIG_NET_RX_BUSY_POLL 418 unsigned long busy_poll_state; 419 #endif 420 struct ef4_special_buffer eventq; 421 unsigned int eventq_mask; 422 unsigned int eventq_read_ptr; 423 int event_test_cpu; 424 425 unsigned int irq_count; 426 unsigned int irq_mod_score; 427 #ifdef CONFIG_RFS_ACCEL 428 unsigned int rfs_filters_added; 429 #define RPS_FLOW_ID_INVALID 0xFFFFFFFF 430 u32 *rps_flow_id; 431 #endif 432 433 unsigned n_rx_tobe_disc; 434 unsigned n_rx_ip_hdr_chksum_err; 435 unsigned n_rx_tcp_udp_chksum_err; 436 unsigned n_rx_mcast_mismatch; 437 unsigned n_rx_frm_trunc; 438 unsigned n_rx_overlength; 439 unsigned n_skbuff_leaks; 440 unsigned int n_rx_nodesc_trunc; 441 unsigned int n_rx_merge_events; 442 unsigned int n_rx_merge_packets; 443 444 unsigned int rx_pkt_n_frags; 445 unsigned int rx_pkt_index; 446 447 struct ef4_rx_queue rx_queue; 448 struct ef4_tx_queue tx_queue[EF4_TXQ_TYPES]; 449 }; 450 451 /** 452 * struct ef4_msi_context - Context for each MSI 453 * @efx: The associated NIC 454 * @index: Index of the channel/IRQ 455 * @name: Name of the channel/IRQ 456 * 457 * Unlike &struct ef4_channel, this is never reallocated and is always 458 * safe for the IRQ handler to access. 459 */ 460 struct ef4_msi_context { 461 struct ef4_nic *efx; 462 unsigned int index; 463 char name[IFNAMSIZ + 6]; 464 }; 465 466 /** 467 * struct ef4_channel_type - distinguishes traffic and extra channels 468 * @handle_no_channel: Handle failure to allocate an extra channel 469 * @pre_probe: Set up extra state prior to initialisation 470 * @post_remove: Tear down extra state after finalisation, if allocated. 471 * May be called on channels that have not been probed. 472 * @get_name: Generate the channel's name (used for its IRQ handler) 473 * @copy: Copy the channel state prior to reallocation. May be %NULL if 474 * reallocation is not supported. 475 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb() 476 * @keep_eventq: Flag for whether event queue should be kept initialised 477 * while the device is stopped 478 */ 479 struct ef4_channel_type { 480 void (*handle_no_channel)(struct ef4_nic *); 481 int (*pre_probe)(struct ef4_channel *); 482 void (*post_remove)(struct ef4_channel *); 483 void (*get_name)(struct ef4_channel *, char *buf, size_t len); 484 struct ef4_channel *(*copy)(const struct ef4_channel *); 485 bool (*receive_skb)(struct ef4_channel *, struct sk_buff *); 486 bool keep_eventq; 487 }; 488 489 enum ef4_led_mode { 490 EF4_LED_OFF = 0, 491 EF4_LED_ON = 1, 492 EF4_LED_DEFAULT = 2 493 }; 494 495 #define STRING_TABLE_LOOKUP(val, member) \ 496 ((val) < member ## _max) ? member ## _names[val] : "(invalid)" 497 498 extern const char *const ef4_loopback_mode_names[]; 499 extern const unsigned int ef4_loopback_mode_max; 500 #define LOOPBACK_MODE(efx) \ 501 STRING_TABLE_LOOKUP((efx)->loopback_mode, ef4_loopback_mode) 502 503 extern const char *const ef4_reset_type_names[]; 504 extern const unsigned int ef4_reset_type_max; 505 #define RESET_TYPE(type) \ 506 STRING_TABLE_LOOKUP(type, ef4_reset_type) 507 508 enum ef4_int_mode { 509 /* Be careful if altering to correct macro below */ 510 EF4_INT_MODE_MSIX = 0, 511 EF4_INT_MODE_MSI = 1, 512 EF4_INT_MODE_LEGACY = 2, 513 EF4_INT_MODE_MAX /* Insert any new items before this */ 514 }; 515 #define EF4_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EF4_INT_MODE_MSI) 516 517 enum nic_state { 518 STATE_UNINIT = 0, /* device being probed/removed or is frozen */ 519 STATE_READY = 1, /* hardware ready and netdev registered */ 520 STATE_DISABLED = 2, /* device disabled due to hardware errors */ 521 STATE_RECOVERY = 3, /* device recovering from PCI error */ 522 }; 523 524 /* Forward declaration */ 525 struct ef4_nic; 526 527 /* Pseudo bit-mask flow control field */ 528 #define EF4_FC_RX FLOW_CTRL_RX 529 #define EF4_FC_TX FLOW_CTRL_TX 530 #define EF4_FC_AUTO 4 531 532 /** 533 * struct ef4_link_state - Current state of the link 534 * @up: Link is up 535 * @fd: Link is full-duplex 536 * @fc: Actual flow control flags 537 * @speed: Link speed (Mbps) 538 */ 539 struct ef4_link_state { 540 bool up; 541 bool fd; 542 u8 fc; 543 unsigned int speed; 544 }; 545 546 static inline bool ef4_link_state_equal(const struct ef4_link_state *left, 547 const struct ef4_link_state *right) 548 { 549 return left->up == right->up && left->fd == right->fd && 550 left->fc == right->fc && left->speed == right->speed; 551 } 552 553 /** 554 * struct ef4_phy_operations - Efx PHY operations table 555 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, 556 * efx->loopback_modes. 557 * @init: Initialise PHY 558 * @fini: Shut down PHY 559 * @reconfigure: Reconfigure PHY (e.g. for new link parameters) 560 * @poll: Update @link_state and report whether it changed. 561 * Serialised by the mac_lock. 562 * @get_link_ksettings: Get ethtool settings. Serialised by the mac_lock. 563 * @set_link_ksettings: Set ethtool settings. Serialised by the mac_lock. 564 * @set_npage_adv: Set abilities advertised in (Extended) Next Page 565 * (only needed where AN bit is set in mmds) 566 * @test_alive: Test that PHY is 'alive' (online) 567 * @test_name: Get the name of a PHY-specific test/result 568 * @run_tests: Run tests and record results as appropriate (offline). 569 * Flags are the ethtool tests flags. 570 */ 571 struct ef4_phy_operations { 572 int (*probe) (struct ef4_nic *efx); 573 int (*init) (struct ef4_nic *efx); 574 void (*fini) (struct ef4_nic *efx); 575 void (*remove) (struct ef4_nic *efx); 576 int (*reconfigure) (struct ef4_nic *efx); 577 bool (*poll) (struct ef4_nic *efx); 578 void (*get_link_ksettings)(struct ef4_nic *efx, 579 struct ethtool_link_ksettings *cmd); 580 int (*set_link_ksettings)(struct ef4_nic *efx, 581 const struct ethtool_link_ksettings *cmd); 582 void (*set_npage_adv) (struct ef4_nic *efx, u32); 583 int (*test_alive) (struct ef4_nic *efx); 584 const char *(*test_name) (struct ef4_nic *efx, unsigned int index); 585 int (*run_tests) (struct ef4_nic *efx, int *results, unsigned flags); 586 int (*get_module_eeprom) (struct ef4_nic *efx, 587 struct ethtool_eeprom *ee, 588 u8 *data); 589 int (*get_module_info) (struct ef4_nic *efx, 590 struct ethtool_modinfo *modinfo); 591 }; 592 593 /** 594 * enum ef4_phy_mode - PHY operating mode flags 595 * @PHY_MODE_NORMAL: on and should pass traffic 596 * @PHY_MODE_TX_DISABLED: on with TX disabled 597 * @PHY_MODE_LOW_POWER: set to low power through MDIO 598 * @PHY_MODE_OFF: switched off through external control 599 * @PHY_MODE_SPECIAL: on but will not pass traffic 600 */ 601 enum ef4_phy_mode { 602 PHY_MODE_NORMAL = 0, 603 PHY_MODE_TX_DISABLED = 1, 604 PHY_MODE_LOW_POWER = 2, 605 PHY_MODE_OFF = 4, 606 PHY_MODE_SPECIAL = 8, 607 }; 608 609 static inline bool ef4_phy_mode_disabled(enum ef4_phy_mode mode) 610 { 611 return !!(mode & ~PHY_MODE_TX_DISABLED); 612 } 613 614 /** 615 * struct ef4_hw_stat_desc - Description of a hardware statistic 616 * @name: Name of the statistic as visible through ethtool, or %NULL if 617 * it should not be exposed 618 * @dma_width: Width in bits (0 for non-DMA statistics) 619 * @offset: Offset within stats (ignored for non-DMA statistics) 620 */ 621 struct ef4_hw_stat_desc { 622 const char *name; 623 u16 dma_width; 624 u16 offset; 625 }; 626 627 /* Number of bits used in a multicast filter hash address */ 628 #define EF4_MCAST_HASH_BITS 8 629 630 /* Number of (single-bit) entries in a multicast filter hash */ 631 #define EF4_MCAST_HASH_ENTRIES (1 << EF4_MCAST_HASH_BITS) 632 633 /* An Efx multicast filter hash */ 634 union ef4_multicast_hash { 635 u8 byte[EF4_MCAST_HASH_ENTRIES / 8]; 636 ef4_oword_t oword[EF4_MCAST_HASH_ENTRIES / sizeof(ef4_oword_t) / 8]; 637 }; 638 639 /** 640 * struct ef4_nic - an Efx NIC 641 * @name: Device name (net device name or bus id before net device registered) 642 * @pci_dev: The PCI device 643 * @node: List node for maintaning primary/secondary function lists 644 * @primary: &struct ef4_nic instance for the primary function of this 645 * controller. May be the same structure, and may be %NULL if no 646 * primary function is bound. Serialised by rtnl_lock. 647 * @secondary_list: List of &struct ef4_nic instances for the secondary PCI 648 * functions of the controller, if this is for the primary function. 649 * Serialised by rtnl_lock. 650 * @type: Controller type attributes 651 * @legacy_irq: IRQ number 652 * @workqueue: Workqueue for port reconfigures and the HW monitor. 653 * Work items do not hold and must not acquire RTNL. 654 * @workqueue_name: Name of workqueue 655 * @reset_work: Scheduled reset workitem 656 * @membase_phys: Memory BAR value as physical address 657 * @membase: Memory BAR value 658 * @interrupt_mode: Interrupt mode 659 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds 660 * @timer_max_ns: Interrupt timer maximum value, in nanoseconds 661 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues 662 * @irq_rx_mod_step_us: Step size for IRQ moderation for RX event queues 663 * @irq_rx_moderation_us: IRQ moderation time for RX event queues 664 * @msg_enable: Log message enable flags 665 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock. 666 * @reset_pending: Bitmask for pending resets 667 * @tx_queue: TX DMA queues 668 * @rx_queue: RX DMA queues 669 * @channel: Channels 670 * @msi_context: Context for each MSI 671 * @extra_channel_types: Types of extra (non-traffic) channels that 672 * should be allocated for this NIC 673 * @rxq_entries: Size of receive queues requested by user. 674 * @txq_entries: Size of transmit queues requested by user. 675 * @txq_stop_thresh: TX queue fill level at or above which we stop it. 676 * @txq_wake_thresh: TX queue fill level at or below which we wake it. 677 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches 678 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches 679 * @sram_lim_qw: Qword address limit of SRAM 680 * @next_buffer_table: First available buffer table id 681 * @n_channels: Number of channels in use 682 * @n_rx_channels: Number of channels used for RX (= number of RX queues) 683 * @n_tx_channels: Number of channels used for TX 684 * @rx_ip_align: RX DMA address offset to have IP header aligned in 685 * in accordance with NET_IP_ALIGN 686 * @rx_dma_len: Current maximum RX DMA length 687 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer 688 * @rx_buffer_truesize: Amortised allocation size of an RX buffer, 689 * for use in sk_buff::truesize 690 * @rx_prefix_size: Size of RX prefix before packet data 691 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data 692 * (valid only if @rx_prefix_size != 0; always negative) 693 * @rx_packet_len_offset: Offset of RX packet length from start of packet data 694 * (valid only for NICs that set %EF4_RX_PKT_PREFIX_LEN; always negative) 695 * @rx_packet_ts_offset: Offset of timestamp from start of packet data 696 * (valid only if channel->sync_timestamps_enabled; always negative) 697 * @rx_hash_key: Toeplitz hash key for RSS 698 * @rx_indir_table: Indirection table for RSS 699 * @rx_scatter: Scatter mode enabled for receives 700 * @int_error_count: Number of internal errors seen recently 701 * @int_error_expire: Time at which error count will be expired 702 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will 703 * acknowledge but do nothing else. 704 * @irq_status: Interrupt status buffer 705 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 706 * @irq_level: IRQ level/index for IRQs not triggered by an event queue 707 * @selftest_work: Work item for asynchronous self-test 708 * @mtd_list: List of MTDs attached to the NIC 709 * @nic_data: Hardware dependent state 710 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, 711 * ef4_monitor() and ef4_reconfigure_port() 712 * @port_enabled: Port enabled indicator. 713 * Serialises ef4_stop_all(), ef4_start_all(), ef4_monitor() and 714 * ef4_mac_work() with kernel interfaces. Safe to read under any 715 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must 716 * be held to modify it. 717 * @port_initialized: Port initialized? 718 * @net_dev: Operating system network device. Consider holding the rtnl lock 719 * @fixed_features: Features which cannot be turned off 720 * @stats_buffer: DMA buffer for statistics 721 * @phy_type: PHY type 722 * @phy_op: PHY interface 723 * @phy_data: PHY private data (including PHY-specific stats) 724 * @mdio: PHY MDIO interface 725 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 726 * @link_advertising: Autonegotiation advertising flags 727 * @link_state: Current state of the link 728 * @n_link_state_changes: Number of times the link has changed state 729 * @unicast_filter: Flag for Falcon-arch simple unicast filter. 730 * Protected by @mac_lock. 731 * @multicast_hash: Multicast hash table for Falcon-arch. 732 * Protected by @mac_lock. 733 * @wanted_fc: Wanted flow control flags 734 * @fc_disable: When non-zero flow control is disabled. Typically used to 735 * ensure that network back pressure doesn't delay dma queue flushes. 736 * Serialised by the rtnl lock. 737 * @mac_work: Work item for changing MAC promiscuity and multicast hash 738 * @loopback_mode: Loopback status 739 * @loopback_modes: Supported loopback mode bitmask 740 * @loopback_selftest: Offline self-test private state 741 * @filter_sem: Filter table rw_semaphore, for freeing the table 742 * @filter_lock: Filter table lock, for mere content changes 743 * @filter_state: Architecture-dependent filter table state 744 * @rps_expire_channel: Next channel to check for expiry 745 * @rps_expire_index: Next index to check for expiry in 746 * @rps_expire_channel's @rps_flow_id 747 * @active_queues: Count of RX and TX queues that haven't been flushed and drained. 748 * @rxq_flush_pending: Count of number of receive queues that need to be flushed. 749 * Decremented when the ef4_flush_rx_queue() is called. 750 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet 751 * completed (either success or failure). Not used when MCDI is used to 752 * flush receive queues. 753 * @flush_wq: wait queue used by ef4_nic_flush_queues() to wait for flush completions. 754 * @vpd_sn: Serial number read from VPD 755 * @monitor_work: Hardware monitor workitem 756 * @biu_lock: BIU (bus interface unit) lock 757 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This 758 * field is used by ef4_test_interrupts() to verify that an 759 * interrupt has occurred. 760 * @stats_lock: Statistics update lock. Must be held when calling 761 * ef4_nic_type::{update,start,stop}_stats. 762 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb 763 * 764 * This is stored in the private area of the &struct net_device. 765 */ 766 struct ef4_nic { 767 /* The following fields should be written very rarely */ 768 769 char name[IFNAMSIZ]; 770 struct list_head node; 771 struct ef4_nic *primary; 772 struct list_head secondary_list; 773 struct pci_dev *pci_dev; 774 unsigned int port_num; 775 const struct ef4_nic_type *type; 776 int legacy_irq; 777 bool eeh_disabled_legacy_irq; 778 struct workqueue_struct *workqueue; 779 char workqueue_name[16]; 780 struct work_struct reset_work; 781 resource_size_t membase_phys; 782 void __iomem *membase; 783 784 enum ef4_int_mode interrupt_mode; 785 unsigned int timer_quantum_ns; 786 unsigned int timer_max_ns; 787 bool irq_rx_adaptive; 788 unsigned int irq_mod_step_us; 789 unsigned int irq_rx_moderation_us; 790 u32 msg_enable; 791 792 enum nic_state state; 793 unsigned long reset_pending; 794 795 struct ef4_channel *channel[EF4_MAX_CHANNELS]; 796 struct ef4_msi_context msi_context[EF4_MAX_CHANNELS]; 797 const struct ef4_channel_type * 798 extra_channel_type[EF4_MAX_EXTRA_CHANNELS]; 799 800 unsigned rxq_entries; 801 unsigned txq_entries; 802 unsigned int txq_stop_thresh; 803 unsigned int txq_wake_thresh; 804 805 unsigned tx_dc_base; 806 unsigned rx_dc_base; 807 unsigned sram_lim_qw; 808 unsigned next_buffer_table; 809 810 unsigned int max_channels; 811 unsigned int max_tx_channels; 812 unsigned n_channels; 813 unsigned n_rx_channels; 814 unsigned rss_spread; 815 unsigned tx_channel_offset; 816 unsigned n_tx_channels; 817 unsigned int rx_ip_align; 818 unsigned int rx_dma_len; 819 unsigned int rx_buffer_order; 820 unsigned int rx_buffer_truesize; 821 unsigned int rx_page_buf_step; 822 unsigned int rx_bufs_per_page; 823 unsigned int rx_pages_per_batch; 824 unsigned int rx_prefix_size; 825 int rx_packet_hash_offset; 826 int rx_packet_len_offset; 827 int rx_packet_ts_offset; 828 u8 rx_hash_key[40]; 829 u32 rx_indir_table[128]; 830 bool rx_scatter; 831 832 unsigned int_error_count; 833 unsigned long int_error_expire; 834 835 bool irq_soft_enabled; 836 struct ef4_buffer irq_status; 837 unsigned irq_zero_count; 838 unsigned irq_level; 839 struct delayed_work selftest_work; 840 841 #ifdef CONFIG_SFC_FALCON_MTD 842 struct list_head mtd_list; 843 #endif 844 845 void *nic_data; 846 847 struct mutex mac_lock; 848 struct work_struct mac_work; 849 bool port_enabled; 850 851 bool mc_bist_for_other_fn; 852 bool port_initialized; 853 struct net_device *net_dev; 854 855 netdev_features_t fixed_features; 856 857 struct ef4_buffer stats_buffer; 858 u64 rx_nodesc_drops_total; 859 u64 rx_nodesc_drops_while_down; 860 bool rx_nodesc_drops_prev_state; 861 862 unsigned int phy_type; 863 const struct ef4_phy_operations *phy_op; 864 void *phy_data; 865 struct mdio_if_info mdio; 866 enum ef4_phy_mode phy_mode; 867 868 u32 link_advertising; 869 struct ef4_link_state link_state; 870 unsigned int n_link_state_changes; 871 872 bool unicast_filter; 873 union ef4_multicast_hash multicast_hash; 874 u8 wanted_fc; 875 unsigned fc_disable; 876 877 atomic_t rx_reset; 878 enum ef4_loopback_mode loopback_mode; 879 u64 loopback_modes; 880 881 void *loopback_selftest; 882 883 struct rw_semaphore filter_sem; 884 spinlock_t filter_lock; 885 void *filter_state; 886 #ifdef CONFIG_RFS_ACCEL 887 unsigned int rps_expire_channel; 888 unsigned int rps_expire_index; 889 #endif 890 891 atomic_t active_queues; 892 atomic_t rxq_flush_pending; 893 atomic_t rxq_flush_outstanding; 894 wait_queue_head_t flush_wq; 895 896 char *vpd_sn; 897 898 /* The following fields may be written more often */ 899 900 struct delayed_work monitor_work ____cacheline_aligned_in_smp; 901 spinlock_t biu_lock; 902 int last_irq_cpu; 903 spinlock_t stats_lock; 904 atomic_t n_rx_noskb_drops; 905 }; 906 907 static inline int ef4_dev_registered(struct ef4_nic *efx) 908 { 909 return efx->net_dev->reg_state == NETREG_REGISTERED; 910 } 911 912 static inline unsigned int ef4_port_num(struct ef4_nic *efx) 913 { 914 return efx->port_num; 915 } 916 917 struct ef4_mtd_partition { 918 struct list_head node; 919 struct mtd_info mtd; 920 const char *dev_type_name; 921 const char *type_name; 922 char name[IFNAMSIZ + 20]; 923 }; 924 925 /** 926 * struct ef4_nic_type - Efx device type definition 927 * @mem_bar: Get the memory BAR 928 * @mem_map_size: Get memory BAR mapped size 929 * @probe: Probe the controller 930 * @remove: Free resources allocated by probe() 931 * @init: Initialise the controller 932 * @dimension_resources: Dimension controller resources (buffer table, 933 * and VIs once the available interrupt resources are clear) 934 * @fini: Shut down the controller 935 * @monitor: Periodic function for polling link state and hardware monitor 936 * @map_reset_reason: Map ethtool reset reason to a reset method 937 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible 938 * @reset: Reset the controller hardware and possibly the PHY. This will 939 * be called while the controller is uninitialised. 940 * @probe_port: Probe the MAC and PHY 941 * @remove_port: Free resources allocated by probe_port() 942 * @handle_global_event: Handle a "global" event (may be %NULL) 943 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues) 944 * @prepare_flush: Prepare the hardware for flushing the DMA queues 945 * (for Falcon architecture) 946 * @finish_flush: Clean up after flushing the DMA queues (for Falcon 947 * architecture) 948 * @prepare_flr: Prepare for an FLR 949 * @finish_flr: Clean up after an FLR 950 * @describe_stats: Describe statistics for ethtool 951 * @update_stats: Update statistics not provided by event handling. 952 * Either argument may be %NULL. 953 * @start_stats: Start the regular fetching of statistics 954 * @pull_stats: Pull stats from the NIC and wait until they arrive. 955 * @stop_stats: Stop the regular fetching of statistics 956 * @set_id_led: Set state of identifying LED or revert to automatic function 957 * @push_irq_moderation: Apply interrupt moderation value 958 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY 959 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL) 960 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings 961 * to the hardware. Serialised by the mac_lock. 962 * @check_mac_fault: Check MAC fault state. True if fault present. 963 * @get_wol: Get WoL configuration from driver state 964 * @set_wol: Push WoL configuration to the NIC 965 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) 966 * @test_chip: Test registers. May use ef4_farch_test_registers(), and is 967 * expected to reset the NIC. 968 * @test_nvram: Test validity of NVRAM contents 969 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must 970 * be separately enabled after this. 971 * @irq_test_generate: Generate a test IRQ 972 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event 973 * queue must be separately disabled before this. 974 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is 975 * a pointer to the &struct ef4_msi_context for the channel. 976 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument 977 * is a pointer to the &struct ef4_nic. 978 * @tx_probe: Allocate resources for TX queue 979 * @tx_init: Initialise TX queue on the NIC 980 * @tx_remove: Free resources for TX queue 981 * @tx_write: Write TX descriptors and doorbell 982 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC 983 * @rx_probe: Allocate resources for RX queue 984 * @rx_init: Initialise RX queue on the NIC 985 * @rx_remove: Free resources for RX queue 986 * @rx_write: Write RX descriptors and doorbell 987 * @rx_defer_refill: Generate a refill reminder event 988 * @ev_probe: Allocate resources for event queue 989 * @ev_init: Initialise event queue on the NIC 990 * @ev_fini: Deinitialise event queue on the NIC 991 * @ev_remove: Free resources for event queue 992 * @ev_process: Process events for a queue, up to the given NAPI quota 993 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ 994 * @ev_test_generate: Generate a test event 995 * @filter_table_probe: Probe filter capabilities and set up filter software state 996 * @filter_table_restore: Restore filters removed from hardware 997 * @filter_table_remove: Remove filters from hardware and tear down software state 998 * @filter_update_rx_scatter: Update filters after change to rx scatter setting 999 * @filter_insert: add or replace a filter 1000 * @filter_remove_safe: remove a filter by ID, carefully 1001 * @filter_get_safe: retrieve a filter by ID, carefully 1002 * @filter_clear_rx: Remove all RX filters whose priority is less than or 1003 * equal to the given priority and is not %EF4_FILTER_PRI_AUTO 1004 * @filter_count_rx_used: Get the number of filters in use at a given priority 1005 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1 1006 * @filter_get_rx_ids: Get list of RX filters at a given priority 1007 * @filter_rfs_insert: Add or replace a filter for RFS. This must be 1008 * atomic. The hardware change may be asynchronous but should 1009 * not be delayed for long. It may fail if this can't be done 1010 * atomically. 1011 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS. 1012 * This must check whether the specified table entry is used by RFS 1013 * and that rps_may_expire_flow() returns true for it. 1014 * @mtd_probe: Probe and add MTD partitions associated with this net device, 1015 * using ef4_mtd_add() 1016 * @mtd_rename: Set an MTD partition name using the net device name 1017 * @mtd_read: Read from an MTD partition 1018 * @mtd_erase: Erase part of an MTD partition 1019 * @mtd_write: Write to an MTD partition 1020 * @mtd_sync: Wait for write-back to complete on MTD partition. This 1021 * also notifies the driver that a writer has finished using this 1022 * partition. 1023 * @set_mac_address: Set the MAC address of the device 1024 * @revision: Hardware architecture revision 1025 * @txd_ptr_tbl_base: TX descriptor ring base address 1026 * @rxd_ptr_tbl_base: RX descriptor ring base address 1027 * @buf_tbl_base: Buffer table base address 1028 * @evq_ptr_tbl_base: Event queue pointer table base address 1029 * @evq_rptr_tbl_base: Event queue read-pointer table base address 1030 * @max_dma_mask: Maximum possible DMA mask 1031 * @rx_prefix_size: Size of RX prefix before packet data 1032 * @rx_hash_offset: Offset of RX flow hash within prefix 1033 * @rx_ts_offset: Offset of timestamp within prefix 1034 * @rx_buffer_padding: Size of padding at end of RX packet 1035 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers 1036 * @always_rx_scatter: NIC will always scatter packets to multiple buffers 1037 * @max_interrupt_mode: Highest capability interrupt mode supported 1038 * from &enum ef4_init_mode. 1039 * @timer_period_max: Maximum period of interrupt timer (in ticks) 1040 * @offload_features: net_device feature flags for protocol offload 1041 * features implemented in hardware 1042 */ 1043 struct ef4_nic_type { 1044 unsigned int mem_bar; 1045 unsigned int (*mem_map_size)(struct ef4_nic *efx); 1046 int (*probe)(struct ef4_nic *efx); 1047 void (*remove)(struct ef4_nic *efx); 1048 int (*init)(struct ef4_nic *efx); 1049 int (*dimension_resources)(struct ef4_nic *efx); 1050 void (*fini)(struct ef4_nic *efx); 1051 void (*monitor)(struct ef4_nic *efx); 1052 enum reset_type (*map_reset_reason)(enum reset_type reason); 1053 int (*map_reset_flags)(u32 *flags); 1054 int (*reset)(struct ef4_nic *efx, enum reset_type method); 1055 int (*probe_port)(struct ef4_nic *efx); 1056 void (*remove_port)(struct ef4_nic *efx); 1057 bool (*handle_global_event)(struct ef4_channel *channel, ef4_qword_t *); 1058 int (*fini_dmaq)(struct ef4_nic *efx); 1059 void (*prepare_flush)(struct ef4_nic *efx); 1060 void (*finish_flush)(struct ef4_nic *efx); 1061 void (*prepare_flr)(struct ef4_nic *efx); 1062 void (*finish_flr)(struct ef4_nic *efx); 1063 size_t (*describe_stats)(struct ef4_nic *efx, u8 *names); 1064 size_t (*update_stats)(struct ef4_nic *efx, u64 *full_stats, 1065 struct rtnl_link_stats64 *core_stats); 1066 void (*start_stats)(struct ef4_nic *efx); 1067 void (*pull_stats)(struct ef4_nic *efx); 1068 void (*stop_stats)(struct ef4_nic *efx); 1069 void (*set_id_led)(struct ef4_nic *efx, enum ef4_led_mode mode); 1070 void (*push_irq_moderation)(struct ef4_channel *channel); 1071 int (*reconfigure_port)(struct ef4_nic *efx); 1072 void (*prepare_enable_fc_tx)(struct ef4_nic *efx); 1073 int (*reconfigure_mac)(struct ef4_nic *efx); 1074 bool (*check_mac_fault)(struct ef4_nic *efx); 1075 void (*get_wol)(struct ef4_nic *efx, struct ethtool_wolinfo *wol); 1076 int (*set_wol)(struct ef4_nic *efx, u32 type); 1077 void (*resume_wol)(struct ef4_nic *efx); 1078 int (*test_chip)(struct ef4_nic *efx, struct ef4_self_tests *tests); 1079 int (*test_nvram)(struct ef4_nic *efx); 1080 void (*irq_enable_master)(struct ef4_nic *efx); 1081 int (*irq_test_generate)(struct ef4_nic *efx); 1082 void (*irq_disable_non_ev)(struct ef4_nic *efx); 1083 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id); 1084 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id); 1085 int (*tx_probe)(struct ef4_tx_queue *tx_queue); 1086 void (*tx_init)(struct ef4_tx_queue *tx_queue); 1087 void (*tx_remove)(struct ef4_tx_queue *tx_queue); 1088 void (*tx_write)(struct ef4_tx_queue *tx_queue); 1089 unsigned int (*tx_limit_len)(struct ef4_tx_queue *tx_queue, 1090 dma_addr_t dma_addr, unsigned int len); 1091 int (*rx_push_rss_config)(struct ef4_nic *efx, bool user, 1092 const u32 *rx_indir_table); 1093 int (*rx_probe)(struct ef4_rx_queue *rx_queue); 1094 void (*rx_init)(struct ef4_rx_queue *rx_queue); 1095 void (*rx_remove)(struct ef4_rx_queue *rx_queue); 1096 void (*rx_write)(struct ef4_rx_queue *rx_queue); 1097 void (*rx_defer_refill)(struct ef4_rx_queue *rx_queue); 1098 int (*ev_probe)(struct ef4_channel *channel); 1099 int (*ev_init)(struct ef4_channel *channel); 1100 void (*ev_fini)(struct ef4_channel *channel); 1101 void (*ev_remove)(struct ef4_channel *channel); 1102 int (*ev_process)(struct ef4_channel *channel, int quota); 1103 void (*ev_read_ack)(struct ef4_channel *channel); 1104 void (*ev_test_generate)(struct ef4_channel *channel); 1105 int (*filter_table_probe)(struct ef4_nic *efx); 1106 void (*filter_table_restore)(struct ef4_nic *efx); 1107 void (*filter_table_remove)(struct ef4_nic *efx); 1108 void (*filter_update_rx_scatter)(struct ef4_nic *efx); 1109 s32 (*filter_insert)(struct ef4_nic *efx, 1110 struct ef4_filter_spec *spec, bool replace); 1111 int (*filter_remove_safe)(struct ef4_nic *efx, 1112 enum ef4_filter_priority priority, 1113 u32 filter_id); 1114 int (*filter_get_safe)(struct ef4_nic *efx, 1115 enum ef4_filter_priority priority, 1116 u32 filter_id, struct ef4_filter_spec *); 1117 int (*filter_clear_rx)(struct ef4_nic *efx, 1118 enum ef4_filter_priority priority); 1119 u32 (*filter_count_rx_used)(struct ef4_nic *efx, 1120 enum ef4_filter_priority priority); 1121 u32 (*filter_get_rx_id_limit)(struct ef4_nic *efx); 1122 s32 (*filter_get_rx_ids)(struct ef4_nic *efx, 1123 enum ef4_filter_priority priority, 1124 u32 *buf, u32 size); 1125 #ifdef CONFIG_RFS_ACCEL 1126 s32 (*filter_rfs_insert)(struct ef4_nic *efx, 1127 struct ef4_filter_spec *spec); 1128 bool (*filter_rfs_expire_one)(struct ef4_nic *efx, u32 flow_id, 1129 unsigned int index); 1130 #endif 1131 #ifdef CONFIG_SFC_FALCON_MTD 1132 int (*mtd_probe)(struct ef4_nic *efx); 1133 void (*mtd_rename)(struct ef4_mtd_partition *part); 1134 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len, 1135 size_t *retlen, u8 *buffer); 1136 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len); 1137 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len, 1138 size_t *retlen, const u8 *buffer); 1139 int (*mtd_sync)(struct mtd_info *mtd); 1140 #endif 1141 int (*get_mac_address)(struct ef4_nic *efx, unsigned char *perm_addr); 1142 int (*set_mac_address)(struct ef4_nic *efx); 1143 1144 int revision; 1145 unsigned int txd_ptr_tbl_base; 1146 unsigned int rxd_ptr_tbl_base; 1147 unsigned int buf_tbl_base; 1148 unsigned int evq_ptr_tbl_base; 1149 unsigned int evq_rptr_tbl_base; 1150 u64 max_dma_mask; 1151 unsigned int rx_prefix_size; 1152 unsigned int rx_hash_offset; 1153 unsigned int rx_ts_offset; 1154 unsigned int rx_buffer_padding; 1155 bool can_rx_scatter; 1156 bool always_rx_scatter; 1157 unsigned int max_interrupt_mode; 1158 unsigned int timer_period_max; 1159 netdev_features_t offload_features; 1160 unsigned int max_rx_ip_filters; 1161 }; 1162 1163 /************************************************************************** 1164 * 1165 * Prototypes and inline functions 1166 * 1167 *************************************************************************/ 1168 1169 static inline struct ef4_channel * 1170 ef4_get_channel(struct ef4_nic *efx, unsigned index) 1171 { 1172 EF4_BUG_ON_PARANOID(index >= efx->n_channels); 1173 return efx->channel[index]; 1174 } 1175 1176 /* Iterate over all used channels */ 1177 #define ef4_for_each_channel(_channel, _efx) \ 1178 for (_channel = (_efx)->channel[0]; \ 1179 _channel; \ 1180 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ 1181 (_efx)->channel[_channel->channel + 1] : NULL) 1182 1183 /* Iterate over all used channels in reverse */ 1184 #define ef4_for_each_channel_rev(_channel, _efx) \ 1185 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ 1186 _channel; \ 1187 _channel = _channel->channel ? \ 1188 (_efx)->channel[_channel->channel - 1] : NULL) 1189 1190 static inline struct ef4_tx_queue * 1191 ef4_get_tx_queue(struct ef4_nic *efx, unsigned index, unsigned type) 1192 { 1193 EF4_BUG_ON_PARANOID(index >= efx->n_tx_channels || 1194 type >= EF4_TXQ_TYPES); 1195 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; 1196 } 1197 1198 static inline bool ef4_channel_has_tx_queues(struct ef4_channel *channel) 1199 { 1200 return channel->channel - channel->efx->tx_channel_offset < 1201 channel->efx->n_tx_channels; 1202 } 1203 1204 static inline struct ef4_tx_queue * 1205 ef4_channel_get_tx_queue(struct ef4_channel *channel, unsigned type) 1206 { 1207 EF4_BUG_ON_PARANOID(!ef4_channel_has_tx_queues(channel) || 1208 type >= EF4_TXQ_TYPES); 1209 return &channel->tx_queue[type]; 1210 } 1211 1212 static inline bool ef4_tx_queue_used(struct ef4_tx_queue *tx_queue) 1213 { 1214 return !(tx_queue->efx->net_dev->num_tc < 2 && 1215 tx_queue->queue & EF4_TXQ_TYPE_HIGHPRI); 1216 } 1217 1218 /* Iterate over all TX queues belonging to a channel */ 1219 #define ef4_for_each_channel_tx_queue(_tx_queue, _channel) \ 1220 if (!ef4_channel_has_tx_queues(_channel)) \ 1221 ; \ 1222 else \ 1223 for (_tx_queue = (_channel)->tx_queue; \ 1224 _tx_queue < (_channel)->tx_queue + EF4_TXQ_TYPES && \ 1225 ef4_tx_queue_used(_tx_queue); \ 1226 _tx_queue++) 1227 1228 /* Iterate over all possible TX queues belonging to a channel */ 1229 #define ef4_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ 1230 if (!ef4_channel_has_tx_queues(_channel)) \ 1231 ; \ 1232 else \ 1233 for (_tx_queue = (_channel)->tx_queue; \ 1234 _tx_queue < (_channel)->tx_queue + EF4_TXQ_TYPES; \ 1235 _tx_queue++) 1236 1237 static inline bool ef4_channel_has_rx_queue(struct ef4_channel *channel) 1238 { 1239 return channel->rx_queue.core_index >= 0; 1240 } 1241 1242 static inline struct ef4_rx_queue * 1243 ef4_channel_get_rx_queue(struct ef4_channel *channel) 1244 { 1245 EF4_BUG_ON_PARANOID(!ef4_channel_has_rx_queue(channel)); 1246 return &channel->rx_queue; 1247 } 1248 1249 /* Iterate over all RX queues belonging to a channel */ 1250 #define ef4_for_each_channel_rx_queue(_rx_queue, _channel) \ 1251 if (!ef4_channel_has_rx_queue(_channel)) \ 1252 ; \ 1253 else \ 1254 for (_rx_queue = &(_channel)->rx_queue; \ 1255 _rx_queue; \ 1256 _rx_queue = NULL) 1257 1258 static inline struct ef4_channel * 1259 ef4_rx_queue_channel(struct ef4_rx_queue *rx_queue) 1260 { 1261 return container_of(rx_queue, struct ef4_channel, rx_queue); 1262 } 1263 1264 static inline int ef4_rx_queue_index(struct ef4_rx_queue *rx_queue) 1265 { 1266 return ef4_rx_queue_channel(rx_queue)->channel; 1267 } 1268 1269 /* Returns a pointer to the specified receive buffer in the RX 1270 * descriptor queue. 1271 */ 1272 static inline struct ef4_rx_buffer *ef4_rx_buffer(struct ef4_rx_queue *rx_queue, 1273 unsigned int index) 1274 { 1275 return &rx_queue->buffer[index]; 1276 } 1277 1278 /** 1279 * EF4_MAX_FRAME_LEN - calculate maximum frame length 1280 * 1281 * This calculates the maximum frame length that will be used for a 1282 * given MTU. The frame length will be equal to the MTU plus a 1283 * constant amount of header space and padding. This is the quantity 1284 * that the net driver will program into the MAC as the maximum frame 1285 * length. 1286 * 1287 * The 10G MAC requires 8-byte alignment on the frame 1288 * length, so we round up to the nearest 8. 1289 * 1290 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an 1291 * XGMII cycle). If the frame length reaches the maximum value in the 1292 * same cycle, the XMAC can miss the IPG altogether. We work around 1293 * this by adding a further 16 bytes. 1294 */ 1295 #define EF4_FRAME_PAD 16 1296 #define EF4_MAX_FRAME_LEN(mtu) \ 1297 (ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EF4_FRAME_PAD), 8)) 1298 1299 /* Get all supported features. 1300 * If a feature is not fixed, it is present in hw_features. 1301 * If a feature is fixed, it does not present in hw_features, but 1302 * always in features. 1303 */ 1304 static inline netdev_features_t ef4_supported_features(const struct ef4_nic *efx) 1305 { 1306 const struct net_device *net_dev = efx->net_dev; 1307 1308 return net_dev->features | net_dev->hw_features; 1309 } 1310 1311 /* Get the current TX queue insert index. */ 1312 static inline unsigned int 1313 ef4_tx_queue_get_insert_index(const struct ef4_tx_queue *tx_queue) 1314 { 1315 return tx_queue->insert_count & tx_queue->ptr_mask; 1316 } 1317 1318 /* Get a TX buffer. */ 1319 static inline struct ef4_tx_buffer * 1320 __ef4_tx_queue_get_insert_buffer(const struct ef4_tx_queue *tx_queue) 1321 { 1322 return &tx_queue->buffer[ef4_tx_queue_get_insert_index(tx_queue)]; 1323 } 1324 1325 /* Get a TX buffer, checking it's not currently in use. */ 1326 static inline struct ef4_tx_buffer * 1327 ef4_tx_queue_get_insert_buffer(const struct ef4_tx_queue *tx_queue) 1328 { 1329 struct ef4_tx_buffer *buffer = 1330 __ef4_tx_queue_get_insert_buffer(tx_queue); 1331 1332 EF4_BUG_ON_PARANOID(buffer->len); 1333 EF4_BUG_ON_PARANOID(buffer->flags); 1334 EF4_BUG_ON_PARANOID(buffer->unmap_len); 1335 1336 return buffer; 1337 } 1338 1339 #endif /* EF4_NET_DRIVER_H */ 1340