1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2018 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include "net_driver.h" 12 #include <linux/module.h> 13 #include "efx_channels.h" 14 #include "efx.h" 15 #include "efx_common.h" 16 #include "tx_common.h" 17 #include "rx_common.h" 18 #include "nic.h" 19 #include "sriov.h" 20 21 /* This is the first interrupt mode to try out of: 22 * 0 => MSI-X 23 * 1 => MSI 24 * 2 => legacy 25 */ 26 static unsigned int interrupt_mode; 27 module_param(interrupt_mode, uint, 0444); 28 MODULE_PARM_DESC(interrupt_mode, 29 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); 30 31 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), 32 * i.e. the number of CPUs among which we may distribute simultaneous 33 * interrupt handling. 34 * 35 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. 36 * The default (0) means to assign an interrupt to each core. 37 */ 38 static unsigned int rss_cpus; 39 module_param(rss_cpus, uint, 0444); 40 MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); 41 42 static unsigned int irq_adapt_low_thresh = 8000; 43 module_param(irq_adapt_low_thresh, uint, 0644); 44 MODULE_PARM_DESC(irq_adapt_low_thresh, 45 "Threshold score for reducing IRQ moderation"); 46 47 static unsigned int irq_adapt_high_thresh = 16000; 48 module_param(irq_adapt_high_thresh, uint, 0644); 49 MODULE_PARM_DESC(irq_adapt_high_thresh, 50 "Threshold score for increasing IRQ moderation"); 51 52 /* This is the weight assigned to each of the (per-channel) virtual 53 * NAPI devices. 54 */ 55 static int napi_weight = 64; 56 57 /*************** 58 * Housekeeping 59 ***************/ 60 61 int efx_channel_dummy_op_int(struct efx_channel *channel) 62 { 63 return 0; 64 } 65 66 void efx_channel_dummy_op_void(struct efx_channel *channel) 67 { 68 } 69 70 static const struct efx_channel_type efx_default_channel_type = { 71 .pre_probe = efx_channel_dummy_op_int, 72 .post_remove = efx_channel_dummy_op_void, 73 .get_name = efx_get_channel_name, 74 .copy = efx_copy_channel, 75 .want_txqs = efx_default_channel_want_txqs, 76 .keep_eventq = false, 77 .want_pio = true, 78 }; 79 80 /************* 81 * INTERRUPTS 82 *************/ 83 84 static unsigned int efx_wanted_parallelism(struct efx_nic *efx) 85 { 86 cpumask_var_t thread_mask; 87 unsigned int count; 88 int cpu; 89 90 if (rss_cpus) { 91 count = rss_cpus; 92 } else { 93 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { 94 netif_warn(efx, probe, efx->net_dev, 95 "RSS disabled due to allocation failure\n"); 96 return 1; 97 } 98 99 count = 0; 100 for_each_online_cpu(cpu) { 101 if (!cpumask_test_cpu(cpu, thread_mask)) { 102 ++count; 103 cpumask_or(thread_mask, thread_mask, 104 topology_sibling_cpumask(cpu)); 105 } 106 } 107 108 free_cpumask_var(thread_mask); 109 } 110 111 if (count > EFX_MAX_RX_QUEUES) { 112 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, 113 "Reducing number of rx queues from %u to %u.\n", 114 count, EFX_MAX_RX_QUEUES); 115 count = EFX_MAX_RX_QUEUES; 116 } 117 118 /* If RSS is requested for the PF *and* VFs then we can't write RSS 119 * table entries that are inaccessible to VFs 120 */ 121 #ifdef CONFIG_SFC_SRIOV 122 if (efx->type->sriov_wanted) { 123 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && 124 count > efx_vf_size(efx)) { 125 netif_warn(efx, probe, efx->net_dev, 126 "Reducing number of RSS channels from %u to %u for " 127 "VF support. Increase vf-msix-limit to use more " 128 "channels on the PF.\n", 129 count, efx_vf_size(efx)); 130 count = efx_vf_size(efx); 131 } 132 } 133 #endif 134 135 return count; 136 } 137 138 static int efx_allocate_msix_channels(struct efx_nic *efx, 139 unsigned int max_channels, 140 unsigned int extra_channels, 141 unsigned int parallelism) 142 { 143 unsigned int n_channels = parallelism; 144 int vec_count; 145 int n_xdp_tx; 146 int n_xdp_ev; 147 148 if (efx_separate_tx_channels) 149 n_channels *= 2; 150 n_channels += extra_channels; 151 152 /* To allow XDP transmit to happen from arbitrary NAPI contexts 153 * we allocate a TX queue per CPU. We share event queues across 154 * multiple tx queues, assuming tx and ev queues are both 155 * maximum size. 156 */ 157 158 n_xdp_tx = num_possible_cpus(); 159 n_xdp_ev = DIV_ROUND_UP(n_xdp_tx, EFX_TXQ_TYPES); 160 161 vec_count = pci_msix_vec_count(efx->pci_dev); 162 if (vec_count < 0) 163 return vec_count; 164 165 max_channels = min_t(unsigned int, vec_count, max_channels); 166 167 /* Check resources. 168 * We need a channel per event queue, plus a VI per tx queue. 169 * This may be more pessimistic than it needs to be. 170 */ 171 if (n_channels + n_xdp_ev > max_channels) { 172 netif_err(efx, drv, efx->net_dev, 173 "Insufficient resources for %d XDP event queues (%d other channels, max %d)\n", 174 n_xdp_ev, n_channels, max_channels); 175 efx->n_xdp_channels = 0; 176 efx->xdp_tx_per_channel = 0; 177 efx->xdp_tx_queue_count = 0; 178 } else { 179 efx->n_xdp_channels = n_xdp_ev; 180 efx->xdp_tx_per_channel = EFX_TXQ_TYPES; 181 efx->xdp_tx_queue_count = n_xdp_tx; 182 n_channels += n_xdp_ev; 183 netif_dbg(efx, drv, efx->net_dev, 184 "Allocating %d TX and %d event queues for XDP\n", 185 n_xdp_tx, n_xdp_ev); 186 } 187 188 if (vec_count < n_channels) { 189 netif_err(efx, drv, efx->net_dev, 190 "WARNING: Insufficient MSI-X vectors available (%d < %u).\n", 191 vec_count, n_channels); 192 netif_err(efx, drv, efx->net_dev, 193 "WARNING: Performance may be reduced.\n"); 194 n_channels = vec_count; 195 } 196 197 n_channels = min(n_channels, max_channels); 198 199 efx->n_channels = n_channels; 200 201 /* Ignore XDP tx channels when creating rx channels. */ 202 n_channels -= efx->n_xdp_channels; 203 204 if (efx_separate_tx_channels) { 205 efx->n_tx_channels = 206 min(max(n_channels / 2, 1U), 207 efx->max_tx_channels); 208 efx->tx_channel_offset = 209 n_channels - efx->n_tx_channels; 210 efx->n_rx_channels = 211 max(n_channels - 212 efx->n_tx_channels, 1U); 213 } else { 214 efx->n_tx_channels = min(n_channels, efx->max_tx_channels); 215 efx->tx_channel_offset = 0; 216 efx->n_rx_channels = n_channels; 217 } 218 219 efx->n_rx_channels = min(efx->n_rx_channels, parallelism); 220 efx->n_tx_channels = min(efx->n_tx_channels, parallelism); 221 222 efx->xdp_channel_offset = n_channels; 223 224 netif_dbg(efx, drv, efx->net_dev, 225 "Allocating %u RX channels\n", 226 efx->n_rx_channels); 227 228 return efx->n_channels; 229 } 230 231 /* Probe the number and type of interrupts we are able to obtain, and 232 * the resulting numbers of channels and RX queues. 233 */ 234 int efx_probe_interrupts(struct efx_nic *efx) 235 { 236 unsigned int extra_channels = 0; 237 unsigned int rss_spread; 238 unsigned int i, j; 239 int rc; 240 241 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) 242 if (efx->extra_channel_type[i]) 243 ++extra_channels; 244 245 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { 246 unsigned int parallelism = efx_wanted_parallelism(efx); 247 struct msix_entry xentries[EFX_MAX_CHANNELS]; 248 unsigned int n_channels; 249 250 rc = efx_allocate_msix_channels(efx, efx->max_channels, 251 extra_channels, parallelism); 252 if (rc >= 0) { 253 n_channels = rc; 254 for (i = 0; i < n_channels; i++) 255 xentries[i].entry = i; 256 rc = pci_enable_msix_range(efx->pci_dev, xentries, 1, 257 n_channels); 258 } 259 if (rc < 0) { 260 /* Fall back to single channel MSI */ 261 netif_err(efx, drv, efx->net_dev, 262 "could not enable MSI-X\n"); 263 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_MSI) 264 efx->interrupt_mode = EFX_INT_MODE_MSI; 265 else 266 return rc; 267 } else if (rc < n_channels) { 268 netif_err(efx, drv, efx->net_dev, 269 "WARNING: Insufficient MSI-X vectors" 270 " available (%d < %u).\n", rc, n_channels); 271 netif_err(efx, drv, efx->net_dev, 272 "WARNING: Performance may be reduced.\n"); 273 n_channels = rc; 274 } 275 276 if (rc > 0) { 277 for (i = 0; i < efx->n_channels; i++) 278 efx_get_channel(efx, i)->irq = 279 xentries[i].vector; 280 } 281 } 282 283 /* Try single interrupt MSI */ 284 if (efx->interrupt_mode == EFX_INT_MODE_MSI) { 285 efx->n_channels = 1; 286 efx->n_rx_channels = 1; 287 efx->n_tx_channels = 1; 288 efx->n_xdp_channels = 0; 289 efx->xdp_channel_offset = efx->n_channels; 290 rc = pci_enable_msi(efx->pci_dev); 291 if (rc == 0) { 292 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; 293 } else { 294 netif_err(efx, drv, efx->net_dev, 295 "could not enable MSI\n"); 296 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_LEGACY) 297 efx->interrupt_mode = EFX_INT_MODE_LEGACY; 298 else 299 return rc; 300 } 301 } 302 303 /* Assume legacy interrupts */ 304 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { 305 efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0); 306 efx->n_rx_channels = 1; 307 efx->n_tx_channels = 1; 308 efx->n_xdp_channels = 0; 309 efx->xdp_channel_offset = efx->n_channels; 310 efx->legacy_irq = efx->pci_dev->irq; 311 } 312 313 /* Assign extra channels if possible, before XDP channels */ 314 efx->n_extra_tx_channels = 0; 315 j = efx->xdp_channel_offset; 316 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { 317 if (!efx->extra_channel_type[i]) 318 continue; 319 if (j <= efx->tx_channel_offset + efx->n_tx_channels) { 320 efx->extra_channel_type[i]->handle_no_channel(efx); 321 } else { 322 --j; 323 efx_get_channel(efx, j)->type = 324 efx->extra_channel_type[i]; 325 if (efx_channel_has_tx_queues(efx_get_channel(efx, j))) 326 efx->n_extra_tx_channels++; 327 } 328 } 329 330 rss_spread = efx->n_rx_channels; 331 /* RSS might be usable on VFs even if it is disabled on the PF */ 332 #ifdef CONFIG_SFC_SRIOV 333 if (efx->type->sriov_wanted) { 334 efx->rss_spread = ((rss_spread > 1 || 335 !efx->type->sriov_wanted(efx)) ? 336 rss_spread : efx_vf_size(efx)); 337 return 0; 338 } 339 #endif 340 efx->rss_spread = rss_spread; 341 342 return 0; 343 } 344 345 #if defined(CONFIG_SMP) 346 void efx_set_interrupt_affinity(struct efx_nic *efx) 347 { 348 struct efx_channel *channel; 349 unsigned int cpu; 350 351 efx_for_each_channel(channel, efx) { 352 cpu = cpumask_local_spread(channel->channel, 353 pcibus_to_node(efx->pci_dev->bus)); 354 irq_set_affinity_hint(channel->irq, cpumask_of(cpu)); 355 } 356 } 357 358 void efx_clear_interrupt_affinity(struct efx_nic *efx) 359 { 360 struct efx_channel *channel; 361 362 efx_for_each_channel(channel, efx) 363 irq_set_affinity_hint(channel->irq, NULL); 364 } 365 #else 366 void 367 efx_set_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused))) 368 { 369 } 370 371 void 372 efx_clear_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused))) 373 { 374 } 375 #endif /* CONFIG_SMP */ 376 377 void efx_remove_interrupts(struct efx_nic *efx) 378 { 379 struct efx_channel *channel; 380 381 /* Remove MSI/MSI-X interrupts */ 382 efx_for_each_channel(channel, efx) 383 channel->irq = 0; 384 pci_disable_msi(efx->pci_dev); 385 pci_disable_msix(efx->pci_dev); 386 387 /* Remove legacy interrupt */ 388 efx->legacy_irq = 0; 389 } 390 391 /*************** 392 * EVENT QUEUES 393 ***************/ 394 395 /* Create event queue 396 * Event queue memory allocations are done only once. If the channel 397 * is reset, the memory buffer will be reused; this guards against 398 * errors during channel reset and also simplifies interrupt handling. 399 */ 400 int efx_probe_eventq(struct efx_channel *channel) 401 { 402 struct efx_nic *efx = channel->efx; 403 unsigned long entries; 404 405 netif_dbg(efx, probe, efx->net_dev, 406 "chan %d create event queue\n", channel->channel); 407 408 /* Build an event queue with room for one event per tx and rx buffer, 409 * plus some extra for link state events and MCDI completions. 410 */ 411 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); 412 EFX_WARN_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); 413 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; 414 415 return efx_nic_probe_eventq(channel); 416 } 417 418 /* Prepare channel's event queue */ 419 int efx_init_eventq(struct efx_channel *channel) 420 { 421 struct efx_nic *efx = channel->efx; 422 int rc; 423 424 EFX_WARN_ON_PARANOID(channel->eventq_init); 425 426 netif_dbg(efx, drv, efx->net_dev, 427 "chan %d init event queue\n", channel->channel); 428 429 rc = efx_nic_init_eventq(channel); 430 if (rc == 0) { 431 efx->type->push_irq_moderation(channel); 432 channel->eventq_read_ptr = 0; 433 channel->eventq_init = true; 434 } 435 return rc; 436 } 437 438 /* Enable event queue processing and NAPI */ 439 void efx_start_eventq(struct efx_channel *channel) 440 { 441 netif_dbg(channel->efx, ifup, channel->efx->net_dev, 442 "chan %d start event queue\n", channel->channel); 443 444 /* Make sure the NAPI handler sees the enabled flag set */ 445 channel->enabled = true; 446 smp_wmb(); 447 448 napi_enable(&channel->napi_str); 449 efx_nic_eventq_read_ack(channel); 450 } 451 452 /* Disable event queue processing and NAPI */ 453 void efx_stop_eventq(struct efx_channel *channel) 454 { 455 if (!channel->enabled) 456 return; 457 458 napi_disable(&channel->napi_str); 459 channel->enabled = false; 460 } 461 462 void efx_fini_eventq(struct efx_channel *channel) 463 { 464 if (!channel->eventq_init) 465 return; 466 467 netif_dbg(channel->efx, drv, channel->efx->net_dev, 468 "chan %d fini event queue\n", channel->channel); 469 470 efx_nic_fini_eventq(channel); 471 channel->eventq_init = false; 472 } 473 474 void efx_remove_eventq(struct efx_channel *channel) 475 { 476 netif_dbg(channel->efx, drv, channel->efx->net_dev, 477 "chan %d remove event queue\n", channel->channel); 478 479 efx_nic_remove_eventq(channel); 480 } 481 482 /************************************************************************** 483 * 484 * Channel handling 485 * 486 *************************************************************************/ 487 488 #ifdef CONFIG_RFS_ACCEL 489 static void efx_filter_rfs_expire(struct work_struct *data) 490 { 491 struct delayed_work *dwork = to_delayed_work(data); 492 struct efx_channel *channel; 493 unsigned int time, quota; 494 495 channel = container_of(dwork, struct efx_channel, filter_work); 496 time = jiffies - channel->rfs_last_expiry; 497 quota = channel->rfs_filter_count * time / (30 * HZ); 498 if (quota >= 20 && __efx_filter_rfs_expire(channel, min(channel->rfs_filter_count, quota))) 499 channel->rfs_last_expiry += time; 500 /* Ensure we do more work eventually even if NAPI poll is not happening */ 501 schedule_delayed_work(dwork, 30 * HZ); 502 } 503 #endif 504 505 /* Allocate and initialise a channel structure. */ 506 struct efx_channel * 507 efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) 508 { 509 struct efx_rx_queue *rx_queue; 510 struct efx_tx_queue *tx_queue; 511 struct efx_channel *channel; 512 int j; 513 514 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 515 if (!channel) 516 return NULL; 517 518 channel->efx = efx; 519 channel->channel = i; 520 channel->type = &efx_default_channel_type; 521 522 for (j = 0; j < EFX_TXQ_TYPES; j++) { 523 tx_queue = &channel->tx_queue[j]; 524 tx_queue->efx = efx; 525 tx_queue->queue = i * EFX_TXQ_TYPES + j; 526 tx_queue->channel = channel; 527 } 528 529 #ifdef CONFIG_RFS_ACCEL 530 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); 531 #endif 532 533 rx_queue = &channel->rx_queue; 534 rx_queue->efx = efx; 535 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0); 536 537 return channel; 538 } 539 540 int efx_init_channels(struct efx_nic *efx) 541 { 542 unsigned int i; 543 544 for (i = 0; i < EFX_MAX_CHANNELS; i++) { 545 efx->channel[i] = efx_alloc_channel(efx, i, NULL); 546 if (!efx->channel[i]) 547 return -ENOMEM; 548 efx->msi_context[i].efx = efx; 549 efx->msi_context[i].index = i; 550 } 551 552 /* Higher numbered interrupt modes are less capable! */ 553 if (WARN_ON_ONCE(efx->type->max_interrupt_mode > 554 efx->type->min_interrupt_mode)) { 555 return -EIO; 556 } 557 efx->interrupt_mode = max(efx->type->max_interrupt_mode, 558 interrupt_mode); 559 efx->interrupt_mode = min(efx->type->min_interrupt_mode, 560 interrupt_mode); 561 562 return 0; 563 } 564 565 void efx_fini_channels(struct efx_nic *efx) 566 { 567 unsigned int i; 568 569 for (i = 0; i < EFX_MAX_CHANNELS; i++) 570 if (efx->channel[i]) { 571 kfree(efx->channel[i]); 572 efx->channel[i] = NULL; 573 } 574 } 575 576 /* Allocate and initialise a channel structure, copying parameters 577 * (but not resources) from an old channel structure. 578 */ 579 struct efx_channel *efx_copy_channel(const struct efx_channel *old_channel) 580 { 581 struct efx_rx_queue *rx_queue; 582 struct efx_tx_queue *tx_queue; 583 struct efx_channel *channel; 584 int j; 585 586 channel = kmalloc(sizeof(*channel), GFP_KERNEL); 587 if (!channel) 588 return NULL; 589 590 *channel = *old_channel; 591 592 channel->napi_dev = NULL; 593 INIT_HLIST_NODE(&channel->napi_str.napi_hash_node); 594 channel->napi_str.napi_id = 0; 595 channel->napi_str.state = 0; 596 memset(&channel->eventq, 0, sizeof(channel->eventq)); 597 598 for (j = 0; j < EFX_TXQ_TYPES; j++) { 599 tx_queue = &channel->tx_queue[j]; 600 if (tx_queue->channel) 601 tx_queue->channel = channel; 602 tx_queue->buffer = NULL; 603 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); 604 } 605 606 rx_queue = &channel->rx_queue; 607 rx_queue->buffer = NULL; 608 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); 609 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0); 610 #ifdef CONFIG_RFS_ACCEL 611 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); 612 #endif 613 614 return channel; 615 } 616 617 static int efx_probe_channel(struct efx_channel *channel) 618 { 619 struct efx_tx_queue *tx_queue; 620 struct efx_rx_queue *rx_queue; 621 int rc; 622 623 netif_dbg(channel->efx, probe, channel->efx->net_dev, 624 "creating channel %d\n", channel->channel); 625 626 rc = channel->type->pre_probe(channel); 627 if (rc) 628 goto fail; 629 630 rc = efx_probe_eventq(channel); 631 if (rc) 632 goto fail; 633 634 efx_for_each_channel_tx_queue(tx_queue, channel) { 635 rc = efx_probe_tx_queue(tx_queue); 636 if (rc) 637 goto fail; 638 } 639 640 efx_for_each_channel_rx_queue(rx_queue, channel) { 641 rc = efx_probe_rx_queue(rx_queue); 642 if (rc) 643 goto fail; 644 } 645 646 channel->rx_list = NULL; 647 648 return 0; 649 650 fail: 651 efx_remove_channel(channel); 652 return rc; 653 } 654 655 void efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) 656 { 657 struct efx_nic *efx = channel->efx; 658 const char *type; 659 int number; 660 661 number = channel->channel; 662 663 if (number >= efx->xdp_channel_offset && 664 !WARN_ON_ONCE(!efx->n_xdp_channels)) { 665 type = "-xdp"; 666 number -= efx->xdp_channel_offset; 667 } else if (efx->tx_channel_offset == 0) { 668 type = ""; 669 } else if (number < efx->tx_channel_offset) { 670 type = "-rx"; 671 } else { 672 type = "-tx"; 673 number -= efx->tx_channel_offset; 674 } 675 snprintf(buf, len, "%s%s-%d", efx->name, type, number); 676 } 677 678 void efx_set_channel_names(struct efx_nic *efx) 679 { 680 struct efx_channel *channel; 681 682 efx_for_each_channel(channel, efx) 683 channel->type->get_name(channel, 684 efx->msi_context[channel->channel].name, 685 sizeof(efx->msi_context[0].name)); 686 } 687 688 int efx_probe_channels(struct efx_nic *efx) 689 { 690 struct efx_channel *channel; 691 int rc; 692 693 /* Restart special buffer allocation */ 694 efx->next_buffer_table = 0; 695 696 /* Probe channels in reverse, so that any 'extra' channels 697 * use the start of the buffer table. This allows the traffic 698 * channels to be resized without moving them or wasting the 699 * entries before them. 700 */ 701 efx_for_each_channel_rev(channel, efx) { 702 rc = efx_probe_channel(channel); 703 if (rc) { 704 netif_err(efx, probe, efx->net_dev, 705 "failed to create channel %d\n", 706 channel->channel); 707 goto fail; 708 } 709 } 710 efx_set_channel_names(efx); 711 712 return 0; 713 714 fail: 715 efx_remove_channels(efx); 716 return rc; 717 } 718 719 void efx_remove_channel(struct efx_channel *channel) 720 { 721 struct efx_tx_queue *tx_queue; 722 struct efx_rx_queue *rx_queue; 723 724 netif_dbg(channel->efx, drv, channel->efx->net_dev, 725 "destroy chan %d\n", channel->channel); 726 727 efx_for_each_channel_rx_queue(rx_queue, channel) 728 efx_remove_rx_queue(rx_queue); 729 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 730 efx_remove_tx_queue(tx_queue); 731 efx_remove_eventq(channel); 732 channel->type->post_remove(channel); 733 } 734 735 void efx_remove_channels(struct efx_nic *efx) 736 { 737 struct efx_channel *channel; 738 739 efx_for_each_channel(channel, efx) 740 efx_remove_channel(channel); 741 742 kfree(efx->xdp_tx_queues); 743 } 744 745 int efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) 746 { 747 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; 748 unsigned int i, next_buffer_table = 0; 749 u32 old_rxq_entries, old_txq_entries; 750 int rc, rc2; 751 752 rc = efx_check_disabled(efx); 753 if (rc) 754 return rc; 755 756 /* Not all channels should be reallocated. We must avoid 757 * reallocating their buffer table entries. 758 */ 759 efx_for_each_channel(channel, efx) { 760 struct efx_rx_queue *rx_queue; 761 struct efx_tx_queue *tx_queue; 762 763 if (channel->type->copy) 764 continue; 765 next_buffer_table = max(next_buffer_table, 766 channel->eventq.index + 767 channel->eventq.entries); 768 efx_for_each_channel_rx_queue(rx_queue, channel) 769 next_buffer_table = max(next_buffer_table, 770 rx_queue->rxd.index + 771 rx_queue->rxd.entries); 772 efx_for_each_channel_tx_queue(tx_queue, channel) 773 next_buffer_table = max(next_buffer_table, 774 tx_queue->txd.index + 775 tx_queue->txd.entries); 776 } 777 778 efx_device_detach_sync(efx); 779 efx_stop_all(efx); 780 efx_soft_disable_interrupts(efx); 781 782 /* Clone channels (where possible) */ 783 memset(other_channel, 0, sizeof(other_channel)); 784 for (i = 0; i < efx->n_channels; i++) { 785 channel = efx->channel[i]; 786 if (channel->type->copy) 787 channel = channel->type->copy(channel); 788 if (!channel) { 789 rc = -ENOMEM; 790 goto out; 791 } 792 other_channel[i] = channel; 793 } 794 795 /* Swap entry counts and channel pointers */ 796 old_rxq_entries = efx->rxq_entries; 797 old_txq_entries = efx->txq_entries; 798 efx->rxq_entries = rxq_entries; 799 efx->txq_entries = txq_entries; 800 for (i = 0; i < efx->n_channels; i++) { 801 channel = efx->channel[i]; 802 efx->channel[i] = other_channel[i]; 803 other_channel[i] = channel; 804 } 805 806 /* Restart buffer table allocation */ 807 efx->next_buffer_table = next_buffer_table; 808 809 for (i = 0; i < efx->n_channels; i++) { 810 channel = efx->channel[i]; 811 if (!channel->type->copy) 812 continue; 813 rc = efx_probe_channel(channel); 814 if (rc) 815 goto rollback; 816 efx_init_napi_channel(efx->channel[i]); 817 } 818 819 out: 820 /* Destroy unused channel structures */ 821 for (i = 0; i < efx->n_channels; i++) { 822 channel = other_channel[i]; 823 if (channel && channel->type->copy) { 824 efx_fini_napi_channel(channel); 825 efx_remove_channel(channel); 826 kfree(channel); 827 } 828 } 829 830 rc2 = efx_soft_enable_interrupts(efx); 831 if (rc2) { 832 rc = rc ? rc : rc2; 833 netif_err(efx, drv, efx->net_dev, 834 "unable to restart interrupts on channel reallocation\n"); 835 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 836 } else { 837 efx_start_all(efx); 838 efx_device_attach_if_not_resetting(efx); 839 } 840 return rc; 841 842 rollback: 843 /* Swap back */ 844 efx->rxq_entries = old_rxq_entries; 845 efx->txq_entries = old_txq_entries; 846 for (i = 0; i < efx->n_channels; i++) { 847 channel = efx->channel[i]; 848 efx->channel[i] = other_channel[i]; 849 other_channel[i] = channel; 850 } 851 goto out; 852 } 853 854 int efx_set_channels(struct efx_nic *efx) 855 { 856 struct efx_channel *channel; 857 struct efx_tx_queue *tx_queue; 858 int xdp_queue_number; 859 860 efx->tx_channel_offset = 861 efx_separate_tx_channels ? 862 efx->n_channels - efx->n_tx_channels : 0; 863 864 if (efx->xdp_tx_queue_count) { 865 EFX_WARN_ON_PARANOID(efx->xdp_tx_queues); 866 867 /* Allocate array for XDP TX queue lookup. */ 868 efx->xdp_tx_queues = kcalloc(efx->xdp_tx_queue_count, 869 sizeof(*efx->xdp_tx_queues), 870 GFP_KERNEL); 871 if (!efx->xdp_tx_queues) 872 return -ENOMEM; 873 } 874 875 /* We need to mark which channels really have RX and TX 876 * queues, and adjust the TX queue numbers if we have separate 877 * RX-only and TX-only channels. 878 */ 879 xdp_queue_number = 0; 880 efx_for_each_channel(channel, efx) { 881 if (channel->channel < efx->n_rx_channels) 882 channel->rx_queue.core_index = channel->channel; 883 else 884 channel->rx_queue.core_index = -1; 885 886 efx_for_each_channel_tx_queue(tx_queue, channel) { 887 tx_queue->queue -= (efx->tx_channel_offset * 888 EFX_TXQ_TYPES); 889 890 if (efx_channel_is_xdp_tx(channel) && 891 xdp_queue_number < efx->xdp_tx_queue_count) { 892 efx->xdp_tx_queues[xdp_queue_number] = tx_queue; 893 xdp_queue_number++; 894 } 895 } 896 } 897 return 0; 898 } 899 900 bool efx_default_channel_want_txqs(struct efx_channel *channel) 901 { 902 return channel->channel - channel->efx->tx_channel_offset < 903 channel->efx->n_tx_channels; 904 } 905 906 /************* 907 * START/STOP 908 *************/ 909 910 int efx_soft_enable_interrupts(struct efx_nic *efx) 911 { 912 struct efx_channel *channel, *end_channel; 913 int rc; 914 915 BUG_ON(efx->state == STATE_DISABLED); 916 917 efx->irq_soft_enabled = true; 918 smp_wmb(); 919 920 efx_for_each_channel(channel, efx) { 921 if (!channel->type->keep_eventq) { 922 rc = efx_init_eventq(channel); 923 if (rc) 924 goto fail; 925 } 926 efx_start_eventq(channel); 927 } 928 929 efx_mcdi_mode_event(efx); 930 931 return 0; 932 fail: 933 end_channel = channel; 934 efx_for_each_channel(channel, efx) { 935 if (channel == end_channel) 936 break; 937 efx_stop_eventq(channel); 938 if (!channel->type->keep_eventq) 939 efx_fini_eventq(channel); 940 } 941 942 return rc; 943 } 944 945 void efx_soft_disable_interrupts(struct efx_nic *efx) 946 { 947 struct efx_channel *channel; 948 949 if (efx->state == STATE_DISABLED) 950 return; 951 952 efx_mcdi_mode_poll(efx); 953 954 efx->irq_soft_enabled = false; 955 smp_wmb(); 956 957 if (efx->legacy_irq) 958 synchronize_irq(efx->legacy_irq); 959 960 efx_for_each_channel(channel, efx) { 961 if (channel->irq) 962 synchronize_irq(channel->irq); 963 964 efx_stop_eventq(channel); 965 if (!channel->type->keep_eventq) 966 efx_fini_eventq(channel); 967 } 968 969 /* Flush the asynchronous MCDI request queue */ 970 efx_mcdi_flush_async(efx); 971 } 972 973 int efx_enable_interrupts(struct efx_nic *efx) 974 { 975 struct efx_channel *channel, *end_channel; 976 int rc; 977 978 /* TODO: Is this really a bug? */ 979 BUG_ON(efx->state == STATE_DISABLED); 980 981 if (efx->eeh_disabled_legacy_irq) { 982 enable_irq(efx->legacy_irq); 983 efx->eeh_disabled_legacy_irq = false; 984 } 985 986 efx->type->irq_enable_master(efx); 987 988 efx_for_each_channel(channel, efx) { 989 if (channel->type->keep_eventq) { 990 rc = efx_init_eventq(channel); 991 if (rc) 992 goto fail; 993 } 994 } 995 996 rc = efx_soft_enable_interrupts(efx); 997 if (rc) 998 goto fail; 999 1000 return 0; 1001 1002 fail: 1003 end_channel = channel; 1004 efx_for_each_channel(channel, efx) { 1005 if (channel == end_channel) 1006 break; 1007 if (channel->type->keep_eventq) 1008 efx_fini_eventq(channel); 1009 } 1010 1011 efx->type->irq_disable_non_ev(efx); 1012 1013 return rc; 1014 } 1015 1016 void efx_disable_interrupts(struct efx_nic *efx) 1017 { 1018 struct efx_channel *channel; 1019 1020 efx_soft_disable_interrupts(efx); 1021 1022 efx_for_each_channel(channel, efx) { 1023 if (channel->type->keep_eventq) 1024 efx_fini_eventq(channel); 1025 } 1026 1027 efx->type->irq_disable_non_ev(efx); 1028 } 1029 1030 void efx_start_channels(struct efx_nic *efx) 1031 { 1032 struct efx_tx_queue *tx_queue; 1033 struct efx_rx_queue *rx_queue; 1034 struct efx_channel *channel; 1035 1036 efx_for_each_channel(channel, efx) { 1037 efx_for_each_channel_tx_queue(tx_queue, channel) { 1038 efx_init_tx_queue(tx_queue); 1039 atomic_inc(&efx->active_queues); 1040 } 1041 1042 efx_for_each_channel_rx_queue(rx_queue, channel) { 1043 efx_init_rx_queue(rx_queue); 1044 atomic_inc(&efx->active_queues); 1045 efx_stop_eventq(channel); 1046 efx_fast_push_rx_descriptors(rx_queue, false); 1047 efx_start_eventq(channel); 1048 } 1049 1050 WARN_ON(channel->rx_pkt_n_frags); 1051 } 1052 } 1053 1054 void efx_stop_channels(struct efx_nic *efx) 1055 { 1056 struct efx_tx_queue *tx_queue; 1057 struct efx_rx_queue *rx_queue; 1058 struct efx_channel *channel; 1059 int rc = 0; 1060 1061 /* Stop RX refill */ 1062 efx_for_each_channel(channel, efx) { 1063 efx_for_each_channel_rx_queue(rx_queue, channel) 1064 rx_queue->refill_enabled = false; 1065 } 1066 1067 efx_for_each_channel(channel, efx) { 1068 /* RX packet processing is pipelined, so wait for the 1069 * NAPI handler to complete. At least event queue 0 1070 * might be kept active by non-data events, so don't 1071 * use napi_synchronize() but actually disable NAPI 1072 * temporarily. 1073 */ 1074 if (efx_channel_has_rx_queue(channel)) { 1075 efx_stop_eventq(channel); 1076 efx_start_eventq(channel); 1077 } 1078 } 1079 1080 if (efx->type->fini_dmaq) 1081 rc = efx->type->fini_dmaq(efx); 1082 1083 if (rc) { 1084 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); 1085 } else { 1086 netif_dbg(efx, drv, efx->net_dev, 1087 "successfully flushed all queues\n"); 1088 } 1089 1090 efx_for_each_channel(channel, efx) { 1091 efx_for_each_channel_rx_queue(rx_queue, channel) 1092 efx_fini_rx_queue(rx_queue); 1093 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 1094 efx_fini_tx_queue(tx_queue); 1095 } 1096 } 1097 1098 /************************************************************************** 1099 * 1100 * NAPI interface 1101 * 1102 *************************************************************************/ 1103 1104 /* Process channel's event queue 1105 * 1106 * This function is responsible for processing the event queue of a 1107 * single channel. The caller must guarantee that this function will 1108 * never be concurrently called more than once on the same channel, 1109 * though different channels may be being processed concurrently. 1110 */ 1111 static int efx_process_channel(struct efx_channel *channel, int budget) 1112 { 1113 struct efx_tx_queue *tx_queue; 1114 struct list_head rx_list; 1115 int spent; 1116 1117 if (unlikely(!channel->enabled)) 1118 return 0; 1119 1120 /* Prepare the batch receive list */ 1121 EFX_WARN_ON_PARANOID(channel->rx_list != NULL); 1122 INIT_LIST_HEAD(&rx_list); 1123 channel->rx_list = &rx_list; 1124 1125 efx_for_each_channel_tx_queue(tx_queue, channel) { 1126 tx_queue->pkts_compl = 0; 1127 tx_queue->bytes_compl = 0; 1128 } 1129 1130 spent = efx_nic_process_eventq(channel, budget); 1131 if (spent && efx_channel_has_rx_queue(channel)) { 1132 struct efx_rx_queue *rx_queue = 1133 efx_channel_get_rx_queue(channel); 1134 1135 efx_rx_flush_packet(channel); 1136 efx_fast_push_rx_descriptors(rx_queue, true); 1137 } 1138 1139 /* Update BQL */ 1140 efx_for_each_channel_tx_queue(tx_queue, channel) { 1141 if (tx_queue->bytes_compl) { 1142 netdev_tx_completed_queue(tx_queue->core_txq, 1143 tx_queue->pkts_compl, 1144 tx_queue->bytes_compl); 1145 } 1146 } 1147 1148 /* Receive any packets we queued up */ 1149 netif_receive_skb_list(channel->rx_list); 1150 channel->rx_list = NULL; 1151 1152 return spent; 1153 } 1154 1155 static void efx_update_irq_mod(struct efx_nic *efx, struct efx_channel *channel) 1156 { 1157 int step = efx->irq_mod_step_us; 1158 1159 if (channel->irq_mod_score < irq_adapt_low_thresh) { 1160 if (channel->irq_moderation_us > step) { 1161 channel->irq_moderation_us -= step; 1162 efx->type->push_irq_moderation(channel); 1163 } 1164 } else if (channel->irq_mod_score > irq_adapt_high_thresh) { 1165 if (channel->irq_moderation_us < 1166 efx->irq_rx_moderation_us) { 1167 channel->irq_moderation_us += step; 1168 efx->type->push_irq_moderation(channel); 1169 } 1170 } 1171 1172 channel->irq_count = 0; 1173 channel->irq_mod_score = 0; 1174 } 1175 1176 /* NAPI poll handler 1177 * 1178 * NAPI guarantees serialisation of polls of the same device, which 1179 * provides the guarantee required by efx_process_channel(). 1180 */ 1181 static int efx_poll(struct napi_struct *napi, int budget) 1182 { 1183 struct efx_channel *channel = 1184 container_of(napi, struct efx_channel, napi_str); 1185 struct efx_nic *efx = channel->efx; 1186 #ifdef CONFIG_RFS_ACCEL 1187 unsigned int time; 1188 #endif 1189 int spent; 1190 1191 netif_vdbg(efx, intr, efx->net_dev, 1192 "channel %d NAPI poll executing on CPU %d\n", 1193 channel->channel, raw_smp_processor_id()); 1194 1195 spent = efx_process_channel(channel, budget); 1196 1197 xdp_do_flush_map(); 1198 1199 if (spent < budget) { 1200 if (efx_channel_has_rx_queue(channel) && 1201 efx->irq_rx_adaptive && 1202 unlikely(++channel->irq_count == 1000)) { 1203 efx_update_irq_mod(efx, channel); 1204 } 1205 1206 #ifdef CONFIG_RFS_ACCEL 1207 /* Perhaps expire some ARFS filters */ 1208 time = jiffies - channel->rfs_last_expiry; 1209 /* Would our quota be >= 20? */ 1210 if (channel->rfs_filter_count * time >= 600 * HZ) 1211 mod_delayed_work(system_wq, &channel->filter_work, 0); 1212 #endif 1213 1214 /* There is no race here; although napi_disable() will 1215 * only wait for napi_complete(), this isn't a problem 1216 * since efx_nic_eventq_read_ack() will have no effect if 1217 * interrupts have already been disabled. 1218 */ 1219 if (napi_complete_done(napi, spent)) 1220 efx_nic_eventq_read_ack(channel); 1221 } 1222 1223 return spent; 1224 } 1225 1226 void efx_init_napi_channel(struct efx_channel *channel) 1227 { 1228 struct efx_nic *efx = channel->efx; 1229 1230 channel->napi_dev = efx->net_dev; 1231 netif_napi_add(channel->napi_dev, &channel->napi_str, 1232 efx_poll, napi_weight); 1233 } 1234 1235 void efx_init_napi(struct efx_nic *efx) 1236 { 1237 struct efx_channel *channel; 1238 1239 efx_for_each_channel(channel, efx) 1240 efx_init_napi_channel(channel); 1241 } 1242 1243 void efx_fini_napi_channel(struct efx_channel *channel) 1244 { 1245 if (channel->napi_dev) 1246 netif_napi_del(&channel->napi_str); 1247 1248 channel->napi_dev = NULL; 1249 } 1250 1251 void efx_fini_napi(struct efx_nic *efx) 1252 { 1253 struct efx_channel *channel; 1254 1255 efx_for_each_channel(channel, efx) 1256 efx_fini_napi_channel(channel); 1257 } 1258