1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2012-2015 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 #ifndef EFX_EF10_REGS_H 11 #define EFX_EF10_REGS_H 12 13 /* EF10 hardware architecture definitions have a name prefix following 14 * the format: 15 * 16 * E<type>_<min-rev><max-rev>_ 17 * 18 * The following <type> strings are used: 19 * 20 * MMIO register Host memory structure 21 * ------------------------------------------------------------- 22 * Address R 23 * Bitfield RF SF 24 * Enumerator FE SE 25 * 26 * <min-rev> is the first revision to which the definition applies: 27 * 28 * D: Huntington A0 29 * 30 * If the definition has been changed or removed in later revisions 31 * then <max-rev> is the last revision to which the definition applies; 32 * otherwise it is "Z". 33 */ 34 35 /************************************************************************** 36 * 37 * EF10 registers and descriptors 38 * 39 ************************************************************************** 40 */ 41 42 /* BIU_HW_REV_ID_REG: */ 43 #define ER_DZ_BIU_HW_REV_ID 0x00000000 44 #define ERF_DZ_HW_REV_ID_LBN 0 45 #define ERF_DZ_HW_REV_ID_WIDTH 32 46 47 /* BIU_MC_SFT_STATUS_REG: */ 48 #define ER_DZ_BIU_MC_SFT_STATUS 0x00000010 49 #define ER_DZ_BIU_MC_SFT_STATUS_STEP 4 50 #define ER_DZ_BIU_MC_SFT_STATUS_ROWS 8 51 #define ERF_DZ_MC_SFT_STATUS_LBN 0 52 #define ERF_DZ_MC_SFT_STATUS_WIDTH 32 53 54 /* BIU_INT_ISR_REG: */ 55 #define ER_DZ_BIU_INT_ISR 0x00000090 56 #define ERF_DZ_ISR_REG_LBN 0 57 #define ERF_DZ_ISR_REG_WIDTH 32 58 59 /* MC_DB_LWRD_REG: */ 60 #define ER_DZ_MC_DB_LWRD 0x00000200 61 #define ERF_DZ_MC_DOORBELL_L_LBN 0 62 #define ERF_DZ_MC_DOORBELL_L_WIDTH 32 63 64 /* MC_DB_HWRD_REG: */ 65 #define ER_DZ_MC_DB_HWRD 0x00000204 66 #define ERF_DZ_MC_DOORBELL_H_LBN 0 67 #define ERF_DZ_MC_DOORBELL_H_WIDTH 32 68 69 /* EVQ_RPTR_REG: */ 70 #define ER_DZ_EVQ_RPTR 0x00000400 71 #define ER_DZ_EVQ_RPTR_STEP 8192 72 #define ER_DZ_EVQ_RPTR_ROWS 2048 73 #define ERF_DZ_EVQ_RPTR_VLD_LBN 15 74 #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 75 #define ERF_DZ_EVQ_RPTR_LBN 0 76 #define ERF_DZ_EVQ_RPTR_WIDTH 15 77 78 /* EVQ_TMR_REG: */ 79 #define ER_DZ_EVQ_TMR 0x00000420 80 #define ER_DZ_EVQ_TMR_STEP 8192 81 #define ER_DZ_EVQ_TMR_ROWS 2048 82 #define ERF_DZ_TC_TIMER_MODE_LBN 14 83 #define ERF_DZ_TC_TIMER_MODE_WIDTH 2 84 #define ERF_DZ_TC_TIMER_VAL_LBN 0 85 #define ERF_DZ_TC_TIMER_VAL_WIDTH 14 86 87 /* RX_DESC_UPD_REG: */ 88 #define ER_DZ_RX_DESC_UPD 0x00000830 89 #define ER_DZ_RX_DESC_UPD_STEP 8192 90 #define ER_DZ_RX_DESC_UPD_ROWS 2048 91 #define ERF_DZ_RX_DESC_WPTR_LBN 0 92 #define ERF_DZ_RX_DESC_WPTR_WIDTH 12 93 94 /* TX_DESC_UPD_REG: */ 95 #define ER_DZ_TX_DESC_UPD 0x00000a10 96 #define ER_DZ_TX_DESC_UPD_STEP 8192 97 #define ER_DZ_TX_DESC_UPD_ROWS 2048 98 #define ERF_DZ_RSVD_LBN 76 99 #define ERF_DZ_RSVD_WIDTH 20 100 #define ERF_DZ_TX_DESC_WPTR_LBN 64 101 #define ERF_DZ_TX_DESC_WPTR_WIDTH 12 102 #define ERF_DZ_TX_DESC_HWORD_LBN 32 103 #define ERF_DZ_TX_DESC_HWORD_WIDTH 32 104 #define ERF_DZ_TX_DESC_LWORD_LBN 0 105 #define ERF_DZ_TX_DESC_LWORD_WIDTH 32 106 107 /* DRIVER_EV */ 108 #define ESF_DZ_DRV_CODE_LBN 60 109 #define ESF_DZ_DRV_CODE_WIDTH 4 110 #define ESF_DZ_DRV_SUB_CODE_LBN 56 111 #define ESF_DZ_DRV_SUB_CODE_WIDTH 4 112 #define ESE_DZ_DRV_TIMER_EV 3 113 #define ESE_DZ_DRV_START_UP_EV 2 114 #define ESE_DZ_DRV_WAKE_UP_EV 1 115 #define ESF_DZ_DRV_SUB_DATA_LBN 0 116 #define ESF_DZ_DRV_SUB_DATA_WIDTH 56 117 #define ESF_DZ_DRV_EVQ_ID_LBN 0 118 #define ESF_DZ_DRV_EVQ_ID_WIDTH 14 119 #define ESF_DZ_DRV_TMR_ID_LBN 0 120 #define ESF_DZ_DRV_TMR_ID_WIDTH 14 121 122 /* EVENT_ENTRY */ 123 #define ESF_DZ_EV_CODE_LBN 60 124 #define ESF_DZ_EV_CODE_WIDTH 4 125 #define ESE_DZ_EV_CODE_MCDI_EV 12 126 #define ESE_DZ_EV_CODE_DRIVER_EV 5 127 #define ESE_DZ_EV_CODE_TX_EV 2 128 #define ESE_DZ_EV_CODE_RX_EV 0 129 #define ESE_DZ_OTHER other 130 #define ESF_DZ_EV_DATA_LBN 0 131 #define ESF_DZ_EV_DATA_WIDTH 60 132 133 /* MC_EVENT */ 134 #define ESF_DZ_MC_CODE_LBN 60 135 #define ESF_DZ_MC_CODE_WIDTH 4 136 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59 137 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1 138 #define ESF_DZ_MC_DROP_EVENT_LBN 58 139 #define ESF_DZ_MC_DROP_EVENT_WIDTH 1 140 #define ESF_DZ_MC_SOFT_LBN 0 141 #define ESF_DZ_MC_SOFT_WIDTH 58 142 143 /* RX_EVENT */ 144 #define ESF_DZ_RX_CODE_LBN 60 145 #define ESF_DZ_RX_CODE_WIDTH 4 146 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59 147 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1 148 #define ESF_DZ_RX_DROP_EVENT_LBN 58 149 #define ESF_DZ_RX_DROP_EVENT_WIDTH 1 150 #define ESF_DD_RX_EV_RSVD2_LBN 54 151 #define ESF_DD_RX_EV_RSVD2_WIDTH 4 152 #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 153 #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 154 #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN 56 155 #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_WIDTH 1 156 #define ESF_EZ_RX_EV_RSVD2_LBN 54 157 #define ESF_EZ_RX_EV_RSVD2_WIDTH 2 158 #define ESF_DZ_RX_EV_SOFT2_LBN 52 159 #define ESF_DZ_RX_EV_SOFT2_WIDTH 2 160 #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 161 #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 162 #define ESF_DZ_RX_L4_CLASS_LBN 45 163 #define ESF_DZ_RX_L4_CLASS_WIDTH 3 164 #define ESE_DZ_L4_CLASS_RSVD7 7 165 #define ESE_DZ_L4_CLASS_RSVD6 6 166 #define ESE_DZ_L4_CLASS_RSVD5 5 167 #define ESE_DZ_L4_CLASS_RSVD4 4 168 #define ESE_DZ_L4_CLASS_RSVD3 3 169 #define ESE_DZ_L4_CLASS_UDP 2 170 #define ESE_DZ_L4_CLASS_TCP 1 171 #define ESE_DZ_L4_CLASS_UNKNOWN 0 172 #define ESF_DZ_RX_L3_CLASS_LBN 42 173 #define ESF_DZ_RX_L3_CLASS_WIDTH 3 174 #define ESE_DZ_L3_CLASS_RSVD7 7 175 #define ESE_DZ_L3_CLASS_IP6_FRAG 6 176 #define ESE_DZ_L3_CLASS_ARP 5 177 #define ESE_DZ_L3_CLASS_IP4_FRAG 4 178 #define ESE_DZ_L3_CLASS_FCOE 3 179 #define ESE_DZ_L3_CLASS_IP6 2 180 #define ESE_DZ_L3_CLASS_IP4 1 181 #define ESE_DZ_L3_CLASS_UNKNOWN 0 182 #define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39 183 #define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3 184 #define ESE_DZ_ETH_TAG_CLASS_RSVD7 7 185 #define ESE_DZ_ETH_TAG_CLASS_RSVD6 6 186 #define ESE_DZ_ETH_TAG_CLASS_RSVD5 5 187 #define ESE_DZ_ETH_TAG_CLASS_RSVD4 4 188 #define ESE_DZ_ETH_TAG_CLASS_RSVD3 3 189 #define ESE_DZ_ETH_TAG_CLASS_VLAN2 2 190 #define ESE_DZ_ETH_TAG_CLASS_VLAN1 1 191 #define ESE_DZ_ETH_TAG_CLASS_NONE 0 192 #define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36 193 #define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3 194 #define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2 195 #define ESE_DZ_ETH_BASE_CLASS_LLC 1 196 #define ESE_DZ_ETH_BASE_CLASS_ETH2 0 197 #define ESF_DZ_RX_MAC_CLASS_LBN 35 198 #define ESF_DZ_RX_MAC_CLASS_WIDTH 1 199 #define ESE_DZ_MAC_CLASS_MCAST 1 200 #define ESE_DZ_MAC_CLASS_UCAST 0 201 #define ESF_DD_RX_EV_SOFT1_LBN 32 202 #define ESF_DD_RX_EV_SOFT1_WIDTH 3 203 #define ESF_EZ_RX_EV_SOFT1_LBN 34 204 #define ESF_EZ_RX_EV_SOFT1_WIDTH 1 205 #define ESF_EZ_RX_ENCAP_HDR_LBN 32 206 #define ESF_EZ_RX_ENCAP_HDR_WIDTH 2 207 #define ESE_EZ_ENCAP_HDR_GRE 2 208 #define ESE_EZ_ENCAP_HDR_VXLAN 1 209 #define ESE_EZ_ENCAP_HDR_NONE 0 210 #define ESF_DD_RX_EV_RSVD1_LBN 30 211 #define ESF_DD_RX_EV_RSVD1_WIDTH 2 212 #define ESF_EZ_RX_EV_RSVD1_LBN 31 213 #define ESF_EZ_RX_EV_RSVD1_WIDTH 1 214 #define ESF_EZ_RX_ABORT_LBN 30 215 #define ESF_EZ_RX_ABORT_WIDTH 1 216 #define ESF_DZ_RX_ECC_ERR_LBN 29 217 #define ESF_DZ_RX_ECC_ERR_WIDTH 1 218 #define ESF_DZ_RX_CRC1_ERR_LBN 28 219 #define ESF_DZ_RX_CRC1_ERR_WIDTH 1 220 #define ESF_DZ_RX_CRC0_ERR_LBN 27 221 #define ESF_DZ_RX_CRC0_ERR_WIDTH 1 222 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26 223 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1 224 #define ESF_DZ_RX_IPCKSUM_ERR_LBN 25 225 #define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1 226 #define ESF_DZ_RX_ECRC_ERR_LBN 24 227 #define ESF_DZ_RX_ECRC_ERR_WIDTH 1 228 #define ESF_DZ_RX_QLABEL_LBN 16 229 #define ESF_DZ_RX_QLABEL_WIDTH 5 230 #define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15 231 #define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1 232 #define ESF_DZ_RX_CONT_LBN 14 233 #define ESF_DZ_RX_CONT_WIDTH 1 234 #define ESF_DZ_RX_BYTES_LBN 0 235 #define ESF_DZ_RX_BYTES_WIDTH 14 236 237 /* RX_KER_DESC */ 238 #define ESF_DZ_RX_KER_RESERVED_LBN 62 239 #define ESF_DZ_RX_KER_RESERVED_WIDTH 2 240 #define ESF_DZ_RX_KER_BYTE_CNT_LBN 48 241 #define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14 242 #define ESF_DZ_RX_KER_BUF_ADDR_LBN 0 243 #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48 244 245 /* TX_CSUM_TSTAMP_DESC */ 246 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 247 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 248 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 249 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 250 #define ESE_DZ_TX_OPTION_DESC_TSO 7 251 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 252 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 253 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_LBN 8 254 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_WIDTH 1 255 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_LBN 7 256 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_WIDTH 1 257 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_LBN 6 258 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_WIDTH 1 259 #define ESF_DZ_TX_TIMESTAMP_LBN 5 260 #define ESF_DZ_TX_TIMESTAMP_WIDTH 1 261 #define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 262 #define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 263 #define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 264 #define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 265 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 266 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 267 #define ESE_DZ_TX_OPTION_CRC_FCOE 1 268 #define ESE_DZ_TX_OPTION_CRC_OFF 0 269 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 270 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 271 #define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 272 #define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 273 274 /* TX_EVENT */ 275 #define ESF_DZ_TX_CODE_LBN 60 276 #define ESF_DZ_TX_CODE_WIDTH 4 277 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59 278 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1 279 #define ESF_DZ_TX_DROP_EVENT_LBN 58 280 #define ESF_DZ_TX_DROP_EVENT_WIDTH 1 281 #define ESF_DD_TX_EV_RSVD_LBN 48 282 #define ESF_DD_TX_EV_RSVD_WIDTH 10 283 #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 284 #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 285 #define ESF_EZ_IP_INNER_CHKSUM_ERR_LBN 56 286 #define ESF_EZ_IP_INNER_CHKSUM_ERR_WIDTH 1 287 #define ESF_EZ_TX_EV_RSVD_LBN 48 288 #define ESF_EZ_TX_EV_RSVD_WIDTH 8 289 #define ESF_DZ_TX_SOFT2_LBN 32 290 #define ESF_DZ_TX_SOFT2_WIDTH 16 291 #define ESF_DD_TX_SOFT1_LBN 24 292 #define ESF_DD_TX_SOFT1_WIDTH 8 293 #define ESF_EZ_TX_CAN_MERGE_LBN 31 294 #define ESF_EZ_TX_CAN_MERGE_WIDTH 1 295 #define ESF_EZ_TX_SOFT1_LBN 24 296 #define ESF_EZ_TX_SOFT1_WIDTH 7 297 #define ESF_DZ_TX_QLABEL_LBN 16 298 #define ESF_DZ_TX_QLABEL_WIDTH 5 299 #define ESF_DZ_TX_DESCR_INDX_LBN 0 300 #define ESF_DZ_TX_DESCR_INDX_WIDTH 16 301 302 /* TX_KER_DESC */ 303 #define ESF_DZ_TX_KER_TYPE_LBN 63 304 #define ESF_DZ_TX_KER_TYPE_WIDTH 1 305 #define ESF_DZ_TX_KER_CONT_LBN 62 306 #define ESF_DZ_TX_KER_CONT_WIDTH 1 307 #define ESF_DZ_TX_KER_BYTE_CNT_LBN 48 308 #define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14 309 #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 310 #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 311 312 /* TX_PIO_DESC */ 313 #define ESF_DZ_TX_PIO_TYPE_LBN 63 314 #define ESF_DZ_TX_PIO_TYPE_WIDTH 1 315 #define ESF_DZ_TX_PIO_OPT_LBN 60 316 #define ESF_DZ_TX_PIO_OPT_WIDTH 3 317 #define ESE_DZ_TX_OPTION_DESC_PIO 1 318 #define ESF_DZ_TX_PIO_CONT_LBN 59 319 #define ESF_DZ_TX_PIO_CONT_WIDTH 1 320 #define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32 321 #define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12 322 #define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0 323 #define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12 324 325 /* TX_TSO_DESC */ 326 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 327 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 328 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 329 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 330 #define ESE_DZ_TX_OPTION_DESC_TSO 7 331 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 332 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 333 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 334 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 335 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 336 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 337 #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 338 #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 339 #define ESF_DZ_TX_TSO_IP_ID_LBN 32 340 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 341 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 342 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 343 344 /* TX_TSO_FATSO2A_DESC */ 345 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 346 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 347 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 348 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 349 #define ESE_DZ_TX_OPTION_DESC_TSO 7 350 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 351 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 352 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 353 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 354 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 355 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 356 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 357 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 358 #define ESF_DZ_TX_TSO_IP_ID_LBN 32 359 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 360 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 361 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 362 363 364 /* TX_TSO_FATSO2B_DESC */ 365 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 366 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 367 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 368 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 369 #define ESE_DZ_TX_OPTION_DESC_TSO 7 370 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 371 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 372 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 373 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 374 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 375 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 376 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 377 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 378 #define ESF_DZ_TX_TSO_OUTER_IP_ID_LBN 0 379 #define ESF_DZ_TX_TSO_OUTER_IP_ID_WIDTH 16 380 #define ESF_DZ_TX_TSO_TCP_MSS_LBN 32 381 #define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16 382 383 384 /*************************************************************************/ 385 386 /* TX_DESC_UPD_REG: Transmit descriptor update register. 387 * We may write just one dword of these registers. 388 */ 389 #define ER_DZ_TX_DESC_UPD_DWORD (ER_DZ_TX_DESC_UPD + 2 * 4) 390 #define ERF_DZ_TX_DESC_WPTR_DWORD_LBN (ERF_DZ_TX_DESC_WPTR_LBN - 2 * 32) 391 #define ERF_DZ_TX_DESC_WPTR_DWORD_WIDTH ERF_DZ_TX_DESC_WPTR_WIDTH 392 393 /* The workaround for bug 35388 requires multiplexing writes through 394 * the TX_DESC_UPD_DWORD address. 395 * TX_DESC_UPD: 0ppppppppppp (bit 11 lost) 396 * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits) 397 * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost) 398 */ 399 #define ER_DD_EVQ_INDIRECT ER_DZ_TX_DESC_UPD_DWORD 400 #define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 401 #define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 402 #define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 403 #define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 404 #define ERF_DD_EVQ_IND_RPTR_LBN 0 405 #define ERF_DD_EVQ_IND_RPTR_WIDTH 8 406 #define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 407 #define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 408 #define EFE_DD_EVQ_IND_TIMER_FLAGS 3 409 #define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 410 #define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 411 #define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 412 #define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 413 414 /* TX_PIOBUF 415 * PIO buffer aperture (paged) 416 */ 417 #define ER_DZ_TX_PIOBUF 4096 418 #define ER_DZ_TX_PIOBUF_SIZE 2048 419 420 /* RX packet prefix */ 421 #define ES_DZ_RX_PREFIX_HASH_OFST 0 422 #define ES_DZ_RX_PREFIX_VLAN1_OFST 4 423 #define ES_DZ_RX_PREFIX_VLAN2_OFST 6 424 #define ES_DZ_RX_PREFIX_PKTLEN_OFST 8 425 #define ES_DZ_RX_PREFIX_TSTAMP_OFST 10 426 #define ES_DZ_RX_PREFIX_SIZE 14 427 428 #endif /* EFX_EF10_REGS_H */ 429