1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2018 Solarflare Communications Inc. 5 * Copyright 2019-2020 Xilinx Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation, incorporated herein by reference. 10 */ 11 12 #include "ef100_nic.h" 13 #include "efx_common.h" 14 #include "efx_channels.h" 15 #include "io.h" 16 #include "selftest.h" 17 #include "ef100_regs.h" 18 #include "mcdi.h" 19 #include "mcdi_pcol.h" 20 #include "mcdi_port_common.h" 21 #include "mcdi_functions.h" 22 #include "mcdi_filters.h" 23 #include "ef100_rx.h" 24 #include "ef100_tx.h" 25 #include "ef100_netdev.h" 26 27 #define EF100_MAX_VIS 4096 28 #define EF100_NUM_MCDI_BUFFERS 1 29 #define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX) 30 31 #define EF100_RESET_PORT ((ETH_RESET_MAC | ETH_RESET_PHY) << ETH_RESET_SHARED_SHIFT) 32 33 /* MCDI 34 */ 35 static u8 *ef100_mcdi_buf(struct efx_nic *efx, u8 bufid, dma_addr_t *dma_addr) 36 { 37 struct ef100_nic_data *nic_data = efx->nic_data; 38 39 if (dma_addr) 40 *dma_addr = nic_data->mcdi_buf.dma_addr + 41 bufid * ALIGN(MCDI_BUF_LEN, 256); 42 return nic_data->mcdi_buf.addr + bufid * ALIGN(MCDI_BUF_LEN, 256); 43 } 44 45 static int ef100_get_warm_boot_count(struct efx_nic *efx) 46 { 47 efx_dword_t reg; 48 49 efx_readd(efx, ®, efx_reg(efx, ER_GZ_MC_SFT_STATUS)); 50 51 if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) == 0xffffffff) { 52 netif_err(efx, hw, efx->net_dev, "Hardware unavailable\n"); 53 efx->state = STATE_DISABLED; 54 return -ENETDOWN; 55 } else { 56 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 57 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 58 } 59 } 60 61 static void ef100_mcdi_request(struct efx_nic *efx, 62 const efx_dword_t *hdr, size_t hdr_len, 63 const efx_dword_t *sdu, size_t sdu_len) 64 { 65 dma_addr_t dma_addr; 66 u8 *pdu = ef100_mcdi_buf(efx, 0, &dma_addr); 67 68 memcpy(pdu, hdr, hdr_len); 69 memcpy(pdu + hdr_len, sdu, sdu_len); 70 wmb(); 71 72 /* The hardware provides 'low' and 'high' (doorbell) registers 73 * for passing the 64-bit address of an MCDI request to 74 * firmware. However the dwords are swapped by firmware. The 75 * least significant bits of the doorbell are then 0 for all 76 * MCDI requests due to alignment. 77 */ 78 _efx_writed(efx, cpu_to_le32((u64)dma_addr >> 32), efx_reg(efx, ER_GZ_MC_DB_LWRD)); 79 _efx_writed(efx, cpu_to_le32((u32)dma_addr), efx_reg(efx, ER_GZ_MC_DB_HWRD)); 80 } 81 82 static bool ef100_mcdi_poll_response(struct efx_nic *efx) 83 { 84 const efx_dword_t hdr = 85 *(const efx_dword_t *)(ef100_mcdi_buf(efx, 0, NULL)); 86 87 rmb(); 88 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 89 } 90 91 static void ef100_mcdi_read_response(struct efx_nic *efx, 92 efx_dword_t *outbuf, size_t offset, 93 size_t outlen) 94 { 95 const u8 *pdu = ef100_mcdi_buf(efx, 0, NULL); 96 97 memcpy(outbuf, pdu + offset, outlen); 98 } 99 100 static int ef100_mcdi_poll_reboot(struct efx_nic *efx) 101 { 102 struct ef100_nic_data *nic_data = efx->nic_data; 103 int rc; 104 105 rc = ef100_get_warm_boot_count(efx); 106 if (rc < 0) { 107 /* The firmware is presumably in the process of 108 * rebooting. However, we are supposed to report each 109 * reboot just once, so we must only do that once we 110 * can read and store the updated warm boot count. 111 */ 112 return 0; 113 } 114 115 if (rc == nic_data->warm_boot_count) 116 return 0; 117 118 nic_data->warm_boot_count = rc; 119 120 return -EIO; 121 } 122 123 static void ef100_mcdi_reboot_detected(struct efx_nic *efx) 124 { 125 } 126 127 /* MCDI calls 128 */ 129 static int ef100_get_mac_address(struct efx_nic *efx, u8 *mac_address) 130 { 131 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 132 size_t outlen; 133 int rc; 134 135 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 136 137 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 138 outbuf, sizeof(outbuf), &outlen); 139 if (rc) 140 return rc; 141 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 142 return -EIO; 143 144 ether_addr_copy(mac_address, 145 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 146 return 0; 147 } 148 149 static int efx_ef100_init_datapath_caps(struct efx_nic *efx) 150 { 151 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V7_OUT_LEN); 152 struct ef100_nic_data *nic_data = efx->nic_data; 153 u8 vi_window_mode; 154 size_t outlen; 155 int rc; 156 157 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 158 159 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 160 outbuf, sizeof(outbuf), &outlen); 161 if (rc) 162 return rc; 163 if (outlen < MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) { 164 netif_err(efx, drv, efx->net_dev, 165 "unable to read datapath firmware capabilities\n"); 166 return -EIO; 167 } 168 169 nic_data->datapath_caps = MCDI_DWORD(outbuf, 170 GET_CAPABILITIES_OUT_FLAGS1); 171 nic_data->datapath_caps2 = MCDI_DWORD(outbuf, 172 GET_CAPABILITIES_V2_OUT_FLAGS2); 173 if (outlen < MC_CMD_GET_CAPABILITIES_V7_OUT_LEN) 174 nic_data->datapath_caps3 = 0; 175 else 176 nic_data->datapath_caps3 = MCDI_DWORD(outbuf, 177 GET_CAPABILITIES_V7_OUT_FLAGS3); 178 179 vi_window_mode = MCDI_BYTE(outbuf, 180 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); 181 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode); 182 if (rc) 183 return rc; 184 185 if (efx_ef100_has_cap(nic_data->datapath_caps2, TX_TSO_V3)) { 186 struct net_device *net_dev = efx->net_dev; 187 netdev_features_t tso = NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_PARTIAL | 188 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM; 189 190 net_dev->features |= tso; 191 net_dev->hw_features |= tso; 192 net_dev->hw_enc_features |= tso; 193 net_dev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM; 194 } 195 efx->num_mac_stats = MCDI_WORD(outbuf, 196 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS); 197 netif_dbg(efx, probe, efx->net_dev, 198 "firmware reports num_mac_stats = %u\n", 199 efx->num_mac_stats); 200 return 0; 201 } 202 203 /* Event handling 204 */ 205 static int ef100_ev_probe(struct efx_channel *channel) 206 { 207 /* Allocate an extra descriptor for the QMDA status completion entry */ 208 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, 209 (channel->eventq_mask + 2) * 210 sizeof(efx_qword_t), 211 GFP_KERNEL); 212 } 213 214 static int ef100_ev_init(struct efx_channel *channel) 215 { 216 struct ef100_nic_data *nic_data = channel->efx->nic_data; 217 218 /* initial phase is 0 */ 219 clear_bit(channel->channel, nic_data->evq_phases); 220 221 return efx_mcdi_ev_init(channel, false, false); 222 } 223 224 static void ef100_ev_read_ack(struct efx_channel *channel) 225 { 226 efx_dword_t evq_prime; 227 228 EFX_POPULATE_DWORD_2(evq_prime, 229 ERF_GZ_EVQ_ID, channel->channel, 230 ERF_GZ_IDX, channel->eventq_read_ptr & 231 channel->eventq_mask); 232 233 efx_writed(channel->efx, &evq_prime, 234 efx_reg(channel->efx, ER_GZ_EVQ_INT_PRIME)); 235 } 236 237 static int ef100_ev_process(struct efx_channel *channel, int quota) 238 { 239 struct efx_nic *efx = channel->efx; 240 struct ef100_nic_data *nic_data; 241 bool evq_phase, old_evq_phase; 242 unsigned int read_ptr; 243 efx_qword_t *p_event; 244 int spent = 0; 245 bool ev_phase; 246 int ev_type; 247 248 if (unlikely(!channel->enabled)) 249 return 0; 250 251 nic_data = efx->nic_data; 252 evq_phase = test_bit(channel->channel, nic_data->evq_phases); 253 old_evq_phase = evq_phase; 254 read_ptr = channel->eventq_read_ptr; 255 BUILD_BUG_ON(ESF_GZ_EV_RXPKTS_PHASE_LBN != ESF_GZ_EV_TXCMPL_PHASE_LBN); 256 257 while (spent < quota) { 258 p_event = efx_event(channel, read_ptr); 259 260 ev_phase = !!EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_PHASE); 261 if (ev_phase != evq_phase) 262 break; 263 264 netif_vdbg(efx, drv, efx->net_dev, 265 "processing event on %d " EFX_QWORD_FMT "\n", 266 channel->channel, EFX_QWORD_VAL(*p_event)); 267 268 ev_type = EFX_QWORD_FIELD(*p_event, ESF_GZ_E_TYPE); 269 270 switch (ev_type) { 271 case ESE_GZ_EF100_EV_RX_PKTS: 272 efx_ef100_ev_rx(channel, p_event); 273 ++spent; 274 break; 275 case ESE_GZ_EF100_EV_MCDI: 276 efx_mcdi_process_event(channel, p_event); 277 break; 278 case ESE_GZ_EF100_EV_TX_COMPLETION: 279 ef100_ev_tx(channel, p_event); 280 break; 281 case ESE_GZ_EF100_EV_DRIVER: 282 netif_info(efx, drv, efx->net_dev, 283 "Driver initiated event " EFX_QWORD_FMT "\n", 284 EFX_QWORD_VAL(*p_event)); 285 break; 286 default: 287 netif_info(efx, drv, efx->net_dev, 288 "Unhandled event " EFX_QWORD_FMT "\n", 289 EFX_QWORD_VAL(*p_event)); 290 } 291 292 ++read_ptr; 293 if ((read_ptr & channel->eventq_mask) == 0) 294 evq_phase = !evq_phase; 295 } 296 297 channel->eventq_read_ptr = read_ptr; 298 if (evq_phase != old_evq_phase) 299 change_bit(channel->channel, nic_data->evq_phases); 300 301 return spent; 302 } 303 304 static irqreturn_t ef100_msi_interrupt(int irq, void *dev_id) 305 { 306 struct efx_msi_context *context = dev_id; 307 struct efx_nic *efx = context->efx; 308 309 netif_vdbg(efx, intr, efx->net_dev, 310 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 311 312 if (likely(READ_ONCE(efx->irq_soft_enabled))) { 313 /* Note test interrupts */ 314 if (context->index == efx->irq_level) 315 efx->last_irq_cpu = raw_smp_processor_id(); 316 317 /* Schedule processing of the channel */ 318 efx_schedule_channel_irq(efx->channel[context->index]); 319 } 320 321 return IRQ_HANDLED; 322 } 323 324 static int ef100_phy_probe(struct efx_nic *efx) 325 { 326 struct efx_mcdi_phy_data *phy_data; 327 int rc; 328 329 /* Probe for the PHY */ 330 efx->phy_data = kzalloc(sizeof(struct efx_mcdi_phy_data), GFP_KERNEL); 331 if (!efx->phy_data) 332 return -ENOMEM; 333 334 rc = efx_mcdi_get_phy_cfg(efx, efx->phy_data); 335 if (rc) 336 return rc; 337 338 /* Populate driver and ethtool settings */ 339 phy_data = efx->phy_data; 340 mcdi_to_ethtool_linkset(phy_data->media, phy_data->supported_cap, 341 efx->link_advertising); 342 efx->fec_config = mcdi_fec_caps_to_ethtool(phy_data->supported_cap, 343 false); 344 345 /* Default to Autonegotiated flow control if the PHY supports it */ 346 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; 347 if (phy_data->supported_cap & (1 << MC_CMD_PHY_CAP_AN_LBN)) 348 efx->wanted_fc |= EFX_FC_AUTO; 349 efx_link_set_wanted_fc(efx, efx->wanted_fc); 350 351 /* Push settings to the PHY. Failure is not fatal, the user can try to 352 * fix it using ethtool. 353 */ 354 rc = efx_mcdi_port_reconfigure(efx); 355 if (rc && rc != -EPERM) 356 netif_warn(efx, drv, efx->net_dev, 357 "could not initialise PHY settings\n"); 358 359 return 0; 360 } 361 362 static int ef100_filter_table_probe(struct efx_nic *efx) 363 { 364 return efx_mcdi_filter_table_probe(efx, true); 365 } 366 367 static int ef100_filter_table_up(struct efx_nic *efx) 368 { 369 int rc; 370 371 rc = efx_mcdi_filter_add_vlan(efx, EFX_FILTER_VID_UNSPEC); 372 if (rc) { 373 efx_mcdi_filter_table_down(efx); 374 return rc; 375 } 376 377 rc = efx_mcdi_filter_add_vlan(efx, 0); 378 if (rc) { 379 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC); 380 efx_mcdi_filter_table_down(efx); 381 } 382 383 return rc; 384 } 385 386 static void ef100_filter_table_down(struct efx_nic *efx) 387 { 388 efx_mcdi_filter_del_vlan(efx, 0); 389 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC); 390 efx_mcdi_filter_table_down(efx); 391 } 392 393 /* Other 394 */ 395 static int ef100_reconfigure_mac(struct efx_nic *efx, bool mtu_only) 396 { 397 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 398 399 efx_mcdi_filter_sync_rx_mode(efx); 400 401 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED)) 402 return efx_mcdi_set_mtu(efx); 403 return efx_mcdi_set_mac(efx); 404 } 405 406 static enum reset_type ef100_map_reset_reason(enum reset_type reason) 407 { 408 if (reason == RESET_TYPE_TX_WATCHDOG) 409 return reason; 410 return RESET_TYPE_DISABLE; 411 } 412 413 static int ef100_map_reset_flags(u32 *flags) 414 { 415 /* Only perform a RESET_TYPE_ALL because we don't support MC_REBOOTs */ 416 if ((*flags & EF100_RESET_PORT)) { 417 *flags &= ~EF100_RESET_PORT; 418 return RESET_TYPE_ALL; 419 } 420 if (*flags & ETH_RESET_MGMT) { 421 *flags &= ~ETH_RESET_MGMT; 422 return RESET_TYPE_DISABLE; 423 } 424 425 return -EINVAL; 426 } 427 428 static int ef100_reset(struct efx_nic *efx, enum reset_type reset_type) 429 { 430 int rc; 431 432 dev_close(efx->net_dev); 433 434 if (reset_type == RESET_TYPE_TX_WATCHDOG) { 435 netif_device_attach(efx->net_dev); 436 __clear_bit(reset_type, &efx->reset_pending); 437 rc = dev_open(efx->net_dev, NULL); 438 } else if (reset_type == RESET_TYPE_ALL) { 439 rc = efx_mcdi_reset(efx, reset_type); 440 if (rc) 441 return rc; 442 443 netif_device_attach(efx->net_dev); 444 445 rc = dev_open(efx->net_dev, NULL); 446 } else { 447 rc = 1; /* Leave the device closed */ 448 } 449 return rc; 450 } 451 452 static void ef100_common_stat_mask(unsigned long *mask) 453 { 454 __set_bit(EF100_STAT_port_rx_packets, mask); 455 __set_bit(EF100_STAT_port_tx_packets, mask); 456 __set_bit(EF100_STAT_port_rx_bytes, mask); 457 __set_bit(EF100_STAT_port_tx_bytes, mask); 458 __set_bit(EF100_STAT_port_rx_multicast, mask); 459 __set_bit(EF100_STAT_port_rx_bad, mask); 460 __set_bit(EF100_STAT_port_rx_align_error, mask); 461 __set_bit(EF100_STAT_port_rx_overflow, mask); 462 } 463 464 static void ef100_ethtool_stat_mask(unsigned long *mask) 465 { 466 __set_bit(EF100_STAT_port_tx_pause, mask); 467 __set_bit(EF100_STAT_port_tx_unicast, mask); 468 __set_bit(EF100_STAT_port_tx_multicast, mask); 469 __set_bit(EF100_STAT_port_tx_broadcast, mask); 470 __set_bit(EF100_STAT_port_tx_lt64, mask); 471 __set_bit(EF100_STAT_port_tx_64, mask); 472 __set_bit(EF100_STAT_port_tx_65_to_127, mask); 473 __set_bit(EF100_STAT_port_tx_128_to_255, mask); 474 __set_bit(EF100_STAT_port_tx_256_to_511, mask); 475 __set_bit(EF100_STAT_port_tx_512_to_1023, mask); 476 __set_bit(EF100_STAT_port_tx_1024_to_15xx, mask); 477 __set_bit(EF100_STAT_port_tx_15xx_to_jumbo, mask); 478 __set_bit(EF100_STAT_port_rx_good, mask); 479 __set_bit(EF100_STAT_port_rx_pause, mask); 480 __set_bit(EF100_STAT_port_rx_unicast, mask); 481 __set_bit(EF100_STAT_port_rx_broadcast, mask); 482 __set_bit(EF100_STAT_port_rx_lt64, mask); 483 __set_bit(EF100_STAT_port_rx_64, mask); 484 __set_bit(EF100_STAT_port_rx_65_to_127, mask); 485 __set_bit(EF100_STAT_port_rx_128_to_255, mask); 486 __set_bit(EF100_STAT_port_rx_256_to_511, mask); 487 __set_bit(EF100_STAT_port_rx_512_to_1023, mask); 488 __set_bit(EF100_STAT_port_rx_1024_to_15xx, mask); 489 __set_bit(EF100_STAT_port_rx_15xx_to_jumbo, mask); 490 __set_bit(EF100_STAT_port_rx_gtjumbo, mask); 491 __set_bit(EF100_STAT_port_rx_bad_gtjumbo, mask); 492 __set_bit(EF100_STAT_port_rx_length_error, mask); 493 __set_bit(EF100_STAT_port_rx_nodesc_drops, mask); 494 __set_bit(GENERIC_STAT_rx_nodesc_trunc, mask); 495 __set_bit(GENERIC_STAT_rx_noskb_drops, mask); 496 } 497 498 #define EF100_DMA_STAT(ext_name, mcdi_name) \ 499 [EF100_STAT_ ## ext_name] = \ 500 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 501 502 static const struct efx_hw_stat_desc ef100_stat_desc[EF100_STAT_COUNT] = { 503 EF100_DMA_STAT(port_tx_bytes, TX_BYTES), 504 EF100_DMA_STAT(port_tx_packets, TX_PKTS), 505 EF100_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 506 EF100_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 507 EF100_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 508 EF100_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 509 EF100_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 510 EF100_DMA_STAT(port_tx_64, TX_64_PKTS), 511 EF100_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 512 EF100_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 513 EF100_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 514 EF100_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 515 EF100_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 516 EF100_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 517 EF100_DMA_STAT(port_rx_bytes, RX_BYTES), 518 EF100_DMA_STAT(port_rx_packets, RX_PKTS), 519 EF100_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 520 EF100_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 521 EF100_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 522 EF100_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 523 EF100_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 524 EF100_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 525 EF100_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 526 EF100_DMA_STAT(port_rx_64, RX_64_PKTS), 527 EF100_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 528 EF100_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 529 EF100_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 530 EF100_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 531 EF100_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 532 EF100_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 533 EF100_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 534 EF100_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 535 EF100_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 536 EF100_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 537 EF100_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 538 EF100_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 539 EFX_GENERIC_SW_STAT(rx_nodesc_trunc), 540 EFX_GENERIC_SW_STAT(rx_noskb_drops), 541 }; 542 543 static size_t ef100_describe_stats(struct efx_nic *efx, u8 *names) 544 { 545 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {}; 546 547 ef100_ethtool_stat_mask(mask); 548 return efx_nic_describe_stats(ef100_stat_desc, EF100_STAT_COUNT, 549 mask, names); 550 } 551 552 static size_t ef100_update_stats_common(struct efx_nic *efx, u64 *full_stats, 553 struct rtnl_link_stats64 *core_stats) 554 { 555 struct ef100_nic_data *nic_data = efx->nic_data; 556 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {}; 557 size_t stats_count = 0, index; 558 u64 *stats = nic_data->stats; 559 560 ef100_ethtool_stat_mask(mask); 561 562 if (full_stats) { 563 for_each_set_bit(index, mask, EF100_STAT_COUNT) { 564 if (ef100_stat_desc[index].name) { 565 *full_stats++ = stats[index]; 566 ++stats_count; 567 } 568 } 569 } 570 571 if (!core_stats) 572 return stats_count; 573 574 core_stats->rx_packets = stats[EF100_STAT_port_rx_packets]; 575 core_stats->tx_packets = stats[EF100_STAT_port_tx_packets]; 576 core_stats->rx_bytes = stats[EF100_STAT_port_rx_bytes]; 577 core_stats->tx_bytes = stats[EF100_STAT_port_tx_bytes]; 578 core_stats->rx_dropped = stats[EF100_STAT_port_rx_nodesc_drops] + 579 stats[GENERIC_STAT_rx_nodesc_trunc] + 580 stats[GENERIC_STAT_rx_noskb_drops]; 581 core_stats->multicast = stats[EF100_STAT_port_rx_multicast]; 582 core_stats->rx_length_errors = 583 stats[EF100_STAT_port_rx_gtjumbo] + 584 stats[EF100_STAT_port_rx_length_error]; 585 core_stats->rx_crc_errors = stats[EF100_STAT_port_rx_bad]; 586 core_stats->rx_frame_errors = 587 stats[EF100_STAT_port_rx_align_error]; 588 core_stats->rx_fifo_errors = stats[EF100_STAT_port_rx_overflow]; 589 core_stats->rx_errors = (core_stats->rx_length_errors + 590 core_stats->rx_crc_errors + 591 core_stats->rx_frame_errors); 592 593 return stats_count; 594 } 595 596 static size_t ef100_update_stats(struct efx_nic *efx, 597 u64 *full_stats, 598 struct rtnl_link_stats64 *core_stats) 599 { 600 __le64 *mc_stats = kmalloc(array_size(efx->num_mac_stats, sizeof(__le64)), GFP_ATOMIC); 601 struct ef100_nic_data *nic_data = efx->nic_data; 602 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {}; 603 u64 *stats = nic_data->stats; 604 605 ef100_common_stat_mask(mask); 606 ef100_ethtool_stat_mask(mask); 607 608 efx_nic_copy_stats(efx, mc_stats); 609 efx_nic_update_stats(ef100_stat_desc, EF100_STAT_COUNT, mask, 610 stats, mc_stats, false); 611 612 kfree(mc_stats); 613 614 return ef100_update_stats_common(efx, full_stats, core_stats); 615 } 616 617 static int efx_ef100_get_phys_port_id(struct efx_nic *efx, 618 struct netdev_phys_item_id *ppid) 619 { 620 struct ef100_nic_data *nic_data = efx->nic_data; 621 622 if (!is_valid_ether_addr(nic_data->port_id)) 623 return -EOPNOTSUPP; 624 625 ppid->id_len = ETH_ALEN; 626 memcpy(ppid->id, nic_data->port_id, ppid->id_len); 627 628 return 0; 629 } 630 631 static int efx_ef100_irq_test_generate(struct efx_nic *efx) 632 { 633 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 634 635 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 636 637 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 638 return efx_mcdi_rpc_quiet(efx, MC_CMD_TRIGGER_INTERRUPT, 639 inbuf, sizeof(inbuf), NULL, 0, NULL); 640 } 641 642 #define EFX_EF100_TEST 1 643 644 static void efx_ef100_ev_test_generate(struct efx_channel *channel) 645 { 646 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 647 struct efx_nic *efx = channel->efx; 648 efx_qword_t event; 649 int rc; 650 651 EFX_POPULATE_QWORD_2(event, 652 ESF_GZ_E_TYPE, ESE_GZ_EF100_EV_DRIVER, 653 ESF_GZ_DRIVER_DATA, EFX_EF100_TEST); 654 655 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 656 657 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 658 * already swapped the data to little-endian order. 659 */ 660 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 661 sizeof(efx_qword_t)); 662 663 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 664 NULL, 0, NULL); 665 if (rc && (rc != -ENETDOWN)) 666 goto fail; 667 668 return; 669 670 fail: 671 WARN_ON(true); 672 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 673 } 674 675 static unsigned int ef100_check_caps(const struct efx_nic *efx, 676 u8 flag, u32 offset) 677 { 678 const struct ef100_nic_data *nic_data = efx->nic_data; 679 680 switch (offset) { 681 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST: 682 return nic_data->datapath_caps & BIT_ULL(flag); 683 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST: 684 return nic_data->datapath_caps2 & BIT_ULL(flag); 685 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST: 686 return nic_data->datapath_caps3 & BIT_ULL(flag); 687 default: 688 return 0; 689 } 690 } 691 692 /* NIC level access functions 693 */ 694 #define EF100_OFFLOAD_FEATURES (NETIF_F_HW_CSUM | NETIF_F_RXCSUM | \ 695 NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_NTUPLE | \ 696 NETIF_F_RXHASH | NETIF_F_RXFCS | NETIF_F_TSO_ECN | NETIF_F_RXALL | \ 697 NETIF_F_HW_VLAN_CTAG_TX) 698 699 const struct efx_nic_type ef100_pf_nic_type = { 700 .revision = EFX_REV_EF100, 701 .is_vf = false, 702 .probe = ef100_probe_pf, 703 .offload_features = EF100_OFFLOAD_FEATURES, 704 .mcdi_max_ver = 2, 705 .mcdi_request = ef100_mcdi_request, 706 .mcdi_poll_response = ef100_mcdi_poll_response, 707 .mcdi_read_response = ef100_mcdi_read_response, 708 .mcdi_poll_reboot = ef100_mcdi_poll_reboot, 709 .mcdi_reboot_detected = ef100_mcdi_reboot_detected, 710 .irq_enable_master = efx_port_dummy_op_void, 711 .irq_test_generate = efx_ef100_irq_test_generate, 712 .irq_disable_non_ev = efx_port_dummy_op_void, 713 .push_irq_moderation = efx_channel_dummy_op_void, 714 .min_interrupt_mode = EFX_INT_MODE_MSIX, 715 .map_reset_reason = ef100_map_reset_reason, 716 .map_reset_flags = ef100_map_reset_flags, 717 .reset = ef100_reset, 718 719 .check_caps = ef100_check_caps, 720 721 .ev_probe = ef100_ev_probe, 722 .ev_init = ef100_ev_init, 723 .ev_fini = efx_mcdi_ev_fini, 724 .ev_remove = efx_mcdi_ev_remove, 725 .irq_handle_msi = ef100_msi_interrupt, 726 .ev_process = ef100_ev_process, 727 .ev_read_ack = ef100_ev_read_ack, 728 .ev_test_generate = efx_ef100_ev_test_generate, 729 .tx_probe = ef100_tx_probe, 730 .tx_init = ef100_tx_init, 731 .tx_write = ef100_tx_write, 732 .tx_enqueue = ef100_enqueue_skb, 733 .rx_probe = efx_mcdi_rx_probe, 734 .rx_init = efx_mcdi_rx_init, 735 .rx_remove = efx_mcdi_rx_remove, 736 .rx_write = ef100_rx_write, 737 .rx_packet = __ef100_rx_packet, 738 .rx_buf_hash_valid = ef100_rx_buf_hash_valid, 739 .fini_dmaq = efx_fini_dmaq, 740 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 741 .filter_table_probe = ef100_filter_table_up, 742 .filter_table_restore = efx_mcdi_filter_table_restore, 743 .filter_table_remove = ef100_filter_table_down, 744 .filter_insert = efx_mcdi_filter_insert, 745 .filter_remove_safe = efx_mcdi_filter_remove_safe, 746 .filter_get_safe = efx_mcdi_filter_get_safe, 747 .filter_clear_rx = efx_mcdi_filter_clear_rx, 748 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 749 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 750 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 751 #ifdef CONFIG_RFS_ACCEL 752 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 753 #endif 754 755 .get_phys_port_id = efx_ef100_get_phys_port_id, 756 757 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN, 758 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8, 759 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8, 760 .rx_hash_key_size = 40, 761 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 762 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 763 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config, 764 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config, 765 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 766 767 .reconfigure_mac = ef100_reconfigure_mac, 768 .reconfigure_port = efx_mcdi_port_reconfigure, 769 .test_nvram = efx_new_mcdi_nvram_test_all, 770 .describe_stats = ef100_describe_stats, 771 .start_stats = efx_mcdi_mac_start_stats, 772 .update_stats = ef100_update_stats, 773 .pull_stats = efx_mcdi_mac_pull_stats, 774 .stop_stats = efx_mcdi_mac_stop_stats, 775 776 /* Per-type bar/size configuration not used on ef100. Location of 777 * registers is defined by extended capabilities. 778 */ 779 .mem_bar = NULL, 780 .mem_map_size = NULL, 781 782 }; 783 784 const struct efx_nic_type ef100_vf_nic_type = { 785 .revision = EFX_REV_EF100, 786 .is_vf = true, 787 .probe = ef100_probe_vf, 788 .offload_features = EF100_OFFLOAD_FEATURES, 789 .mcdi_max_ver = 2, 790 .mcdi_request = ef100_mcdi_request, 791 .mcdi_poll_response = ef100_mcdi_poll_response, 792 .mcdi_read_response = ef100_mcdi_read_response, 793 .mcdi_poll_reboot = ef100_mcdi_poll_reboot, 794 .mcdi_reboot_detected = ef100_mcdi_reboot_detected, 795 .irq_enable_master = efx_port_dummy_op_void, 796 .irq_test_generate = efx_ef100_irq_test_generate, 797 .irq_disable_non_ev = efx_port_dummy_op_void, 798 .push_irq_moderation = efx_channel_dummy_op_void, 799 .min_interrupt_mode = EFX_INT_MODE_MSIX, 800 .map_reset_reason = ef100_map_reset_reason, 801 .map_reset_flags = ef100_map_reset_flags, 802 .reset = ef100_reset, 803 .check_caps = ef100_check_caps, 804 .ev_probe = ef100_ev_probe, 805 .ev_init = ef100_ev_init, 806 .ev_fini = efx_mcdi_ev_fini, 807 .ev_remove = efx_mcdi_ev_remove, 808 .irq_handle_msi = ef100_msi_interrupt, 809 .ev_process = ef100_ev_process, 810 .ev_read_ack = ef100_ev_read_ack, 811 .ev_test_generate = efx_ef100_ev_test_generate, 812 .tx_probe = ef100_tx_probe, 813 .tx_init = ef100_tx_init, 814 .tx_write = ef100_tx_write, 815 .tx_enqueue = ef100_enqueue_skb, 816 .rx_probe = efx_mcdi_rx_probe, 817 .rx_init = efx_mcdi_rx_init, 818 .rx_remove = efx_mcdi_rx_remove, 819 .rx_write = ef100_rx_write, 820 .rx_packet = __ef100_rx_packet, 821 .rx_buf_hash_valid = ef100_rx_buf_hash_valid, 822 .fini_dmaq = efx_fini_dmaq, 823 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 824 .filter_table_probe = ef100_filter_table_up, 825 .filter_table_restore = efx_mcdi_filter_table_restore, 826 .filter_table_remove = ef100_filter_table_down, 827 .filter_insert = efx_mcdi_filter_insert, 828 .filter_remove_safe = efx_mcdi_filter_remove_safe, 829 .filter_get_safe = efx_mcdi_filter_get_safe, 830 .filter_clear_rx = efx_mcdi_filter_clear_rx, 831 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 832 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 833 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 834 #ifdef CONFIG_RFS_ACCEL 835 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 836 #endif 837 838 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN, 839 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8, 840 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8, 841 .rx_hash_key_size = 40, 842 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 843 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 844 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 845 846 .reconfigure_mac = ef100_reconfigure_mac, 847 .test_nvram = efx_new_mcdi_nvram_test_all, 848 .describe_stats = ef100_describe_stats, 849 .start_stats = efx_mcdi_mac_start_stats, 850 .update_stats = ef100_update_stats, 851 .pull_stats = efx_mcdi_mac_pull_stats, 852 .stop_stats = efx_mcdi_mac_stop_stats, 853 854 .mem_bar = NULL, 855 .mem_map_size = NULL, 856 857 }; 858 859 static int compare_versions(const char *a, const char *b) 860 { 861 int a_major, a_minor, a_point, a_patch; 862 int b_major, b_minor, b_point, b_patch; 863 int a_matched, b_matched; 864 865 a_matched = sscanf(a, "%d.%d.%d.%d", &a_major, &a_minor, &a_point, &a_patch); 866 b_matched = sscanf(b, "%d.%d.%d.%d", &b_major, &b_minor, &b_point, &b_patch); 867 868 if (a_matched == 4 && b_matched != 4) 869 return +1; 870 871 if (a_matched != 4 && b_matched == 4) 872 return -1; 873 874 if (a_matched != 4 && b_matched != 4) 875 return 0; 876 877 if (a_major != b_major) 878 return a_major - b_major; 879 880 if (a_minor != b_minor) 881 return a_minor - b_minor; 882 883 if (a_point != b_point) 884 return a_point - b_point; 885 886 return a_patch - b_patch; 887 } 888 889 enum ef100_tlv_state_machine { 890 EF100_TLV_TYPE, 891 EF100_TLV_TYPE_CONT, 892 EF100_TLV_LENGTH, 893 EF100_TLV_VALUE 894 }; 895 896 struct ef100_tlv_state { 897 enum ef100_tlv_state_machine state; 898 u64 value; 899 u32 value_offset; 900 u16 type; 901 u8 len; 902 }; 903 904 static int ef100_tlv_feed(struct ef100_tlv_state *state, u8 byte) 905 { 906 switch (state->state) { 907 case EF100_TLV_TYPE: 908 state->type = byte & 0x7f; 909 state->state = (byte & 0x80) ? EF100_TLV_TYPE_CONT 910 : EF100_TLV_LENGTH; 911 /* Clear ready to read in a new entry */ 912 state->value = 0; 913 state->value_offset = 0; 914 return 0; 915 case EF100_TLV_TYPE_CONT: 916 state->type |= byte << 7; 917 state->state = EF100_TLV_LENGTH; 918 return 0; 919 case EF100_TLV_LENGTH: 920 state->len = byte; 921 /* We only handle TLVs that fit in a u64 */ 922 if (state->len > sizeof(state->value)) 923 return -EOPNOTSUPP; 924 /* len may be zero, implying a value of zero */ 925 state->state = state->len ? EF100_TLV_VALUE : EF100_TLV_TYPE; 926 return 0; 927 case EF100_TLV_VALUE: 928 state->value |= ((u64)byte) << (state->value_offset * 8); 929 state->value_offset++; 930 if (state->value_offset >= state->len) 931 state->state = EF100_TLV_TYPE; 932 return 0; 933 default: /* state machine error, can't happen */ 934 WARN_ON_ONCE(1); 935 return -EIO; 936 } 937 } 938 939 static int ef100_process_design_param(struct efx_nic *efx, 940 const struct ef100_tlv_state *reader) 941 { 942 struct ef100_nic_data *nic_data = efx->nic_data; 943 944 switch (reader->type) { 945 case ESE_EF100_DP_GZ_PAD: /* padding, skip it */ 946 return 0; 947 case ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS: 948 /* Driver doesn't support timestamping yet, so we don't care */ 949 return 0; 950 case ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS: 951 /* Driver doesn't support unsolicited-event credits yet, so 952 * we don't care 953 */ 954 return 0; 955 case ESE_EF100_DP_GZ_NMMU_GROUP_SIZE: 956 /* Driver doesn't manage the NMMU (so we don't care) */ 957 return 0; 958 case ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS: 959 /* Driver uses CHECKSUM_COMPLETE, so we don't care about 960 * protocol checksum validation 961 */ 962 return 0; 963 case ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN: 964 nic_data->tso_max_hdr_len = min_t(u64, reader->value, 0xffff); 965 return 0; 966 case ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS: 967 /* We always put HDR_NUM_SEGS=1 in our TSO descriptors */ 968 if (!reader->value) { 969 netif_err(efx, probe, efx->net_dev, 970 "TSO_MAX_HDR_NUM_SEGS < 1\n"); 971 return -EOPNOTSUPP; 972 } 973 return 0; 974 case ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY: 975 case ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY: 976 /* Our TXQ and RXQ sizes are always power-of-two and thus divisible by 977 * EFX_MIN_DMAQ_SIZE, so we just need to check that 978 * EFX_MIN_DMAQ_SIZE is divisible by GRANULARITY. 979 * This is very unlikely to fail. 980 */ 981 if (!reader->value || reader->value > EFX_MIN_DMAQ_SIZE || 982 EFX_MIN_DMAQ_SIZE % (u32)reader->value) { 983 netif_err(efx, probe, efx->net_dev, 984 "%s size granularity is %llu, can't guarantee safety\n", 985 reader->type == ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY ? "RXQ" : "TXQ", 986 reader->value); 987 return -EOPNOTSUPP; 988 } 989 return 0; 990 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN: 991 nic_data->tso_max_payload_len = min_t(u64, reader->value, GSO_MAX_SIZE); 992 efx->net_dev->gso_max_size = nic_data->tso_max_payload_len; 993 return 0; 994 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS: 995 nic_data->tso_max_payload_num_segs = min_t(u64, reader->value, 0xffff); 996 efx->net_dev->gso_max_segs = nic_data->tso_max_payload_num_segs; 997 return 0; 998 case ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES: 999 nic_data->tso_max_frames = min_t(u64, reader->value, 0xffff); 1000 return 0; 1001 case ESE_EF100_DP_GZ_COMPAT: 1002 if (reader->value) { 1003 netif_err(efx, probe, efx->net_dev, 1004 "DP_COMPAT has unknown bits %#llx, driver not compatible with this hw\n", 1005 reader->value); 1006 return -EOPNOTSUPP; 1007 } 1008 return 0; 1009 case ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN: 1010 /* Driver doesn't use mem2mem transfers */ 1011 return 0; 1012 case ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS: 1013 /* Driver doesn't currently use EVQ_TIMER */ 1014 return 0; 1015 case ESE_EF100_DP_GZ_NMMU_PAGE_SIZES: 1016 /* Driver doesn't manage the NMMU (so we don't care) */ 1017 return 0; 1018 case ESE_EF100_DP_GZ_VI_STRIDES: 1019 /* We never try to set the VI stride, and we don't rely on 1020 * being able to find VIs past VI 0 until after we've learned 1021 * the current stride from MC_CMD_GET_CAPABILITIES. 1022 * So the value of this shouldn't matter. 1023 */ 1024 if (reader->value != ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT) 1025 netif_dbg(efx, probe, efx->net_dev, 1026 "NIC has other than default VI_STRIDES (mask " 1027 "%#llx), early probing might use wrong one\n", 1028 reader->value); 1029 return 0; 1030 case ESE_EF100_DP_GZ_RX_MAX_RUNT: 1031 /* Driver doesn't look at L2_STATUS:LEN_ERR bit, so we don't 1032 * care whether it indicates runt or overlength for any given 1033 * packet, so we don't care about this parameter. 1034 */ 1035 return 0; 1036 default: 1037 /* Host interface says "Drivers should ignore design parameters 1038 * that they do not recognise." 1039 */ 1040 netif_dbg(efx, probe, efx->net_dev, 1041 "Ignoring unrecognised design parameter %u\n", 1042 reader->type); 1043 return 0; 1044 } 1045 } 1046 1047 static int ef100_check_design_params(struct efx_nic *efx) 1048 { 1049 struct ef100_tlv_state reader = {}; 1050 u32 total_len, offset = 0; 1051 efx_dword_t reg; 1052 int rc = 0, i; 1053 u32 data; 1054 1055 efx_readd(efx, ®, ER_GZ_PARAMS_TLV_LEN); 1056 total_len = EFX_DWORD_FIELD(reg, EFX_DWORD_0); 1057 netif_dbg(efx, probe, efx->net_dev, "%u bytes of design parameters\n", 1058 total_len); 1059 while (offset < total_len) { 1060 efx_readd(efx, ®, ER_GZ_PARAMS_TLV + offset); 1061 data = EFX_DWORD_FIELD(reg, EFX_DWORD_0); 1062 for (i = 0; i < sizeof(data); i++) { 1063 rc = ef100_tlv_feed(&reader, data); 1064 /* Got a complete value? */ 1065 if (!rc && reader.state == EF100_TLV_TYPE) 1066 rc = ef100_process_design_param(efx, &reader); 1067 if (rc) 1068 goto out; 1069 data >>= 8; 1070 offset++; 1071 } 1072 } 1073 /* Check we didn't end halfway through a TLV entry, which could either 1074 * mean that the TLV stream is truncated or just that it's corrupted 1075 * and our state machine is out of sync. 1076 */ 1077 if (reader.state != EF100_TLV_TYPE) { 1078 if (reader.state == EF100_TLV_TYPE_CONT) 1079 netif_err(efx, probe, efx->net_dev, 1080 "truncated design parameter (incomplete type %u)\n", 1081 reader.type); 1082 else 1083 netif_err(efx, probe, efx->net_dev, 1084 "truncated design parameter %u\n", 1085 reader.type); 1086 rc = -EIO; 1087 } 1088 out: 1089 return rc; 1090 } 1091 1092 /* NIC probe and remove 1093 */ 1094 static int ef100_probe_main(struct efx_nic *efx) 1095 { 1096 unsigned int bar_size = resource_size(&efx->pci_dev->resource[efx->mem_bar]); 1097 struct net_device *net_dev = efx->net_dev; 1098 struct ef100_nic_data *nic_data; 1099 char fw_version[32]; 1100 int i, rc; 1101 1102 if (WARN_ON(bar_size == 0)) 1103 return -EIO; 1104 1105 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 1106 if (!nic_data) 1107 return -ENOMEM; 1108 efx->nic_data = nic_data; 1109 nic_data->efx = efx; 1110 net_dev->features |= efx->type->offload_features; 1111 net_dev->hw_features |= efx->type->offload_features; 1112 net_dev->hw_enc_features |= efx->type->offload_features; 1113 net_dev->vlan_features |= NETIF_F_HW_CSUM | NETIF_F_SG | 1114 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO; 1115 1116 /* Populate design-parameter defaults */ 1117 nic_data->tso_max_hdr_len = ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT; 1118 nic_data->tso_max_frames = ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT; 1119 nic_data->tso_max_payload_num_segs = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT; 1120 nic_data->tso_max_payload_len = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT; 1121 net_dev->gso_max_segs = ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT; 1122 /* Read design parameters */ 1123 rc = ef100_check_design_params(efx); 1124 if (rc) { 1125 netif_err(efx, probe, efx->net_dev, 1126 "Unsupported design parameters\n"); 1127 goto fail; 1128 } 1129 1130 /* we assume later that we can copy from this buffer in dwords */ 1131 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 1132 1133 /* MCDI buffers must be 256 byte aligned. */ 1134 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, MCDI_BUF_LEN, 1135 GFP_KERNEL); 1136 if (rc) 1137 goto fail; 1138 1139 /* Get the MC's warm boot count. In case it's rebooting right 1140 * now, be prepared to retry. 1141 */ 1142 i = 0; 1143 for (;;) { 1144 rc = ef100_get_warm_boot_count(efx); 1145 if (rc >= 0) 1146 break; 1147 if (++i == 5) 1148 goto fail; 1149 ssleep(1); 1150 } 1151 nic_data->warm_boot_count = rc; 1152 1153 /* In case we're recovering from a crash (kexec), we want to 1154 * cancel any outstanding request by the previous user of this 1155 * function. We send a special message using the least 1156 * significant bits of the 'high' (doorbell) register. 1157 */ 1158 _efx_writed(efx, cpu_to_le32(1), efx_reg(efx, ER_GZ_MC_DB_HWRD)); 1159 1160 /* Post-IO section. */ 1161 1162 rc = efx_mcdi_init(efx); 1163 if (!rc && efx->mcdi->fn_flags & 1164 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT)) { 1165 netif_info(efx, probe, efx->net_dev, 1166 "No network port on this PCI function"); 1167 rc = -ENODEV; 1168 } 1169 if (rc) 1170 goto fail; 1171 /* Reset (most) configuration for this function */ 1172 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 1173 if (rc) 1174 goto fail; 1175 /* Enable event logging */ 1176 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 1177 if (rc) 1178 goto fail; 1179 1180 rc = efx_get_pf_index(efx, &nic_data->pf_index); 1181 if (rc) 1182 goto fail; 1183 1184 rc = efx_ef100_init_datapath_caps(efx); 1185 if (rc < 0) 1186 goto fail; 1187 1188 efx->max_vis = EF100_MAX_VIS; 1189 1190 rc = efx_mcdi_port_get_number(efx); 1191 if (rc < 0) 1192 goto fail; 1193 efx->port_num = rc; 1194 1195 efx_mcdi_print_fwver(efx, fw_version, sizeof(fw_version)); 1196 netif_dbg(efx, drv, efx->net_dev, "Firmware version %s\n", fw_version); 1197 1198 if (compare_versions(fw_version, "1.1.0.1000") < 0) { 1199 netif_info(efx, drv, efx->net_dev, "Firmware uses old event descriptors\n"); 1200 rc = -EINVAL; 1201 goto fail; 1202 } 1203 1204 if (efx_has_cap(efx, UNSOL_EV_CREDIT_SUPPORTED)) { 1205 netif_info(efx, drv, efx->net_dev, "Firmware uses unsolicited-event credits\n"); 1206 rc = -EINVAL; 1207 goto fail; 1208 } 1209 1210 rc = ef100_phy_probe(efx); 1211 if (rc) 1212 goto fail; 1213 1214 down_write(&efx->filter_sem); 1215 rc = ef100_filter_table_probe(efx); 1216 up_write(&efx->filter_sem); 1217 if (rc) 1218 goto fail; 1219 1220 netdev_rss_key_fill(efx->rss_context.rx_hash_key, 1221 sizeof(efx->rss_context.rx_hash_key)); 1222 1223 /* Don't fail init if RSS setup doesn't work. */ 1224 efx_mcdi_push_default_indir_table(efx, efx->n_rx_channels); 1225 1226 rc = ef100_register_netdev(efx); 1227 if (rc) 1228 goto fail; 1229 1230 return 0; 1231 fail: 1232 return rc; 1233 } 1234 1235 int ef100_probe_pf(struct efx_nic *efx) 1236 { 1237 struct net_device *net_dev = efx->net_dev; 1238 struct ef100_nic_data *nic_data; 1239 int rc = ef100_probe_main(efx); 1240 1241 if (rc) 1242 goto fail; 1243 1244 nic_data = efx->nic_data; 1245 rc = ef100_get_mac_address(efx, net_dev->perm_addr); 1246 if (rc) 1247 goto fail; 1248 /* Assign MAC address */ 1249 memcpy(net_dev->dev_addr, net_dev->perm_addr, ETH_ALEN); 1250 memcpy(nic_data->port_id, net_dev->perm_addr, ETH_ALEN); 1251 1252 return 0; 1253 1254 fail: 1255 return rc; 1256 } 1257 1258 int ef100_probe_vf(struct efx_nic *efx) 1259 { 1260 return ef100_probe_main(efx); 1261 } 1262 1263 void ef100_remove(struct efx_nic *efx) 1264 { 1265 struct ef100_nic_data *nic_data = efx->nic_data; 1266 1267 ef100_unregister_netdev(efx); 1268 1269 down_write(&efx->filter_sem); 1270 efx_mcdi_filter_table_remove(efx); 1271 up_write(&efx->filter_sem); 1272 efx_fini_channels(efx); 1273 kfree(efx->phy_data); 1274 efx->phy_data = NULL; 1275 efx_mcdi_detach(efx); 1276 efx_mcdi_fini(efx); 1277 if (nic_data) 1278 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 1279 kfree(nic_data); 1280 efx->nic_data = NULL; 1281 } 1282