1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2018 Solarflare Communications Inc. 5 * Copyright 2019-2020 Xilinx Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation, incorporated herein by reference. 10 */ 11 12 #include "ef100_nic.h" 13 #include "efx_common.h" 14 #include "efx_channels.h" 15 #include "io.h" 16 #include "selftest.h" 17 #include "ef100_regs.h" 18 #include "mcdi.h" 19 #include "mcdi_pcol.h" 20 #include "mcdi_port_common.h" 21 #include "mcdi_functions.h" 22 #include "mcdi_filters.h" 23 #include "ef100_rx.h" 24 #include "ef100_tx.h" 25 #include "ef100_netdev.h" 26 27 #define EF100_MAX_VIS 4096 28 #define EF100_NUM_MCDI_BUFFERS 1 29 #define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX) 30 31 #define EF100_RESET_PORT ((ETH_RESET_MAC | ETH_RESET_PHY) << ETH_RESET_SHARED_SHIFT) 32 33 /* MCDI 34 */ 35 static u8 *ef100_mcdi_buf(struct efx_nic *efx, u8 bufid, dma_addr_t *dma_addr) 36 { 37 struct ef100_nic_data *nic_data = efx->nic_data; 38 39 if (dma_addr) 40 *dma_addr = nic_data->mcdi_buf.dma_addr + 41 bufid * ALIGN(MCDI_BUF_LEN, 256); 42 return nic_data->mcdi_buf.addr + bufid * ALIGN(MCDI_BUF_LEN, 256); 43 } 44 45 static int ef100_get_warm_boot_count(struct efx_nic *efx) 46 { 47 efx_dword_t reg; 48 49 efx_readd(efx, ®, efx_reg(efx, ER_GZ_MC_SFT_STATUS)); 50 51 if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) == 0xffffffff) { 52 netif_err(efx, hw, efx->net_dev, "Hardware unavailable\n"); 53 efx->state = STATE_DISABLED; 54 return -ENETDOWN; 55 } else { 56 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 57 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 58 } 59 } 60 61 static void ef100_mcdi_request(struct efx_nic *efx, 62 const efx_dword_t *hdr, size_t hdr_len, 63 const efx_dword_t *sdu, size_t sdu_len) 64 { 65 dma_addr_t dma_addr; 66 u8 *pdu = ef100_mcdi_buf(efx, 0, &dma_addr); 67 68 memcpy(pdu, hdr, hdr_len); 69 memcpy(pdu + hdr_len, sdu, sdu_len); 70 wmb(); 71 72 /* The hardware provides 'low' and 'high' (doorbell) registers 73 * for passing the 64-bit address of an MCDI request to 74 * firmware. However the dwords are swapped by firmware. The 75 * least significant bits of the doorbell are then 0 for all 76 * MCDI requests due to alignment. 77 */ 78 _efx_writed(efx, cpu_to_le32((u64)dma_addr >> 32), efx_reg(efx, ER_GZ_MC_DB_LWRD)); 79 _efx_writed(efx, cpu_to_le32((u32)dma_addr), efx_reg(efx, ER_GZ_MC_DB_HWRD)); 80 } 81 82 static bool ef100_mcdi_poll_response(struct efx_nic *efx) 83 { 84 const efx_dword_t hdr = 85 *(const efx_dword_t *)(ef100_mcdi_buf(efx, 0, NULL)); 86 87 rmb(); 88 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 89 } 90 91 static void ef100_mcdi_read_response(struct efx_nic *efx, 92 efx_dword_t *outbuf, size_t offset, 93 size_t outlen) 94 { 95 const u8 *pdu = ef100_mcdi_buf(efx, 0, NULL); 96 97 memcpy(outbuf, pdu + offset, outlen); 98 } 99 100 static int ef100_mcdi_poll_reboot(struct efx_nic *efx) 101 { 102 struct ef100_nic_data *nic_data = efx->nic_data; 103 int rc; 104 105 rc = ef100_get_warm_boot_count(efx); 106 if (rc < 0) { 107 /* The firmware is presumably in the process of 108 * rebooting. However, we are supposed to report each 109 * reboot just once, so we must only do that once we 110 * can read and store the updated warm boot count. 111 */ 112 return 0; 113 } 114 115 if (rc == nic_data->warm_boot_count) 116 return 0; 117 118 nic_data->warm_boot_count = rc; 119 120 return -EIO; 121 } 122 123 static void ef100_mcdi_reboot_detected(struct efx_nic *efx) 124 { 125 } 126 127 /* MCDI calls 128 */ 129 static int ef100_get_mac_address(struct efx_nic *efx, u8 *mac_address) 130 { 131 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 132 size_t outlen; 133 int rc; 134 135 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 136 137 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 138 outbuf, sizeof(outbuf), &outlen); 139 if (rc) 140 return rc; 141 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 142 return -EIO; 143 144 ether_addr_copy(mac_address, 145 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 146 return 0; 147 } 148 149 static int efx_ef100_init_datapath_caps(struct efx_nic *efx) 150 { 151 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V7_OUT_LEN); 152 struct ef100_nic_data *nic_data = efx->nic_data; 153 u8 vi_window_mode; 154 size_t outlen; 155 int rc; 156 157 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 158 159 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 160 outbuf, sizeof(outbuf), &outlen); 161 if (rc) 162 return rc; 163 if (outlen < MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) { 164 netif_err(efx, drv, efx->net_dev, 165 "unable to read datapath firmware capabilities\n"); 166 return -EIO; 167 } 168 169 nic_data->datapath_caps = MCDI_DWORD(outbuf, 170 GET_CAPABILITIES_OUT_FLAGS1); 171 nic_data->datapath_caps2 = MCDI_DWORD(outbuf, 172 GET_CAPABILITIES_V2_OUT_FLAGS2); 173 if (outlen < MC_CMD_GET_CAPABILITIES_V7_OUT_LEN) 174 nic_data->datapath_caps3 = 0; 175 else 176 nic_data->datapath_caps3 = MCDI_DWORD(outbuf, 177 GET_CAPABILITIES_V7_OUT_FLAGS3); 178 179 vi_window_mode = MCDI_BYTE(outbuf, 180 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); 181 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode); 182 if (rc) 183 return rc; 184 185 if (efx_ef100_has_cap(nic_data->datapath_caps2, TX_TSO_V3)) { 186 struct net_device *net_dev = efx->net_dev; 187 netdev_features_t tso = NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_PARTIAL | 188 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM | 189 NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM; 190 191 net_dev->features |= tso; 192 net_dev->hw_features |= tso; 193 net_dev->hw_enc_features |= tso; 194 /* EF100 HW can only offload outer checksums if they are UDP, 195 * so for GRE_CSUM we have to use GSO_PARTIAL. 196 */ 197 net_dev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 198 } 199 efx->num_mac_stats = MCDI_WORD(outbuf, 200 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS); 201 netif_dbg(efx, probe, efx->net_dev, 202 "firmware reports num_mac_stats = %u\n", 203 efx->num_mac_stats); 204 return 0; 205 } 206 207 /* Event handling 208 */ 209 static int ef100_ev_probe(struct efx_channel *channel) 210 { 211 /* Allocate an extra descriptor for the QMDA status completion entry */ 212 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, 213 (channel->eventq_mask + 2) * 214 sizeof(efx_qword_t), 215 GFP_KERNEL); 216 } 217 218 static int ef100_ev_init(struct efx_channel *channel) 219 { 220 struct ef100_nic_data *nic_data = channel->efx->nic_data; 221 222 /* initial phase is 0 */ 223 clear_bit(channel->channel, nic_data->evq_phases); 224 225 return efx_mcdi_ev_init(channel, false, false); 226 } 227 228 static void ef100_ev_read_ack(struct efx_channel *channel) 229 { 230 efx_dword_t evq_prime; 231 232 EFX_POPULATE_DWORD_2(evq_prime, 233 ERF_GZ_EVQ_ID, channel->channel, 234 ERF_GZ_IDX, channel->eventq_read_ptr & 235 channel->eventq_mask); 236 237 efx_writed(channel->efx, &evq_prime, 238 efx_reg(channel->efx, ER_GZ_EVQ_INT_PRIME)); 239 } 240 241 static int ef100_ev_process(struct efx_channel *channel, int quota) 242 { 243 struct efx_nic *efx = channel->efx; 244 struct ef100_nic_data *nic_data; 245 bool evq_phase, old_evq_phase; 246 unsigned int read_ptr; 247 efx_qword_t *p_event; 248 int spent = 0; 249 bool ev_phase; 250 int ev_type; 251 252 if (unlikely(!channel->enabled)) 253 return 0; 254 255 nic_data = efx->nic_data; 256 evq_phase = test_bit(channel->channel, nic_data->evq_phases); 257 old_evq_phase = evq_phase; 258 read_ptr = channel->eventq_read_ptr; 259 BUILD_BUG_ON(ESF_GZ_EV_RXPKTS_PHASE_LBN != ESF_GZ_EV_TXCMPL_PHASE_LBN); 260 261 while (spent < quota) { 262 p_event = efx_event(channel, read_ptr); 263 264 ev_phase = !!EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_PHASE); 265 if (ev_phase != evq_phase) 266 break; 267 268 netif_vdbg(efx, drv, efx->net_dev, 269 "processing event on %d " EFX_QWORD_FMT "\n", 270 channel->channel, EFX_QWORD_VAL(*p_event)); 271 272 ev_type = EFX_QWORD_FIELD(*p_event, ESF_GZ_E_TYPE); 273 274 switch (ev_type) { 275 case ESE_GZ_EF100_EV_RX_PKTS: 276 efx_ef100_ev_rx(channel, p_event); 277 ++spent; 278 break; 279 case ESE_GZ_EF100_EV_MCDI: 280 efx_mcdi_process_event(channel, p_event); 281 break; 282 case ESE_GZ_EF100_EV_TX_COMPLETION: 283 ef100_ev_tx(channel, p_event); 284 break; 285 case ESE_GZ_EF100_EV_DRIVER: 286 netif_info(efx, drv, efx->net_dev, 287 "Driver initiated event " EFX_QWORD_FMT "\n", 288 EFX_QWORD_VAL(*p_event)); 289 break; 290 default: 291 netif_info(efx, drv, efx->net_dev, 292 "Unhandled event " EFX_QWORD_FMT "\n", 293 EFX_QWORD_VAL(*p_event)); 294 } 295 296 ++read_ptr; 297 if ((read_ptr & channel->eventq_mask) == 0) 298 evq_phase = !evq_phase; 299 } 300 301 channel->eventq_read_ptr = read_ptr; 302 if (evq_phase != old_evq_phase) 303 change_bit(channel->channel, nic_data->evq_phases); 304 305 return spent; 306 } 307 308 static irqreturn_t ef100_msi_interrupt(int irq, void *dev_id) 309 { 310 struct efx_msi_context *context = dev_id; 311 struct efx_nic *efx = context->efx; 312 313 netif_vdbg(efx, intr, efx->net_dev, 314 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 315 316 if (likely(READ_ONCE(efx->irq_soft_enabled))) { 317 /* Note test interrupts */ 318 if (context->index == efx->irq_level) 319 efx->last_irq_cpu = raw_smp_processor_id(); 320 321 /* Schedule processing of the channel */ 322 efx_schedule_channel_irq(efx->channel[context->index]); 323 } 324 325 return IRQ_HANDLED; 326 } 327 328 static int ef100_phy_probe(struct efx_nic *efx) 329 { 330 struct efx_mcdi_phy_data *phy_data; 331 int rc; 332 333 /* Probe for the PHY */ 334 efx->phy_data = kzalloc(sizeof(struct efx_mcdi_phy_data), GFP_KERNEL); 335 if (!efx->phy_data) 336 return -ENOMEM; 337 338 rc = efx_mcdi_get_phy_cfg(efx, efx->phy_data); 339 if (rc) 340 return rc; 341 342 /* Populate driver and ethtool settings */ 343 phy_data = efx->phy_data; 344 mcdi_to_ethtool_linkset(phy_data->media, phy_data->supported_cap, 345 efx->link_advertising); 346 efx->fec_config = mcdi_fec_caps_to_ethtool(phy_data->supported_cap, 347 false); 348 349 /* Default to Autonegotiated flow control if the PHY supports it */ 350 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; 351 if (phy_data->supported_cap & (1 << MC_CMD_PHY_CAP_AN_LBN)) 352 efx->wanted_fc |= EFX_FC_AUTO; 353 efx_link_set_wanted_fc(efx, efx->wanted_fc); 354 355 /* Push settings to the PHY. Failure is not fatal, the user can try to 356 * fix it using ethtool. 357 */ 358 rc = efx_mcdi_port_reconfigure(efx); 359 if (rc && rc != -EPERM) 360 netif_warn(efx, drv, efx->net_dev, 361 "could not initialise PHY settings\n"); 362 363 return 0; 364 } 365 366 static int ef100_filter_table_probe(struct efx_nic *efx) 367 { 368 return efx_mcdi_filter_table_probe(efx, true); 369 } 370 371 static int ef100_filter_table_up(struct efx_nic *efx) 372 { 373 int rc; 374 375 rc = efx_mcdi_filter_add_vlan(efx, EFX_FILTER_VID_UNSPEC); 376 if (rc) { 377 efx_mcdi_filter_table_down(efx); 378 return rc; 379 } 380 381 rc = efx_mcdi_filter_add_vlan(efx, 0); 382 if (rc) { 383 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC); 384 efx_mcdi_filter_table_down(efx); 385 } 386 387 return rc; 388 } 389 390 static void ef100_filter_table_down(struct efx_nic *efx) 391 { 392 efx_mcdi_filter_del_vlan(efx, 0); 393 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC); 394 efx_mcdi_filter_table_down(efx); 395 } 396 397 /* Other 398 */ 399 static int ef100_reconfigure_mac(struct efx_nic *efx, bool mtu_only) 400 { 401 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 402 403 efx_mcdi_filter_sync_rx_mode(efx); 404 405 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED)) 406 return efx_mcdi_set_mtu(efx); 407 return efx_mcdi_set_mac(efx); 408 } 409 410 static enum reset_type ef100_map_reset_reason(enum reset_type reason) 411 { 412 if (reason == RESET_TYPE_TX_WATCHDOG) 413 return reason; 414 return RESET_TYPE_DISABLE; 415 } 416 417 static int ef100_map_reset_flags(u32 *flags) 418 { 419 /* Only perform a RESET_TYPE_ALL because we don't support MC_REBOOTs */ 420 if ((*flags & EF100_RESET_PORT)) { 421 *flags &= ~EF100_RESET_PORT; 422 return RESET_TYPE_ALL; 423 } 424 if (*flags & ETH_RESET_MGMT) { 425 *flags &= ~ETH_RESET_MGMT; 426 return RESET_TYPE_DISABLE; 427 } 428 429 return -EINVAL; 430 } 431 432 static int ef100_reset(struct efx_nic *efx, enum reset_type reset_type) 433 { 434 int rc; 435 436 dev_close(efx->net_dev); 437 438 if (reset_type == RESET_TYPE_TX_WATCHDOG) { 439 netif_device_attach(efx->net_dev); 440 __clear_bit(reset_type, &efx->reset_pending); 441 rc = dev_open(efx->net_dev, NULL); 442 } else if (reset_type == RESET_TYPE_ALL) { 443 rc = efx_mcdi_reset(efx, reset_type); 444 if (rc) 445 return rc; 446 447 netif_device_attach(efx->net_dev); 448 449 rc = dev_open(efx->net_dev, NULL); 450 } else { 451 rc = 1; /* Leave the device closed */ 452 } 453 return rc; 454 } 455 456 static void ef100_common_stat_mask(unsigned long *mask) 457 { 458 __set_bit(EF100_STAT_port_rx_packets, mask); 459 __set_bit(EF100_STAT_port_tx_packets, mask); 460 __set_bit(EF100_STAT_port_rx_bytes, mask); 461 __set_bit(EF100_STAT_port_tx_bytes, mask); 462 __set_bit(EF100_STAT_port_rx_multicast, mask); 463 __set_bit(EF100_STAT_port_rx_bad, mask); 464 __set_bit(EF100_STAT_port_rx_align_error, mask); 465 __set_bit(EF100_STAT_port_rx_overflow, mask); 466 } 467 468 static void ef100_ethtool_stat_mask(unsigned long *mask) 469 { 470 __set_bit(EF100_STAT_port_tx_pause, mask); 471 __set_bit(EF100_STAT_port_tx_unicast, mask); 472 __set_bit(EF100_STAT_port_tx_multicast, mask); 473 __set_bit(EF100_STAT_port_tx_broadcast, mask); 474 __set_bit(EF100_STAT_port_tx_lt64, mask); 475 __set_bit(EF100_STAT_port_tx_64, mask); 476 __set_bit(EF100_STAT_port_tx_65_to_127, mask); 477 __set_bit(EF100_STAT_port_tx_128_to_255, mask); 478 __set_bit(EF100_STAT_port_tx_256_to_511, mask); 479 __set_bit(EF100_STAT_port_tx_512_to_1023, mask); 480 __set_bit(EF100_STAT_port_tx_1024_to_15xx, mask); 481 __set_bit(EF100_STAT_port_tx_15xx_to_jumbo, mask); 482 __set_bit(EF100_STAT_port_rx_good, mask); 483 __set_bit(EF100_STAT_port_rx_pause, mask); 484 __set_bit(EF100_STAT_port_rx_unicast, mask); 485 __set_bit(EF100_STAT_port_rx_broadcast, mask); 486 __set_bit(EF100_STAT_port_rx_lt64, mask); 487 __set_bit(EF100_STAT_port_rx_64, mask); 488 __set_bit(EF100_STAT_port_rx_65_to_127, mask); 489 __set_bit(EF100_STAT_port_rx_128_to_255, mask); 490 __set_bit(EF100_STAT_port_rx_256_to_511, mask); 491 __set_bit(EF100_STAT_port_rx_512_to_1023, mask); 492 __set_bit(EF100_STAT_port_rx_1024_to_15xx, mask); 493 __set_bit(EF100_STAT_port_rx_15xx_to_jumbo, mask); 494 __set_bit(EF100_STAT_port_rx_gtjumbo, mask); 495 __set_bit(EF100_STAT_port_rx_bad_gtjumbo, mask); 496 __set_bit(EF100_STAT_port_rx_length_error, mask); 497 __set_bit(EF100_STAT_port_rx_nodesc_drops, mask); 498 __set_bit(GENERIC_STAT_rx_nodesc_trunc, mask); 499 __set_bit(GENERIC_STAT_rx_noskb_drops, mask); 500 } 501 502 #define EF100_DMA_STAT(ext_name, mcdi_name) \ 503 [EF100_STAT_ ## ext_name] = \ 504 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 505 506 static const struct efx_hw_stat_desc ef100_stat_desc[EF100_STAT_COUNT] = { 507 EF100_DMA_STAT(port_tx_bytes, TX_BYTES), 508 EF100_DMA_STAT(port_tx_packets, TX_PKTS), 509 EF100_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 510 EF100_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 511 EF100_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 512 EF100_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 513 EF100_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 514 EF100_DMA_STAT(port_tx_64, TX_64_PKTS), 515 EF100_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 516 EF100_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 517 EF100_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 518 EF100_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 519 EF100_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 520 EF100_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 521 EF100_DMA_STAT(port_rx_bytes, RX_BYTES), 522 EF100_DMA_STAT(port_rx_packets, RX_PKTS), 523 EF100_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 524 EF100_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 525 EF100_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 526 EF100_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 527 EF100_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 528 EF100_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 529 EF100_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 530 EF100_DMA_STAT(port_rx_64, RX_64_PKTS), 531 EF100_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 532 EF100_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 533 EF100_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 534 EF100_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 535 EF100_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 536 EF100_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 537 EF100_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 538 EF100_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 539 EF100_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 540 EF100_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 541 EF100_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 542 EF100_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 543 EFX_GENERIC_SW_STAT(rx_nodesc_trunc), 544 EFX_GENERIC_SW_STAT(rx_noskb_drops), 545 }; 546 547 static size_t ef100_describe_stats(struct efx_nic *efx, u8 *names) 548 { 549 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {}; 550 551 ef100_ethtool_stat_mask(mask); 552 return efx_nic_describe_stats(ef100_stat_desc, EF100_STAT_COUNT, 553 mask, names); 554 } 555 556 static size_t ef100_update_stats_common(struct efx_nic *efx, u64 *full_stats, 557 struct rtnl_link_stats64 *core_stats) 558 { 559 struct ef100_nic_data *nic_data = efx->nic_data; 560 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {}; 561 size_t stats_count = 0, index; 562 u64 *stats = nic_data->stats; 563 564 ef100_ethtool_stat_mask(mask); 565 566 if (full_stats) { 567 for_each_set_bit(index, mask, EF100_STAT_COUNT) { 568 if (ef100_stat_desc[index].name) { 569 *full_stats++ = stats[index]; 570 ++stats_count; 571 } 572 } 573 } 574 575 if (!core_stats) 576 return stats_count; 577 578 core_stats->rx_packets = stats[EF100_STAT_port_rx_packets]; 579 core_stats->tx_packets = stats[EF100_STAT_port_tx_packets]; 580 core_stats->rx_bytes = stats[EF100_STAT_port_rx_bytes]; 581 core_stats->tx_bytes = stats[EF100_STAT_port_tx_bytes]; 582 core_stats->rx_dropped = stats[EF100_STAT_port_rx_nodesc_drops] + 583 stats[GENERIC_STAT_rx_nodesc_trunc] + 584 stats[GENERIC_STAT_rx_noskb_drops]; 585 core_stats->multicast = stats[EF100_STAT_port_rx_multicast]; 586 core_stats->rx_length_errors = 587 stats[EF100_STAT_port_rx_gtjumbo] + 588 stats[EF100_STAT_port_rx_length_error]; 589 core_stats->rx_crc_errors = stats[EF100_STAT_port_rx_bad]; 590 core_stats->rx_frame_errors = 591 stats[EF100_STAT_port_rx_align_error]; 592 core_stats->rx_fifo_errors = stats[EF100_STAT_port_rx_overflow]; 593 core_stats->rx_errors = (core_stats->rx_length_errors + 594 core_stats->rx_crc_errors + 595 core_stats->rx_frame_errors); 596 597 return stats_count; 598 } 599 600 static size_t ef100_update_stats(struct efx_nic *efx, 601 u64 *full_stats, 602 struct rtnl_link_stats64 *core_stats) 603 { 604 __le64 *mc_stats = kmalloc(array_size(efx->num_mac_stats, sizeof(__le64)), GFP_ATOMIC); 605 struct ef100_nic_data *nic_data = efx->nic_data; 606 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {}; 607 u64 *stats = nic_data->stats; 608 609 ef100_common_stat_mask(mask); 610 ef100_ethtool_stat_mask(mask); 611 612 efx_nic_copy_stats(efx, mc_stats); 613 efx_nic_update_stats(ef100_stat_desc, EF100_STAT_COUNT, mask, 614 stats, mc_stats, false); 615 616 kfree(mc_stats); 617 618 return ef100_update_stats_common(efx, full_stats, core_stats); 619 } 620 621 static int efx_ef100_get_phys_port_id(struct efx_nic *efx, 622 struct netdev_phys_item_id *ppid) 623 { 624 struct ef100_nic_data *nic_data = efx->nic_data; 625 626 if (!is_valid_ether_addr(nic_data->port_id)) 627 return -EOPNOTSUPP; 628 629 ppid->id_len = ETH_ALEN; 630 memcpy(ppid->id, nic_data->port_id, ppid->id_len); 631 632 return 0; 633 } 634 635 static int efx_ef100_irq_test_generate(struct efx_nic *efx) 636 { 637 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 638 639 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 640 641 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 642 return efx_mcdi_rpc_quiet(efx, MC_CMD_TRIGGER_INTERRUPT, 643 inbuf, sizeof(inbuf), NULL, 0, NULL); 644 } 645 646 #define EFX_EF100_TEST 1 647 648 static void efx_ef100_ev_test_generate(struct efx_channel *channel) 649 { 650 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 651 struct efx_nic *efx = channel->efx; 652 efx_qword_t event; 653 int rc; 654 655 EFX_POPULATE_QWORD_2(event, 656 ESF_GZ_E_TYPE, ESE_GZ_EF100_EV_DRIVER, 657 ESF_GZ_DRIVER_DATA, EFX_EF100_TEST); 658 659 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 660 661 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 662 * already swapped the data to little-endian order. 663 */ 664 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 665 sizeof(efx_qword_t)); 666 667 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 668 NULL, 0, NULL); 669 if (rc && (rc != -ENETDOWN)) 670 goto fail; 671 672 return; 673 674 fail: 675 WARN_ON(true); 676 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 677 } 678 679 static unsigned int ef100_check_caps(const struct efx_nic *efx, 680 u8 flag, u32 offset) 681 { 682 const struct ef100_nic_data *nic_data = efx->nic_data; 683 684 switch (offset) { 685 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST: 686 return nic_data->datapath_caps & BIT_ULL(flag); 687 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST: 688 return nic_data->datapath_caps2 & BIT_ULL(flag); 689 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST: 690 return nic_data->datapath_caps3 & BIT_ULL(flag); 691 default: 692 return 0; 693 } 694 } 695 696 /* NIC level access functions 697 */ 698 #define EF100_OFFLOAD_FEATURES (NETIF_F_HW_CSUM | NETIF_F_RXCSUM | \ 699 NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_NTUPLE | \ 700 NETIF_F_RXHASH | NETIF_F_RXFCS | NETIF_F_TSO_ECN | NETIF_F_RXALL | \ 701 NETIF_F_HW_VLAN_CTAG_TX) 702 703 const struct efx_nic_type ef100_pf_nic_type = { 704 .revision = EFX_REV_EF100, 705 .is_vf = false, 706 .probe = ef100_probe_pf, 707 .offload_features = EF100_OFFLOAD_FEATURES, 708 .mcdi_max_ver = 2, 709 .mcdi_request = ef100_mcdi_request, 710 .mcdi_poll_response = ef100_mcdi_poll_response, 711 .mcdi_read_response = ef100_mcdi_read_response, 712 .mcdi_poll_reboot = ef100_mcdi_poll_reboot, 713 .mcdi_reboot_detected = ef100_mcdi_reboot_detected, 714 .irq_enable_master = efx_port_dummy_op_void, 715 .irq_test_generate = efx_ef100_irq_test_generate, 716 .irq_disable_non_ev = efx_port_dummy_op_void, 717 .push_irq_moderation = efx_channel_dummy_op_void, 718 .min_interrupt_mode = EFX_INT_MODE_MSIX, 719 .map_reset_reason = ef100_map_reset_reason, 720 .map_reset_flags = ef100_map_reset_flags, 721 .reset = ef100_reset, 722 723 .check_caps = ef100_check_caps, 724 725 .ev_probe = ef100_ev_probe, 726 .ev_init = ef100_ev_init, 727 .ev_fini = efx_mcdi_ev_fini, 728 .ev_remove = efx_mcdi_ev_remove, 729 .irq_handle_msi = ef100_msi_interrupt, 730 .ev_process = ef100_ev_process, 731 .ev_read_ack = ef100_ev_read_ack, 732 .ev_test_generate = efx_ef100_ev_test_generate, 733 .tx_probe = ef100_tx_probe, 734 .tx_init = ef100_tx_init, 735 .tx_write = ef100_tx_write, 736 .tx_enqueue = ef100_enqueue_skb, 737 .rx_probe = efx_mcdi_rx_probe, 738 .rx_init = efx_mcdi_rx_init, 739 .rx_remove = efx_mcdi_rx_remove, 740 .rx_write = ef100_rx_write, 741 .rx_packet = __ef100_rx_packet, 742 .rx_buf_hash_valid = ef100_rx_buf_hash_valid, 743 .fini_dmaq = efx_fini_dmaq, 744 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 745 .filter_table_probe = ef100_filter_table_up, 746 .filter_table_restore = efx_mcdi_filter_table_restore, 747 .filter_table_remove = ef100_filter_table_down, 748 .filter_insert = efx_mcdi_filter_insert, 749 .filter_remove_safe = efx_mcdi_filter_remove_safe, 750 .filter_get_safe = efx_mcdi_filter_get_safe, 751 .filter_clear_rx = efx_mcdi_filter_clear_rx, 752 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 753 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 754 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 755 #ifdef CONFIG_RFS_ACCEL 756 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 757 #endif 758 759 .get_phys_port_id = efx_ef100_get_phys_port_id, 760 761 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN, 762 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8, 763 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8, 764 .rx_hash_key_size = 40, 765 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 766 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 767 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config, 768 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config, 769 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 770 771 .reconfigure_mac = ef100_reconfigure_mac, 772 .reconfigure_port = efx_mcdi_port_reconfigure, 773 .test_nvram = efx_new_mcdi_nvram_test_all, 774 .describe_stats = ef100_describe_stats, 775 .start_stats = efx_mcdi_mac_start_stats, 776 .update_stats = ef100_update_stats, 777 .pull_stats = efx_mcdi_mac_pull_stats, 778 .stop_stats = efx_mcdi_mac_stop_stats, 779 780 /* Per-type bar/size configuration not used on ef100. Location of 781 * registers is defined by extended capabilities. 782 */ 783 .mem_bar = NULL, 784 .mem_map_size = NULL, 785 786 }; 787 788 const struct efx_nic_type ef100_vf_nic_type = { 789 .revision = EFX_REV_EF100, 790 .is_vf = true, 791 .probe = ef100_probe_vf, 792 .offload_features = EF100_OFFLOAD_FEATURES, 793 .mcdi_max_ver = 2, 794 .mcdi_request = ef100_mcdi_request, 795 .mcdi_poll_response = ef100_mcdi_poll_response, 796 .mcdi_read_response = ef100_mcdi_read_response, 797 .mcdi_poll_reboot = ef100_mcdi_poll_reboot, 798 .mcdi_reboot_detected = ef100_mcdi_reboot_detected, 799 .irq_enable_master = efx_port_dummy_op_void, 800 .irq_test_generate = efx_ef100_irq_test_generate, 801 .irq_disable_non_ev = efx_port_dummy_op_void, 802 .push_irq_moderation = efx_channel_dummy_op_void, 803 .min_interrupt_mode = EFX_INT_MODE_MSIX, 804 .map_reset_reason = ef100_map_reset_reason, 805 .map_reset_flags = ef100_map_reset_flags, 806 .reset = ef100_reset, 807 .check_caps = ef100_check_caps, 808 .ev_probe = ef100_ev_probe, 809 .ev_init = ef100_ev_init, 810 .ev_fini = efx_mcdi_ev_fini, 811 .ev_remove = efx_mcdi_ev_remove, 812 .irq_handle_msi = ef100_msi_interrupt, 813 .ev_process = ef100_ev_process, 814 .ev_read_ack = ef100_ev_read_ack, 815 .ev_test_generate = efx_ef100_ev_test_generate, 816 .tx_probe = ef100_tx_probe, 817 .tx_init = ef100_tx_init, 818 .tx_write = ef100_tx_write, 819 .tx_enqueue = ef100_enqueue_skb, 820 .rx_probe = efx_mcdi_rx_probe, 821 .rx_init = efx_mcdi_rx_init, 822 .rx_remove = efx_mcdi_rx_remove, 823 .rx_write = ef100_rx_write, 824 .rx_packet = __ef100_rx_packet, 825 .rx_buf_hash_valid = ef100_rx_buf_hash_valid, 826 .fini_dmaq = efx_fini_dmaq, 827 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 828 .filter_table_probe = ef100_filter_table_up, 829 .filter_table_restore = efx_mcdi_filter_table_restore, 830 .filter_table_remove = ef100_filter_table_down, 831 .filter_insert = efx_mcdi_filter_insert, 832 .filter_remove_safe = efx_mcdi_filter_remove_safe, 833 .filter_get_safe = efx_mcdi_filter_get_safe, 834 .filter_clear_rx = efx_mcdi_filter_clear_rx, 835 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 836 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 837 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 838 #ifdef CONFIG_RFS_ACCEL 839 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 840 #endif 841 842 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN, 843 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8, 844 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8, 845 .rx_hash_key_size = 40, 846 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 847 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 848 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 849 850 .reconfigure_mac = ef100_reconfigure_mac, 851 .test_nvram = efx_new_mcdi_nvram_test_all, 852 .describe_stats = ef100_describe_stats, 853 .start_stats = efx_mcdi_mac_start_stats, 854 .update_stats = ef100_update_stats, 855 .pull_stats = efx_mcdi_mac_pull_stats, 856 .stop_stats = efx_mcdi_mac_stop_stats, 857 858 .mem_bar = NULL, 859 .mem_map_size = NULL, 860 861 }; 862 863 static int compare_versions(const char *a, const char *b) 864 { 865 int a_major, a_minor, a_point, a_patch; 866 int b_major, b_minor, b_point, b_patch; 867 int a_matched, b_matched; 868 869 a_matched = sscanf(a, "%d.%d.%d.%d", &a_major, &a_minor, &a_point, &a_patch); 870 b_matched = sscanf(b, "%d.%d.%d.%d", &b_major, &b_minor, &b_point, &b_patch); 871 872 if (a_matched == 4 && b_matched != 4) 873 return +1; 874 875 if (a_matched != 4 && b_matched == 4) 876 return -1; 877 878 if (a_matched != 4 && b_matched != 4) 879 return 0; 880 881 if (a_major != b_major) 882 return a_major - b_major; 883 884 if (a_minor != b_minor) 885 return a_minor - b_minor; 886 887 if (a_point != b_point) 888 return a_point - b_point; 889 890 return a_patch - b_patch; 891 } 892 893 enum ef100_tlv_state_machine { 894 EF100_TLV_TYPE, 895 EF100_TLV_TYPE_CONT, 896 EF100_TLV_LENGTH, 897 EF100_TLV_VALUE 898 }; 899 900 struct ef100_tlv_state { 901 enum ef100_tlv_state_machine state; 902 u64 value; 903 u32 value_offset; 904 u16 type; 905 u8 len; 906 }; 907 908 static int ef100_tlv_feed(struct ef100_tlv_state *state, u8 byte) 909 { 910 switch (state->state) { 911 case EF100_TLV_TYPE: 912 state->type = byte & 0x7f; 913 state->state = (byte & 0x80) ? EF100_TLV_TYPE_CONT 914 : EF100_TLV_LENGTH; 915 /* Clear ready to read in a new entry */ 916 state->value = 0; 917 state->value_offset = 0; 918 return 0; 919 case EF100_TLV_TYPE_CONT: 920 state->type |= byte << 7; 921 state->state = EF100_TLV_LENGTH; 922 return 0; 923 case EF100_TLV_LENGTH: 924 state->len = byte; 925 /* We only handle TLVs that fit in a u64 */ 926 if (state->len > sizeof(state->value)) 927 return -EOPNOTSUPP; 928 /* len may be zero, implying a value of zero */ 929 state->state = state->len ? EF100_TLV_VALUE : EF100_TLV_TYPE; 930 return 0; 931 case EF100_TLV_VALUE: 932 state->value |= ((u64)byte) << (state->value_offset * 8); 933 state->value_offset++; 934 if (state->value_offset >= state->len) 935 state->state = EF100_TLV_TYPE; 936 return 0; 937 default: /* state machine error, can't happen */ 938 WARN_ON_ONCE(1); 939 return -EIO; 940 } 941 } 942 943 static int ef100_process_design_param(struct efx_nic *efx, 944 const struct ef100_tlv_state *reader) 945 { 946 struct ef100_nic_data *nic_data = efx->nic_data; 947 948 switch (reader->type) { 949 case ESE_EF100_DP_GZ_PAD: /* padding, skip it */ 950 return 0; 951 case ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS: 952 /* Driver doesn't support timestamping yet, so we don't care */ 953 return 0; 954 case ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS: 955 /* Driver doesn't support unsolicited-event credits yet, so 956 * we don't care 957 */ 958 return 0; 959 case ESE_EF100_DP_GZ_NMMU_GROUP_SIZE: 960 /* Driver doesn't manage the NMMU (so we don't care) */ 961 return 0; 962 case ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS: 963 /* Driver uses CHECKSUM_COMPLETE, so we don't care about 964 * protocol checksum validation 965 */ 966 return 0; 967 case ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN: 968 nic_data->tso_max_hdr_len = min_t(u64, reader->value, 0xffff); 969 return 0; 970 case ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS: 971 /* We always put HDR_NUM_SEGS=1 in our TSO descriptors */ 972 if (!reader->value) { 973 netif_err(efx, probe, efx->net_dev, 974 "TSO_MAX_HDR_NUM_SEGS < 1\n"); 975 return -EOPNOTSUPP; 976 } 977 return 0; 978 case ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY: 979 case ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY: 980 /* Our TXQ and RXQ sizes are always power-of-two and thus divisible by 981 * EFX_MIN_DMAQ_SIZE, so we just need to check that 982 * EFX_MIN_DMAQ_SIZE is divisible by GRANULARITY. 983 * This is very unlikely to fail. 984 */ 985 if (!reader->value || reader->value > EFX_MIN_DMAQ_SIZE || 986 EFX_MIN_DMAQ_SIZE % (u32)reader->value) { 987 netif_err(efx, probe, efx->net_dev, 988 "%s size granularity is %llu, can't guarantee safety\n", 989 reader->type == ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY ? "RXQ" : "TXQ", 990 reader->value); 991 return -EOPNOTSUPP; 992 } 993 return 0; 994 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN: 995 nic_data->tso_max_payload_len = min_t(u64, reader->value, GSO_MAX_SIZE); 996 efx->net_dev->gso_max_size = nic_data->tso_max_payload_len; 997 return 0; 998 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS: 999 nic_data->tso_max_payload_num_segs = min_t(u64, reader->value, 0xffff); 1000 efx->net_dev->gso_max_segs = nic_data->tso_max_payload_num_segs; 1001 return 0; 1002 case ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES: 1003 nic_data->tso_max_frames = min_t(u64, reader->value, 0xffff); 1004 return 0; 1005 case ESE_EF100_DP_GZ_COMPAT: 1006 if (reader->value) { 1007 netif_err(efx, probe, efx->net_dev, 1008 "DP_COMPAT has unknown bits %#llx, driver not compatible with this hw\n", 1009 reader->value); 1010 return -EOPNOTSUPP; 1011 } 1012 return 0; 1013 case ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN: 1014 /* Driver doesn't use mem2mem transfers */ 1015 return 0; 1016 case ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS: 1017 /* Driver doesn't currently use EVQ_TIMER */ 1018 return 0; 1019 case ESE_EF100_DP_GZ_NMMU_PAGE_SIZES: 1020 /* Driver doesn't manage the NMMU (so we don't care) */ 1021 return 0; 1022 case ESE_EF100_DP_GZ_VI_STRIDES: 1023 /* We never try to set the VI stride, and we don't rely on 1024 * being able to find VIs past VI 0 until after we've learned 1025 * the current stride from MC_CMD_GET_CAPABILITIES. 1026 * So the value of this shouldn't matter. 1027 */ 1028 if (reader->value != ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT) 1029 netif_dbg(efx, probe, efx->net_dev, 1030 "NIC has other than default VI_STRIDES (mask " 1031 "%#llx), early probing might use wrong one\n", 1032 reader->value); 1033 return 0; 1034 case ESE_EF100_DP_GZ_RX_MAX_RUNT: 1035 /* Driver doesn't look at L2_STATUS:LEN_ERR bit, so we don't 1036 * care whether it indicates runt or overlength for any given 1037 * packet, so we don't care about this parameter. 1038 */ 1039 return 0; 1040 default: 1041 /* Host interface says "Drivers should ignore design parameters 1042 * that they do not recognise." 1043 */ 1044 netif_dbg(efx, probe, efx->net_dev, 1045 "Ignoring unrecognised design parameter %u\n", 1046 reader->type); 1047 return 0; 1048 } 1049 } 1050 1051 static int ef100_check_design_params(struct efx_nic *efx) 1052 { 1053 struct ef100_tlv_state reader = {}; 1054 u32 total_len, offset = 0; 1055 efx_dword_t reg; 1056 int rc = 0, i; 1057 u32 data; 1058 1059 efx_readd(efx, ®, ER_GZ_PARAMS_TLV_LEN); 1060 total_len = EFX_DWORD_FIELD(reg, EFX_DWORD_0); 1061 netif_dbg(efx, probe, efx->net_dev, "%u bytes of design parameters\n", 1062 total_len); 1063 while (offset < total_len) { 1064 efx_readd(efx, ®, ER_GZ_PARAMS_TLV + offset); 1065 data = EFX_DWORD_FIELD(reg, EFX_DWORD_0); 1066 for (i = 0; i < sizeof(data); i++) { 1067 rc = ef100_tlv_feed(&reader, data); 1068 /* Got a complete value? */ 1069 if (!rc && reader.state == EF100_TLV_TYPE) 1070 rc = ef100_process_design_param(efx, &reader); 1071 if (rc) 1072 goto out; 1073 data >>= 8; 1074 offset++; 1075 } 1076 } 1077 /* Check we didn't end halfway through a TLV entry, which could either 1078 * mean that the TLV stream is truncated or just that it's corrupted 1079 * and our state machine is out of sync. 1080 */ 1081 if (reader.state != EF100_TLV_TYPE) { 1082 if (reader.state == EF100_TLV_TYPE_CONT) 1083 netif_err(efx, probe, efx->net_dev, 1084 "truncated design parameter (incomplete type %u)\n", 1085 reader.type); 1086 else 1087 netif_err(efx, probe, efx->net_dev, 1088 "truncated design parameter %u\n", 1089 reader.type); 1090 rc = -EIO; 1091 } 1092 out: 1093 return rc; 1094 } 1095 1096 /* NIC probe and remove 1097 */ 1098 static int ef100_probe_main(struct efx_nic *efx) 1099 { 1100 unsigned int bar_size = resource_size(&efx->pci_dev->resource[efx->mem_bar]); 1101 struct net_device *net_dev = efx->net_dev; 1102 struct ef100_nic_data *nic_data; 1103 char fw_version[32]; 1104 int i, rc; 1105 1106 if (WARN_ON(bar_size == 0)) 1107 return -EIO; 1108 1109 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 1110 if (!nic_data) 1111 return -ENOMEM; 1112 efx->nic_data = nic_data; 1113 nic_data->efx = efx; 1114 net_dev->features |= efx->type->offload_features; 1115 net_dev->hw_features |= efx->type->offload_features; 1116 net_dev->hw_enc_features |= efx->type->offload_features; 1117 net_dev->vlan_features |= NETIF_F_HW_CSUM | NETIF_F_SG | 1118 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO; 1119 1120 /* Populate design-parameter defaults */ 1121 nic_data->tso_max_hdr_len = ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT; 1122 nic_data->tso_max_frames = ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT; 1123 nic_data->tso_max_payload_num_segs = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT; 1124 nic_data->tso_max_payload_len = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT; 1125 net_dev->gso_max_segs = ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT; 1126 /* Read design parameters */ 1127 rc = ef100_check_design_params(efx); 1128 if (rc) { 1129 netif_err(efx, probe, efx->net_dev, 1130 "Unsupported design parameters\n"); 1131 goto fail; 1132 } 1133 1134 /* we assume later that we can copy from this buffer in dwords */ 1135 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 1136 1137 /* MCDI buffers must be 256 byte aligned. */ 1138 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, MCDI_BUF_LEN, 1139 GFP_KERNEL); 1140 if (rc) 1141 goto fail; 1142 1143 /* Get the MC's warm boot count. In case it's rebooting right 1144 * now, be prepared to retry. 1145 */ 1146 i = 0; 1147 for (;;) { 1148 rc = ef100_get_warm_boot_count(efx); 1149 if (rc >= 0) 1150 break; 1151 if (++i == 5) 1152 goto fail; 1153 ssleep(1); 1154 } 1155 nic_data->warm_boot_count = rc; 1156 1157 /* In case we're recovering from a crash (kexec), we want to 1158 * cancel any outstanding request by the previous user of this 1159 * function. We send a special message using the least 1160 * significant bits of the 'high' (doorbell) register. 1161 */ 1162 _efx_writed(efx, cpu_to_le32(1), efx_reg(efx, ER_GZ_MC_DB_HWRD)); 1163 1164 /* Post-IO section. */ 1165 1166 rc = efx_mcdi_init(efx); 1167 if (!rc && efx->mcdi->fn_flags & 1168 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT)) { 1169 netif_info(efx, probe, efx->net_dev, 1170 "No network port on this PCI function"); 1171 rc = -ENODEV; 1172 } 1173 if (rc) 1174 goto fail; 1175 /* Reset (most) configuration for this function */ 1176 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 1177 if (rc) 1178 goto fail; 1179 /* Enable event logging */ 1180 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 1181 if (rc) 1182 goto fail; 1183 1184 rc = efx_get_pf_index(efx, &nic_data->pf_index); 1185 if (rc) 1186 goto fail; 1187 1188 rc = efx_ef100_init_datapath_caps(efx); 1189 if (rc < 0) 1190 goto fail; 1191 1192 efx->max_vis = EF100_MAX_VIS; 1193 1194 rc = efx_mcdi_port_get_number(efx); 1195 if (rc < 0) 1196 goto fail; 1197 efx->port_num = rc; 1198 1199 efx_mcdi_print_fwver(efx, fw_version, sizeof(fw_version)); 1200 netif_dbg(efx, drv, efx->net_dev, "Firmware version %s\n", fw_version); 1201 1202 if (compare_versions(fw_version, "1.1.0.1000") < 0) { 1203 netif_info(efx, drv, efx->net_dev, "Firmware uses old event descriptors\n"); 1204 rc = -EINVAL; 1205 goto fail; 1206 } 1207 1208 if (efx_has_cap(efx, UNSOL_EV_CREDIT_SUPPORTED)) { 1209 netif_info(efx, drv, efx->net_dev, "Firmware uses unsolicited-event credits\n"); 1210 rc = -EINVAL; 1211 goto fail; 1212 } 1213 1214 rc = ef100_phy_probe(efx); 1215 if (rc) 1216 goto fail; 1217 1218 down_write(&efx->filter_sem); 1219 rc = ef100_filter_table_probe(efx); 1220 up_write(&efx->filter_sem); 1221 if (rc) 1222 goto fail; 1223 1224 netdev_rss_key_fill(efx->rss_context.rx_hash_key, 1225 sizeof(efx->rss_context.rx_hash_key)); 1226 1227 /* Don't fail init if RSS setup doesn't work. */ 1228 efx_mcdi_push_default_indir_table(efx, efx->n_rx_channels); 1229 1230 rc = ef100_register_netdev(efx); 1231 if (rc) 1232 goto fail; 1233 1234 return 0; 1235 fail: 1236 return rc; 1237 } 1238 1239 int ef100_probe_pf(struct efx_nic *efx) 1240 { 1241 struct net_device *net_dev = efx->net_dev; 1242 struct ef100_nic_data *nic_data; 1243 int rc = ef100_probe_main(efx); 1244 1245 if (rc) 1246 goto fail; 1247 1248 nic_data = efx->nic_data; 1249 rc = ef100_get_mac_address(efx, net_dev->perm_addr); 1250 if (rc) 1251 goto fail; 1252 /* Assign MAC address */ 1253 memcpy(net_dev->dev_addr, net_dev->perm_addr, ETH_ALEN); 1254 memcpy(nic_data->port_id, net_dev->perm_addr, ETH_ALEN); 1255 1256 return 0; 1257 1258 fail: 1259 return rc; 1260 } 1261 1262 int ef100_probe_vf(struct efx_nic *efx) 1263 { 1264 return ef100_probe_main(efx); 1265 } 1266 1267 void ef100_remove(struct efx_nic *efx) 1268 { 1269 struct ef100_nic_data *nic_data = efx->nic_data; 1270 1271 ef100_unregister_netdev(efx); 1272 1273 down_write(&efx->filter_sem); 1274 efx_mcdi_filter_table_remove(efx); 1275 up_write(&efx->filter_sem); 1276 efx_fini_channels(efx); 1277 kfree(efx->phy_data); 1278 efx->phy_data = NULL; 1279 efx_mcdi_detach(efx); 1280 efx_mcdi_fini(efx); 1281 if (nic_data) 1282 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 1283 kfree(nic_data); 1284 efx->nic_data = NULL; 1285 } 1286