1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2018 Solarflare Communications Inc. 5 * Copyright 2019-2022 Xilinx Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation, incorporated herein by reference. 10 */ 11 12 #include "ef100_nic.h" 13 #include "efx_common.h" 14 #include "efx_channels.h" 15 #include "io.h" 16 #include "selftest.h" 17 #include "ef100_regs.h" 18 #include "mcdi.h" 19 #include "mcdi_pcol.h" 20 #include "mcdi_port_common.h" 21 #include "mcdi_functions.h" 22 #include "mcdi_filters.h" 23 #include "ef100_rx.h" 24 #include "ef100_tx.h" 25 #include "ef100_sriov.h" 26 #include "ef100_netdev.h" 27 #include "tc.h" 28 #include "mae.h" 29 #include "rx_common.h" 30 31 #define EF100_MAX_VIS 4096 32 #define EF100_NUM_MCDI_BUFFERS 1 33 #define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX) 34 35 #define EF100_RESET_PORT ((ETH_RESET_MAC | ETH_RESET_PHY) << ETH_RESET_SHARED_SHIFT) 36 37 /* MCDI 38 */ 39 static u8 *ef100_mcdi_buf(struct efx_nic *efx, u8 bufid, dma_addr_t *dma_addr) 40 { 41 struct ef100_nic_data *nic_data = efx->nic_data; 42 43 if (dma_addr) 44 *dma_addr = nic_data->mcdi_buf.dma_addr + 45 bufid * ALIGN(MCDI_BUF_LEN, 256); 46 return nic_data->mcdi_buf.addr + bufid * ALIGN(MCDI_BUF_LEN, 256); 47 } 48 49 static int ef100_get_warm_boot_count(struct efx_nic *efx) 50 { 51 efx_dword_t reg; 52 53 efx_readd(efx, ®, efx_reg(efx, ER_GZ_MC_SFT_STATUS)); 54 55 if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) == 0xffffffff) { 56 netif_err(efx, hw, efx->net_dev, "Hardware unavailable\n"); 57 efx->state = STATE_DISABLED; 58 return -ENETDOWN; 59 } else { 60 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 61 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 62 } 63 } 64 65 static void ef100_mcdi_request(struct efx_nic *efx, 66 const efx_dword_t *hdr, size_t hdr_len, 67 const efx_dword_t *sdu, size_t sdu_len) 68 { 69 dma_addr_t dma_addr; 70 u8 *pdu = ef100_mcdi_buf(efx, 0, &dma_addr); 71 72 memcpy(pdu, hdr, hdr_len); 73 memcpy(pdu + hdr_len, sdu, sdu_len); 74 wmb(); 75 76 /* The hardware provides 'low' and 'high' (doorbell) registers 77 * for passing the 64-bit address of an MCDI request to 78 * firmware. However the dwords are swapped by firmware. The 79 * least significant bits of the doorbell are then 0 for all 80 * MCDI requests due to alignment. 81 */ 82 _efx_writed(efx, cpu_to_le32((u64)dma_addr >> 32), efx_reg(efx, ER_GZ_MC_DB_LWRD)); 83 _efx_writed(efx, cpu_to_le32((u32)dma_addr), efx_reg(efx, ER_GZ_MC_DB_HWRD)); 84 } 85 86 static bool ef100_mcdi_poll_response(struct efx_nic *efx) 87 { 88 const efx_dword_t hdr = 89 *(const efx_dword_t *)(ef100_mcdi_buf(efx, 0, NULL)); 90 91 rmb(); 92 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 93 } 94 95 static void ef100_mcdi_read_response(struct efx_nic *efx, 96 efx_dword_t *outbuf, size_t offset, 97 size_t outlen) 98 { 99 const u8 *pdu = ef100_mcdi_buf(efx, 0, NULL); 100 101 memcpy(outbuf, pdu + offset, outlen); 102 } 103 104 static int ef100_mcdi_poll_reboot(struct efx_nic *efx) 105 { 106 struct ef100_nic_data *nic_data = efx->nic_data; 107 int rc; 108 109 rc = ef100_get_warm_boot_count(efx); 110 if (rc < 0) { 111 /* The firmware is presumably in the process of 112 * rebooting. However, we are supposed to report each 113 * reboot just once, so we must only do that once we 114 * can read and store the updated warm boot count. 115 */ 116 return 0; 117 } 118 119 if (rc == nic_data->warm_boot_count) 120 return 0; 121 122 nic_data->warm_boot_count = rc; 123 124 return -EIO; 125 } 126 127 static void ef100_mcdi_reboot_detected(struct efx_nic *efx) 128 { 129 } 130 131 /* MCDI calls 132 */ 133 static int ef100_get_mac_address(struct efx_nic *efx, u8 *mac_address) 134 { 135 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 136 size_t outlen; 137 int rc; 138 139 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 140 141 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 142 outbuf, sizeof(outbuf), &outlen); 143 if (rc) 144 return rc; 145 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 146 return -EIO; 147 148 ether_addr_copy(mac_address, 149 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 150 return 0; 151 } 152 153 int efx_ef100_init_datapath_caps(struct efx_nic *efx) 154 { 155 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V7_OUT_LEN); 156 struct ef100_nic_data *nic_data = efx->nic_data; 157 u8 vi_window_mode; 158 size_t outlen; 159 int rc; 160 161 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 162 163 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 164 outbuf, sizeof(outbuf), &outlen); 165 if (rc) 166 return rc; 167 if (outlen < MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) { 168 netif_err(efx, drv, efx->net_dev, 169 "unable to read datapath firmware capabilities\n"); 170 return -EIO; 171 } 172 173 nic_data->datapath_caps = MCDI_DWORD(outbuf, 174 GET_CAPABILITIES_OUT_FLAGS1); 175 nic_data->datapath_caps2 = MCDI_DWORD(outbuf, 176 GET_CAPABILITIES_V2_OUT_FLAGS2); 177 if (outlen < MC_CMD_GET_CAPABILITIES_V7_OUT_LEN) 178 nic_data->datapath_caps3 = 0; 179 else 180 nic_data->datapath_caps3 = MCDI_DWORD(outbuf, 181 GET_CAPABILITIES_V7_OUT_FLAGS3); 182 183 vi_window_mode = MCDI_BYTE(outbuf, 184 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); 185 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode); 186 if (rc) 187 return rc; 188 189 if (efx_ef100_has_cap(nic_data->datapath_caps2, TX_TSO_V3)) { 190 struct net_device *net_dev = efx->net_dev; 191 netdev_features_t tso = NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_PARTIAL | 192 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM | 193 NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM; 194 195 net_dev->features |= tso; 196 net_dev->hw_features |= tso; 197 net_dev->hw_enc_features |= tso; 198 /* EF100 HW can only offload outer checksums if they are UDP, 199 * so for GRE_CSUM we have to use GSO_PARTIAL. 200 */ 201 net_dev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 202 } 203 efx->num_mac_stats = MCDI_WORD(outbuf, 204 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS); 205 netif_dbg(efx, probe, efx->net_dev, 206 "firmware reports num_mac_stats = %u\n", 207 efx->num_mac_stats); 208 return 0; 209 } 210 211 /* Event handling 212 */ 213 static int ef100_ev_probe(struct efx_channel *channel) 214 { 215 /* Allocate an extra descriptor for the QMDA status completion entry */ 216 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, 217 (channel->eventq_mask + 2) * 218 sizeof(efx_qword_t), 219 GFP_KERNEL); 220 } 221 222 static int ef100_ev_init(struct efx_channel *channel) 223 { 224 struct ef100_nic_data *nic_data = channel->efx->nic_data; 225 226 /* initial phase is 0 */ 227 clear_bit(channel->channel, nic_data->evq_phases); 228 229 return efx_mcdi_ev_init(channel, false, false); 230 } 231 232 static void ef100_ev_read_ack(struct efx_channel *channel) 233 { 234 efx_dword_t evq_prime; 235 236 EFX_POPULATE_DWORD_2(evq_prime, 237 ERF_GZ_EVQ_ID, channel->channel, 238 ERF_GZ_IDX, channel->eventq_read_ptr & 239 channel->eventq_mask); 240 241 efx_writed(channel->efx, &evq_prime, 242 efx_reg(channel->efx, ER_GZ_EVQ_INT_PRIME)); 243 } 244 245 static int ef100_ev_process(struct efx_channel *channel, int quota) 246 { 247 struct efx_nic *efx = channel->efx; 248 struct ef100_nic_data *nic_data; 249 bool evq_phase, old_evq_phase; 250 unsigned int read_ptr; 251 efx_qword_t *p_event; 252 int spent = 0; 253 bool ev_phase; 254 int ev_type; 255 256 if (unlikely(!channel->enabled)) 257 return 0; 258 259 nic_data = efx->nic_data; 260 evq_phase = test_bit(channel->channel, nic_data->evq_phases); 261 old_evq_phase = evq_phase; 262 read_ptr = channel->eventq_read_ptr; 263 BUILD_BUG_ON(ESF_GZ_EV_RXPKTS_PHASE_LBN != ESF_GZ_EV_TXCMPL_PHASE_LBN); 264 265 while (spent < quota) { 266 p_event = efx_event(channel, read_ptr); 267 268 ev_phase = !!EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_PHASE); 269 if (ev_phase != evq_phase) 270 break; 271 272 netif_vdbg(efx, drv, efx->net_dev, 273 "processing event on %d " EFX_QWORD_FMT "\n", 274 channel->channel, EFX_QWORD_VAL(*p_event)); 275 276 ev_type = EFX_QWORD_FIELD(*p_event, ESF_GZ_E_TYPE); 277 278 switch (ev_type) { 279 case ESE_GZ_EF100_EV_RX_PKTS: 280 efx_ef100_ev_rx(channel, p_event); 281 ++spent; 282 break; 283 case ESE_GZ_EF100_EV_MCDI: 284 efx_mcdi_process_event(channel, p_event); 285 break; 286 case ESE_GZ_EF100_EV_TX_COMPLETION: 287 ef100_ev_tx(channel, p_event); 288 break; 289 case ESE_GZ_EF100_EV_DRIVER: 290 netif_info(efx, drv, efx->net_dev, 291 "Driver initiated event " EFX_QWORD_FMT "\n", 292 EFX_QWORD_VAL(*p_event)); 293 break; 294 default: 295 netif_info(efx, drv, efx->net_dev, 296 "Unhandled event " EFX_QWORD_FMT "\n", 297 EFX_QWORD_VAL(*p_event)); 298 } 299 300 ++read_ptr; 301 if ((read_ptr & channel->eventq_mask) == 0) 302 evq_phase = !evq_phase; 303 } 304 305 channel->eventq_read_ptr = read_ptr; 306 if (evq_phase != old_evq_phase) 307 change_bit(channel->channel, nic_data->evq_phases); 308 309 return spent; 310 } 311 312 static irqreturn_t ef100_msi_interrupt(int irq, void *dev_id) 313 { 314 struct efx_msi_context *context = dev_id; 315 struct efx_nic *efx = context->efx; 316 317 netif_vdbg(efx, intr, efx->net_dev, 318 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 319 320 if (likely(READ_ONCE(efx->irq_soft_enabled))) { 321 /* Note test interrupts */ 322 if (context->index == efx->irq_level) 323 efx->last_irq_cpu = raw_smp_processor_id(); 324 325 /* Schedule processing of the channel */ 326 efx_schedule_channel_irq(efx->channel[context->index]); 327 } 328 329 return IRQ_HANDLED; 330 } 331 332 int ef100_phy_probe(struct efx_nic *efx) 333 { 334 struct efx_mcdi_phy_data *phy_data; 335 int rc; 336 337 /* Probe for the PHY */ 338 efx->phy_data = kzalloc(sizeof(struct efx_mcdi_phy_data), GFP_KERNEL); 339 if (!efx->phy_data) 340 return -ENOMEM; 341 342 rc = efx_mcdi_get_phy_cfg(efx, efx->phy_data); 343 if (rc) 344 return rc; 345 346 /* Populate driver and ethtool settings */ 347 phy_data = efx->phy_data; 348 mcdi_to_ethtool_linkset(phy_data->media, phy_data->supported_cap, 349 efx->link_advertising); 350 efx->fec_config = mcdi_fec_caps_to_ethtool(phy_data->supported_cap, 351 false); 352 353 /* Default to Autonegotiated flow control if the PHY supports it */ 354 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; 355 if (phy_data->supported_cap & (1 << MC_CMD_PHY_CAP_AN_LBN)) 356 efx->wanted_fc |= EFX_FC_AUTO; 357 efx_link_set_wanted_fc(efx, efx->wanted_fc); 358 359 /* Push settings to the PHY. Failure is not fatal, the user can try to 360 * fix it using ethtool. 361 */ 362 rc = efx_mcdi_port_reconfigure(efx); 363 if (rc && rc != -EPERM) 364 netif_warn(efx, drv, efx->net_dev, 365 "could not initialise PHY settings\n"); 366 367 return 0; 368 } 369 370 int ef100_filter_table_probe(struct efx_nic *efx) 371 { 372 return efx_mcdi_filter_table_probe(efx, true); 373 } 374 375 static int ef100_filter_table_up(struct efx_nic *efx) 376 { 377 int rc; 378 379 down_write(&efx->filter_sem); 380 rc = efx_mcdi_filter_add_vlan(efx, EFX_FILTER_VID_UNSPEC); 381 if (rc) 382 goto fail_unspec; 383 384 rc = efx_mcdi_filter_add_vlan(efx, 0); 385 if (rc) 386 goto fail_vlan0; 387 /* Drop the lock: we've finished altering table existence, and 388 * filter insertion will need to take the lock for read. 389 */ 390 up_write(&efx->filter_sem); 391 #ifdef CONFIG_SFC_SRIOV 392 rc = efx_tc_insert_rep_filters(efx); 393 /* Rep filter failure is nonfatal */ 394 if (rc) 395 netif_warn(efx, drv, efx->net_dev, 396 "Failed to insert representor filters, rc %d\n", 397 rc); 398 #endif 399 return 0; 400 401 fail_vlan0: 402 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC); 403 fail_unspec: 404 efx_mcdi_filter_table_down(efx); 405 up_write(&efx->filter_sem); 406 return rc; 407 } 408 409 static void ef100_filter_table_down(struct efx_nic *efx) 410 { 411 #ifdef CONFIG_SFC_SRIOV 412 efx_tc_remove_rep_filters(efx); 413 #endif 414 down_write(&efx->filter_sem); 415 efx_mcdi_filter_del_vlan(efx, 0); 416 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC); 417 efx_mcdi_filter_table_down(efx); 418 up_write(&efx->filter_sem); 419 } 420 421 /* Other 422 */ 423 static int ef100_reconfigure_mac(struct efx_nic *efx, bool mtu_only) 424 { 425 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 426 427 efx_mcdi_filter_sync_rx_mode(efx); 428 429 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED)) 430 return efx_mcdi_set_mtu(efx); 431 return efx_mcdi_set_mac(efx); 432 } 433 434 static enum reset_type ef100_map_reset_reason(enum reset_type reason) 435 { 436 if (reason == RESET_TYPE_TX_WATCHDOG) 437 return reason; 438 return RESET_TYPE_DISABLE; 439 } 440 441 static int ef100_map_reset_flags(u32 *flags) 442 { 443 /* Only perform a RESET_TYPE_ALL because we don't support MC_REBOOTs */ 444 if ((*flags & EF100_RESET_PORT)) { 445 *flags &= ~EF100_RESET_PORT; 446 return RESET_TYPE_ALL; 447 } 448 if (*flags & ETH_RESET_MGMT) { 449 *flags &= ~ETH_RESET_MGMT; 450 return RESET_TYPE_DISABLE; 451 } 452 453 return -EINVAL; 454 } 455 456 static int ef100_reset(struct efx_nic *efx, enum reset_type reset_type) 457 { 458 int rc; 459 460 dev_close(efx->net_dev); 461 462 if (reset_type == RESET_TYPE_TX_WATCHDOG) { 463 netif_device_attach(efx->net_dev); 464 __clear_bit(reset_type, &efx->reset_pending); 465 rc = dev_open(efx->net_dev, NULL); 466 } else if (reset_type == RESET_TYPE_ALL) { 467 rc = efx_mcdi_reset(efx, reset_type); 468 if (rc) 469 return rc; 470 471 netif_device_attach(efx->net_dev); 472 473 rc = dev_open(efx->net_dev, NULL); 474 } else { 475 rc = 1; /* Leave the device closed */ 476 } 477 return rc; 478 } 479 480 static void ef100_common_stat_mask(unsigned long *mask) 481 { 482 __set_bit(EF100_STAT_port_rx_packets, mask); 483 __set_bit(EF100_STAT_port_tx_packets, mask); 484 __set_bit(EF100_STAT_port_rx_bytes, mask); 485 __set_bit(EF100_STAT_port_tx_bytes, mask); 486 __set_bit(EF100_STAT_port_rx_multicast, mask); 487 __set_bit(EF100_STAT_port_rx_bad, mask); 488 __set_bit(EF100_STAT_port_rx_align_error, mask); 489 __set_bit(EF100_STAT_port_rx_overflow, mask); 490 } 491 492 static void ef100_ethtool_stat_mask(unsigned long *mask) 493 { 494 __set_bit(EF100_STAT_port_tx_pause, mask); 495 __set_bit(EF100_STAT_port_tx_unicast, mask); 496 __set_bit(EF100_STAT_port_tx_multicast, mask); 497 __set_bit(EF100_STAT_port_tx_broadcast, mask); 498 __set_bit(EF100_STAT_port_tx_lt64, mask); 499 __set_bit(EF100_STAT_port_tx_64, mask); 500 __set_bit(EF100_STAT_port_tx_65_to_127, mask); 501 __set_bit(EF100_STAT_port_tx_128_to_255, mask); 502 __set_bit(EF100_STAT_port_tx_256_to_511, mask); 503 __set_bit(EF100_STAT_port_tx_512_to_1023, mask); 504 __set_bit(EF100_STAT_port_tx_1024_to_15xx, mask); 505 __set_bit(EF100_STAT_port_tx_15xx_to_jumbo, mask); 506 __set_bit(EF100_STAT_port_rx_good, mask); 507 __set_bit(EF100_STAT_port_rx_pause, mask); 508 __set_bit(EF100_STAT_port_rx_unicast, mask); 509 __set_bit(EF100_STAT_port_rx_broadcast, mask); 510 __set_bit(EF100_STAT_port_rx_lt64, mask); 511 __set_bit(EF100_STAT_port_rx_64, mask); 512 __set_bit(EF100_STAT_port_rx_65_to_127, mask); 513 __set_bit(EF100_STAT_port_rx_128_to_255, mask); 514 __set_bit(EF100_STAT_port_rx_256_to_511, mask); 515 __set_bit(EF100_STAT_port_rx_512_to_1023, mask); 516 __set_bit(EF100_STAT_port_rx_1024_to_15xx, mask); 517 __set_bit(EF100_STAT_port_rx_15xx_to_jumbo, mask); 518 __set_bit(EF100_STAT_port_rx_gtjumbo, mask); 519 __set_bit(EF100_STAT_port_rx_bad_gtjumbo, mask); 520 __set_bit(EF100_STAT_port_rx_length_error, mask); 521 __set_bit(EF100_STAT_port_rx_nodesc_drops, mask); 522 __set_bit(GENERIC_STAT_rx_nodesc_trunc, mask); 523 __set_bit(GENERIC_STAT_rx_noskb_drops, mask); 524 } 525 526 #define EF100_DMA_STAT(ext_name, mcdi_name) \ 527 [EF100_STAT_ ## ext_name] = \ 528 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 529 530 static const struct efx_hw_stat_desc ef100_stat_desc[EF100_STAT_COUNT] = { 531 EF100_DMA_STAT(port_tx_bytes, TX_BYTES), 532 EF100_DMA_STAT(port_tx_packets, TX_PKTS), 533 EF100_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 534 EF100_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 535 EF100_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 536 EF100_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 537 EF100_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 538 EF100_DMA_STAT(port_tx_64, TX_64_PKTS), 539 EF100_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 540 EF100_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 541 EF100_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 542 EF100_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 543 EF100_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 544 EF100_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 545 EF100_DMA_STAT(port_rx_bytes, RX_BYTES), 546 EF100_DMA_STAT(port_rx_packets, RX_PKTS), 547 EF100_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 548 EF100_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 549 EF100_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 550 EF100_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 551 EF100_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 552 EF100_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 553 EF100_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 554 EF100_DMA_STAT(port_rx_64, RX_64_PKTS), 555 EF100_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 556 EF100_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 557 EF100_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 558 EF100_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 559 EF100_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 560 EF100_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 561 EF100_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 562 EF100_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 563 EF100_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 564 EF100_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 565 EF100_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 566 EF100_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 567 EFX_GENERIC_SW_STAT(rx_nodesc_trunc), 568 EFX_GENERIC_SW_STAT(rx_noskb_drops), 569 }; 570 571 static size_t ef100_describe_stats(struct efx_nic *efx, u8 *names) 572 { 573 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {}; 574 575 ef100_ethtool_stat_mask(mask); 576 return efx_nic_describe_stats(ef100_stat_desc, EF100_STAT_COUNT, 577 mask, names); 578 } 579 580 static size_t ef100_update_stats_common(struct efx_nic *efx, u64 *full_stats, 581 struct rtnl_link_stats64 *core_stats) 582 { 583 struct ef100_nic_data *nic_data = efx->nic_data; 584 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {}; 585 size_t stats_count = 0, index; 586 u64 *stats = nic_data->stats; 587 588 ef100_ethtool_stat_mask(mask); 589 590 if (full_stats) { 591 for_each_set_bit(index, mask, EF100_STAT_COUNT) { 592 if (ef100_stat_desc[index].name) { 593 *full_stats++ = stats[index]; 594 ++stats_count; 595 } 596 } 597 } 598 599 if (!core_stats) 600 return stats_count; 601 602 core_stats->rx_packets = stats[EF100_STAT_port_rx_packets]; 603 core_stats->tx_packets = stats[EF100_STAT_port_tx_packets]; 604 core_stats->rx_bytes = stats[EF100_STAT_port_rx_bytes]; 605 core_stats->tx_bytes = stats[EF100_STAT_port_tx_bytes]; 606 core_stats->rx_dropped = stats[EF100_STAT_port_rx_nodesc_drops] + 607 stats[GENERIC_STAT_rx_nodesc_trunc] + 608 stats[GENERIC_STAT_rx_noskb_drops]; 609 core_stats->multicast = stats[EF100_STAT_port_rx_multicast]; 610 core_stats->rx_length_errors = 611 stats[EF100_STAT_port_rx_gtjumbo] + 612 stats[EF100_STAT_port_rx_length_error]; 613 core_stats->rx_crc_errors = stats[EF100_STAT_port_rx_bad]; 614 core_stats->rx_frame_errors = 615 stats[EF100_STAT_port_rx_align_error]; 616 core_stats->rx_fifo_errors = stats[EF100_STAT_port_rx_overflow]; 617 core_stats->rx_errors = (core_stats->rx_length_errors + 618 core_stats->rx_crc_errors + 619 core_stats->rx_frame_errors); 620 621 return stats_count; 622 } 623 624 static size_t ef100_update_stats(struct efx_nic *efx, 625 u64 *full_stats, 626 struct rtnl_link_stats64 *core_stats) 627 { 628 __le64 *mc_stats = kmalloc(array_size(efx->num_mac_stats, sizeof(__le64)), GFP_ATOMIC); 629 struct ef100_nic_data *nic_data = efx->nic_data; 630 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {}; 631 u64 *stats = nic_data->stats; 632 633 ef100_common_stat_mask(mask); 634 ef100_ethtool_stat_mask(mask); 635 636 if (!mc_stats) 637 return 0; 638 639 efx_nic_copy_stats(efx, mc_stats); 640 efx_nic_update_stats(ef100_stat_desc, EF100_STAT_COUNT, mask, 641 stats, mc_stats, false); 642 643 kfree(mc_stats); 644 645 return ef100_update_stats_common(efx, full_stats, core_stats); 646 } 647 648 static int efx_ef100_get_phys_port_id(struct efx_nic *efx, 649 struct netdev_phys_item_id *ppid) 650 { 651 struct ef100_nic_data *nic_data = efx->nic_data; 652 653 if (!is_valid_ether_addr(nic_data->port_id)) 654 return -EOPNOTSUPP; 655 656 ppid->id_len = ETH_ALEN; 657 memcpy(ppid->id, nic_data->port_id, ppid->id_len); 658 659 return 0; 660 } 661 662 static int efx_ef100_irq_test_generate(struct efx_nic *efx) 663 { 664 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 665 666 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 667 668 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 669 return efx_mcdi_rpc_quiet(efx, MC_CMD_TRIGGER_INTERRUPT, 670 inbuf, sizeof(inbuf), NULL, 0, NULL); 671 } 672 673 #define EFX_EF100_TEST 1 674 675 static void efx_ef100_ev_test_generate(struct efx_channel *channel) 676 { 677 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 678 struct efx_nic *efx = channel->efx; 679 efx_qword_t event; 680 int rc; 681 682 EFX_POPULATE_QWORD_2(event, 683 ESF_GZ_E_TYPE, ESE_GZ_EF100_EV_DRIVER, 684 ESF_GZ_DRIVER_DATA, EFX_EF100_TEST); 685 686 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 687 688 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 689 * already swapped the data to little-endian order. 690 */ 691 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 692 sizeof(efx_qword_t)); 693 694 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 695 NULL, 0, NULL); 696 if (rc && (rc != -ENETDOWN)) 697 goto fail; 698 699 return; 700 701 fail: 702 WARN_ON(true); 703 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 704 } 705 706 static unsigned int ef100_check_caps(const struct efx_nic *efx, 707 u8 flag, u32 offset) 708 { 709 const struct ef100_nic_data *nic_data = efx->nic_data; 710 711 switch (offset) { 712 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST: 713 return nic_data->datapath_caps & BIT_ULL(flag); 714 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST: 715 return nic_data->datapath_caps2 & BIT_ULL(flag); 716 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST: 717 return nic_data->datapath_caps3 & BIT_ULL(flag); 718 default: 719 return 0; 720 } 721 } 722 723 static unsigned int efx_ef100_recycle_ring_size(const struct efx_nic *efx) 724 { 725 /* Maximum link speed for Riverhead is 100G */ 726 return 10 * EFX_RECYCLE_RING_SIZE_10G; 727 } 728 729 #ifdef CONFIG_SFC_SRIOV 730 static int efx_ef100_get_base_mport(struct efx_nic *efx) 731 { 732 struct ef100_nic_data *nic_data = efx->nic_data; 733 u32 selector, id; 734 int rc; 735 736 /* Construct mport selector for "physical network port" */ 737 efx_mae_mport_wire(efx, &selector); 738 /* Look up actual mport ID */ 739 rc = efx_mae_lookup_mport(efx, selector, &id); 740 if (rc) 741 return rc; 742 /* The ID should always fit in 16 bits, because that's how wide the 743 * corresponding fields in the RX prefix & TX override descriptor are 744 */ 745 if (id >> 16) 746 netif_warn(efx, probe, efx->net_dev, "Bad base m-port id %#x\n", 747 id); 748 nic_data->base_mport = id; 749 nic_data->have_mport = true; 750 return 0; 751 } 752 #endif 753 754 static int compare_versions(const char *a, const char *b) 755 { 756 int a_major, a_minor, a_point, a_patch; 757 int b_major, b_minor, b_point, b_patch; 758 int a_matched, b_matched; 759 760 a_matched = sscanf(a, "%d.%d.%d.%d", &a_major, &a_minor, &a_point, &a_patch); 761 b_matched = sscanf(b, "%d.%d.%d.%d", &b_major, &b_minor, &b_point, &b_patch); 762 763 if (a_matched == 4 && b_matched != 4) 764 return +1; 765 766 if (a_matched != 4 && b_matched == 4) 767 return -1; 768 769 if (a_matched != 4 && b_matched != 4) 770 return 0; 771 772 if (a_major != b_major) 773 return a_major - b_major; 774 775 if (a_minor != b_minor) 776 return a_minor - b_minor; 777 778 if (a_point != b_point) 779 return a_point - b_point; 780 781 return a_patch - b_patch; 782 } 783 784 enum ef100_tlv_state_machine { 785 EF100_TLV_TYPE, 786 EF100_TLV_TYPE_CONT, 787 EF100_TLV_LENGTH, 788 EF100_TLV_VALUE 789 }; 790 791 struct ef100_tlv_state { 792 enum ef100_tlv_state_machine state; 793 u64 value; 794 u32 value_offset; 795 u16 type; 796 u8 len; 797 }; 798 799 static int ef100_tlv_feed(struct ef100_tlv_state *state, u8 byte) 800 { 801 switch (state->state) { 802 case EF100_TLV_TYPE: 803 state->type = byte & 0x7f; 804 state->state = (byte & 0x80) ? EF100_TLV_TYPE_CONT 805 : EF100_TLV_LENGTH; 806 /* Clear ready to read in a new entry */ 807 state->value = 0; 808 state->value_offset = 0; 809 return 0; 810 case EF100_TLV_TYPE_CONT: 811 state->type |= byte << 7; 812 state->state = EF100_TLV_LENGTH; 813 return 0; 814 case EF100_TLV_LENGTH: 815 state->len = byte; 816 /* We only handle TLVs that fit in a u64 */ 817 if (state->len > sizeof(state->value)) 818 return -EOPNOTSUPP; 819 /* len may be zero, implying a value of zero */ 820 state->state = state->len ? EF100_TLV_VALUE : EF100_TLV_TYPE; 821 return 0; 822 case EF100_TLV_VALUE: 823 state->value |= ((u64)byte) << (state->value_offset * 8); 824 state->value_offset++; 825 if (state->value_offset >= state->len) 826 state->state = EF100_TLV_TYPE; 827 return 0; 828 default: /* state machine error, can't happen */ 829 WARN_ON_ONCE(1); 830 return -EIO; 831 } 832 } 833 834 static int ef100_process_design_param(struct efx_nic *efx, 835 const struct ef100_tlv_state *reader) 836 { 837 struct ef100_nic_data *nic_data = efx->nic_data; 838 839 switch (reader->type) { 840 case ESE_EF100_DP_GZ_PAD: /* padding, skip it */ 841 return 0; 842 case ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS: 843 /* Driver doesn't support timestamping yet, so we don't care */ 844 return 0; 845 case ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS: 846 /* Driver doesn't support unsolicited-event credits yet, so 847 * we don't care 848 */ 849 return 0; 850 case ESE_EF100_DP_GZ_NMMU_GROUP_SIZE: 851 /* Driver doesn't manage the NMMU (so we don't care) */ 852 return 0; 853 case ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS: 854 /* Driver uses CHECKSUM_COMPLETE, so we don't care about 855 * protocol checksum validation 856 */ 857 return 0; 858 case ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN: 859 nic_data->tso_max_hdr_len = min_t(u64, reader->value, 0xffff); 860 return 0; 861 case ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS: 862 /* We always put HDR_NUM_SEGS=1 in our TSO descriptors */ 863 if (!reader->value) { 864 netif_err(efx, probe, efx->net_dev, 865 "TSO_MAX_HDR_NUM_SEGS < 1\n"); 866 return -EOPNOTSUPP; 867 } 868 return 0; 869 case ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY: 870 case ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY: 871 /* Our TXQ and RXQ sizes are always power-of-two and thus divisible by 872 * EFX_MIN_DMAQ_SIZE, so we just need to check that 873 * EFX_MIN_DMAQ_SIZE is divisible by GRANULARITY. 874 * This is very unlikely to fail. 875 */ 876 if (!reader->value || reader->value > EFX_MIN_DMAQ_SIZE || 877 EFX_MIN_DMAQ_SIZE % (u32)reader->value) { 878 netif_err(efx, probe, efx->net_dev, 879 "%s size granularity is %llu, can't guarantee safety\n", 880 reader->type == ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY ? "RXQ" : "TXQ", 881 reader->value); 882 return -EOPNOTSUPP; 883 } 884 return 0; 885 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN: 886 nic_data->tso_max_payload_len = min_t(u64, reader->value, 887 GSO_LEGACY_MAX_SIZE); 888 netif_set_tso_max_size(efx->net_dev, 889 nic_data->tso_max_payload_len); 890 return 0; 891 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS: 892 nic_data->tso_max_payload_num_segs = min_t(u64, reader->value, 0xffff); 893 netif_set_tso_max_segs(efx->net_dev, 894 nic_data->tso_max_payload_num_segs); 895 return 0; 896 case ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES: 897 nic_data->tso_max_frames = min_t(u64, reader->value, 0xffff); 898 return 0; 899 case ESE_EF100_DP_GZ_COMPAT: 900 if (reader->value) { 901 netif_err(efx, probe, efx->net_dev, 902 "DP_COMPAT has unknown bits %#llx, driver not compatible with this hw\n", 903 reader->value); 904 return -EOPNOTSUPP; 905 } 906 return 0; 907 case ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN: 908 /* Driver doesn't use mem2mem transfers */ 909 return 0; 910 case ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS: 911 /* Driver doesn't currently use EVQ_TIMER */ 912 return 0; 913 case ESE_EF100_DP_GZ_NMMU_PAGE_SIZES: 914 /* Driver doesn't manage the NMMU (so we don't care) */ 915 return 0; 916 case ESE_EF100_DP_GZ_VI_STRIDES: 917 /* We never try to set the VI stride, and we don't rely on 918 * being able to find VIs past VI 0 until after we've learned 919 * the current stride from MC_CMD_GET_CAPABILITIES. 920 * So the value of this shouldn't matter. 921 */ 922 if (reader->value != ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT) 923 netif_dbg(efx, probe, efx->net_dev, 924 "NIC has other than default VI_STRIDES (mask " 925 "%#llx), early probing might use wrong one\n", 926 reader->value); 927 return 0; 928 case ESE_EF100_DP_GZ_RX_MAX_RUNT: 929 /* Driver doesn't look at L2_STATUS:LEN_ERR bit, so we don't 930 * care whether it indicates runt or overlength for any given 931 * packet, so we don't care about this parameter. 932 */ 933 return 0; 934 default: 935 /* Host interface says "Drivers should ignore design parameters 936 * that they do not recognise." 937 */ 938 netif_dbg(efx, probe, efx->net_dev, 939 "Ignoring unrecognised design parameter %u\n", 940 reader->type); 941 return 0; 942 } 943 } 944 945 static int ef100_check_design_params(struct efx_nic *efx) 946 { 947 struct ef100_tlv_state reader = {}; 948 u32 total_len, offset = 0; 949 efx_dword_t reg; 950 int rc = 0, i; 951 u32 data; 952 953 efx_readd(efx, ®, ER_GZ_PARAMS_TLV_LEN); 954 total_len = EFX_DWORD_FIELD(reg, EFX_DWORD_0); 955 pci_dbg(efx->pci_dev, "%u bytes of design parameters\n", total_len); 956 while (offset < total_len) { 957 efx_readd(efx, ®, ER_GZ_PARAMS_TLV + offset); 958 data = EFX_DWORD_FIELD(reg, EFX_DWORD_0); 959 for (i = 0; i < sizeof(data); i++) { 960 rc = ef100_tlv_feed(&reader, data); 961 /* Got a complete value? */ 962 if (!rc && reader.state == EF100_TLV_TYPE) 963 rc = ef100_process_design_param(efx, &reader); 964 if (rc) 965 goto out; 966 data >>= 8; 967 offset++; 968 } 969 } 970 /* Check we didn't end halfway through a TLV entry, which could either 971 * mean that the TLV stream is truncated or just that it's corrupted 972 * and our state machine is out of sync. 973 */ 974 if (reader.state != EF100_TLV_TYPE) { 975 if (reader.state == EF100_TLV_TYPE_CONT) 976 netif_err(efx, probe, efx->net_dev, 977 "truncated design parameter (incomplete type %u)\n", 978 reader.type); 979 else 980 netif_err(efx, probe, efx->net_dev, 981 "truncated design parameter %u\n", 982 reader.type); 983 rc = -EIO; 984 } 985 out: 986 return rc; 987 } 988 989 /* NIC probe and remove 990 */ 991 static int ef100_probe_main(struct efx_nic *efx) 992 { 993 unsigned int bar_size = resource_size(&efx->pci_dev->resource[efx->mem_bar]); 994 struct ef100_nic_data *nic_data; 995 char fw_version[32]; 996 u32 priv_mask = 0; 997 int i, rc; 998 999 if (WARN_ON(bar_size == 0)) 1000 return -EIO; 1001 1002 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 1003 if (!nic_data) 1004 return -ENOMEM; 1005 efx->nic_data = nic_data; 1006 nic_data->efx = efx; 1007 efx->max_vis = EF100_MAX_VIS; 1008 1009 /* Populate design-parameter defaults */ 1010 nic_data->tso_max_hdr_len = ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT; 1011 nic_data->tso_max_frames = ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT; 1012 nic_data->tso_max_payload_num_segs = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT; 1013 nic_data->tso_max_payload_len = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT; 1014 1015 /* Read design parameters */ 1016 rc = ef100_check_design_params(efx); 1017 if (rc) { 1018 pci_err(efx->pci_dev, "Unsupported design parameters\n"); 1019 goto fail; 1020 } 1021 1022 /* we assume later that we can copy from this buffer in dwords */ 1023 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 1024 1025 /* MCDI buffers must be 256 byte aligned. */ 1026 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, MCDI_BUF_LEN, 1027 GFP_KERNEL); 1028 if (rc) 1029 goto fail; 1030 1031 /* Get the MC's warm boot count. In case it's rebooting right 1032 * now, be prepared to retry. 1033 */ 1034 i = 0; 1035 for (;;) { 1036 rc = ef100_get_warm_boot_count(efx); 1037 if (rc >= 0) 1038 break; 1039 if (++i == 5) 1040 goto fail; 1041 ssleep(1); 1042 } 1043 nic_data->warm_boot_count = rc; 1044 1045 /* In case we're recovering from a crash (kexec), we want to 1046 * cancel any outstanding request by the previous user of this 1047 * function. We send a special message using the least 1048 * significant bits of the 'high' (doorbell) register. 1049 */ 1050 _efx_writed(efx, cpu_to_le32(1), efx_reg(efx, ER_GZ_MC_DB_HWRD)); 1051 1052 /* Post-IO section. */ 1053 1054 rc = efx_mcdi_init(efx); 1055 if (rc) 1056 goto fail; 1057 /* Reset (most) configuration for this function */ 1058 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 1059 if (rc) 1060 goto fail; 1061 /* Enable event logging */ 1062 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 1063 if (rc) 1064 goto fail; 1065 1066 rc = efx_get_pf_index(efx, &nic_data->pf_index); 1067 if (rc) 1068 goto fail; 1069 1070 rc = efx_mcdi_port_get_number(efx); 1071 if (rc < 0) 1072 goto fail; 1073 efx->port_num = rc; 1074 1075 efx_mcdi_print_fwver(efx, fw_version, sizeof(fw_version)); 1076 pci_dbg(efx->pci_dev, "Firmware version %s\n", fw_version); 1077 1078 rc = efx_mcdi_get_privilege_mask(efx, &priv_mask); 1079 if (rc) /* non-fatal, and priv_mask will still be 0 */ 1080 pci_info(efx->pci_dev, 1081 "Failed to get privilege mask from FW, rc %d\n", rc); 1082 nic_data->grp_mae = !!(priv_mask & MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE); 1083 1084 if (compare_versions(fw_version, "1.1.0.1000") < 0) { 1085 pci_info(efx->pci_dev, "Firmware uses old event descriptors\n"); 1086 rc = -EINVAL; 1087 goto fail; 1088 } 1089 1090 if (efx_has_cap(efx, UNSOL_EV_CREDIT_SUPPORTED)) { 1091 pci_info(efx->pci_dev, "Firmware uses unsolicited-event credits\n"); 1092 rc = -EINVAL; 1093 goto fail; 1094 } 1095 1096 return 0; 1097 fail: 1098 return rc; 1099 } 1100 1101 int ef100_probe_netdev_pf(struct efx_nic *efx) 1102 { 1103 struct ef100_nic_data *nic_data = efx->nic_data; 1104 struct net_device *net_dev = efx->net_dev; 1105 int rc; 1106 1107 rc = ef100_get_mac_address(efx, net_dev->perm_addr); 1108 if (rc) 1109 goto fail; 1110 /* Assign MAC address */ 1111 eth_hw_addr_set(net_dev, net_dev->perm_addr); 1112 memcpy(nic_data->port_id, net_dev->perm_addr, ETH_ALEN); 1113 1114 if (!nic_data->grp_mae) 1115 return 0; 1116 1117 #ifdef CONFIG_SFC_SRIOV 1118 rc = efx_init_struct_tc(efx); 1119 if (rc) 1120 return rc; 1121 1122 rc = efx_ef100_get_base_mport(efx); 1123 if (rc) { 1124 netif_warn(efx, probe, net_dev, 1125 "Failed to probe base mport rc %d; representors will not function\n", 1126 rc); 1127 } 1128 1129 rc = efx_init_tc(efx); 1130 if (rc) { 1131 /* Either we don't have an MAE at all (i.e. legacy v-switching), 1132 * or we do but we failed to probe it. In the latter case, we 1133 * may not have set up default rules, in which case we won't be 1134 * able to pass any traffic. However, we don't fail the probe, 1135 * because the user might need to use the netdevice to apply 1136 * configuration changes to fix whatever's wrong with the MAE. 1137 */ 1138 netif_warn(efx, probe, net_dev, "Failed to probe MAE rc %d\n", 1139 rc); 1140 } else { 1141 net_dev->features |= NETIF_F_HW_TC; 1142 efx->fixed_features |= NETIF_F_HW_TC; 1143 } 1144 #endif 1145 return 0; 1146 1147 fail: 1148 return rc; 1149 } 1150 1151 int ef100_probe_vf(struct efx_nic *efx) 1152 { 1153 return ef100_probe_main(efx); 1154 } 1155 1156 void ef100_remove(struct efx_nic *efx) 1157 { 1158 struct ef100_nic_data *nic_data = efx->nic_data; 1159 1160 efx_mcdi_detach(efx); 1161 efx_mcdi_fini(efx); 1162 if (nic_data) 1163 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 1164 kfree(nic_data); 1165 efx->nic_data = NULL; 1166 } 1167 1168 /* NIC level access functions 1169 */ 1170 #define EF100_OFFLOAD_FEATURES (NETIF_F_HW_CSUM | NETIF_F_RXCSUM | \ 1171 NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_NTUPLE | \ 1172 NETIF_F_RXHASH | NETIF_F_RXFCS | NETIF_F_TSO_ECN | NETIF_F_RXALL | \ 1173 NETIF_F_HW_VLAN_CTAG_TX) 1174 1175 const struct efx_nic_type ef100_pf_nic_type = { 1176 .revision = EFX_REV_EF100, 1177 .is_vf = false, 1178 .probe = ef100_probe_main, 1179 .offload_features = EF100_OFFLOAD_FEATURES, 1180 .mcdi_max_ver = 2, 1181 .mcdi_request = ef100_mcdi_request, 1182 .mcdi_poll_response = ef100_mcdi_poll_response, 1183 .mcdi_read_response = ef100_mcdi_read_response, 1184 .mcdi_poll_reboot = ef100_mcdi_poll_reboot, 1185 .mcdi_reboot_detected = ef100_mcdi_reboot_detected, 1186 .irq_enable_master = efx_port_dummy_op_void, 1187 .irq_test_generate = efx_ef100_irq_test_generate, 1188 .irq_disable_non_ev = efx_port_dummy_op_void, 1189 .push_irq_moderation = efx_channel_dummy_op_void, 1190 .min_interrupt_mode = EFX_INT_MODE_MSIX, 1191 .map_reset_reason = ef100_map_reset_reason, 1192 .map_reset_flags = ef100_map_reset_flags, 1193 .reset = ef100_reset, 1194 1195 .check_caps = ef100_check_caps, 1196 1197 .ev_probe = ef100_ev_probe, 1198 .ev_init = ef100_ev_init, 1199 .ev_fini = efx_mcdi_ev_fini, 1200 .ev_remove = efx_mcdi_ev_remove, 1201 .irq_handle_msi = ef100_msi_interrupt, 1202 .ev_process = ef100_ev_process, 1203 .ev_read_ack = ef100_ev_read_ack, 1204 .ev_test_generate = efx_ef100_ev_test_generate, 1205 .tx_probe = ef100_tx_probe, 1206 .tx_init = ef100_tx_init, 1207 .tx_write = ef100_tx_write, 1208 .tx_enqueue = ef100_enqueue_skb, 1209 .rx_probe = efx_mcdi_rx_probe, 1210 .rx_init = efx_mcdi_rx_init, 1211 .rx_remove = efx_mcdi_rx_remove, 1212 .rx_write = ef100_rx_write, 1213 .rx_packet = __ef100_rx_packet, 1214 .rx_buf_hash_valid = ef100_rx_buf_hash_valid, 1215 .fini_dmaq = efx_fini_dmaq, 1216 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 1217 .filter_table_probe = ef100_filter_table_up, 1218 .filter_table_restore = efx_mcdi_filter_table_restore, 1219 .filter_table_remove = ef100_filter_table_down, 1220 .filter_insert = efx_mcdi_filter_insert, 1221 .filter_remove_safe = efx_mcdi_filter_remove_safe, 1222 .filter_get_safe = efx_mcdi_filter_get_safe, 1223 .filter_clear_rx = efx_mcdi_filter_clear_rx, 1224 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 1225 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 1226 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 1227 #ifdef CONFIG_RFS_ACCEL 1228 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 1229 #endif 1230 1231 .get_phys_port_id = efx_ef100_get_phys_port_id, 1232 1233 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN, 1234 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8, 1235 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8, 1236 .rx_hash_key_size = 40, 1237 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 1238 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 1239 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config, 1240 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config, 1241 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 1242 .rx_recycle_ring_size = efx_ef100_recycle_ring_size, 1243 1244 .reconfigure_mac = ef100_reconfigure_mac, 1245 .reconfigure_port = efx_mcdi_port_reconfigure, 1246 .test_nvram = efx_new_mcdi_nvram_test_all, 1247 .describe_stats = ef100_describe_stats, 1248 .start_stats = efx_mcdi_mac_start_stats, 1249 .update_stats = ef100_update_stats, 1250 .pull_stats = efx_mcdi_mac_pull_stats, 1251 .stop_stats = efx_mcdi_mac_stop_stats, 1252 #ifdef CONFIG_SFC_SRIOV 1253 .sriov_configure = efx_ef100_sriov_configure, 1254 #endif 1255 1256 /* Per-type bar/size configuration not used on ef100. Location of 1257 * registers is defined by extended capabilities. 1258 */ 1259 .mem_bar = NULL, 1260 .mem_map_size = NULL, 1261 1262 }; 1263 1264 const struct efx_nic_type ef100_vf_nic_type = { 1265 .revision = EFX_REV_EF100, 1266 .is_vf = true, 1267 .probe = ef100_probe_vf, 1268 .offload_features = EF100_OFFLOAD_FEATURES, 1269 .mcdi_max_ver = 2, 1270 .mcdi_request = ef100_mcdi_request, 1271 .mcdi_poll_response = ef100_mcdi_poll_response, 1272 .mcdi_read_response = ef100_mcdi_read_response, 1273 .mcdi_poll_reboot = ef100_mcdi_poll_reboot, 1274 .mcdi_reboot_detected = ef100_mcdi_reboot_detected, 1275 .irq_enable_master = efx_port_dummy_op_void, 1276 .irq_test_generate = efx_ef100_irq_test_generate, 1277 .irq_disable_non_ev = efx_port_dummy_op_void, 1278 .push_irq_moderation = efx_channel_dummy_op_void, 1279 .min_interrupt_mode = EFX_INT_MODE_MSIX, 1280 .map_reset_reason = ef100_map_reset_reason, 1281 .map_reset_flags = ef100_map_reset_flags, 1282 .reset = ef100_reset, 1283 .check_caps = ef100_check_caps, 1284 .ev_probe = ef100_ev_probe, 1285 .ev_init = ef100_ev_init, 1286 .ev_fini = efx_mcdi_ev_fini, 1287 .ev_remove = efx_mcdi_ev_remove, 1288 .irq_handle_msi = ef100_msi_interrupt, 1289 .ev_process = ef100_ev_process, 1290 .ev_read_ack = ef100_ev_read_ack, 1291 .ev_test_generate = efx_ef100_ev_test_generate, 1292 .tx_probe = ef100_tx_probe, 1293 .tx_init = ef100_tx_init, 1294 .tx_write = ef100_tx_write, 1295 .tx_enqueue = ef100_enqueue_skb, 1296 .rx_probe = efx_mcdi_rx_probe, 1297 .rx_init = efx_mcdi_rx_init, 1298 .rx_remove = efx_mcdi_rx_remove, 1299 .rx_write = ef100_rx_write, 1300 .rx_packet = __ef100_rx_packet, 1301 .rx_buf_hash_valid = ef100_rx_buf_hash_valid, 1302 .fini_dmaq = efx_fini_dmaq, 1303 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 1304 .filter_table_probe = ef100_filter_table_up, 1305 .filter_table_restore = efx_mcdi_filter_table_restore, 1306 .filter_table_remove = ef100_filter_table_down, 1307 .filter_insert = efx_mcdi_filter_insert, 1308 .filter_remove_safe = efx_mcdi_filter_remove_safe, 1309 .filter_get_safe = efx_mcdi_filter_get_safe, 1310 .filter_clear_rx = efx_mcdi_filter_clear_rx, 1311 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 1312 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 1313 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 1314 #ifdef CONFIG_RFS_ACCEL 1315 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 1316 #endif 1317 1318 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN, 1319 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8, 1320 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8, 1321 .rx_hash_key_size = 40, 1322 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 1323 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 1324 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 1325 .rx_recycle_ring_size = efx_ef100_recycle_ring_size, 1326 1327 .reconfigure_mac = ef100_reconfigure_mac, 1328 .test_nvram = efx_new_mcdi_nvram_test_all, 1329 .describe_stats = ef100_describe_stats, 1330 .start_stats = efx_mcdi_mac_start_stats, 1331 .update_stats = ef100_update_stats, 1332 .pull_stats = efx_mcdi_mac_pull_stats, 1333 .stop_stats = efx_mcdi_mac_stop_stats, 1334 1335 .mem_bar = NULL, 1336 .mem_map_size = NULL, 1337 1338 }; 1339