1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2012-2013 Solarflare Communications Inc. 5 */ 6 7 #include "net_driver.h" 8 #include "rx_common.h" 9 #include "ef10_regs.h" 10 #include "io.h" 11 #include "mcdi.h" 12 #include "mcdi_pcol.h" 13 #include "mcdi_port.h" 14 #include "mcdi_port_common.h" 15 #include "mcdi_functions.h" 16 #include "nic.h" 17 #include "mcdi_filters.h" 18 #include "workarounds.h" 19 #include "selftest.h" 20 #include "ef10_sriov.h" 21 #include <linux/in.h> 22 #include <linux/jhash.h> 23 #include <linux/wait.h> 24 #include <linux/workqueue.h> 25 #include <net/udp_tunnel.h> 26 27 /* Hardware control for EF10 architecture including 'Huntington'. */ 28 29 #define EFX_EF10_DRVGEN_EV 7 30 enum { 31 EFX_EF10_TEST = 1, 32 EFX_EF10_REFILL, 33 }; 34 35 /* VLAN list entry */ 36 struct efx_ef10_vlan { 37 struct list_head list; 38 u16 vid; 39 }; 40 41 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading); 42 static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels; 43 44 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 45 { 46 efx_dword_t reg; 47 48 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 49 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 50 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 51 } 52 53 /* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for 54 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O 55 * bar; PFs use BAR 0/1 for memory. 56 */ 57 static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx) 58 { 59 switch (efx->pci_dev->device) { 60 case 0x0b03: /* SFC9250 PF */ 61 return 0; 62 default: 63 return 2; 64 } 65 } 66 67 /* All VFs use BAR 0/1 for memory */ 68 static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx) 69 { 70 return 0; 71 } 72 73 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 74 { 75 int bar; 76 77 bar = efx->type->mem_bar(efx); 78 return resource_size(&efx->pci_dev->resource[bar]); 79 } 80 81 static bool efx_ef10_is_vf(struct efx_nic *efx) 82 { 83 return efx->type->is_vf; 84 } 85 86 #ifdef CONFIG_SFC_SRIOV 87 static int efx_ef10_get_vf_index(struct efx_nic *efx) 88 { 89 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 90 struct efx_ef10_nic_data *nic_data = efx->nic_data; 91 size_t outlen; 92 int rc; 93 94 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 95 sizeof(outbuf), &outlen); 96 if (rc) 97 return rc; 98 if (outlen < sizeof(outbuf)) 99 return -EIO; 100 101 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF); 102 return 0; 103 } 104 #endif 105 106 static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 107 { 108 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN); 109 struct efx_ef10_nic_data *nic_data = efx->nic_data; 110 size_t outlen; 111 int rc; 112 113 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 114 115 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 116 outbuf, sizeof(outbuf), &outlen); 117 if (rc) 118 return rc; 119 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) { 120 netif_err(efx, drv, efx->net_dev, 121 "unable to read datapath firmware capabilities\n"); 122 return -EIO; 123 } 124 125 nic_data->datapath_caps = 126 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 127 128 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) { 129 nic_data->datapath_caps2 = MCDI_DWORD(outbuf, 130 GET_CAPABILITIES_V2_OUT_FLAGS2); 131 nic_data->piobuf_size = MCDI_WORD(outbuf, 132 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF); 133 } else { 134 nic_data->datapath_caps2 = 0; 135 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE; 136 } 137 138 /* record the DPCPU firmware IDs to determine VEB vswitching support. 139 */ 140 nic_data->rx_dpcpu_fw_id = 141 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); 142 nic_data->tx_dpcpu_fw_id = 143 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); 144 145 if (!(nic_data->datapath_caps & 146 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 147 netif_err(efx, probe, efx->net_dev, 148 "current firmware does not support an RX prefix\n"); 149 return -ENODEV; 150 } 151 152 if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) { 153 u8 vi_window_mode = MCDI_BYTE(outbuf, 154 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); 155 156 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode); 157 if (rc) 158 return rc; 159 } else { 160 /* keep default VI stride */ 161 netif_dbg(efx, probe, efx->net_dev, 162 "firmware did not report VI window mode, assuming vi_stride = %u\n", 163 efx->vi_stride); 164 } 165 166 if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) { 167 efx->num_mac_stats = MCDI_WORD(outbuf, 168 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS); 169 netif_dbg(efx, probe, efx->net_dev, 170 "firmware reports num_mac_stats = %u\n", 171 efx->num_mac_stats); 172 } else { 173 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */ 174 netif_dbg(efx, probe, efx->net_dev, 175 "firmware did not report num_mac_stats, assuming %u\n", 176 efx->num_mac_stats); 177 } 178 179 return 0; 180 } 181 182 static void efx_ef10_read_licensed_features(struct efx_nic *efx) 183 { 184 MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN); 185 MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN); 186 struct efx_ef10_nic_data *nic_data = efx->nic_data; 187 size_t outlen; 188 int rc; 189 190 MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP, 191 MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE); 192 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf, sizeof(inbuf), 193 outbuf, sizeof(outbuf), &outlen); 194 if (rc || (outlen < MC_CMD_LICENSING_V3_OUT_LEN)) 195 return; 196 197 nic_data->licensed_features = MCDI_QWORD(outbuf, 198 LICENSING_V3_OUT_LICENSED_FEATURES); 199 } 200 201 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 202 { 203 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 204 int rc; 205 206 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 207 outbuf, sizeof(outbuf), NULL); 208 if (rc) 209 return rc; 210 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 211 return rc > 0 ? rc : -ERANGE; 212 } 213 214 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx) 215 { 216 struct efx_ef10_nic_data *nic_data = efx->nic_data; 217 unsigned int implemented; 218 unsigned int enabled; 219 int rc; 220 221 nic_data->workaround_35388 = false; 222 nic_data->workaround_61265 = false; 223 224 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 225 226 if (rc == -ENOSYS) { 227 /* Firmware without GET_WORKAROUNDS - not a problem. */ 228 rc = 0; 229 } else if (rc == 0) { 230 /* Bug61265 workaround is always enabled if implemented. */ 231 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265) 232 nic_data->workaround_61265 = true; 233 234 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 235 nic_data->workaround_35388 = true; 236 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 237 /* Workaround is implemented but not enabled. 238 * Try to enable it. 239 */ 240 rc = efx_mcdi_set_workaround(efx, 241 MC_CMD_WORKAROUND_BUG35388, 242 true, NULL); 243 if (rc == 0) 244 nic_data->workaround_35388 = true; 245 /* If we failed to set the workaround just carry on. */ 246 rc = 0; 247 } 248 } 249 250 netif_dbg(efx, probe, efx->net_dev, 251 "workaround for bug 35388 is %sabled\n", 252 nic_data->workaround_35388 ? "en" : "dis"); 253 netif_dbg(efx, probe, efx->net_dev, 254 "workaround for bug 61265 is %sabled\n", 255 nic_data->workaround_61265 ? "en" : "dis"); 256 257 return rc; 258 } 259 260 static void efx_ef10_process_timer_config(struct efx_nic *efx, 261 const efx_dword_t *data) 262 { 263 unsigned int max_count; 264 265 if (EFX_EF10_WORKAROUND_61265(efx)) { 266 efx->timer_quantum_ns = MCDI_DWORD(data, 267 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS); 268 efx->timer_max_ns = MCDI_DWORD(data, 269 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS); 270 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 271 efx->timer_quantum_ns = MCDI_DWORD(data, 272 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT); 273 max_count = MCDI_DWORD(data, 274 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT); 275 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 276 } else { 277 efx->timer_quantum_ns = MCDI_DWORD(data, 278 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT); 279 max_count = MCDI_DWORD(data, 280 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT); 281 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 282 } 283 284 netif_dbg(efx, probe, efx->net_dev, 285 "got timer properties from MC: quantum %u ns; max %u ns\n", 286 efx->timer_quantum_ns, efx->timer_max_ns); 287 } 288 289 static int efx_ef10_get_timer_config(struct efx_nic *efx) 290 { 291 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN); 292 int rc; 293 294 rc = efx_ef10_get_timer_workarounds(efx); 295 if (rc) 296 return rc; 297 298 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0, 299 outbuf, sizeof(outbuf), NULL); 300 301 if (rc == 0) { 302 efx_ef10_process_timer_config(efx, outbuf); 303 } else if (rc == -ENOSYS || rc == -EPERM) { 304 /* Not available - fall back to Huntington defaults. */ 305 unsigned int quantum; 306 307 rc = efx_ef10_get_sysclk_freq(efx); 308 if (rc < 0) 309 return rc; 310 311 quantum = 1536000 / rc; /* 1536 cycles */ 312 efx->timer_quantum_ns = quantum; 313 efx->timer_max_ns = efx->type->timer_period_max * quantum; 314 rc = 0; 315 } else { 316 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, 317 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN, 318 NULL, 0, rc); 319 } 320 321 return rc; 322 } 323 324 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address) 325 { 326 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 327 size_t outlen; 328 int rc; 329 330 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 331 332 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 333 outbuf, sizeof(outbuf), &outlen); 334 if (rc) 335 return rc; 336 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 337 return -EIO; 338 339 ether_addr_copy(mac_address, 340 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 341 return 0; 342 } 343 344 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address) 345 { 346 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN); 347 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 348 size_t outlen; 349 int num_addrs, rc; 350 351 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 352 EVB_PORT_ID_ASSIGNED); 353 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf, 354 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 355 356 if (rc) 357 return rc; 358 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) 359 return -EIO; 360 361 num_addrs = MCDI_DWORD(outbuf, 362 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT); 363 364 WARN_ON(num_addrs != 1); 365 366 ether_addr_copy(mac_address, 367 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR)); 368 369 return 0; 370 } 371 372 static ssize_t efx_ef10_show_link_control_flag(struct device *dev, 373 struct device_attribute *attr, 374 char *buf) 375 { 376 struct efx_nic *efx = dev_get_drvdata(dev); 377 378 return sprintf(buf, "%d\n", 379 ((efx->mcdi->fn_flags) & 380 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 381 ? 1 : 0); 382 } 383 384 static ssize_t efx_ef10_show_primary_flag(struct device *dev, 385 struct device_attribute *attr, 386 char *buf) 387 { 388 struct efx_nic *efx = dev_get_drvdata(dev); 389 390 return sprintf(buf, "%d\n", 391 ((efx->mcdi->fn_flags) & 392 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)) 393 ? 1 : 0); 394 } 395 396 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid) 397 { 398 struct efx_ef10_nic_data *nic_data = efx->nic_data; 399 struct efx_ef10_vlan *vlan; 400 401 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 402 403 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 404 if (vlan->vid == vid) 405 return vlan; 406 } 407 408 return NULL; 409 } 410 411 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid) 412 { 413 struct efx_ef10_nic_data *nic_data = efx->nic_data; 414 struct efx_ef10_vlan *vlan; 415 int rc; 416 417 mutex_lock(&nic_data->vlan_lock); 418 419 vlan = efx_ef10_find_vlan(efx, vid); 420 if (vlan) { 421 /* We add VID 0 on init. 8021q adds it on module init 422 * for all interfaces with VLAN filtring feature. 423 */ 424 if (vid == 0) 425 goto done_unlock; 426 netif_warn(efx, drv, efx->net_dev, 427 "VLAN %u already added\n", vid); 428 rc = -EALREADY; 429 goto fail_exist; 430 } 431 432 rc = -ENOMEM; 433 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 434 if (!vlan) 435 goto fail_alloc; 436 437 vlan->vid = vid; 438 439 list_add_tail(&vlan->list, &nic_data->vlan_list); 440 441 if (efx->filter_state) { 442 mutex_lock(&efx->mac_lock); 443 down_write(&efx->filter_sem); 444 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 445 up_write(&efx->filter_sem); 446 mutex_unlock(&efx->mac_lock); 447 if (rc) 448 goto fail_filter_add_vlan; 449 } 450 451 done_unlock: 452 mutex_unlock(&nic_data->vlan_lock); 453 return 0; 454 455 fail_filter_add_vlan: 456 list_del(&vlan->list); 457 kfree(vlan); 458 fail_alloc: 459 fail_exist: 460 mutex_unlock(&nic_data->vlan_lock); 461 return rc; 462 } 463 464 static void efx_ef10_del_vlan_internal(struct efx_nic *efx, 465 struct efx_ef10_vlan *vlan) 466 { 467 struct efx_ef10_nic_data *nic_data = efx->nic_data; 468 469 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 470 471 if (efx->filter_state) { 472 down_write(&efx->filter_sem); 473 efx_mcdi_filter_del_vlan(efx, vlan->vid); 474 up_write(&efx->filter_sem); 475 } 476 477 list_del(&vlan->list); 478 kfree(vlan); 479 } 480 481 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid) 482 { 483 struct efx_ef10_nic_data *nic_data = efx->nic_data; 484 struct efx_ef10_vlan *vlan; 485 int rc = 0; 486 487 /* 8021q removes VID 0 on module unload for all interfaces 488 * with VLAN filtering feature. We need to keep it to receive 489 * untagged traffic. 490 */ 491 if (vid == 0) 492 return 0; 493 494 mutex_lock(&nic_data->vlan_lock); 495 496 vlan = efx_ef10_find_vlan(efx, vid); 497 if (!vlan) { 498 netif_err(efx, drv, efx->net_dev, 499 "VLAN %u to be deleted not found\n", vid); 500 rc = -ENOENT; 501 } else { 502 efx_ef10_del_vlan_internal(efx, vlan); 503 } 504 505 mutex_unlock(&nic_data->vlan_lock); 506 507 return rc; 508 } 509 510 static void efx_ef10_cleanup_vlans(struct efx_nic *efx) 511 { 512 struct efx_ef10_nic_data *nic_data = efx->nic_data; 513 struct efx_ef10_vlan *vlan, *next_vlan; 514 515 mutex_lock(&nic_data->vlan_lock); 516 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list) 517 efx_ef10_del_vlan_internal(efx, vlan); 518 mutex_unlock(&nic_data->vlan_lock); 519 } 520 521 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag, 522 NULL); 523 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL); 524 525 static int efx_ef10_probe(struct efx_nic *efx) 526 { 527 struct efx_ef10_nic_data *nic_data; 528 int i, rc; 529 530 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 531 if (!nic_data) 532 return -ENOMEM; 533 efx->nic_data = nic_data; 534 535 /* we assume later that we can copy from this buffer in dwords */ 536 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 537 538 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 539 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 540 if (rc) 541 goto fail1; 542 543 /* Get the MC's warm boot count. In case it's rebooting right 544 * now, be prepared to retry. 545 */ 546 i = 0; 547 for (;;) { 548 rc = efx_ef10_get_warm_boot_count(efx); 549 if (rc >= 0) 550 break; 551 if (++i == 5) 552 goto fail2; 553 ssleep(1); 554 } 555 nic_data->warm_boot_count = rc; 556 557 /* In case we're recovering from a crash (kexec), we want to 558 * cancel any outstanding request by the previous user of this 559 * function. We send a special message using the least 560 * significant bits of the 'high' (doorbell) register. 561 */ 562 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 563 564 rc = efx_mcdi_init(efx); 565 if (rc) 566 goto fail2; 567 568 mutex_init(&nic_data->udp_tunnels_lock); 569 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) 570 nic_data->udp_tunnels[i].type = 571 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID; 572 573 /* Reset (most) configuration for this function */ 574 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 575 if (rc) 576 goto fail3; 577 578 /* Enable event logging */ 579 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 580 if (rc) 581 goto fail3; 582 583 rc = device_create_file(&efx->pci_dev->dev, 584 &dev_attr_link_control_flag); 585 if (rc) 586 goto fail3; 587 588 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 589 if (rc) 590 goto fail4; 591 592 rc = efx_get_pf_index(efx, &nic_data->pf_index); 593 if (rc) 594 goto fail5; 595 596 rc = efx_ef10_init_datapath_caps(efx); 597 if (rc < 0) 598 goto fail5; 599 600 efx_ef10_read_licensed_features(efx); 601 602 /* We can have one VI for each vi_stride-byte region. 603 * However, until we use TX option descriptors we need two TX queues 604 * per channel. 605 */ 606 efx->tx_queues_per_channel = 2; 607 efx->max_vis = efx_ef10_mem_map_size(efx) / efx->vi_stride; 608 if (!efx->max_vis) { 609 netif_err(efx, drv, efx->net_dev, "error determining max VIs\n"); 610 rc = -EIO; 611 goto fail5; 612 } 613 efx->max_channels = min_t(unsigned int, EFX_MAX_CHANNELS, 614 efx->max_vis / efx->tx_queues_per_channel); 615 efx->max_tx_channels = efx->max_channels; 616 if (WARN_ON(efx->max_channels == 0)) { 617 rc = -EIO; 618 goto fail5; 619 } 620 621 efx->rx_packet_len_offset = 622 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 623 624 if (nic_data->datapath_caps & 625 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN)) 626 efx->net_dev->hw_features |= NETIF_F_RXFCS; 627 628 rc = efx_mcdi_port_get_number(efx); 629 if (rc < 0) 630 goto fail5; 631 efx->port_num = rc; 632 633 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr); 634 if (rc) 635 goto fail5; 636 637 rc = efx_ef10_get_timer_config(efx); 638 if (rc < 0) 639 goto fail5; 640 641 rc = efx_mcdi_mon_probe(efx); 642 if (rc && rc != -EPERM) 643 goto fail5; 644 645 efx_ptp_defer_probe_with_channel(efx); 646 647 #ifdef CONFIG_SFC_SRIOV 648 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) { 649 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 650 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 651 652 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id); 653 } else 654 #endif 655 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr); 656 657 INIT_LIST_HEAD(&nic_data->vlan_list); 658 mutex_init(&nic_data->vlan_lock); 659 660 /* Add unspecified VID to support VLAN filtering being disabled */ 661 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC); 662 if (rc) 663 goto fail_add_vid_unspec; 664 665 /* If VLAN filtering is enabled, we need VID 0 to get untagged 666 * traffic. It is added automatically if 8021q module is loaded, 667 * but we can't rely on it since module may be not loaded. 668 */ 669 rc = efx_ef10_add_vlan(efx, 0); 670 if (rc) 671 goto fail_add_vid_0; 672 673 if (nic_data->datapath_caps & 674 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) && 675 efx->mcdi->fn_flags & 676 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)) 677 efx->net_dev->udp_tunnel_nic_info = &efx_ef10_udp_tunnels; 678 679 return 0; 680 681 fail_add_vid_0: 682 efx_ef10_cleanup_vlans(efx); 683 fail_add_vid_unspec: 684 mutex_destroy(&nic_data->vlan_lock); 685 efx_ptp_remove(efx); 686 efx_mcdi_mon_remove(efx); 687 fail5: 688 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 689 fail4: 690 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 691 fail3: 692 efx_mcdi_detach(efx); 693 694 mutex_lock(&nic_data->udp_tunnels_lock); 695 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 696 (void)efx_ef10_set_udp_tnl_ports(efx, true); 697 mutex_unlock(&nic_data->udp_tunnels_lock); 698 mutex_destroy(&nic_data->udp_tunnels_lock); 699 700 efx_mcdi_fini(efx); 701 fail2: 702 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 703 fail1: 704 kfree(nic_data); 705 efx->nic_data = NULL; 706 return rc; 707 } 708 709 #ifdef EFX_USE_PIO 710 711 static void efx_ef10_free_piobufs(struct efx_nic *efx) 712 { 713 struct efx_ef10_nic_data *nic_data = efx->nic_data; 714 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 715 unsigned int i; 716 int rc; 717 718 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 719 720 for (i = 0; i < nic_data->n_piobufs; i++) { 721 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 722 nic_data->piobuf_handle[i]); 723 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 724 NULL, 0, NULL); 725 WARN_ON(rc); 726 } 727 728 nic_data->n_piobufs = 0; 729 } 730 731 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 732 { 733 struct efx_ef10_nic_data *nic_data = efx->nic_data; 734 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 735 unsigned int i; 736 size_t outlen; 737 int rc = 0; 738 739 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 740 741 for (i = 0; i < n; i++) { 742 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 743 outbuf, sizeof(outbuf), &outlen); 744 if (rc) { 745 /* Don't display the MC error if we didn't have space 746 * for a VF. 747 */ 748 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC)) 749 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF, 750 0, outbuf, outlen, rc); 751 break; 752 } 753 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 754 rc = -EIO; 755 break; 756 } 757 nic_data->piobuf_handle[i] = 758 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 759 netif_dbg(efx, probe, efx->net_dev, 760 "allocated PIO buffer %u handle %x\n", i, 761 nic_data->piobuf_handle[i]); 762 } 763 764 nic_data->n_piobufs = i; 765 if (rc) 766 efx_ef10_free_piobufs(efx); 767 return rc; 768 } 769 770 static int efx_ef10_link_piobufs(struct efx_nic *efx) 771 { 772 struct efx_ef10_nic_data *nic_data = efx->nic_data; 773 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN); 774 struct efx_channel *channel; 775 struct efx_tx_queue *tx_queue; 776 unsigned int offset, index; 777 int rc; 778 779 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 780 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 781 782 /* Link a buffer to each VI in the write-combining mapping */ 783 for (index = 0; index < nic_data->n_piobufs; ++index) { 784 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 785 nic_data->piobuf_handle[index]); 786 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 787 nic_data->pio_write_vi_base + index); 788 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 789 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 790 NULL, 0, NULL); 791 if (rc) { 792 netif_err(efx, drv, efx->net_dev, 793 "failed to link VI %u to PIO buffer %u (%d)\n", 794 nic_data->pio_write_vi_base + index, index, 795 rc); 796 goto fail; 797 } 798 netif_dbg(efx, probe, efx->net_dev, 799 "linked VI %u to PIO buffer %u\n", 800 nic_data->pio_write_vi_base + index, index); 801 } 802 803 /* Link a buffer to each TX queue */ 804 efx_for_each_channel(channel, efx) { 805 /* Extra channels, even those with TXQs (PTP), do not require 806 * PIO resources. 807 */ 808 if (!channel->type->want_pio || 809 channel->channel >= efx->xdp_channel_offset) 810 continue; 811 812 efx_for_each_channel_tx_queue(tx_queue, channel) { 813 /* We assign the PIO buffers to queues in 814 * reverse order to allow for the following 815 * special case. 816 */ 817 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 818 tx_queue->channel->channel - 1) * 819 efx_piobuf_size); 820 index = offset / nic_data->piobuf_size; 821 offset = offset % nic_data->piobuf_size; 822 823 /* When the host page size is 4K, the first 824 * host page in the WC mapping may be within 825 * the same VI page as the last TX queue. We 826 * can only link one buffer to each VI. 827 */ 828 if (tx_queue->queue == nic_data->pio_write_vi_base) { 829 BUG_ON(index != 0); 830 rc = 0; 831 } else { 832 MCDI_SET_DWORD(inbuf, 833 LINK_PIOBUF_IN_PIOBUF_HANDLE, 834 nic_data->piobuf_handle[index]); 835 MCDI_SET_DWORD(inbuf, 836 LINK_PIOBUF_IN_TXQ_INSTANCE, 837 tx_queue->queue); 838 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 839 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 840 NULL, 0, NULL); 841 } 842 843 if (rc) { 844 /* This is non-fatal; the TX path just 845 * won't use PIO for this queue 846 */ 847 netif_err(efx, drv, efx->net_dev, 848 "failed to link VI %u to PIO buffer %u (%d)\n", 849 tx_queue->queue, index, rc); 850 tx_queue->piobuf = NULL; 851 } else { 852 tx_queue->piobuf = 853 nic_data->pio_write_base + 854 index * efx->vi_stride + offset; 855 tx_queue->piobuf_offset = offset; 856 netif_dbg(efx, probe, efx->net_dev, 857 "linked VI %u to PIO buffer %u offset %x addr %p\n", 858 tx_queue->queue, index, 859 tx_queue->piobuf_offset, 860 tx_queue->piobuf); 861 } 862 } 863 } 864 865 return 0; 866 867 fail: 868 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same 869 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter. 870 */ 871 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN); 872 while (index--) { 873 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 874 nic_data->pio_write_vi_base + index); 875 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 876 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 877 NULL, 0, NULL); 878 } 879 return rc; 880 } 881 882 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 883 { 884 struct efx_channel *channel; 885 struct efx_tx_queue *tx_queue; 886 887 /* All our existing PIO buffers went away */ 888 efx_for_each_channel(channel, efx) 889 efx_for_each_channel_tx_queue(tx_queue, channel) 890 tx_queue->piobuf = NULL; 891 } 892 893 #else /* !EFX_USE_PIO */ 894 895 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 896 { 897 return n == 0 ? 0 : -ENOBUFS; 898 } 899 900 static int efx_ef10_link_piobufs(struct efx_nic *efx) 901 { 902 return 0; 903 } 904 905 static void efx_ef10_free_piobufs(struct efx_nic *efx) 906 { 907 } 908 909 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 910 { 911 } 912 913 #endif /* EFX_USE_PIO */ 914 915 static void efx_ef10_remove(struct efx_nic *efx) 916 { 917 struct efx_ef10_nic_data *nic_data = efx->nic_data; 918 int rc; 919 920 #ifdef CONFIG_SFC_SRIOV 921 struct efx_ef10_nic_data *nic_data_pf; 922 struct pci_dev *pci_dev_pf; 923 struct efx_nic *efx_pf; 924 struct ef10_vf *vf; 925 926 if (efx->pci_dev->is_virtfn) { 927 pci_dev_pf = efx->pci_dev->physfn; 928 if (pci_dev_pf) { 929 efx_pf = pci_get_drvdata(pci_dev_pf); 930 nic_data_pf = efx_pf->nic_data; 931 vf = nic_data_pf->vf + nic_data->vf_index; 932 vf->efx = NULL; 933 } else 934 netif_info(efx, drv, efx->net_dev, 935 "Could not get the PF id from VF\n"); 936 } 937 #endif 938 939 efx_ef10_cleanup_vlans(efx); 940 mutex_destroy(&nic_data->vlan_lock); 941 942 efx_ptp_remove(efx); 943 944 efx_mcdi_mon_remove(efx); 945 946 efx_mcdi_rx_free_indir_table(efx); 947 948 if (nic_data->wc_membase) 949 iounmap(nic_data->wc_membase); 950 951 rc = efx_mcdi_free_vis(efx); 952 WARN_ON(rc != 0); 953 954 if (!nic_data->must_restore_piobufs) 955 efx_ef10_free_piobufs(efx); 956 957 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 958 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 959 960 efx_mcdi_detach(efx); 961 962 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 963 mutex_lock(&nic_data->udp_tunnels_lock); 964 (void)efx_ef10_set_udp_tnl_ports(efx, true); 965 mutex_unlock(&nic_data->udp_tunnels_lock); 966 967 mutex_destroy(&nic_data->udp_tunnels_lock); 968 969 efx_mcdi_fini(efx); 970 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 971 kfree(nic_data); 972 } 973 974 static int efx_ef10_probe_pf(struct efx_nic *efx) 975 { 976 return efx_ef10_probe(efx); 977 } 978 979 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id, 980 u32 *port_flags, u32 *vadaptor_flags, 981 unsigned int *vlan_tags) 982 { 983 struct efx_ef10_nic_data *nic_data = efx->nic_data; 984 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN); 985 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN); 986 size_t outlen; 987 int rc; 988 989 if (nic_data->datapath_caps & 990 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) { 991 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID, 992 port_id); 993 994 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf), 995 outbuf, sizeof(outbuf), &outlen); 996 if (rc) 997 return rc; 998 999 if (outlen < sizeof(outbuf)) { 1000 rc = -EIO; 1001 return rc; 1002 } 1003 } 1004 1005 if (port_flags) 1006 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS); 1007 if (vadaptor_flags) 1008 *vadaptor_flags = 1009 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS); 1010 if (vlan_tags) 1011 *vlan_tags = 1012 MCDI_DWORD(outbuf, 1013 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS); 1014 1015 return 0; 1016 } 1017 1018 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id) 1019 { 1020 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN); 1021 1022 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 1023 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf), 1024 NULL, 0, NULL); 1025 } 1026 1027 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id) 1028 { 1029 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN); 1030 1031 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 1032 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf), 1033 NULL, 0, NULL); 1034 } 1035 1036 int efx_ef10_vport_add_mac(struct efx_nic *efx, 1037 unsigned int port_id, u8 *mac) 1038 { 1039 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN); 1040 1041 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id); 1042 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac); 1043 1044 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf, 1045 sizeof(inbuf), NULL, 0, NULL); 1046 } 1047 1048 int efx_ef10_vport_del_mac(struct efx_nic *efx, 1049 unsigned int port_id, u8 *mac) 1050 { 1051 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN); 1052 1053 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id); 1054 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac); 1055 1056 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf, 1057 sizeof(inbuf), NULL, 0, NULL); 1058 } 1059 1060 #ifdef CONFIG_SFC_SRIOV 1061 static int efx_ef10_probe_vf(struct efx_nic *efx) 1062 { 1063 int rc; 1064 struct pci_dev *pci_dev_pf; 1065 1066 /* If the parent PF has no VF data structure, it doesn't know about this 1067 * VF so fail probe. The VF needs to be re-created. This can happen 1068 * if the PF driver is unloaded while the VF is assigned to a guest. 1069 */ 1070 pci_dev_pf = efx->pci_dev->physfn; 1071 if (pci_dev_pf) { 1072 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 1073 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data; 1074 1075 if (!nic_data_pf->vf) { 1076 netif_info(efx, drv, efx->net_dev, 1077 "The VF cannot link to its parent PF; " 1078 "please destroy and re-create the VF\n"); 1079 return -EBUSY; 1080 } 1081 } 1082 1083 rc = efx_ef10_probe(efx); 1084 if (rc) 1085 return rc; 1086 1087 rc = efx_ef10_get_vf_index(efx); 1088 if (rc) 1089 goto fail; 1090 1091 if (efx->pci_dev->is_virtfn) { 1092 if (efx->pci_dev->physfn) { 1093 struct efx_nic *efx_pf = 1094 pci_get_drvdata(efx->pci_dev->physfn); 1095 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data; 1096 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1097 1098 nic_data_p->vf[nic_data->vf_index].efx = efx; 1099 nic_data_p->vf[nic_data->vf_index].pci_dev = 1100 efx->pci_dev; 1101 } else 1102 netif_info(efx, drv, efx->net_dev, 1103 "Could not get the PF id from VF\n"); 1104 } 1105 1106 return 0; 1107 1108 fail: 1109 efx_ef10_remove(efx); 1110 return rc; 1111 } 1112 #else 1113 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused))) 1114 { 1115 return 0; 1116 } 1117 #endif 1118 1119 static int efx_ef10_alloc_vis(struct efx_nic *efx, 1120 unsigned int min_vis, unsigned int max_vis) 1121 { 1122 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1123 1124 return efx_mcdi_alloc_vis(efx, min_vis, max_vis, &nic_data->vi_base, 1125 &nic_data->n_allocated_vis); 1126 } 1127 1128 /* Note that the failure path of this function does not free 1129 * resources, as this will be done by efx_ef10_remove(). 1130 */ 1131 static int efx_ef10_dimension_resources(struct efx_nic *efx) 1132 { 1133 unsigned int min_vis = max_t(unsigned int, efx->tx_queues_per_channel, 1134 efx_separate_tx_channels ? 2 : 1); 1135 unsigned int channel_vis, pio_write_vi_base, max_vis; 1136 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1137 unsigned int uc_mem_map_size, wc_mem_map_size; 1138 void __iomem *membase; 1139 int rc; 1140 1141 channel_vis = max(efx->n_channels, 1142 ((efx->n_tx_channels + efx->n_extra_tx_channels) * 1143 efx->tx_queues_per_channel) + 1144 efx->n_xdp_channels * efx->xdp_tx_per_channel); 1145 if (efx->max_vis && efx->max_vis < channel_vis) { 1146 netif_dbg(efx, drv, efx->net_dev, 1147 "Reducing channel VIs from %u to %u\n", 1148 channel_vis, efx->max_vis); 1149 channel_vis = efx->max_vis; 1150 } 1151 1152 #ifdef EFX_USE_PIO 1153 /* Try to allocate PIO buffers if wanted and if the full 1154 * number of PIO buffers would be sufficient to allocate one 1155 * copy-buffer per TX channel. Failure is non-fatal, as there 1156 * are only a small number of PIO buffers shared between all 1157 * functions of the controller. 1158 */ 1159 if (efx_piobuf_size != 0 && 1160 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 1161 efx->n_tx_channels) { 1162 unsigned int n_piobufs = 1163 DIV_ROUND_UP(efx->n_tx_channels, 1164 nic_data->piobuf_size / efx_piobuf_size); 1165 1166 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 1167 if (rc == -ENOSPC) 1168 netif_dbg(efx, probe, efx->net_dev, 1169 "out of PIO buffers; cannot allocate more\n"); 1170 else if (rc == -EPERM) 1171 netif_dbg(efx, probe, efx->net_dev, 1172 "not permitted to allocate PIO buffers\n"); 1173 else if (rc) 1174 netif_err(efx, probe, efx->net_dev, 1175 "failed to allocate PIO buffers (%d)\n", rc); 1176 else 1177 netif_dbg(efx, probe, efx->net_dev, 1178 "allocated %u PIO buffers\n", n_piobufs); 1179 } 1180 #else 1181 nic_data->n_piobufs = 0; 1182 #endif 1183 1184 /* PIO buffers should be mapped with write-combining enabled, 1185 * and we want to make single UC and WC mappings rather than 1186 * several of each (in fact that's the only option if host 1187 * page size is >4K). So we may allocate some extra VIs just 1188 * for writing PIO buffers through. 1189 * 1190 * The UC mapping contains (channel_vis - 1) complete VIs and the 1191 * first 4K of the next VI. Then the WC mapping begins with 1192 * the remainder of this last VI. 1193 */ 1194 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride + 1195 ER_DZ_TX_PIOBUF); 1196 if (nic_data->n_piobufs) { 1197 /* pio_write_vi_base rounds down to give the number of complete 1198 * VIs inside the UC mapping. 1199 */ 1200 pio_write_vi_base = uc_mem_map_size / efx->vi_stride; 1201 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 1202 nic_data->n_piobufs) * 1203 efx->vi_stride) - 1204 uc_mem_map_size); 1205 max_vis = pio_write_vi_base + nic_data->n_piobufs; 1206 } else { 1207 pio_write_vi_base = 0; 1208 wc_mem_map_size = 0; 1209 max_vis = channel_vis; 1210 } 1211 1212 /* In case the last attached driver failed to free VIs, do it now */ 1213 rc = efx_mcdi_free_vis(efx); 1214 if (rc != 0) 1215 return rc; 1216 1217 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 1218 if (rc != 0) 1219 return rc; 1220 1221 if (nic_data->n_allocated_vis < channel_vis) { 1222 netif_info(efx, drv, efx->net_dev, 1223 "Could not allocate enough VIs to satisfy RSS" 1224 " requirements. Performance may not be optimal.\n"); 1225 /* We didn't get the VIs to populate our channels. 1226 * We could keep what we got but then we'd have more 1227 * interrupts than we need. 1228 * Instead calculate new max_channels and restart 1229 */ 1230 efx->max_channels = nic_data->n_allocated_vis; 1231 efx->max_tx_channels = 1232 nic_data->n_allocated_vis / efx->tx_queues_per_channel; 1233 1234 efx_mcdi_free_vis(efx); 1235 return -EAGAIN; 1236 } 1237 1238 /* If we didn't get enough VIs to map all the PIO buffers, free the 1239 * PIO buffers 1240 */ 1241 if (nic_data->n_piobufs && 1242 nic_data->n_allocated_vis < 1243 pio_write_vi_base + nic_data->n_piobufs) { 1244 netif_dbg(efx, probe, efx->net_dev, 1245 "%u VIs are not sufficient to map %u PIO buffers\n", 1246 nic_data->n_allocated_vis, nic_data->n_piobufs); 1247 efx_ef10_free_piobufs(efx); 1248 } 1249 1250 /* Shrink the original UC mapping of the memory BAR */ 1251 membase = ioremap(efx->membase_phys, uc_mem_map_size); 1252 if (!membase) { 1253 netif_err(efx, probe, efx->net_dev, 1254 "could not shrink memory BAR to %x\n", 1255 uc_mem_map_size); 1256 return -ENOMEM; 1257 } 1258 iounmap(efx->membase); 1259 efx->membase = membase; 1260 1261 /* Set up the WC mapping if needed */ 1262 if (wc_mem_map_size) { 1263 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 1264 uc_mem_map_size, 1265 wc_mem_map_size); 1266 if (!nic_data->wc_membase) { 1267 netif_err(efx, probe, efx->net_dev, 1268 "could not allocate WC mapping of size %x\n", 1269 wc_mem_map_size); 1270 return -ENOMEM; 1271 } 1272 nic_data->pio_write_vi_base = pio_write_vi_base; 1273 nic_data->pio_write_base = 1274 nic_data->wc_membase + 1275 (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF - 1276 uc_mem_map_size); 1277 1278 rc = efx_ef10_link_piobufs(efx); 1279 if (rc) 1280 efx_ef10_free_piobufs(efx); 1281 } 1282 1283 netif_dbg(efx, probe, efx->net_dev, 1284 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 1285 &efx->membase_phys, efx->membase, uc_mem_map_size, 1286 nic_data->wc_membase, wc_mem_map_size); 1287 1288 return 0; 1289 } 1290 1291 static void efx_ef10_fini_nic(struct efx_nic *efx) 1292 { 1293 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1294 1295 kfree(nic_data->mc_stats); 1296 nic_data->mc_stats = NULL; 1297 } 1298 1299 static int efx_ef10_init_nic(struct efx_nic *efx) 1300 { 1301 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1302 int rc; 1303 1304 if (nic_data->must_check_datapath_caps) { 1305 rc = efx_ef10_init_datapath_caps(efx); 1306 if (rc) 1307 return rc; 1308 nic_data->must_check_datapath_caps = false; 1309 } 1310 1311 if (efx->must_realloc_vis) { 1312 /* We cannot let the number of VIs change now */ 1313 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 1314 nic_data->n_allocated_vis); 1315 if (rc) 1316 return rc; 1317 efx->must_realloc_vis = false; 1318 } 1319 1320 nic_data->mc_stats = kmalloc(efx->num_mac_stats * sizeof(__le64), 1321 GFP_KERNEL); 1322 if (!nic_data->mc_stats) 1323 return -ENOMEM; 1324 1325 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 1326 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 1327 if (rc == 0) { 1328 rc = efx_ef10_link_piobufs(efx); 1329 if (rc) 1330 efx_ef10_free_piobufs(efx); 1331 } 1332 1333 /* Log an error on failure, but this is non-fatal. 1334 * Permission errors are less important - we've presumably 1335 * had the PIO buffer licence removed. 1336 */ 1337 if (rc == -EPERM) 1338 netif_dbg(efx, drv, efx->net_dev, 1339 "not permitted to restore PIO buffers\n"); 1340 else if (rc) 1341 netif_err(efx, drv, efx->net_dev, 1342 "failed to restore PIO buffers (%d)\n", rc); 1343 nic_data->must_restore_piobufs = false; 1344 } 1345 1346 /* don't fail init if RSS setup doesn't work */ 1347 rc = efx->type->rx_push_rss_config(efx, false, 1348 efx->rss_context.rx_indir_table, NULL); 1349 1350 return 0; 1351 } 1352 1353 static void efx_ef10_table_reset_mc_allocations(struct efx_nic *efx) 1354 { 1355 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1356 #ifdef CONFIG_SFC_SRIOV 1357 unsigned int i; 1358 #endif 1359 1360 /* All our allocations have been reset */ 1361 efx->must_realloc_vis = true; 1362 efx_mcdi_filter_table_reset_mc_allocations(efx); 1363 nic_data->must_restore_piobufs = true; 1364 efx_ef10_forget_old_piobufs(efx); 1365 efx->rss_context.context_id = EFX_MCDI_RSS_CONTEXT_INVALID; 1366 1367 /* Driver-created vswitches and vports must be re-created */ 1368 nic_data->must_probe_vswitching = true; 1369 efx->vport_id = EVB_PORT_ID_ASSIGNED; 1370 #ifdef CONFIG_SFC_SRIOV 1371 if (nic_data->vf) 1372 for (i = 0; i < efx->vf_count; i++) 1373 nic_data->vf[i].vport_id = 0; 1374 #endif 1375 } 1376 1377 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason) 1378 { 1379 if (reason == RESET_TYPE_MC_FAILURE) 1380 return RESET_TYPE_DATAPATH; 1381 1382 return efx_mcdi_map_reset_reason(reason); 1383 } 1384 1385 static int efx_ef10_map_reset_flags(u32 *flags) 1386 { 1387 enum { 1388 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 1389 ETH_RESET_SHARED_SHIFT), 1390 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 1391 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 1392 ETH_RESET_PHY | ETH_RESET_MGMT) << 1393 ETH_RESET_SHARED_SHIFT) 1394 }; 1395 1396 /* We assume for now that our PCI function is permitted to 1397 * reset everything. 1398 */ 1399 1400 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 1401 *flags &= ~EF10_RESET_MC; 1402 return RESET_TYPE_WORLD; 1403 } 1404 1405 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 1406 *flags &= ~EF10_RESET_PORT; 1407 return RESET_TYPE_ALL; 1408 } 1409 1410 /* no invisible reset implemented */ 1411 1412 return -EINVAL; 1413 } 1414 1415 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 1416 { 1417 int rc = efx_mcdi_reset(efx, reset_type); 1418 1419 /* Unprivileged functions return -EPERM, but need to return success 1420 * here so that the datapath is brought back up. 1421 */ 1422 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM) 1423 rc = 0; 1424 1425 /* If it was a port reset, trigger reallocation of MC resources. 1426 * Note that on an MC reset nothing needs to be done now because we'll 1427 * detect the MC reset later and handle it then. 1428 * For an FLR, we never get an MC reset event, but the MC has reset all 1429 * resources assigned to us, so we have to trigger reallocation now. 1430 */ 1431 if ((reset_type == RESET_TYPE_ALL || 1432 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) 1433 efx_ef10_table_reset_mc_allocations(efx); 1434 return rc; 1435 } 1436 1437 #define EF10_DMA_STAT(ext_name, mcdi_name) \ 1438 [EF10_STAT_ ## ext_name] = \ 1439 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1440 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 1441 [EF10_STAT_ ## int_name] = \ 1442 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1443 #define EF10_OTHER_STAT(ext_name) \ 1444 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1445 1446 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 1447 EF10_DMA_STAT(port_tx_bytes, TX_BYTES), 1448 EF10_DMA_STAT(port_tx_packets, TX_PKTS), 1449 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 1450 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS), 1451 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 1452 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 1453 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 1454 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 1455 EF10_DMA_STAT(port_tx_64, TX_64_PKTS), 1456 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 1457 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 1458 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 1459 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 1460 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 1461 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 1462 EF10_DMA_STAT(port_rx_bytes, RX_BYTES), 1463 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES), 1464 EF10_OTHER_STAT(port_rx_good_bytes), 1465 EF10_OTHER_STAT(port_rx_bad_bytes), 1466 EF10_DMA_STAT(port_rx_packets, RX_PKTS), 1467 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 1468 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 1469 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 1470 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS), 1471 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 1472 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 1473 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 1474 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 1475 EF10_DMA_STAT(port_rx_64, RX_64_PKTS), 1476 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 1477 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 1478 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 1479 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 1480 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 1481 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 1482 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 1483 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 1484 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 1485 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 1486 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 1487 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 1488 EFX_GENERIC_SW_STAT(rx_nodesc_trunc), 1489 EFX_GENERIC_SW_STAT(rx_noskb_drops), 1490 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 1491 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 1492 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 1493 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 1494 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB), 1495 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB), 1496 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING), 1497 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 1498 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 1499 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 1500 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS), 1501 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS), 1502 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS), 1503 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES), 1504 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS), 1505 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES), 1506 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS), 1507 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES), 1508 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS), 1509 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES), 1510 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW), 1511 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS), 1512 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES), 1513 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS), 1514 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES), 1515 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS), 1516 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES), 1517 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS), 1518 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES), 1519 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW), 1520 EF10_DMA_STAT(fec_uncorrected_errors, FEC_UNCORRECTED_ERRORS), 1521 EF10_DMA_STAT(fec_corrected_errors, FEC_CORRECTED_ERRORS), 1522 EF10_DMA_STAT(fec_corrected_symbols_lane0, FEC_CORRECTED_SYMBOLS_LANE0), 1523 EF10_DMA_STAT(fec_corrected_symbols_lane1, FEC_CORRECTED_SYMBOLS_LANE1), 1524 EF10_DMA_STAT(fec_corrected_symbols_lane2, FEC_CORRECTED_SYMBOLS_LANE2), 1525 EF10_DMA_STAT(fec_corrected_symbols_lane3, FEC_CORRECTED_SYMBOLS_LANE3), 1526 EF10_DMA_STAT(ctpio_vi_busy_fallback, CTPIO_VI_BUSY_FALLBACK), 1527 EF10_DMA_STAT(ctpio_long_write_success, CTPIO_LONG_WRITE_SUCCESS), 1528 EF10_DMA_STAT(ctpio_missing_dbell_fail, CTPIO_MISSING_DBELL_FAIL), 1529 EF10_DMA_STAT(ctpio_overflow_fail, CTPIO_OVERFLOW_FAIL), 1530 EF10_DMA_STAT(ctpio_underflow_fail, CTPIO_UNDERFLOW_FAIL), 1531 EF10_DMA_STAT(ctpio_timeout_fail, CTPIO_TIMEOUT_FAIL), 1532 EF10_DMA_STAT(ctpio_noncontig_wr_fail, CTPIO_NONCONTIG_WR_FAIL), 1533 EF10_DMA_STAT(ctpio_frm_clobber_fail, CTPIO_FRM_CLOBBER_FAIL), 1534 EF10_DMA_STAT(ctpio_invalid_wr_fail, CTPIO_INVALID_WR_FAIL), 1535 EF10_DMA_STAT(ctpio_vi_clobber_fallback, CTPIO_VI_CLOBBER_FALLBACK), 1536 EF10_DMA_STAT(ctpio_unqualified_fallback, CTPIO_UNQUALIFIED_FALLBACK), 1537 EF10_DMA_STAT(ctpio_runt_fallback, CTPIO_RUNT_FALLBACK), 1538 EF10_DMA_STAT(ctpio_success, CTPIO_SUCCESS), 1539 EF10_DMA_STAT(ctpio_fallback, CTPIO_FALLBACK), 1540 EF10_DMA_STAT(ctpio_poison, CTPIO_POISON), 1541 EF10_DMA_STAT(ctpio_erase, CTPIO_ERASE), 1542 }; 1543 1544 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \ 1545 (1ULL << EF10_STAT_port_tx_packets) | \ 1546 (1ULL << EF10_STAT_port_tx_pause) | \ 1547 (1ULL << EF10_STAT_port_tx_unicast) | \ 1548 (1ULL << EF10_STAT_port_tx_multicast) | \ 1549 (1ULL << EF10_STAT_port_tx_broadcast) | \ 1550 (1ULL << EF10_STAT_port_rx_bytes) | \ 1551 (1ULL << \ 1552 EF10_STAT_port_rx_bytes_minus_good_bytes) | \ 1553 (1ULL << EF10_STAT_port_rx_good_bytes) | \ 1554 (1ULL << EF10_STAT_port_rx_bad_bytes) | \ 1555 (1ULL << EF10_STAT_port_rx_packets) | \ 1556 (1ULL << EF10_STAT_port_rx_good) | \ 1557 (1ULL << EF10_STAT_port_rx_bad) | \ 1558 (1ULL << EF10_STAT_port_rx_pause) | \ 1559 (1ULL << EF10_STAT_port_rx_control) | \ 1560 (1ULL << EF10_STAT_port_rx_unicast) | \ 1561 (1ULL << EF10_STAT_port_rx_multicast) | \ 1562 (1ULL << EF10_STAT_port_rx_broadcast) | \ 1563 (1ULL << EF10_STAT_port_rx_lt64) | \ 1564 (1ULL << EF10_STAT_port_rx_64) | \ 1565 (1ULL << EF10_STAT_port_rx_65_to_127) | \ 1566 (1ULL << EF10_STAT_port_rx_128_to_255) | \ 1567 (1ULL << EF10_STAT_port_rx_256_to_511) | \ 1568 (1ULL << EF10_STAT_port_rx_512_to_1023) |\ 1569 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\ 1570 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\ 1571 (1ULL << EF10_STAT_port_rx_gtjumbo) | \ 1572 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\ 1573 (1ULL << EF10_STAT_port_rx_overflow) | \ 1574 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\ 1575 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ 1576 (1ULL << GENERIC_STAT_rx_noskb_drops)) 1577 1578 /* On 7000 series NICs, these statistics are only provided by the 10G MAC. 1579 * For a 10G/40G switchable port we do not expose these because they might 1580 * not include all the packets they should. 1581 * On 8000 series NICs these statistics are always provided. 1582 */ 1583 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \ 1584 (1ULL << EF10_STAT_port_tx_lt64) | \ 1585 (1ULL << EF10_STAT_port_tx_64) | \ 1586 (1ULL << EF10_STAT_port_tx_65_to_127) |\ 1587 (1ULL << EF10_STAT_port_tx_128_to_255) |\ 1588 (1ULL << EF10_STAT_port_tx_256_to_511) |\ 1589 (1ULL << EF10_STAT_port_tx_512_to_1023) |\ 1590 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\ 1591 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo)) 1592 1593 /* These statistics are only provided by the 40G MAC. For a 10G/40G 1594 * switchable port we do expose these because the errors will otherwise 1595 * be silent. 1596 */ 1597 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\ 1598 (1ULL << EF10_STAT_port_rx_length_error)) 1599 1600 /* These statistics are only provided if the firmware supports the 1601 * capability PM_AND_RXDP_COUNTERS. 1602 */ 1603 #define HUNT_PM_AND_RXDP_STAT_MASK ( \ 1604 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \ 1605 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \ 1606 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \ 1607 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \ 1608 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \ 1609 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \ 1610 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \ 1611 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \ 1612 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \ 1613 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \ 1614 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \ 1615 (1ULL << EF10_STAT_port_rx_dp_hlb_wait)) 1616 1617 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V2, 1618 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V2 in 1619 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1620 * These bits are in the second u64 of the raw mask. 1621 */ 1622 #define EF10_FEC_STAT_MASK ( \ 1623 (1ULL << (EF10_STAT_fec_uncorrected_errors - 64)) | \ 1624 (1ULL << (EF10_STAT_fec_corrected_errors - 64)) | \ 1625 (1ULL << (EF10_STAT_fec_corrected_symbols_lane0 - 64)) | \ 1626 (1ULL << (EF10_STAT_fec_corrected_symbols_lane1 - 64)) | \ 1627 (1ULL << (EF10_STAT_fec_corrected_symbols_lane2 - 64)) | \ 1628 (1ULL << (EF10_STAT_fec_corrected_symbols_lane3 - 64))) 1629 1630 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V3, 1631 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V3 in 1632 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1633 * These bits are in the second u64 of the raw mask. 1634 */ 1635 #define EF10_CTPIO_STAT_MASK ( \ 1636 (1ULL << (EF10_STAT_ctpio_vi_busy_fallback - 64)) | \ 1637 (1ULL << (EF10_STAT_ctpio_long_write_success - 64)) | \ 1638 (1ULL << (EF10_STAT_ctpio_missing_dbell_fail - 64)) | \ 1639 (1ULL << (EF10_STAT_ctpio_overflow_fail - 64)) | \ 1640 (1ULL << (EF10_STAT_ctpio_underflow_fail - 64)) | \ 1641 (1ULL << (EF10_STAT_ctpio_timeout_fail - 64)) | \ 1642 (1ULL << (EF10_STAT_ctpio_noncontig_wr_fail - 64)) | \ 1643 (1ULL << (EF10_STAT_ctpio_frm_clobber_fail - 64)) | \ 1644 (1ULL << (EF10_STAT_ctpio_invalid_wr_fail - 64)) | \ 1645 (1ULL << (EF10_STAT_ctpio_vi_clobber_fallback - 64)) | \ 1646 (1ULL << (EF10_STAT_ctpio_unqualified_fallback - 64)) | \ 1647 (1ULL << (EF10_STAT_ctpio_runt_fallback - 64)) | \ 1648 (1ULL << (EF10_STAT_ctpio_success - 64)) | \ 1649 (1ULL << (EF10_STAT_ctpio_fallback - 64)) | \ 1650 (1ULL << (EF10_STAT_ctpio_poison - 64)) | \ 1651 (1ULL << (EF10_STAT_ctpio_erase - 64))) 1652 1653 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 1654 { 1655 u64 raw_mask = HUNT_COMMON_STAT_MASK; 1656 u32 port_caps = efx_mcdi_phy_get_caps(efx); 1657 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1658 1659 if (!(efx->mcdi->fn_flags & 1660 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 1661 return 0; 1662 1663 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) { 1664 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 1665 /* 8000 series have everything even at 40G */ 1666 if (nic_data->datapath_caps2 & 1667 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN)) 1668 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1669 } else { 1670 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1671 } 1672 1673 if (nic_data->datapath_caps & 1674 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 1675 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 1676 1677 return raw_mask; 1678 } 1679 1680 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 1681 { 1682 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1683 u64 raw_mask[2]; 1684 1685 raw_mask[0] = efx_ef10_raw_stat_mask(efx); 1686 1687 /* Only show vadaptor stats when EVB capability is present */ 1688 if (nic_data->datapath_caps & 1689 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) { 1690 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1); 1691 raw_mask[1] = (1ULL << (EF10_STAT_V1_COUNT - 64)) - 1; 1692 } else { 1693 raw_mask[1] = 0; 1694 } 1695 /* Only show FEC stats when NIC supports MC_CMD_MAC_STATS_V2 */ 1696 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V2) 1697 raw_mask[1] |= EF10_FEC_STAT_MASK; 1698 1699 /* CTPIO stats appear in V3. Only show them on devices that actually 1700 * support CTPIO. Although this driver doesn't use CTPIO others might, 1701 * and we may be reporting the stats for the underlying port. 1702 */ 1703 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V3 && 1704 (nic_data->datapath_caps2 & 1705 (1 << MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN))) 1706 raw_mask[1] |= EF10_CTPIO_STAT_MASK; 1707 1708 #if BITS_PER_LONG == 64 1709 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2); 1710 mask[0] = raw_mask[0]; 1711 mask[1] = raw_mask[1]; 1712 #else 1713 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3); 1714 mask[0] = raw_mask[0] & 0xffffffff; 1715 mask[1] = raw_mask[0] >> 32; 1716 mask[2] = raw_mask[1] & 0xffffffff; 1717 #endif 1718 } 1719 1720 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 1721 { 1722 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1723 1724 efx_ef10_get_stat_mask(efx, mask); 1725 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1726 mask, names); 1727 } 1728 1729 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats, 1730 struct rtnl_link_stats64 *core_stats) 1731 { 1732 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1733 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1734 u64 *stats = nic_data->stats; 1735 size_t stats_count = 0, index; 1736 1737 efx_ef10_get_stat_mask(efx, mask); 1738 1739 if (full_stats) { 1740 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 1741 if (efx_ef10_stat_desc[index].name) { 1742 *full_stats++ = stats[index]; 1743 ++stats_count; 1744 } 1745 } 1746 } 1747 1748 if (!core_stats) 1749 return stats_count; 1750 1751 if (nic_data->datapath_caps & 1752 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) { 1753 /* Use vadaptor stats. */ 1754 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] + 1755 stats[EF10_STAT_rx_multicast] + 1756 stats[EF10_STAT_rx_broadcast]; 1757 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] + 1758 stats[EF10_STAT_tx_multicast] + 1759 stats[EF10_STAT_tx_broadcast]; 1760 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] + 1761 stats[EF10_STAT_rx_multicast_bytes] + 1762 stats[EF10_STAT_rx_broadcast_bytes]; 1763 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] + 1764 stats[EF10_STAT_tx_multicast_bytes] + 1765 stats[EF10_STAT_tx_broadcast_bytes]; 1766 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] + 1767 stats[GENERIC_STAT_rx_noskb_drops]; 1768 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 1769 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 1770 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 1771 core_stats->rx_errors = core_stats->rx_crc_errors; 1772 core_stats->tx_errors = stats[EF10_STAT_tx_bad]; 1773 } else { 1774 /* Use port stats. */ 1775 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets]; 1776 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets]; 1777 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes]; 1778 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes]; 1779 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] + 1780 stats[GENERIC_STAT_rx_nodesc_trunc] + 1781 stats[GENERIC_STAT_rx_noskb_drops]; 1782 core_stats->multicast = stats[EF10_STAT_port_rx_multicast]; 1783 core_stats->rx_length_errors = 1784 stats[EF10_STAT_port_rx_gtjumbo] + 1785 stats[EF10_STAT_port_rx_length_error]; 1786 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad]; 1787 core_stats->rx_frame_errors = 1788 stats[EF10_STAT_port_rx_align_error]; 1789 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow]; 1790 core_stats->rx_errors = (core_stats->rx_length_errors + 1791 core_stats->rx_crc_errors + 1792 core_stats->rx_frame_errors); 1793 } 1794 1795 return stats_count; 1796 } 1797 1798 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats, 1799 struct rtnl_link_stats64 *core_stats) 1800 { 1801 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1802 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1803 u64 *stats = nic_data->stats; 1804 1805 efx_ef10_get_stat_mask(efx, mask); 1806 1807 efx_nic_copy_stats(efx, nic_data->mc_stats); 1808 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1809 mask, stats, nic_data->mc_stats, false); 1810 1811 /* Update derived statistics */ 1812 efx_nic_fix_nodesc_drop_stat(efx, 1813 &stats[EF10_STAT_port_rx_nodesc_drops]); 1814 /* MC Firmware reads RX_BYTES and RX_GOOD_BYTES from the MAC. 1815 * It then calculates RX_BAD_BYTES and DMAs it to us with RX_BYTES. 1816 * We report these as port_rx_ stats. We are not given RX_GOOD_BYTES. 1817 * Here we calculate port_rx_good_bytes. 1818 */ 1819 stats[EF10_STAT_port_rx_good_bytes] = 1820 stats[EF10_STAT_port_rx_bytes] - 1821 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]; 1822 1823 /* The asynchronous reads used to calculate RX_BAD_BYTES in 1824 * MC Firmware are done such that we should not see an increase in 1825 * RX_BAD_BYTES when a good packet has arrived. Unfortunately this 1826 * does mean that the stat can decrease at times. Here we do not 1827 * update the stat unless it has increased or has gone to zero 1828 * (In the case of the NIC rebooting). 1829 * Please see Bug 33781 for a discussion of why things work this way. 1830 */ 1831 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes], 1832 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]); 1833 efx_update_sw_stats(efx, stats); 1834 1835 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1836 } 1837 1838 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx) 1839 __must_hold(&efx->stats_lock) 1840 { 1841 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN); 1842 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1843 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1844 __le64 generation_start, generation_end; 1845 u64 *stats = nic_data->stats; 1846 u32 dma_len = efx->num_mac_stats * sizeof(u64); 1847 struct efx_buffer stats_buf; 1848 __le64 *dma_stats; 1849 int rc; 1850 1851 spin_unlock_bh(&efx->stats_lock); 1852 1853 if (in_interrupt()) { 1854 /* If in atomic context, cannot update stats. Just update the 1855 * software stats and return so the caller can continue. 1856 */ 1857 spin_lock_bh(&efx->stats_lock); 1858 efx_update_sw_stats(efx, stats); 1859 return 0; 1860 } 1861 1862 efx_ef10_get_stat_mask(efx, mask); 1863 1864 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC); 1865 if (rc) { 1866 spin_lock_bh(&efx->stats_lock); 1867 return rc; 1868 } 1869 1870 dma_stats = stats_buf.addr; 1871 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID; 1872 1873 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr); 1874 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD, 1875 MAC_STATS_IN_DMA, 1); 1876 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len); 1877 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1878 1879 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf), 1880 NULL, 0, NULL); 1881 spin_lock_bh(&efx->stats_lock); 1882 if (rc) { 1883 /* Expect ENOENT if DMA queues have not been set up */ 1884 if (rc != -ENOENT || atomic_read(&efx->active_queues)) 1885 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS, 1886 sizeof(inbuf), NULL, 0, rc); 1887 goto out; 1888 } 1889 1890 generation_end = dma_stats[efx->num_mac_stats - 1]; 1891 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) { 1892 WARN_ON_ONCE(1); 1893 goto out; 1894 } 1895 rmb(); 1896 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1897 stats, stats_buf.addr, false); 1898 rmb(); 1899 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1900 if (generation_end != generation_start) { 1901 rc = -EAGAIN; 1902 goto out; 1903 } 1904 1905 efx_update_sw_stats(efx, stats); 1906 out: 1907 efx_nic_free_buffer(efx, &stats_buf); 1908 return rc; 1909 } 1910 1911 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats, 1912 struct rtnl_link_stats64 *core_stats) 1913 { 1914 if (efx_ef10_try_update_nic_stats_vf(efx)) 1915 return 0; 1916 1917 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1918 } 1919 1920 static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1921 { 1922 struct efx_nic *efx = channel->efx; 1923 unsigned int mode, usecs; 1924 efx_dword_t timer_cmd; 1925 1926 if (channel->irq_moderation_us) { 1927 mode = 3; 1928 usecs = channel->irq_moderation_us; 1929 } else { 1930 mode = 0; 1931 usecs = 0; 1932 } 1933 1934 if (EFX_EF10_WORKAROUND_61265(efx)) { 1935 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN); 1936 unsigned int ns = usecs * 1000; 1937 1938 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE, 1939 channel->channel); 1940 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns); 1941 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns); 1942 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode); 1943 1944 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR, 1945 inbuf, sizeof(inbuf), 0, NULL, 0); 1946 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 1947 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 1948 1949 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 1950 EFE_DD_EVQ_IND_TIMER_FLAGS, 1951 ERF_DD_EVQ_IND_TIMER_MODE, mode, 1952 ERF_DD_EVQ_IND_TIMER_VAL, ticks); 1953 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 1954 channel->channel); 1955 } else { 1956 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 1957 1958 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 1959 ERF_DZ_TC_TIMER_VAL, ticks, 1960 ERF_FZ_TC_TMR_REL_VAL, ticks); 1961 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 1962 channel->channel); 1963 } 1964 } 1965 1966 static void efx_ef10_get_wol_vf(struct efx_nic *efx, 1967 struct ethtool_wolinfo *wol) {} 1968 1969 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type) 1970 { 1971 return -EOPNOTSUPP; 1972 } 1973 1974 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 1975 { 1976 wol->supported = 0; 1977 wol->wolopts = 0; 1978 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1979 } 1980 1981 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 1982 { 1983 if (type != 0) 1984 return -EINVAL; 1985 return 0; 1986 } 1987 1988 static void efx_ef10_mcdi_request(struct efx_nic *efx, 1989 const efx_dword_t *hdr, size_t hdr_len, 1990 const efx_dword_t *sdu, size_t sdu_len) 1991 { 1992 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1993 u8 *pdu = nic_data->mcdi_buf.addr; 1994 1995 memcpy(pdu, hdr, hdr_len); 1996 memcpy(pdu + hdr_len, sdu, sdu_len); 1997 wmb(); 1998 1999 /* The hardware provides 'low' and 'high' (doorbell) registers 2000 * for passing the 64-bit address of an MCDI request to 2001 * firmware. However the dwords are swapped by firmware. The 2002 * least significant bits of the doorbell are then 0 for all 2003 * MCDI requests due to alignment. 2004 */ 2005 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 2006 ER_DZ_MC_DB_LWRD); 2007 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 2008 ER_DZ_MC_DB_HWRD); 2009 } 2010 2011 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 2012 { 2013 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2014 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 2015 2016 rmb(); 2017 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 2018 } 2019 2020 static void 2021 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 2022 size_t offset, size_t outlen) 2023 { 2024 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2025 const u8 *pdu = nic_data->mcdi_buf.addr; 2026 2027 memcpy(outbuf, pdu + offset, outlen); 2028 } 2029 2030 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx) 2031 { 2032 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2033 2034 /* All our allocations have been reset */ 2035 efx_ef10_table_reset_mc_allocations(efx); 2036 2037 /* The datapath firmware might have been changed */ 2038 nic_data->must_check_datapath_caps = true; 2039 2040 /* MAC statistics have been cleared on the NIC; clear the local 2041 * statistic that we update with efx_update_diff_stat(). 2042 */ 2043 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0; 2044 } 2045 2046 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 2047 { 2048 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2049 int rc; 2050 2051 rc = efx_ef10_get_warm_boot_count(efx); 2052 if (rc < 0) { 2053 /* The firmware is presumably in the process of 2054 * rebooting. However, we are supposed to report each 2055 * reboot just once, so we must only do that once we 2056 * can read and store the updated warm boot count. 2057 */ 2058 return 0; 2059 } 2060 2061 if (rc == nic_data->warm_boot_count) 2062 return 0; 2063 2064 nic_data->warm_boot_count = rc; 2065 efx_ef10_mcdi_reboot_detected(efx); 2066 2067 return -EIO; 2068 } 2069 2070 /* Handle an MSI interrupt 2071 * 2072 * Handle an MSI hardware interrupt. This routine schedules event 2073 * queue processing. No interrupt acknowledgement cycle is necessary. 2074 * Also, we never need to check that the interrupt is for us, since 2075 * MSI interrupts cannot be shared. 2076 */ 2077 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 2078 { 2079 struct efx_msi_context *context = dev_id; 2080 struct efx_nic *efx = context->efx; 2081 2082 netif_vdbg(efx, intr, efx->net_dev, 2083 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 2084 2085 if (likely(READ_ONCE(efx->irq_soft_enabled))) { 2086 /* Note test interrupts */ 2087 if (context->index == efx->irq_level) 2088 efx->last_irq_cpu = raw_smp_processor_id(); 2089 2090 /* Schedule processing of the channel */ 2091 efx_schedule_channel_irq(efx->channel[context->index]); 2092 } 2093 2094 return IRQ_HANDLED; 2095 } 2096 2097 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 2098 { 2099 struct efx_nic *efx = dev_id; 2100 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled); 2101 struct efx_channel *channel; 2102 efx_dword_t reg; 2103 u32 queues; 2104 2105 /* Read the ISR which also ACKs the interrupts */ 2106 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 2107 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 2108 2109 if (queues == 0) 2110 return IRQ_NONE; 2111 2112 if (likely(soft_enabled)) { 2113 /* Note test interrupts */ 2114 if (queues & (1U << efx->irq_level)) 2115 efx->last_irq_cpu = raw_smp_processor_id(); 2116 2117 efx_for_each_channel(channel, efx) { 2118 if (queues & 1) 2119 efx_schedule_channel_irq(channel); 2120 queues >>= 1; 2121 } 2122 } 2123 2124 netif_vdbg(efx, intr, efx->net_dev, 2125 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 2126 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 2127 2128 return IRQ_HANDLED; 2129 } 2130 2131 static int efx_ef10_irq_test_generate(struct efx_nic *efx) 2132 { 2133 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 2134 2135 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true, 2136 NULL) == 0) 2137 return -ENOTSUPP; 2138 2139 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 2140 2141 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 2142 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 2143 inbuf, sizeof(inbuf), NULL, 0, NULL); 2144 } 2145 2146 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 2147 { 2148 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 2149 (tx_queue->ptr_mask + 1) * 2150 sizeof(efx_qword_t), 2151 GFP_KERNEL); 2152 } 2153 2154 /* This writes to the TX_DESC_WPTR and also pushes data */ 2155 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 2156 const efx_qword_t *txd) 2157 { 2158 unsigned int write_ptr; 2159 efx_oword_t reg; 2160 2161 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2162 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 2163 reg.qword[0] = *txd; 2164 efx_writeo_page(tx_queue->efx, ®, 2165 ER_DZ_TX_DESC_UPD, tx_queue->queue); 2166 } 2167 2168 /* Add Firmware-Assisted TSO v2 option descriptors to a queue. 2169 */ 2170 static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, 2171 struct sk_buff *skb, 2172 bool *data_mapped) 2173 { 2174 struct efx_tx_buffer *buffer; 2175 struct tcphdr *tcp; 2176 struct iphdr *ip; 2177 2178 u16 ipv4_id; 2179 u32 seqnum; 2180 u32 mss; 2181 2182 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2); 2183 2184 mss = skb_shinfo(skb)->gso_size; 2185 2186 if (unlikely(mss < 4)) { 2187 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss); 2188 return -EINVAL; 2189 } 2190 2191 ip = ip_hdr(skb); 2192 if (ip->version == 4) { 2193 /* Modify IPv4 header if needed. */ 2194 ip->tot_len = 0; 2195 ip->check = 0; 2196 ipv4_id = ntohs(ip->id); 2197 } else { 2198 /* Modify IPv6 header if needed. */ 2199 struct ipv6hdr *ipv6 = ipv6_hdr(skb); 2200 2201 ipv6->payload_len = 0; 2202 ipv4_id = 0; 2203 } 2204 2205 tcp = tcp_hdr(skb); 2206 seqnum = ntohl(tcp->seq); 2207 2208 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2209 2210 buffer->flags = EFX_TX_BUF_OPTION; 2211 buffer->len = 0; 2212 buffer->unmap_len = 0; 2213 EFX_POPULATE_QWORD_5(buffer->option, 2214 ESF_DZ_TX_DESC_IS_OPT, 1, 2215 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2216 ESF_DZ_TX_TSO_OPTION_TYPE, 2217 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A, 2218 ESF_DZ_TX_TSO_IP_ID, ipv4_id, 2219 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum 2220 ); 2221 ++tx_queue->insert_count; 2222 2223 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2224 2225 buffer->flags = EFX_TX_BUF_OPTION; 2226 buffer->len = 0; 2227 buffer->unmap_len = 0; 2228 EFX_POPULATE_QWORD_4(buffer->option, 2229 ESF_DZ_TX_DESC_IS_OPT, 1, 2230 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2231 ESF_DZ_TX_TSO_OPTION_TYPE, 2232 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B, 2233 ESF_DZ_TX_TSO_TCP_MSS, mss 2234 ); 2235 ++tx_queue->insert_count; 2236 2237 return 0; 2238 } 2239 2240 static u32 efx_ef10_tso_versions(struct efx_nic *efx) 2241 { 2242 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2243 u32 tso_versions = 0; 2244 2245 if (nic_data->datapath_caps & 2246 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) 2247 tso_versions |= BIT(1); 2248 if (nic_data->datapath_caps2 & 2249 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) 2250 tso_versions |= BIT(2); 2251 return tso_versions; 2252 } 2253 2254 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 2255 { 2256 bool csum_offload = tx_queue->label & EFX_TXQ_TYPE_OFFLOAD; 2257 struct efx_channel *channel = tx_queue->channel; 2258 struct efx_nic *efx = tx_queue->efx; 2259 struct efx_ef10_nic_data *nic_data; 2260 bool tso_v2 = false; 2261 efx_qword_t *txd; 2262 int rc; 2263 2264 nic_data = efx->nic_data; 2265 2266 /* Only attempt to enable TX timestamping if we have the license for it, 2267 * otherwise TXQ init will fail 2268 */ 2269 if (!(nic_data->licensed_features & 2270 (1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN))) { 2271 tx_queue->timestamping = false; 2272 /* Disable sync events on this channel. */ 2273 if (efx->type->ptp_set_ts_sync_events) 2274 efx->type->ptp_set_ts_sync_events(efx, false, false); 2275 } 2276 2277 /* TSOv2 is a limited resource that can only be configured on a limited 2278 * number of queues. TSO without checksum offload is not really a thing, 2279 * so we only enable it for those queues. 2280 * TSOv2 cannot be used with Hardware timestamping, and is never needed 2281 * for XDP tx. 2282 */ 2283 if (csum_offload && (nic_data->datapath_caps2 & 2284 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) && 2285 !tx_queue->timestamping && !tx_queue->xdp_tx) { 2286 tso_v2 = true; 2287 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n", 2288 channel->channel); 2289 } 2290 2291 rc = efx_mcdi_tx_init(tx_queue, tso_v2); 2292 if (rc) 2293 goto fail; 2294 2295 /* A previous user of this TX queue might have set us up the 2296 * bomb by writing a descriptor to the TX push collector but 2297 * not the doorbell. (Each collector belongs to a port, not a 2298 * queue or function, so cannot easily be reset.) We must 2299 * attempt to push a no-op descriptor in its place. 2300 */ 2301 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 2302 tx_queue->insert_count = 1; 2303 txd = efx_tx_desc(tx_queue, 0); 2304 EFX_POPULATE_QWORD_5(*txd, 2305 ESF_DZ_TX_DESC_IS_OPT, true, 2306 ESF_DZ_TX_OPTION_TYPE, 2307 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 2308 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 2309 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload, 2310 ESF_DZ_TX_TIMESTAMP, tx_queue->timestamping); 2311 tx_queue->write_count = 1; 2312 2313 if (tso_v2) { 2314 tx_queue->handle_tso = efx_ef10_tx_tso_desc; 2315 tx_queue->tso_version = 2; 2316 } else if (nic_data->datapath_caps & 2317 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) { 2318 tx_queue->tso_version = 1; 2319 } 2320 2321 wmb(); 2322 efx_ef10_push_tx_desc(tx_queue, txd); 2323 2324 return; 2325 2326 fail: 2327 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 2328 tx_queue->queue); 2329 } 2330 2331 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 2332 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 2333 { 2334 unsigned int write_ptr; 2335 efx_dword_t reg; 2336 2337 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2338 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 2339 efx_writed_page(tx_queue->efx, ®, 2340 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 2341 } 2342 2343 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff 2344 2345 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue, 2346 dma_addr_t dma_addr, unsigned int len) 2347 { 2348 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) { 2349 /* If we need to break across multiple descriptors we should 2350 * stop at a page boundary. This assumes the length limit is 2351 * greater than the page size. 2352 */ 2353 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN; 2354 2355 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE); 2356 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr; 2357 } 2358 2359 return len; 2360 } 2361 2362 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 2363 { 2364 unsigned int old_write_count = tx_queue->write_count; 2365 struct efx_tx_buffer *buffer; 2366 unsigned int write_ptr; 2367 efx_qword_t *txd; 2368 2369 tx_queue->xmit_more_available = false; 2370 if (unlikely(tx_queue->write_count == tx_queue->insert_count)) 2371 return; 2372 2373 do { 2374 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2375 buffer = &tx_queue->buffer[write_ptr]; 2376 txd = efx_tx_desc(tx_queue, write_ptr); 2377 ++tx_queue->write_count; 2378 2379 /* Create TX descriptor ring entry */ 2380 if (buffer->flags & EFX_TX_BUF_OPTION) { 2381 *txd = buffer->option; 2382 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1) 2383 /* PIO descriptor */ 2384 tx_queue->packet_write_count = tx_queue->write_count; 2385 } else { 2386 tx_queue->packet_write_count = tx_queue->write_count; 2387 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 2388 EFX_POPULATE_QWORD_3( 2389 *txd, 2390 ESF_DZ_TX_KER_CONT, 2391 buffer->flags & EFX_TX_BUF_CONT, 2392 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 2393 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 2394 } 2395 } while (tx_queue->write_count != tx_queue->insert_count); 2396 2397 wmb(); /* Ensure descriptors are written before they are fetched */ 2398 2399 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 2400 txd = efx_tx_desc(tx_queue, 2401 old_write_count & tx_queue->ptr_mask); 2402 efx_ef10_push_tx_desc(tx_queue, txd); 2403 ++tx_queue->pushes; 2404 } else { 2405 efx_ef10_notify_tx_desc(tx_queue); 2406 } 2407 } 2408 2409 static int efx_ef10_probe_multicast_chaining(struct efx_nic *efx) 2410 { 2411 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2412 unsigned int enabled, implemented; 2413 bool want_workaround_26807; 2414 int rc; 2415 2416 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 2417 if (rc == -ENOSYS) { 2418 /* GET_WORKAROUNDS was implemented before this workaround, 2419 * thus it must be unavailable in this firmware. 2420 */ 2421 nic_data->workaround_26807 = false; 2422 return 0; 2423 } 2424 if (rc) 2425 return rc; 2426 want_workaround_26807 = 2427 implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807; 2428 nic_data->workaround_26807 = 2429 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807); 2430 2431 if (want_workaround_26807 && !nic_data->workaround_26807) { 2432 unsigned int flags; 2433 2434 rc = efx_mcdi_set_workaround(efx, 2435 MC_CMD_WORKAROUND_BUG26807, 2436 true, &flags); 2437 if (!rc) { 2438 if (flags & 2439 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) { 2440 netif_info(efx, drv, efx->net_dev, 2441 "other functions on NIC have been reset\n"); 2442 2443 /* With MCFW v4.6.x and earlier, the 2444 * boot count will have incremented, 2445 * so re-read the warm_boot_count 2446 * value now to ensure this function 2447 * doesn't think it has changed next 2448 * time it checks. 2449 */ 2450 rc = efx_ef10_get_warm_boot_count(efx); 2451 if (rc >= 0) { 2452 nic_data->warm_boot_count = rc; 2453 rc = 0; 2454 } 2455 } 2456 nic_data->workaround_26807 = true; 2457 } else if (rc == -EPERM) { 2458 rc = 0; 2459 } 2460 } 2461 return rc; 2462 } 2463 2464 static int efx_ef10_filter_table_probe(struct efx_nic *efx) 2465 { 2466 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2467 int rc = efx_ef10_probe_multicast_chaining(efx); 2468 struct efx_mcdi_filter_vlan *vlan; 2469 2470 if (rc) 2471 return rc; 2472 rc = efx_mcdi_filter_table_probe(efx, nic_data->workaround_26807); 2473 2474 if (rc) 2475 return rc; 2476 2477 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 2478 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 2479 if (rc) 2480 goto fail_add_vlan; 2481 } 2482 return 0; 2483 2484 fail_add_vlan: 2485 efx_mcdi_filter_table_remove(efx); 2486 return rc; 2487 } 2488 2489 /* This creates an entry in the RX descriptor queue */ 2490 static inline void 2491 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 2492 { 2493 struct efx_rx_buffer *rx_buf; 2494 efx_qword_t *rxd; 2495 2496 rxd = efx_rx_desc(rx_queue, index); 2497 rx_buf = efx_rx_buffer(rx_queue, index); 2498 EFX_POPULATE_QWORD_2(*rxd, 2499 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 2500 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 2501 } 2502 2503 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 2504 { 2505 struct efx_nic *efx = rx_queue->efx; 2506 unsigned int write_count; 2507 efx_dword_t reg; 2508 2509 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 2510 write_count = rx_queue->added_count & ~7; 2511 if (rx_queue->notified_count == write_count) 2512 return; 2513 2514 do 2515 efx_ef10_build_rx_desc( 2516 rx_queue, 2517 rx_queue->notified_count & rx_queue->ptr_mask); 2518 while (++rx_queue->notified_count != write_count); 2519 2520 wmb(); 2521 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 2522 write_count & rx_queue->ptr_mask); 2523 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 2524 efx_rx_queue_index(rx_queue)); 2525 } 2526 2527 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 2528 2529 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 2530 { 2531 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2532 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2533 efx_qword_t event; 2534 2535 EFX_POPULATE_QWORD_2(event, 2536 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2537 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 2538 2539 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2540 2541 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2542 * already swapped the data to little-endian order. 2543 */ 2544 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2545 sizeof(efx_qword_t)); 2546 2547 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 2548 inbuf, sizeof(inbuf), 0, 2549 efx_ef10_rx_defer_refill_complete, 0); 2550 } 2551 2552 static void 2553 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 2554 int rc, efx_dword_t *outbuf, 2555 size_t outlen_actual) 2556 { 2557 /* nothing to do */ 2558 } 2559 2560 static int efx_ef10_ev_init(struct efx_channel *channel) 2561 { 2562 struct efx_nic *efx = channel->efx; 2563 struct efx_ef10_nic_data *nic_data; 2564 bool use_v2, cut_thru; 2565 2566 nic_data = efx->nic_data; 2567 use_v2 = nic_data->datapath_caps2 & 2568 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN; 2569 cut_thru = !(nic_data->datapath_caps & 2570 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 2571 return efx_mcdi_ev_init(channel, cut_thru, use_v2); 2572 } 2573 2574 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 2575 unsigned int rx_queue_label) 2576 { 2577 struct efx_nic *efx = rx_queue->efx; 2578 2579 netif_info(efx, hw, efx->net_dev, 2580 "rx event arrived on queue %d labeled as queue %u\n", 2581 efx_rx_queue_index(rx_queue), rx_queue_label); 2582 2583 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2584 } 2585 2586 static void 2587 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 2588 unsigned int actual, unsigned int expected) 2589 { 2590 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 2591 struct efx_nic *efx = rx_queue->efx; 2592 2593 netif_info(efx, hw, efx->net_dev, 2594 "dropped %d events (index=%d expected=%d)\n", 2595 dropped, actual, expected); 2596 2597 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2598 } 2599 2600 /* partially received RX was aborted. clean up. */ 2601 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 2602 { 2603 unsigned int rx_desc_ptr; 2604 2605 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 2606 "scattered RX aborted (dropping %u buffers)\n", 2607 rx_queue->scatter_n); 2608 2609 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 2610 2611 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 2612 0, EFX_RX_PKT_DISCARD); 2613 2614 rx_queue->removed_count += rx_queue->scatter_n; 2615 rx_queue->scatter_n = 0; 2616 rx_queue->scatter_len = 0; 2617 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 2618 } 2619 2620 static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel, 2621 unsigned int n_packets, 2622 unsigned int rx_encap_hdr, 2623 unsigned int rx_l3_class, 2624 unsigned int rx_l4_class, 2625 const efx_qword_t *event) 2626 { 2627 struct efx_nic *efx = channel->efx; 2628 bool handled = false; 2629 2630 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) { 2631 if (!(efx->net_dev->features & NETIF_F_RXALL)) { 2632 if (!efx->loopback_selftest) 2633 channel->n_rx_eth_crc_err += n_packets; 2634 return EFX_RX_PKT_DISCARD; 2635 } 2636 handled = true; 2637 } 2638 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) { 2639 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2640 rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2641 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2642 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2643 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2644 netdev_WARN(efx->net_dev, 2645 "invalid class for RX_IPCKSUM_ERR: event=" 2646 EFX_QWORD_FMT "\n", 2647 EFX_QWORD_VAL(*event)); 2648 if (!efx->loopback_selftest) 2649 *(rx_encap_hdr ? 2650 &channel->n_rx_outer_ip_hdr_chksum_err : 2651 &channel->n_rx_ip_hdr_chksum_err) += n_packets; 2652 return 0; 2653 } 2654 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) { 2655 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2656 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2657 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2658 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2659 rx_l4_class != ESE_FZ_L4_CLASS_UDP)))) 2660 netdev_WARN(efx->net_dev, 2661 "invalid class for RX_TCPUDP_CKSUM_ERR: event=" 2662 EFX_QWORD_FMT "\n", 2663 EFX_QWORD_VAL(*event)); 2664 if (!efx->loopback_selftest) 2665 *(rx_encap_hdr ? 2666 &channel->n_rx_outer_tcp_udp_chksum_err : 2667 &channel->n_rx_tcp_udp_chksum_err) += n_packets; 2668 return 0; 2669 } 2670 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) { 2671 if (unlikely(!rx_encap_hdr)) 2672 netdev_WARN(efx->net_dev, 2673 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event=" 2674 EFX_QWORD_FMT "\n", 2675 EFX_QWORD_VAL(*event)); 2676 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2677 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2678 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2679 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2680 netdev_WARN(efx->net_dev, 2681 "invalid class for RX_IP_INNER_CHKSUM_ERR: event=" 2682 EFX_QWORD_FMT "\n", 2683 EFX_QWORD_VAL(*event)); 2684 if (!efx->loopback_selftest) 2685 channel->n_rx_inner_ip_hdr_chksum_err += n_packets; 2686 return 0; 2687 } 2688 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) { 2689 if (unlikely(!rx_encap_hdr)) 2690 netdev_WARN(efx->net_dev, 2691 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2692 EFX_QWORD_FMT "\n", 2693 EFX_QWORD_VAL(*event)); 2694 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2695 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2696 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2697 rx_l4_class != ESE_FZ_L4_CLASS_UDP))) 2698 netdev_WARN(efx->net_dev, 2699 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2700 EFX_QWORD_FMT "\n", 2701 EFX_QWORD_VAL(*event)); 2702 if (!efx->loopback_selftest) 2703 channel->n_rx_inner_tcp_udp_chksum_err += n_packets; 2704 return 0; 2705 } 2706 2707 WARN_ON(!handled); /* No error bits were recognised */ 2708 return 0; 2709 } 2710 2711 static int efx_ef10_handle_rx_event(struct efx_channel *channel, 2712 const efx_qword_t *event) 2713 { 2714 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label; 2715 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr; 2716 unsigned int n_descs, n_packets, i; 2717 struct efx_nic *efx = channel->efx; 2718 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2719 struct efx_rx_queue *rx_queue; 2720 efx_qword_t errors; 2721 bool rx_cont; 2722 u16 flags = 0; 2723 2724 if (unlikely(READ_ONCE(efx->reset_pending))) 2725 return 0; 2726 2727 /* Basic packet information */ 2728 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 2729 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 2730 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 2731 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS); 2732 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS); 2733 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 2734 rx_encap_hdr = 2735 nic_data->datapath_caps & 2736 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ? 2737 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) : 2738 ESE_EZ_ENCAP_HDR_NONE; 2739 2740 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 2741 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 2742 EFX_QWORD_FMT "\n", 2743 EFX_QWORD_VAL(*event)); 2744 2745 rx_queue = efx_channel_get_rx_queue(channel); 2746 2747 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 2748 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 2749 2750 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 2751 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2752 2753 if (n_descs != rx_queue->scatter_n + 1) { 2754 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2755 2756 /* detect rx abort */ 2757 if (unlikely(n_descs == rx_queue->scatter_n)) { 2758 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 2759 netdev_WARN(efx->net_dev, 2760 "invalid RX abort: scatter_n=%u event=" 2761 EFX_QWORD_FMT "\n", 2762 rx_queue->scatter_n, 2763 EFX_QWORD_VAL(*event)); 2764 efx_ef10_handle_rx_abort(rx_queue); 2765 return 0; 2766 } 2767 2768 /* Check that RX completion merging is valid, i.e. 2769 * the current firmware supports it and this is a 2770 * non-scattered packet. 2771 */ 2772 if (!(nic_data->datapath_caps & 2773 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 2774 rx_queue->scatter_n != 0 || rx_cont) { 2775 efx_ef10_handle_rx_bad_lbits( 2776 rx_queue, next_ptr_lbits, 2777 (rx_queue->removed_count + 2778 rx_queue->scatter_n + 1) & 2779 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2780 return 0; 2781 } 2782 2783 /* Merged completion for multiple non-scattered packets */ 2784 rx_queue->scatter_n = 1; 2785 rx_queue->scatter_len = 0; 2786 n_packets = n_descs; 2787 ++channel->n_rx_merge_events; 2788 channel->n_rx_merge_packets += n_packets; 2789 flags |= EFX_RX_PKT_PREFIX_LEN; 2790 } else { 2791 ++rx_queue->scatter_n; 2792 rx_queue->scatter_len += rx_bytes; 2793 if (rx_cont) 2794 return 0; 2795 n_packets = 1; 2796 } 2797 2798 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1, 2799 ESF_DZ_RX_IPCKSUM_ERR, 1, 2800 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1, 2801 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1, 2802 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1); 2803 EFX_AND_QWORD(errors, *event, errors); 2804 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) { 2805 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets, 2806 rx_encap_hdr, 2807 rx_l3_class, rx_l4_class, 2808 event); 2809 } else { 2810 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP || 2811 rx_l4_class == ESE_FZ_L4_CLASS_UDP; 2812 2813 switch (rx_encap_hdr) { 2814 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */ 2815 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */ 2816 if (tcpudp) 2817 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */ 2818 break; 2819 case ESE_EZ_ENCAP_HDR_GRE: 2820 case ESE_EZ_ENCAP_HDR_NONE: 2821 if (tcpudp) 2822 flags |= EFX_RX_PKT_CSUMMED; 2823 break; 2824 default: 2825 netdev_WARN(efx->net_dev, 2826 "unknown encapsulation type: event=" 2827 EFX_QWORD_FMT "\n", 2828 EFX_QWORD_VAL(*event)); 2829 } 2830 } 2831 2832 if (rx_l4_class == ESE_FZ_L4_CLASS_TCP) 2833 flags |= EFX_RX_PKT_TCP; 2834 2835 channel->irq_mod_score += 2 * n_packets; 2836 2837 /* Handle received packet(s) */ 2838 for (i = 0; i < n_packets; i++) { 2839 efx_rx_packet(rx_queue, 2840 rx_queue->removed_count & rx_queue->ptr_mask, 2841 rx_queue->scatter_n, rx_queue->scatter_len, 2842 flags); 2843 rx_queue->removed_count += rx_queue->scatter_n; 2844 } 2845 2846 rx_queue->scatter_n = 0; 2847 rx_queue->scatter_len = 0; 2848 2849 return n_packets; 2850 } 2851 2852 static u32 efx_ef10_extract_event_ts(efx_qword_t *event) 2853 { 2854 u32 tstamp; 2855 2856 tstamp = EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI); 2857 tstamp <<= 16; 2858 tstamp |= EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO); 2859 2860 return tstamp; 2861 } 2862 2863 static void 2864 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 2865 { 2866 struct efx_nic *efx = channel->efx; 2867 struct efx_tx_queue *tx_queue; 2868 unsigned int tx_ev_desc_ptr; 2869 unsigned int tx_ev_q_label; 2870 unsigned int tx_ev_type; 2871 u64 ts_part; 2872 2873 if (unlikely(READ_ONCE(efx->reset_pending))) 2874 return; 2875 2876 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 2877 return; 2878 2879 /* Get the transmit queue */ 2880 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 2881 tx_queue = efx_channel_get_tx_queue(channel, 2882 tx_ev_q_label % EFX_TXQ_TYPES); 2883 2884 if (!tx_queue->timestamping) { 2885 /* Transmit completion */ 2886 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 2887 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 2888 return; 2889 } 2890 2891 /* Transmit timestamps are only available for 8XXX series. They result 2892 * in up to three events per packet. These occur in order, and are: 2893 * - the normal completion event (may be omitted) 2894 * - the low part of the timestamp 2895 * - the high part of the timestamp 2896 * 2897 * It's possible for multiple completion events to appear before the 2898 * corresponding timestamps. So we can for example get: 2899 * COMP N 2900 * COMP N+1 2901 * TS_LO N 2902 * TS_HI N 2903 * TS_LO N+1 2904 * TS_HI N+1 2905 * 2906 * In addition it's also possible for the adjacent completions to be 2907 * merged, so we may not see COMP N above. As such, the completion 2908 * events are not very useful here. 2909 * 2910 * Each part of the timestamp is itself split across two 16 bit 2911 * fields in the event. 2912 */ 2913 tx_ev_type = EFX_QWORD_FIELD(*event, ESF_EZ_TX_SOFT1); 2914 2915 switch (tx_ev_type) { 2916 case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION: 2917 /* Ignore this event - see above. */ 2918 break; 2919 2920 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO: 2921 ts_part = efx_ef10_extract_event_ts(event); 2922 tx_queue->completed_timestamp_minor = ts_part; 2923 break; 2924 2925 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI: 2926 ts_part = efx_ef10_extract_event_ts(event); 2927 tx_queue->completed_timestamp_major = ts_part; 2928 2929 efx_xmit_done_single(tx_queue); 2930 break; 2931 2932 default: 2933 netif_err(efx, hw, efx->net_dev, 2934 "channel %d unknown tx event type %d (data " 2935 EFX_QWORD_FMT ")\n", 2936 channel->channel, tx_ev_type, 2937 EFX_QWORD_VAL(*event)); 2938 break; 2939 } 2940 } 2941 2942 static void 2943 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 2944 { 2945 struct efx_nic *efx = channel->efx; 2946 int subcode; 2947 2948 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 2949 2950 switch (subcode) { 2951 case ESE_DZ_DRV_TIMER_EV: 2952 case ESE_DZ_DRV_WAKE_UP_EV: 2953 break; 2954 case ESE_DZ_DRV_START_UP_EV: 2955 /* event queue init complete. ok. */ 2956 break; 2957 default: 2958 netif_err(efx, hw, efx->net_dev, 2959 "channel %d unknown driver event type %d" 2960 " (data " EFX_QWORD_FMT ")\n", 2961 channel->channel, subcode, 2962 EFX_QWORD_VAL(*event)); 2963 2964 } 2965 } 2966 2967 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 2968 efx_qword_t *event) 2969 { 2970 struct efx_nic *efx = channel->efx; 2971 u32 subcode; 2972 2973 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 2974 2975 switch (subcode) { 2976 case EFX_EF10_TEST: 2977 channel->event_test_cpu = raw_smp_processor_id(); 2978 break; 2979 case EFX_EF10_REFILL: 2980 /* The queue must be empty, so we won't receive any rx 2981 * events, so efx_process_channel() won't refill the 2982 * queue. Refill it here 2983 */ 2984 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 2985 break; 2986 default: 2987 netif_err(efx, hw, efx->net_dev, 2988 "channel %d unknown driver event type %u" 2989 " (data " EFX_QWORD_FMT ")\n", 2990 channel->channel, (unsigned) subcode, 2991 EFX_QWORD_VAL(*event)); 2992 } 2993 } 2994 2995 static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 2996 { 2997 struct efx_nic *efx = channel->efx; 2998 efx_qword_t event, *p_event; 2999 unsigned int read_ptr; 3000 int ev_code; 3001 int spent = 0; 3002 3003 if (quota <= 0) 3004 return spent; 3005 3006 read_ptr = channel->eventq_read_ptr; 3007 3008 for (;;) { 3009 p_event = efx_event(channel, read_ptr); 3010 event = *p_event; 3011 3012 if (!efx_event_present(&event)) 3013 break; 3014 3015 EFX_SET_QWORD(*p_event); 3016 3017 ++read_ptr; 3018 3019 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 3020 3021 netif_vdbg(efx, drv, efx->net_dev, 3022 "processing event on %d " EFX_QWORD_FMT "\n", 3023 channel->channel, EFX_QWORD_VAL(event)); 3024 3025 switch (ev_code) { 3026 case ESE_DZ_EV_CODE_MCDI_EV: 3027 efx_mcdi_process_event(channel, &event); 3028 break; 3029 case ESE_DZ_EV_CODE_RX_EV: 3030 spent += efx_ef10_handle_rx_event(channel, &event); 3031 if (spent >= quota) { 3032 /* XXX can we split a merged event to 3033 * avoid going over-quota? 3034 */ 3035 spent = quota; 3036 goto out; 3037 } 3038 break; 3039 case ESE_DZ_EV_CODE_TX_EV: 3040 efx_ef10_handle_tx_event(channel, &event); 3041 break; 3042 case ESE_DZ_EV_CODE_DRIVER_EV: 3043 efx_ef10_handle_driver_event(channel, &event); 3044 if (++spent == quota) 3045 goto out; 3046 break; 3047 case EFX_EF10_DRVGEN_EV: 3048 efx_ef10_handle_driver_generated_event(channel, &event); 3049 break; 3050 default: 3051 netif_err(efx, hw, efx->net_dev, 3052 "channel %d unknown event type %d" 3053 " (data " EFX_QWORD_FMT ")\n", 3054 channel->channel, ev_code, 3055 EFX_QWORD_VAL(event)); 3056 } 3057 } 3058 3059 out: 3060 channel->eventq_read_ptr = read_ptr; 3061 return spent; 3062 } 3063 3064 static void efx_ef10_ev_read_ack(struct efx_channel *channel) 3065 { 3066 struct efx_nic *efx = channel->efx; 3067 efx_dword_t rptr; 3068 3069 if (EFX_EF10_WORKAROUND_35388(efx)) { 3070 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 3071 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 3072 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 3073 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 3074 3075 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3076 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 3077 ERF_DD_EVQ_IND_RPTR, 3078 (channel->eventq_read_ptr & 3079 channel->eventq_mask) >> 3080 ERF_DD_EVQ_IND_RPTR_WIDTH); 3081 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3082 channel->channel); 3083 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3084 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 3085 ERF_DD_EVQ_IND_RPTR, 3086 channel->eventq_read_ptr & 3087 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 3088 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3089 channel->channel); 3090 } else { 3091 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 3092 channel->eventq_read_ptr & 3093 channel->eventq_mask); 3094 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 3095 } 3096 } 3097 3098 static void efx_ef10_ev_test_generate(struct efx_channel *channel) 3099 { 3100 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 3101 struct efx_nic *efx = channel->efx; 3102 efx_qword_t event; 3103 int rc; 3104 3105 EFX_POPULATE_QWORD_2(event, 3106 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 3107 ESF_DZ_EV_DATA, EFX_EF10_TEST); 3108 3109 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 3110 3111 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 3112 * already swapped the data to little-endian order. 3113 */ 3114 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 3115 sizeof(efx_qword_t)); 3116 3117 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 3118 NULL, 0, NULL); 3119 if (rc != 0) 3120 goto fail; 3121 3122 return; 3123 3124 fail: 3125 WARN_ON(true); 3126 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 3127 } 3128 3129 static void efx_ef10_prepare_flr(struct efx_nic *efx) 3130 { 3131 atomic_set(&efx->active_queues, 0); 3132 } 3133 3134 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx) 3135 { 3136 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3137 u8 mac_old[ETH_ALEN]; 3138 int rc, rc2; 3139 3140 /* Only reconfigure a PF-created vport */ 3141 if (is_zero_ether_addr(nic_data->vport_mac)) 3142 return 0; 3143 3144 efx_device_detach_sync(efx); 3145 efx_net_stop(efx->net_dev); 3146 down_write(&efx->filter_sem); 3147 efx_mcdi_filter_table_remove(efx); 3148 up_write(&efx->filter_sem); 3149 3150 rc = efx_ef10_vadaptor_free(efx, efx->vport_id); 3151 if (rc) 3152 goto restore_filters; 3153 3154 ether_addr_copy(mac_old, nic_data->vport_mac); 3155 rc = efx_ef10_vport_del_mac(efx, efx->vport_id, 3156 nic_data->vport_mac); 3157 if (rc) 3158 goto restore_vadaptor; 3159 3160 rc = efx_ef10_vport_add_mac(efx, efx->vport_id, 3161 efx->net_dev->dev_addr); 3162 if (!rc) { 3163 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr); 3164 } else { 3165 rc2 = efx_ef10_vport_add_mac(efx, efx->vport_id, mac_old); 3166 if (rc2) { 3167 /* Failed to add original MAC, so clear vport_mac */ 3168 eth_zero_addr(nic_data->vport_mac); 3169 goto reset_nic; 3170 } 3171 } 3172 3173 restore_vadaptor: 3174 rc2 = efx_ef10_vadaptor_alloc(efx, efx->vport_id); 3175 if (rc2) 3176 goto reset_nic; 3177 restore_filters: 3178 down_write(&efx->filter_sem); 3179 rc2 = efx_ef10_filter_table_probe(efx); 3180 up_write(&efx->filter_sem); 3181 if (rc2) 3182 goto reset_nic; 3183 3184 rc2 = efx_net_open(efx->net_dev); 3185 if (rc2) 3186 goto reset_nic; 3187 3188 efx_device_attach_if_not_resetting(efx); 3189 3190 return rc; 3191 3192 reset_nic: 3193 netif_err(efx, drv, efx->net_dev, 3194 "Failed to restore when changing MAC address - scheduling reset\n"); 3195 efx_schedule_reset(efx, RESET_TYPE_DATAPATH); 3196 3197 return rc ? rc : rc2; 3198 } 3199 3200 static int efx_ef10_set_mac_address(struct efx_nic *efx) 3201 { 3202 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN); 3203 bool was_enabled = efx->port_enabled; 3204 int rc; 3205 3206 efx_device_detach_sync(efx); 3207 efx_net_stop(efx->net_dev); 3208 3209 mutex_lock(&efx->mac_lock); 3210 down_write(&efx->filter_sem); 3211 efx_mcdi_filter_table_remove(efx); 3212 3213 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR), 3214 efx->net_dev->dev_addr); 3215 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID, 3216 efx->vport_id); 3217 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf, 3218 sizeof(inbuf), NULL, 0, NULL); 3219 3220 efx_ef10_filter_table_probe(efx); 3221 up_write(&efx->filter_sem); 3222 mutex_unlock(&efx->mac_lock); 3223 3224 if (was_enabled) 3225 efx_net_open(efx->net_dev); 3226 efx_device_attach_if_not_resetting(efx); 3227 3228 #ifdef CONFIG_SFC_SRIOV 3229 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) { 3230 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3231 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 3232 3233 if (rc == -EPERM) { 3234 struct efx_nic *efx_pf; 3235 3236 /* Switch to PF and change MAC address on vport */ 3237 efx_pf = pci_get_drvdata(pci_dev_pf); 3238 3239 rc = efx_ef10_sriov_set_vf_mac(efx_pf, 3240 nic_data->vf_index, 3241 efx->net_dev->dev_addr); 3242 } else if (!rc) { 3243 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 3244 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data; 3245 unsigned int i; 3246 3247 /* MAC address successfully changed by VF (with MAC 3248 * spoofing) so update the parent PF if possible. 3249 */ 3250 for (i = 0; i < efx_pf->vf_count; ++i) { 3251 struct ef10_vf *vf = nic_data->vf + i; 3252 3253 if (vf->efx == efx) { 3254 ether_addr_copy(vf->mac, 3255 efx->net_dev->dev_addr); 3256 return 0; 3257 } 3258 } 3259 } 3260 } else 3261 #endif 3262 if (rc == -EPERM) { 3263 netif_err(efx, drv, efx->net_dev, 3264 "Cannot change MAC address; use sfboot to enable" 3265 " mac-spoofing on this interface\n"); 3266 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) { 3267 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC 3268 * fall-back to the method of changing the MAC address on the 3269 * vport. This only applies to PFs because such versions of 3270 * MCFW do not support VFs. 3271 */ 3272 rc = efx_ef10_vport_set_mac_address(efx); 3273 } else if (rc) { 3274 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC, 3275 sizeof(inbuf), NULL, 0, rc); 3276 } 3277 3278 return rc; 3279 } 3280 3281 static int efx_ef10_mac_reconfigure(struct efx_nic *efx, bool mtu_only) 3282 { 3283 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 3284 3285 efx_mcdi_filter_sync_rx_mode(efx); 3286 3287 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED)) 3288 return efx_mcdi_set_mtu(efx); 3289 return efx_mcdi_set_mac(efx); 3290 } 3291 3292 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 3293 { 3294 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 3295 3296 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 3297 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 3298 NULL, 0, NULL); 3299 } 3300 3301 /* MC BISTs follow a different poll mechanism to phy BISTs. 3302 * The BIST is done in the poll handler on the MC, and the MCDI command 3303 * will block until the BIST is done. 3304 */ 3305 static int efx_ef10_poll_bist(struct efx_nic *efx) 3306 { 3307 int rc; 3308 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 3309 size_t outlen; 3310 u32 result; 3311 3312 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 3313 outbuf, sizeof(outbuf), &outlen); 3314 if (rc != 0) 3315 return rc; 3316 3317 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 3318 return -EIO; 3319 3320 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 3321 switch (result) { 3322 case MC_CMD_POLL_BIST_PASSED: 3323 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 3324 return 0; 3325 case MC_CMD_POLL_BIST_TIMEOUT: 3326 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 3327 return -EIO; 3328 case MC_CMD_POLL_BIST_FAILED: 3329 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 3330 return -EIO; 3331 default: 3332 netif_err(efx, hw, efx->net_dev, 3333 "BIST returned unknown result %u", result); 3334 return -EIO; 3335 } 3336 } 3337 3338 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 3339 { 3340 int rc; 3341 3342 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 3343 3344 rc = efx_ef10_start_bist(efx, bist_type); 3345 if (rc != 0) 3346 return rc; 3347 3348 return efx_ef10_poll_bist(efx); 3349 } 3350 3351 static int 3352 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 3353 { 3354 int rc, rc2; 3355 3356 efx_reset_down(efx, RESET_TYPE_WORLD); 3357 3358 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 3359 NULL, 0, NULL, 0, NULL); 3360 if (rc != 0) 3361 goto out; 3362 3363 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 3364 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 3365 3366 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 3367 3368 out: 3369 if (rc == -EPERM) 3370 rc = 0; 3371 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 3372 return rc ? rc : rc2; 3373 } 3374 3375 #ifdef CONFIG_SFC_MTD 3376 3377 struct efx_ef10_nvram_type_info { 3378 u16 type, type_mask; 3379 u8 port; 3380 const char *name; 3381 }; 3382 3383 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 3384 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 3385 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 3386 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 3387 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 3388 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 3389 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 3390 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 3391 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 3392 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 3393 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 3394 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 3395 { NVRAM_PARTITION_TYPE_MUM_FIRMWARE, 0, 0, "sfc_mumfw" }, 3396 { NVRAM_PARTITION_TYPE_EXPANSION_UEFI, 0, 0, "sfc_uefi" }, 3397 { NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS, 0, 0, "sfc_dynamic_cfg_dflt" }, 3398 { NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS, 0, 0, "sfc_exp_rom_cfg_dflt" }, 3399 { NVRAM_PARTITION_TYPE_STATUS, 0, 0, "sfc_status" }, 3400 { NVRAM_PARTITION_TYPE_BUNDLE, 0, 0, "sfc_bundle" }, 3401 { NVRAM_PARTITION_TYPE_BUNDLE_METADATA, 0, 0, "sfc_bundle_metadata" }, 3402 }; 3403 #define EF10_NVRAM_PARTITION_COUNT ARRAY_SIZE(efx_ef10_nvram_types) 3404 3405 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 3406 struct efx_mcdi_mtd_partition *part, 3407 unsigned int type, 3408 unsigned long *found) 3409 { 3410 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 3411 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 3412 const struct efx_ef10_nvram_type_info *info; 3413 size_t size, erase_size, outlen; 3414 int type_idx = 0; 3415 bool protected; 3416 int rc; 3417 3418 for (type_idx = 0; ; type_idx++) { 3419 if (type_idx == EF10_NVRAM_PARTITION_COUNT) 3420 return -ENODEV; 3421 info = efx_ef10_nvram_types + type_idx; 3422 if ((type & ~info->type_mask) == info->type) 3423 break; 3424 } 3425 if (info->port != efx_port_num(efx)) 3426 return -ENODEV; 3427 3428 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 3429 if (rc) 3430 return rc; 3431 if (protected && 3432 (type != NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS && 3433 type != NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS)) 3434 /* Hide protected partitions that don't provide defaults. */ 3435 return -ENODEV; 3436 3437 if (protected) 3438 /* Protected partitions are read only. */ 3439 erase_size = 0; 3440 3441 /* If we've already exposed a partition of this type, hide this 3442 * duplicate. All operations on MTDs are keyed by the type anyway, 3443 * so we can't act on the duplicate. 3444 */ 3445 if (__test_and_set_bit(type_idx, found)) 3446 return -EEXIST; 3447 3448 part->nvram_type = type; 3449 3450 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 3451 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 3452 outbuf, sizeof(outbuf), &outlen); 3453 if (rc) 3454 return rc; 3455 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 3456 return -EIO; 3457 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 3458 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 3459 part->fw_subtype = MCDI_DWORD(outbuf, 3460 NVRAM_METADATA_OUT_SUBTYPE); 3461 3462 part->common.dev_type_name = "EF10 NVRAM manager"; 3463 part->common.type_name = info->name; 3464 3465 part->common.mtd.type = MTD_NORFLASH; 3466 part->common.mtd.flags = MTD_CAP_NORFLASH; 3467 part->common.mtd.size = size; 3468 part->common.mtd.erasesize = erase_size; 3469 /* sfc_status is read-only */ 3470 if (!erase_size) 3471 part->common.mtd.flags |= MTD_NO_ERASE; 3472 3473 return 0; 3474 } 3475 3476 static int efx_ef10_mtd_probe(struct efx_nic *efx) 3477 { 3478 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 3479 DECLARE_BITMAP(found, EF10_NVRAM_PARTITION_COUNT) = { 0 }; 3480 struct efx_mcdi_mtd_partition *parts; 3481 size_t outlen, n_parts_total, i, n_parts; 3482 unsigned int type; 3483 int rc; 3484 3485 ASSERT_RTNL(); 3486 3487 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 3488 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 3489 outbuf, sizeof(outbuf), &outlen); 3490 if (rc) 3491 return rc; 3492 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 3493 return -EIO; 3494 3495 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 3496 if (n_parts_total > 3497 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 3498 return -EIO; 3499 3500 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 3501 if (!parts) 3502 return -ENOMEM; 3503 3504 n_parts = 0; 3505 for (i = 0; i < n_parts_total; i++) { 3506 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 3507 i); 3508 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type, 3509 found); 3510 if (rc == -EEXIST || rc == -ENODEV) 3511 continue; 3512 if (rc) 3513 goto fail; 3514 n_parts++; 3515 } 3516 3517 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 3518 fail: 3519 if (rc) 3520 kfree(parts); 3521 return rc; 3522 } 3523 3524 #endif /* CONFIG_SFC_MTD */ 3525 3526 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 3527 { 3528 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 3529 } 3530 3531 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx, 3532 u32 host_time) {} 3533 3534 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 3535 bool temp) 3536 { 3537 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 3538 int rc; 3539 3540 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 3541 channel->sync_events_state == SYNC_EVENTS_VALID || 3542 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 3543 return 0; 3544 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 3545 3546 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 3547 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3548 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 3549 channel->channel); 3550 3551 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3552 inbuf, sizeof(inbuf), NULL, 0, NULL); 3553 3554 if (rc != 0) 3555 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3556 SYNC_EVENTS_DISABLED; 3557 3558 return rc; 3559 } 3560 3561 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 3562 bool temp) 3563 { 3564 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 3565 int rc; 3566 3567 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 3568 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 3569 return 0; 3570 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 3571 channel->sync_events_state = SYNC_EVENTS_DISABLED; 3572 return 0; 3573 } 3574 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3575 SYNC_EVENTS_DISABLED; 3576 3577 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 3578 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3579 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 3580 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 3581 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 3582 channel->channel); 3583 3584 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3585 inbuf, sizeof(inbuf), NULL, 0, NULL); 3586 3587 return rc; 3588 } 3589 3590 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 3591 bool temp) 3592 { 3593 int (*set)(struct efx_channel *channel, bool temp); 3594 struct efx_channel *channel; 3595 3596 set = en ? 3597 efx_ef10_rx_enable_timestamping : 3598 efx_ef10_rx_disable_timestamping; 3599 3600 channel = efx_ptp_channel(efx); 3601 if (channel) { 3602 int rc = set(channel, temp); 3603 if (en && rc != 0) { 3604 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 3605 return rc; 3606 } 3607 } 3608 3609 return 0; 3610 } 3611 3612 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx, 3613 struct hwtstamp_config *init) 3614 { 3615 return -EOPNOTSUPP; 3616 } 3617 3618 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 3619 struct hwtstamp_config *init) 3620 { 3621 int rc; 3622 3623 switch (init->rx_filter) { 3624 case HWTSTAMP_FILTER_NONE: 3625 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 3626 /* if TX timestamping is still requested then leave PTP on */ 3627 return efx_ptp_change_mode(efx, 3628 init->tx_type != HWTSTAMP_TX_OFF, 0); 3629 case HWTSTAMP_FILTER_ALL: 3630 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3631 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3632 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3633 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3634 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3635 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3636 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3637 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3638 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3639 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3640 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3641 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3642 case HWTSTAMP_FILTER_NTP_ALL: 3643 init->rx_filter = HWTSTAMP_FILTER_ALL; 3644 rc = efx_ptp_change_mode(efx, true, 0); 3645 if (!rc) 3646 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 3647 if (rc) 3648 efx_ptp_change_mode(efx, false, 0); 3649 return rc; 3650 default: 3651 return -ERANGE; 3652 } 3653 } 3654 3655 static int efx_ef10_get_phys_port_id(struct efx_nic *efx, 3656 struct netdev_phys_item_id *ppid) 3657 { 3658 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3659 3660 if (!is_valid_ether_addr(nic_data->port_id)) 3661 return -EOPNOTSUPP; 3662 3663 ppid->id_len = ETH_ALEN; 3664 memcpy(ppid->id, nic_data->port_id, ppid->id_len); 3665 3666 return 0; 3667 } 3668 3669 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3670 { 3671 if (proto != htons(ETH_P_8021Q)) 3672 return -EINVAL; 3673 3674 return efx_ef10_add_vlan(efx, vid); 3675 } 3676 3677 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3678 { 3679 if (proto != htons(ETH_P_8021Q)) 3680 return -EINVAL; 3681 3682 return efx_ef10_del_vlan(efx, vid); 3683 } 3684 3685 /* We rely on the MCDI wiping out our TX rings if it made any changes to the 3686 * ports table, ensuring that any TSO descriptors that were made on a now- 3687 * removed tunnel port will be blown away and won't break things when we try 3688 * to transmit them using the new ports table. 3689 */ 3690 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading) 3691 { 3692 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3693 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX); 3694 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN); 3695 bool will_reset = false; 3696 size_t num_entries = 0; 3697 size_t inlen, outlen; 3698 size_t i; 3699 int rc; 3700 efx_dword_t flags_and_num_entries; 3701 3702 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock)); 3703 3704 nic_data->udp_tunnels_dirty = false; 3705 3706 if (!(nic_data->datapath_caps & 3707 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) { 3708 efx_device_attach_if_not_resetting(efx); 3709 return 0; 3710 } 3711 3712 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) > 3713 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM); 3714 3715 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) { 3716 if (nic_data->udp_tunnels[i].type != 3717 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID) { 3718 efx_dword_t entry; 3719 3720 EFX_POPULATE_DWORD_2(entry, 3721 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT, 3722 ntohs(nic_data->udp_tunnels[i].port), 3723 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL, 3724 nic_data->udp_tunnels[i].type); 3725 *_MCDI_ARRAY_DWORD(inbuf, 3726 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES, 3727 num_entries++) = entry; 3728 } 3729 } 3730 3731 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST - 3732 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 != 3733 EFX_WORD_1_LBN); 3734 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 != 3735 EFX_WORD_1_WIDTH); 3736 EFX_POPULATE_DWORD_2(flags_and_num_entries, 3737 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING, 3738 !!unloading, 3739 EFX_WORD_1, num_entries); 3740 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) = 3741 flags_and_num_entries; 3742 3743 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries); 3744 3745 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS, 3746 inbuf, inlen, outbuf, sizeof(outbuf), &outlen); 3747 if (rc == -EIO) { 3748 /* Most likely the MC rebooted due to another function also 3749 * setting its tunnel port list. Mark the tunnel port list as 3750 * dirty, so it will be pushed upon coming up from the reboot. 3751 */ 3752 nic_data->udp_tunnels_dirty = true; 3753 return 0; 3754 } 3755 3756 if (rc) { 3757 /* expected not available on unprivileged functions */ 3758 if (rc != -EPERM) 3759 netif_warn(efx, drv, efx->net_dev, 3760 "Unable to set UDP tunnel ports; rc=%d.\n", rc); 3761 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) & 3762 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) { 3763 netif_info(efx, drv, efx->net_dev, 3764 "Rebooting MC due to UDP tunnel port list change\n"); 3765 will_reset = true; 3766 if (unloading) 3767 /* Delay for the MC reset to complete. This will make 3768 * unloading other functions a bit smoother. This is a 3769 * race, but the other unload will work whichever way 3770 * it goes, this just avoids an unnecessary error 3771 * message. 3772 */ 3773 msleep(100); 3774 } 3775 if (!will_reset && !unloading) { 3776 /* The caller will have detached, relying on the MC reset to 3777 * trigger a re-attach. Since there won't be an MC reset, we 3778 * have to do the attach ourselves. 3779 */ 3780 efx_device_attach_if_not_resetting(efx); 3781 } 3782 3783 return rc; 3784 } 3785 3786 static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx) 3787 { 3788 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3789 int rc = 0; 3790 3791 mutex_lock(&nic_data->udp_tunnels_lock); 3792 if (nic_data->udp_tunnels_dirty) { 3793 /* Make sure all TX are stopped while we modify the table, else 3794 * we might race against an efx_features_check(). 3795 */ 3796 efx_device_detach_sync(efx); 3797 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3798 } 3799 mutex_unlock(&nic_data->udp_tunnels_lock); 3800 return rc; 3801 } 3802 3803 static int efx_ef10_udp_tnl_set_port(struct net_device *dev, 3804 unsigned int table, unsigned int entry, 3805 struct udp_tunnel_info *ti) 3806 { 3807 struct efx_nic *efx = netdev_priv(dev); 3808 struct efx_ef10_nic_data *nic_data; 3809 int efx_tunnel_type, rc; 3810 3811 if (ti->type == UDP_TUNNEL_TYPE_VXLAN) 3812 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN; 3813 else 3814 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE; 3815 3816 nic_data = efx->nic_data; 3817 if (!(nic_data->datapath_caps & 3818 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3819 return -EOPNOTSUPP; 3820 3821 mutex_lock(&nic_data->udp_tunnels_lock); 3822 /* Make sure all TX are stopped while we add to the table, else we 3823 * might race against an efx_features_check(). 3824 */ 3825 efx_device_detach_sync(efx); 3826 nic_data->udp_tunnels[entry].type = efx_tunnel_type; 3827 nic_data->udp_tunnels[entry].port = ti->port; 3828 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3829 mutex_unlock(&nic_data->udp_tunnels_lock); 3830 3831 return rc; 3832 } 3833 3834 /* Called under the TX lock with the TX queue running, hence no-one can be 3835 * in the middle of updating the UDP tunnels table. However, they could 3836 * have tried and failed the MCDI, in which case they'll have set the dirty 3837 * flag before dropping their locks. 3838 */ 3839 static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port) 3840 { 3841 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3842 size_t i; 3843 3844 if (!(nic_data->datapath_caps & 3845 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3846 return false; 3847 3848 if (nic_data->udp_tunnels_dirty) 3849 /* SW table may not match HW state, so just assume we can't 3850 * use any UDP tunnel offloads. 3851 */ 3852 return false; 3853 3854 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) 3855 if (nic_data->udp_tunnels[i].type != 3856 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID && 3857 nic_data->udp_tunnels[i].port == port) 3858 return true; 3859 3860 return false; 3861 } 3862 3863 static int efx_ef10_udp_tnl_unset_port(struct net_device *dev, 3864 unsigned int table, unsigned int entry, 3865 struct udp_tunnel_info *ti) 3866 { 3867 struct efx_nic *efx = netdev_priv(dev); 3868 struct efx_ef10_nic_data *nic_data; 3869 int rc; 3870 3871 nic_data = efx->nic_data; 3872 3873 mutex_lock(&nic_data->udp_tunnels_lock); 3874 /* Make sure all TX are stopped while we remove from the table, else we 3875 * might race against an efx_features_check(). 3876 */ 3877 efx_device_detach_sync(efx); 3878 nic_data->udp_tunnels[entry].type = TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID; 3879 nic_data->udp_tunnels[entry].port = 0; 3880 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3881 mutex_unlock(&nic_data->udp_tunnels_lock); 3882 3883 return rc; 3884 } 3885 3886 static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels = { 3887 .set_port = efx_ef10_udp_tnl_set_port, 3888 .unset_port = efx_ef10_udp_tnl_unset_port, 3889 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP, 3890 .tables = { 3891 { 3892 .n_entries = 16, 3893 .tunnel_types = UDP_TUNNEL_TYPE_VXLAN | 3894 UDP_TUNNEL_TYPE_GENEVE, 3895 }, 3896 }, 3897 }; 3898 3899 /* EF10 may have multiple datapath firmware variants within a 3900 * single version. Report which variants are running. 3901 */ 3902 static size_t efx_ef10_print_additional_fwver(struct efx_nic *efx, char *buf, 3903 size_t len) 3904 { 3905 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3906 3907 return scnprintf(buf, len, " rx%x tx%x", 3908 nic_data->rx_dpcpu_fw_id, 3909 nic_data->tx_dpcpu_fw_id); 3910 } 3911 3912 static unsigned int ef10_check_caps(const struct efx_nic *efx, 3913 u8 flag, 3914 u32 offset) 3915 { 3916 const struct efx_ef10_nic_data *nic_data = efx->nic_data; 3917 3918 switch (offset) { 3919 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST): 3920 return nic_data->datapath_caps & BIT_ULL(flag); 3921 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST): 3922 return nic_data->datapath_caps2 & BIT_ULL(flag); 3923 default: 3924 return 0; 3925 } 3926 } 3927 3928 #define EF10_OFFLOAD_FEATURES \ 3929 (NETIF_F_IP_CSUM | \ 3930 NETIF_F_HW_VLAN_CTAG_FILTER | \ 3931 NETIF_F_IPV6_CSUM | \ 3932 NETIF_F_RXHASH | \ 3933 NETIF_F_NTUPLE) 3934 3935 const struct efx_nic_type efx_hunt_a0_vf_nic_type = { 3936 .is_vf = true, 3937 .mem_bar = efx_ef10_vf_mem_bar, 3938 .mem_map_size = efx_ef10_mem_map_size, 3939 .probe = efx_ef10_probe_vf, 3940 .remove = efx_ef10_remove, 3941 .dimension_resources = efx_ef10_dimension_resources, 3942 .init = efx_ef10_init_nic, 3943 .fini = efx_ef10_fini_nic, 3944 .map_reset_reason = efx_ef10_map_reset_reason, 3945 .map_reset_flags = efx_ef10_map_reset_flags, 3946 .reset = efx_ef10_reset, 3947 .probe_port = efx_mcdi_port_probe, 3948 .remove_port = efx_mcdi_port_remove, 3949 .fini_dmaq = efx_fini_dmaq, 3950 .prepare_flr = efx_ef10_prepare_flr, 3951 .finish_flr = efx_port_dummy_op_void, 3952 .describe_stats = efx_ef10_describe_stats, 3953 .update_stats = efx_ef10_update_stats_vf, 3954 .start_stats = efx_port_dummy_op_void, 3955 .pull_stats = efx_port_dummy_op_void, 3956 .stop_stats = efx_port_dummy_op_void, 3957 .set_id_led = efx_mcdi_set_id_led, 3958 .push_irq_moderation = efx_ef10_push_irq_moderation, 3959 .reconfigure_mac = efx_ef10_mac_reconfigure, 3960 .check_mac_fault = efx_mcdi_mac_check_fault, 3961 .reconfigure_port = efx_mcdi_port_reconfigure, 3962 .get_wol = efx_ef10_get_wol_vf, 3963 .set_wol = efx_ef10_set_wol_vf, 3964 .resume_wol = efx_port_dummy_op_void, 3965 .mcdi_request = efx_ef10_mcdi_request, 3966 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 3967 .mcdi_read_response = efx_ef10_mcdi_read_response, 3968 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 3969 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 3970 .irq_enable_master = efx_port_dummy_op_void, 3971 .irq_test_generate = efx_ef10_irq_test_generate, 3972 .irq_disable_non_ev = efx_port_dummy_op_void, 3973 .irq_handle_msi = efx_ef10_msi_interrupt, 3974 .irq_handle_legacy = efx_ef10_legacy_interrupt, 3975 .tx_probe = efx_ef10_tx_probe, 3976 .tx_init = efx_ef10_tx_init, 3977 .tx_remove = efx_mcdi_tx_remove, 3978 .tx_write = efx_ef10_tx_write, 3979 .tx_limit_len = efx_ef10_tx_limit_len, 3980 .rx_push_rss_config = efx_mcdi_vf_rx_push_rss_config, 3981 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 3982 .rx_probe = efx_mcdi_rx_probe, 3983 .rx_init = efx_mcdi_rx_init, 3984 .rx_remove = efx_mcdi_rx_remove, 3985 .rx_write = efx_ef10_rx_write, 3986 .rx_defer_refill = efx_ef10_rx_defer_refill, 3987 .ev_probe = efx_mcdi_ev_probe, 3988 .ev_init = efx_ef10_ev_init, 3989 .ev_fini = efx_mcdi_ev_fini, 3990 .ev_remove = efx_mcdi_ev_remove, 3991 .ev_process = efx_ef10_ev_process, 3992 .ev_read_ack = efx_ef10_ev_read_ack, 3993 .ev_test_generate = efx_ef10_ev_test_generate, 3994 .filter_table_probe = efx_ef10_filter_table_probe, 3995 .filter_table_restore = efx_mcdi_filter_table_restore, 3996 .filter_table_remove = efx_mcdi_filter_table_remove, 3997 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 3998 .filter_insert = efx_mcdi_filter_insert, 3999 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4000 .filter_get_safe = efx_mcdi_filter_get_safe, 4001 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4002 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4003 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4004 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4005 #ifdef CONFIG_RFS_ACCEL 4006 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4007 #endif 4008 #ifdef CONFIG_SFC_MTD 4009 .mtd_probe = efx_port_dummy_op_int, 4010 #endif 4011 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf, 4012 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf, 4013 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4014 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4015 #ifdef CONFIG_SFC_SRIOV 4016 .vswitching_probe = efx_ef10_vswitching_probe_vf, 4017 .vswitching_restore = efx_ef10_vswitching_restore_vf, 4018 .vswitching_remove = efx_ef10_vswitching_remove_vf, 4019 #endif 4020 .get_mac_address = efx_ef10_get_mac_address_vf, 4021 .set_mac_address = efx_ef10_set_mac_address, 4022 4023 .get_phys_port_id = efx_ef10_get_phys_port_id, 4024 .revision = EFX_REV_HUNT_A0, 4025 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4026 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4027 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4028 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4029 .can_rx_scatter = true, 4030 .always_rx_scatter = true, 4031 .min_interrupt_mode = EFX_INT_MODE_MSIX, 4032 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4033 .offload_features = EF10_OFFLOAD_FEATURES, 4034 .mcdi_max_ver = 2, 4035 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4036 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4037 1 << HWTSTAMP_FILTER_ALL, 4038 .rx_hash_key_size = 40, 4039 .check_caps = ef10_check_caps, 4040 .print_additional_fwver = efx_ef10_print_additional_fwver, 4041 }; 4042 4043 const struct efx_nic_type efx_hunt_a0_nic_type = { 4044 .is_vf = false, 4045 .mem_bar = efx_ef10_pf_mem_bar, 4046 .mem_map_size = efx_ef10_mem_map_size, 4047 .probe = efx_ef10_probe_pf, 4048 .remove = efx_ef10_remove, 4049 .dimension_resources = efx_ef10_dimension_resources, 4050 .init = efx_ef10_init_nic, 4051 .fini = efx_ef10_fini_nic, 4052 .map_reset_reason = efx_ef10_map_reset_reason, 4053 .map_reset_flags = efx_ef10_map_reset_flags, 4054 .reset = efx_ef10_reset, 4055 .probe_port = efx_mcdi_port_probe, 4056 .remove_port = efx_mcdi_port_remove, 4057 .fini_dmaq = efx_fini_dmaq, 4058 .prepare_flr = efx_ef10_prepare_flr, 4059 .finish_flr = efx_port_dummy_op_void, 4060 .describe_stats = efx_ef10_describe_stats, 4061 .update_stats = efx_ef10_update_stats_pf, 4062 .start_stats = efx_mcdi_mac_start_stats, 4063 .pull_stats = efx_mcdi_mac_pull_stats, 4064 .stop_stats = efx_mcdi_mac_stop_stats, 4065 .set_id_led = efx_mcdi_set_id_led, 4066 .push_irq_moderation = efx_ef10_push_irq_moderation, 4067 .reconfigure_mac = efx_ef10_mac_reconfigure, 4068 .check_mac_fault = efx_mcdi_mac_check_fault, 4069 .reconfigure_port = efx_mcdi_port_reconfigure, 4070 .get_wol = efx_ef10_get_wol, 4071 .set_wol = efx_ef10_set_wol, 4072 .resume_wol = efx_port_dummy_op_void, 4073 .test_chip = efx_ef10_test_chip, 4074 .test_nvram = efx_mcdi_nvram_test_all, 4075 .mcdi_request = efx_ef10_mcdi_request, 4076 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4077 .mcdi_read_response = efx_ef10_mcdi_read_response, 4078 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4079 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4080 .irq_enable_master = efx_port_dummy_op_void, 4081 .irq_test_generate = efx_ef10_irq_test_generate, 4082 .irq_disable_non_ev = efx_port_dummy_op_void, 4083 .irq_handle_msi = efx_ef10_msi_interrupt, 4084 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4085 .tx_probe = efx_ef10_tx_probe, 4086 .tx_init = efx_ef10_tx_init, 4087 .tx_remove = efx_mcdi_tx_remove, 4088 .tx_write = efx_ef10_tx_write, 4089 .tx_limit_len = efx_ef10_tx_limit_len, 4090 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 4091 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 4092 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config, 4093 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config, 4094 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 4095 .rx_probe = efx_mcdi_rx_probe, 4096 .rx_init = efx_mcdi_rx_init, 4097 .rx_remove = efx_mcdi_rx_remove, 4098 .rx_write = efx_ef10_rx_write, 4099 .rx_defer_refill = efx_ef10_rx_defer_refill, 4100 .ev_probe = efx_mcdi_ev_probe, 4101 .ev_init = efx_ef10_ev_init, 4102 .ev_fini = efx_mcdi_ev_fini, 4103 .ev_remove = efx_mcdi_ev_remove, 4104 .ev_process = efx_ef10_ev_process, 4105 .ev_read_ack = efx_ef10_ev_read_ack, 4106 .ev_test_generate = efx_ef10_ev_test_generate, 4107 .filter_table_probe = efx_ef10_filter_table_probe, 4108 .filter_table_restore = efx_mcdi_filter_table_restore, 4109 .filter_table_remove = efx_mcdi_filter_table_remove, 4110 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 4111 .filter_insert = efx_mcdi_filter_insert, 4112 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4113 .filter_get_safe = efx_mcdi_filter_get_safe, 4114 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4115 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4116 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4117 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4118 #ifdef CONFIG_RFS_ACCEL 4119 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4120 #endif 4121 #ifdef CONFIG_SFC_MTD 4122 .mtd_probe = efx_ef10_mtd_probe, 4123 .mtd_rename = efx_mcdi_mtd_rename, 4124 .mtd_read = efx_mcdi_mtd_read, 4125 .mtd_erase = efx_mcdi_mtd_erase, 4126 .mtd_write = efx_mcdi_mtd_write, 4127 .mtd_sync = efx_mcdi_mtd_sync, 4128 #endif 4129 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 4130 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 4131 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 4132 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4133 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4134 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports, 4135 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port, 4136 #ifdef CONFIG_SFC_SRIOV 4137 .sriov_configure = efx_ef10_sriov_configure, 4138 .sriov_init = efx_ef10_sriov_init, 4139 .sriov_fini = efx_ef10_sriov_fini, 4140 .sriov_wanted = efx_ef10_sriov_wanted, 4141 .sriov_reset = efx_ef10_sriov_reset, 4142 .sriov_flr = efx_ef10_sriov_flr, 4143 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, 4144 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, 4145 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, 4146 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, 4147 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state, 4148 .vswitching_probe = efx_ef10_vswitching_probe_pf, 4149 .vswitching_restore = efx_ef10_vswitching_restore_pf, 4150 .vswitching_remove = efx_ef10_vswitching_remove_pf, 4151 #endif 4152 .get_mac_address = efx_ef10_get_mac_address_pf, 4153 .set_mac_address = efx_ef10_set_mac_address, 4154 .tso_versions = efx_ef10_tso_versions, 4155 4156 .get_phys_port_id = efx_ef10_get_phys_port_id, 4157 .revision = EFX_REV_HUNT_A0, 4158 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4159 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4160 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4161 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4162 .can_rx_scatter = true, 4163 .always_rx_scatter = true, 4164 .option_descriptors = true, 4165 .min_interrupt_mode = EFX_INT_MODE_LEGACY, 4166 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4167 .offload_features = EF10_OFFLOAD_FEATURES, 4168 .mcdi_max_ver = 2, 4169 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4170 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4171 1 << HWTSTAMP_FILTER_ALL, 4172 .rx_hash_key_size = 40, 4173 .check_caps = ef10_check_caps, 4174 .print_additional_fwver = efx_ef10_print_additional_fwver, 4175 }; 4176