1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2012-2013 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 #include "net_driver.h" 11 #include "ef10_regs.h" 12 #include "io.h" 13 #include "mcdi.h" 14 #include "mcdi_pcol.h" 15 #include "nic.h" 16 #include "workarounds.h" 17 #include "selftest.h" 18 #include "ef10_sriov.h" 19 #include <linux/in.h> 20 #include <linux/jhash.h> 21 #include <linux/wait.h> 22 #include <linux/workqueue.h> 23 24 /* Hardware control for EF10 architecture including 'Huntington'. */ 25 26 #define EFX_EF10_DRVGEN_EV 7 27 enum { 28 EFX_EF10_TEST = 1, 29 EFX_EF10_REFILL, 30 }; 31 32 /* The reserved RSS context value */ 33 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff 34 /* The maximum size of a shared RSS context */ 35 /* TODO: this should really be from the mcdi protocol export */ 36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL 37 38 /* The filter table(s) are managed by firmware and we have write-only 39 * access. When removing filters we must identify them to the 40 * firmware by a 64-bit handle, but this is too wide for Linux kernel 41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to 42 * be able to tell in advance whether a requested insertion will 43 * replace an existing filter. Therefore we maintain a software hash 44 * table, which should be at least as large as the hardware hash 45 * table. 46 * 47 * Huntington has a single 8K filter table shared between all filter 48 * types and both ports. 49 */ 50 #define HUNT_FILTER_TBL_ROWS 8192 51 52 #define EFX_EF10_FILTER_ID_INVALID 0xffff 53 54 #define EFX_EF10_FILTER_DEV_UC_MAX 32 55 #define EFX_EF10_FILTER_DEV_MC_MAX 256 56 57 /* VLAN list entry */ 58 struct efx_ef10_vlan { 59 struct list_head list; 60 u16 vid; 61 }; 62 63 /* Per-VLAN filters information */ 64 struct efx_ef10_filter_vlan { 65 struct list_head list; 66 u16 vid; 67 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX]; 68 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX]; 69 u16 ucdef; 70 u16 bcast; 71 u16 mcdef; 72 }; 73 74 struct efx_ef10_dev_addr { 75 u8 addr[ETH_ALEN]; 76 }; 77 78 struct efx_ef10_filter_table { 79 /* The MCDI match masks supported by this fw & hw, in order of priority */ 80 u32 rx_match_mcdi_flags[ 81 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM]; 82 unsigned int rx_match_count; 83 84 struct { 85 unsigned long spec; /* pointer to spec plus flag bits */ 86 /* BUSY flag indicates that an update is in progress. AUTO_OLD is 87 * used to mark and sweep MAC filters for the device address lists. 88 */ 89 #define EFX_EF10_FILTER_FLAG_BUSY 1UL 90 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL 91 #define EFX_EF10_FILTER_FLAGS 3UL 92 u64 handle; /* firmware handle */ 93 } *entry; 94 wait_queue_head_t waitq; 95 /* Shadow of net_device address lists, guarded by mac_lock */ 96 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX]; 97 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX]; 98 int dev_uc_count; 99 int dev_mc_count; 100 bool uc_promisc; 101 bool mc_promisc; 102 /* Whether in multicast promiscuous mode when last changed */ 103 bool mc_promisc_last; 104 bool vlan_filter; 105 struct list_head vlan_list; 106 }; 107 108 /* An arbitrary search limit for the software hash table */ 109 #define EFX_EF10_FILTER_SEARCH_LIMIT 200 110 111 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx); 112 static void efx_ef10_filter_table_remove(struct efx_nic *efx); 113 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid); 114 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx, 115 struct efx_ef10_filter_vlan *vlan); 116 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid); 117 118 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 119 { 120 efx_dword_t reg; 121 122 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 123 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 124 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 125 } 126 127 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 128 { 129 int bar; 130 131 bar = efx->type->mem_bar; 132 return resource_size(&efx->pci_dev->resource[bar]); 133 } 134 135 static bool efx_ef10_is_vf(struct efx_nic *efx) 136 { 137 return efx->type->is_vf; 138 } 139 140 static int efx_ef10_get_pf_index(struct efx_nic *efx) 141 { 142 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 143 struct efx_ef10_nic_data *nic_data = efx->nic_data; 144 size_t outlen; 145 int rc; 146 147 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 148 sizeof(outbuf), &outlen); 149 if (rc) 150 return rc; 151 if (outlen < sizeof(outbuf)) 152 return -EIO; 153 154 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF); 155 return 0; 156 } 157 158 #ifdef CONFIG_SFC_SRIOV 159 static int efx_ef10_get_vf_index(struct efx_nic *efx) 160 { 161 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 162 struct efx_ef10_nic_data *nic_data = efx->nic_data; 163 size_t outlen; 164 int rc; 165 166 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 167 sizeof(outbuf), &outlen); 168 if (rc) 169 return rc; 170 if (outlen < sizeof(outbuf)) 171 return -EIO; 172 173 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF); 174 return 0; 175 } 176 #endif 177 178 static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 179 { 180 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN); 181 struct efx_ef10_nic_data *nic_data = efx->nic_data; 182 size_t outlen; 183 int rc; 184 185 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 186 187 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 188 outbuf, sizeof(outbuf), &outlen); 189 if (rc) 190 return rc; 191 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) { 192 netif_err(efx, drv, efx->net_dev, 193 "unable to read datapath firmware capabilities\n"); 194 return -EIO; 195 } 196 197 nic_data->datapath_caps = 198 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 199 200 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) 201 nic_data->datapath_caps2 = MCDI_DWORD(outbuf, 202 GET_CAPABILITIES_V2_OUT_FLAGS2); 203 else 204 nic_data->datapath_caps2 = 0; 205 206 /* record the DPCPU firmware IDs to determine VEB vswitching support. 207 */ 208 nic_data->rx_dpcpu_fw_id = 209 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); 210 nic_data->tx_dpcpu_fw_id = 211 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); 212 213 if (!(nic_data->datapath_caps & 214 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 215 netif_err(efx, probe, efx->net_dev, 216 "current firmware does not support an RX prefix\n"); 217 return -ENODEV; 218 } 219 220 return 0; 221 } 222 223 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 224 { 225 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 226 int rc; 227 228 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 229 outbuf, sizeof(outbuf), NULL); 230 if (rc) 231 return rc; 232 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 233 return rc > 0 ? rc : -ERANGE; 234 } 235 236 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx) 237 { 238 struct efx_ef10_nic_data *nic_data = efx->nic_data; 239 unsigned int implemented; 240 unsigned int enabled; 241 int rc; 242 243 nic_data->workaround_35388 = false; 244 nic_data->workaround_61265 = false; 245 246 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 247 248 if (rc == -ENOSYS) { 249 /* Firmware without GET_WORKAROUNDS - not a problem. */ 250 rc = 0; 251 } else if (rc == 0) { 252 /* Bug61265 workaround is always enabled if implemented. */ 253 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265) 254 nic_data->workaround_61265 = true; 255 256 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 257 nic_data->workaround_35388 = true; 258 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 259 /* Workaround is implemented but not enabled. 260 * Try to enable it. 261 */ 262 rc = efx_mcdi_set_workaround(efx, 263 MC_CMD_WORKAROUND_BUG35388, 264 true, NULL); 265 if (rc == 0) 266 nic_data->workaround_35388 = true; 267 /* If we failed to set the workaround just carry on. */ 268 rc = 0; 269 } 270 } 271 272 netif_dbg(efx, probe, efx->net_dev, 273 "workaround for bug 35388 is %sabled\n", 274 nic_data->workaround_35388 ? "en" : "dis"); 275 netif_dbg(efx, probe, efx->net_dev, 276 "workaround for bug 61265 is %sabled\n", 277 nic_data->workaround_61265 ? "en" : "dis"); 278 279 return rc; 280 } 281 282 static void efx_ef10_process_timer_config(struct efx_nic *efx, 283 const efx_dword_t *data) 284 { 285 unsigned int max_count; 286 287 if (EFX_EF10_WORKAROUND_61265(efx)) { 288 efx->timer_quantum_ns = MCDI_DWORD(data, 289 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS); 290 efx->timer_max_ns = MCDI_DWORD(data, 291 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS); 292 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 293 efx->timer_quantum_ns = MCDI_DWORD(data, 294 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT); 295 max_count = MCDI_DWORD(data, 296 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT); 297 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 298 } else { 299 efx->timer_quantum_ns = MCDI_DWORD(data, 300 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT); 301 max_count = MCDI_DWORD(data, 302 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT); 303 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 304 } 305 306 netif_dbg(efx, probe, efx->net_dev, 307 "got timer properties from MC: quantum %u ns; max %u ns\n", 308 efx->timer_quantum_ns, efx->timer_max_ns); 309 } 310 311 static int efx_ef10_get_timer_config(struct efx_nic *efx) 312 { 313 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN); 314 int rc; 315 316 rc = efx_ef10_get_timer_workarounds(efx); 317 if (rc) 318 return rc; 319 320 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0, 321 outbuf, sizeof(outbuf), NULL); 322 323 if (rc == 0) { 324 efx_ef10_process_timer_config(efx, outbuf); 325 } else if (rc == -ENOSYS || rc == -EPERM) { 326 /* Not available - fall back to Huntington defaults. */ 327 unsigned int quantum; 328 329 rc = efx_ef10_get_sysclk_freq(efx); 330 if (rc < 0) 331 return rc; 332 333 quantum = 1536000 / rc; /* 1536 cycles */ 334 efx->timer_quantum_ns = quantum; 335 efx->timer_max_ns = efx->type->timer_period_max * quantum; 336 rc = 0; 337 } else { 338 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, 339 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN, 340 NULL, 0, rc); 341 } 342 343 return rc; 344 } 345 346 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address) 347 { 348 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 349 size_t outlen; 350 int rc; 351 352 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 353 354 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 355 outbuf, sizeof(outbuf), &outlen); 356 if (rc) 357 return rc; 358 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 359 return -EIO; 360 361 ether_addr_copy(mac_address, 362 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 363 return 0; 364 } 365 366 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address) 367 { 368 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN); 369 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 370 size_t outlen; 371 int num_addrs, rc; 372 373 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 374 EVB_PORT_ID_ASSIGNED); 375 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf, 376 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 377 378 if (rc) 379 return rc; 380 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) 381 return -EIO; 382 383 num_addrs = MCDI_DWORD(outbuf, 384 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT); 385 386 WARN_ON(num_addrs != 1); 387 388 ether_addr_copy(mac_address, 389 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR)); 390 391 return 0; 392 } 393 394 static ssize_t efx_ef10_show_link_control_flag(struct device *dev, 395 struct device_attribute *attr, 396 char *buf) 397 { 398 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 399 400 return sprintf(buf, "%d\n", 401 ((efx->mcdi->fn_flags) & 402 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 403 ? 1 : 0); 404 } 405 406 static ssize_t efx_ef10_show_primary_flag(struct device *dev, 407 struct device_attribute *attr, 408 char *buf) 409 { 410 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 411 412 return sprintf(buf, "%d\n", 413 ((efx->mcdi->fn_flags) & 414 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)) 415 ? 1 : 0); 416 } 417 418 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid) 419 { 420 struct efx_ef10_nic_data *nic_data = efx->nic_data; 421 struct efx_ef10_vlan *vlan; 422 423 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 424 425 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 426 if (vlan->vid == vid) 427 return vlan; 428 } 429 430 return NULL; 431 } 432 433 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid) 434 { 435 struct efx_ef10_nic_data *nic_data = efx->nic_data; 436 struct efx_ef10_vlan *vlan; 437 int rc; 438 439 mutex_lock(&nic_data->vlan_lock); 440 441 vlan = efx_ef10_find_vlan(efx, vid); 442 if (vlan) { 443 /* We add VID 0 on init. 8021q adds it on module init 444 * for all interfaces with VLAN filtring feature. 445 */ 446 if (vid == 0) 447 goto done_unlock; 448 netif_warn(efx, drv, efx->net_dev, 449 "VLAN %u already added\n", vid); 450 rc = -EALREADY; 451 goto fail_exist; 452 } 453 454 rc = -ENOMEM; 455 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 456 if (!vlan) 457 goto fail_alloc; 458 459 vlan->vid = vid; 460 461 list_add_tail(&vlan->list, &nic_data->vlan_list); 462 463 if (efx->filter_state) { 464 mutex_lock(&efx->mac_lock); 465 down_write(&efx->filter_sem); 466 rc = efx_ef10_filter_add_vlan(efx, vlan->vid); 467 up_write(&efx->filter_sem); 468 mutex_unlock(&efx->mac_lock); 469 if (rc) 470 goto fail_filter_add_vlan; 471 } 472 473 done_unlock: 474 mutex_unlock(&nic_data->vlan_lock); 475 return 0; 476 477 fail_filter_add_vlan: 478 list_del(&vlan->list); 479 kfree(vlan); 480 fail_alloc: 481 fail_exist: 482 mutex_unlock(&nic_data->vlan_lock); 483 return rc; 484 } 485 486 static void efx_ef10_del_vlan_internal(struct efx_nic *efx, 487 struct efx_ef10_vlan *vlan) 488 { 489 struct efx_ef10_nic_data *nic_data = efx->nic_data; 490 491 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 492 493 if (efx->filter_state) { 494 down_write(&efx->filter_sem); 495 efx_ef10_filter_del_vlan(efx, vlan->vid); 496 up_write(&efx->filter_sem); 497 } 498 499 list_del(&vlan->list); 500 kfree(vlan); 501 } 502 503 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid) 504 { 505 struct efx_ef10_nic_data *nic_data = efx->nic_data; 506 struct efx_ef10_vlan *vlan; 507 int rc = 0; 508 509 /* 8021q removes VID 0 on module unload for all interfaces 510 * with VLAN filtering feature. We need to keep it to receive 511 * untagged traffic. 512 */ 513 if (vid == 0) 514 return 0; 515 516 mutex_lock(&nic_data->vlan_lock); 517 518 vlan = efx_ef10_find_vlan(efx, vid); 519 if (!vlan) { 520 netif_err(efx, drv, efx->net_dev, 521 "VLAN %u to be deleted not found\n", vid); 522 rc = -ENOENT; 523 } else { 524 efx_ef10_del_vlan_internal(efx, vlan); 525 } 526 527 mutex_unlock(&nic_data->vlan_lock); 528 529 return rc; 530 } 531 532 static void efx_ef10_cleanup_vlans(struct efx_nic *efx) 533 { 534 struct efx_ef10_nic_data *nic_data = efx->nic_data; 535 struct efx_ef10_vlan *vlan, *next_vlan; 536 537 mutex_lock(&nic_data->vlan_lock); 538 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list) 539 efx_ef10_del_vlan_internal(efx, vlan); 540 mutex_unlock(&nic_data->vlan_lock); 541 } 542 543 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag, 544 NULL); 545 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL); 546 547 static int efx_ef10_probe(struct efx_nic *efx) 548 { 549 struct efx_ef10_nic_data *nic_data; 550 struct net_device *net_dev = efx->net_dev; 551 int i, rc; 552 553 /* We can have one VI for each 8K region. However, until we 554 * use TX option descriptors we need two TX queues per channel. 555 */ 556 efx->max_channels = min_t(unsigned int, 557 EFX_MAX_CHANNELS, 558 efx_ef10_mem_map_size(efx) / 559 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES)); 560 efx->max_tx_channels = efx->max_channels; 561 if (WARN_ON(efx->max_channels == 0)) 562 return -EIO; 563 564 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 565 if (!nic_data) 566 return -ENOMEM; 567 efx->nic_data = nic_data; 568 569 /* we assume later that we can copy from this buffer in dwords */ 570 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 571 572 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 573 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 574 if (rc) 575 goto fail1; 576 577 /* Get the MC's warm boot count. In case it's rebooting right 578 * now, be prepared to retry. 579 */ 580 i = 0; 581 for (;;) { 582 rc = efx_ef10_get_warm_boot_count(efx); 583 if (rc >= 0) 584 break; 585 if (++i == 5) 586 goto fail2; 587 ssleep(1); 588 } 589 nic_data->warm_boot_count = rc; 590 591 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 592 593 nic_data->vport_id = EVB_PORT_ID_ASSIGNED; 594 595 /* In case we're recovering from a crash (kexec), we want to 596 * cancel any outstanding request by the previous user of this 597 * function. We send a special message using the least 598 * significant bits of the 'high' (doorbell) register. 599 */ 600 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 601 602 rc = efx_mcdi_init(efx); 603 if (rc) 604 goto fail2; 605 606 /* Reset (most) configuration for this function */ 607 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 608 if (rc) 609 goto fail3; 610 611 /* Enable event logging */ 612 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 613 if (rc) 614 goto fail3; 615 616 rc = device_create_file(&efx->pci_dev->dev, 617 &dev_attr_link_control_flag); 618 if (rc) 619 goto fail3; 620 621 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 622 if (rc) 623 goto fail4; 624 625 rc = efx_ef10_get_pf_index(efx); 626 if (rc) 627 goto fail5; 628 629 rc = efx_ef10_init_datapath_caps(efx); 630 if (rc < 0) 631 goto fail5; 632 633 efx->rx_packet_len_offset = 634 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 635 636 rc = efx_mcdi_port_get_number(efx); 637 if (rc < 0) 638 goto fail5; 639 efx->port_num = rc; 640 net_dev->dev_port = rc; 641 642 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr); 643 if (rc) 644 goto fail5; 645 646 rc = efx_ef10_get_timer_config(efx); 647 if (rc < 0) 648 goto fail5; 649 650 rc = efx_mcdi_mon_probe(efx); 651 if (rc && rc != -EPERM) 652 goto fail5; 653 654 efx_ptp_probe(efx, NULL); 655 656 #ifdef CONFIG_SFC_SRIOV 657 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) { 658 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 659 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 660 661 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id); 662 } else 663 #endif 664 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr); 665 666 INIT_LIST_HEAD(&nic_data->vlan_list); 667 mutex_init(&nic_data->vlan_lock); 668 669 /* Add unspecified VID to support VLAN filtering being disabled */ 670 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC); 671 if (rc) 672 goto fail_add_vid_unspec; 673 674 /* If VLAN filtering is enabled, we need VID 0 to get untagged 675 * traffic. It is added automatically if 8021q module is loaded, 676 * but we can't rely on it since module may be not loaded. 677 */ 678 rc = efx_ef10_add_vlan(efx, 0); 679 if (rc) 680 goto fail_add_vid_0; 681 682 return 0; 683 684 fail_add_vid_0: 685 efx_ef10_cleanup_vlans(efx); 686 fail_add_vid_unspec: 687 mutex_destroy(&nic_data->vlan_lock); 688 efx_ptp_remove(efx); 689 efx_mcdi_mon_remove(efx); 690 fail5: 691 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 692 fail4: 693 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 694 fail3: 695 efx_mcdi_fini(efx); 696 fail2: 697 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 698 fail1: 699 kfree(nic_data); 700 efx->nic_data = NULL; 701 return rc; 702 } 703 704 static int efx_ef10_free_vis(struct efx_nic *efx) 705 { 706 MCDI_DECLARE_BUF_ERR(outbuf); 707 size_t outlen; 708 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0, 709 outbuf, sizeof(outbuf), &outlen); 710 711 /* -EALREADY means nothing to free, so ignore */ 712 if (rc == -EALREADY) 713 rc = 0; 714 if (rc) 715 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen, 716 rc); 717 return rc; 718 } 719 720 #ifdef EFX_USE_PIO 721 722 static void efx_ef10_free_piobufs(struct efx_nic *efx) 723 { 724 struct efx_ef10_nic_data *nic_data = efx->nic_data; 725 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 726 unsigned int i; 727 int rc; 728 729 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 730 731 for (i = 0; i < nic_data->n_piobufs; i++) { 732 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 733 nic_data->piobuf_handle[i]); 734 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 735 NULL, 0, NULL); 736 WARN_ON(rc); 737 } 738 739 nic_data->n_piobufs = 0; 740 } 741 742 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 743 { 744 struct efx_ef10_nic_data *nic_data = efx->nic_data; 745 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 746 unsigned int i; 747 size_t outlen; 748 int rc = 0; 749 750 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 751 752 for (i = 0; i < n; i++) { 753 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 754 outbuf, sizeof(outbuf), &outlen); 755 if (rc) { 756 /* Don't display the MC error if we didn't have space 757 * for a VF. 758 */ 759 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC)) 760 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF, 761 0, outbuf, outlen, rc); 762 break; 763 } 764 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 765 rc = -EIO; 766 break; 767 } 768 nic_data->piobuf_handle[i] = 769 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 770 netif_dbg(efx, probe, efx->net_dev, 771 "allocated PIO buffer %u handle %x\n", i, 772 nic_data->piobuf_handle[i]); 773 } 774 775 nic_data->n_piobufs = i; 776 if (rc) 777 efx_ef10_free_piobufs(efx); 778 return rc; 779 } 780 781 static int efx_ef10_link_piobufs(struct efx_nic *efx) 782 { 783 struct efx_ef10_nic_data *nic_data = efx->nic_data; 784 _MCDI_DECLARE_BUF(inbuf, 785 max(MC_CMD_LINK_PIOBUF_IN_LEN, 786 MC_CMD_UNLINK_PIOBUF_IN_LEN)); 787 struct efx_channel *channel; 788 struct efx_tx_queue *tx_queue; 789 unsigned int offset, index; 790 int rc; 791 792 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 793 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 794 795 memset(inbuf, 0, sizeof(inbuf)); 796 797 /* Link a buffer to each VI in the write-combining mapping */ 798 for (index = 0; index < nic_data->n_piobufs; ++index) { 799 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 800 nic_data->piobuf_handle[index]); 801 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 802 nic_data->pio_write_vi_base + index); 803 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 804 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 805 NULL, 0, NULL); 806 if (rc) { 807 netif_err(efx, drv, efx->net_dev, 808 "failed to link VI %u to PIO buffer %u (%d)\n", 809 nic_data->pio_write_vi_base + index, index, 810 rc); 811 goto fail; 812 } 813 netif_dbg(efx, probe, efx->net_dev, 814 "linked VI %u to PIO buffer %u\n", 815 nic_data->pio_write_vi_base + index, index); 816 } 817 818 /* Link a buffer to each TX queue */ 819 efx_for_each_channel(channel, efx) { 820 efx_for_each_channel_tx_queue(tx_queue, channel) { 821 /* We assign the PIO buffers to queues in 822 * reverse order to allow for the following 823 * special case. 824 */ 825 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 826 tx_queue->channel->channel - 1) * 827 efx_piobuf_size); 828 index = offset / ER_DZ_TX_PIOBUF_SIZE; 829 offset = offset % ER_DZ_TX_PIOBUF_SIZE; 830 831 /* When the host page size is 4K, the first 832 * host page in the WC mapping may be within 833 * the same VI page as the last TX queue. We 834 * can only link one buffer to each VI. 835 */ 836 if (tx_queue->queue == nic_data->pio_write_vi_base) { 837 BUG_ON(index != 0); 838 rc = 0; 839 } else { 840 MCDI_SET_DWORD(inbuf, 841 LINK_PIOBUF_IN_PIOBUF_HANDLE, 842 nic_data->piobuf_handle[index]); 843 MCDI_SET_DWORD(inbuf, 844 LINK_PIOBUF_IN_TXQ_INSTANCE, 845 tx_queue->queue); 846 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 847 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 848 NULL, 0, NULL); 849 } 850 851 if (rc) { 852 /* This is non-fatal; the TX path just 853 * won't use PIO for this queue 854 */ 855 netif_err(efx, drv, efx->net_dev, 856 "failed to link VI %u to PIO buffer %u (%d)\n", 857 tx_queue->queue, index, rc); 858 tx_queue->piobuf = NULL; 859 } else { 860 tx_queue->piobuf = 861 nic_data->pio_write_base + 862 index * EFX_VI_PAGE_SIZE + offset; 863 tx_queue->piobuf_offset = offset; 864 netif_dbg(efx, probe, efx->net_dev, 865 "linked VI %u to PIO buffer %u offset %x addr %p\n", 866 tx_queue->queue, index, 867 tx_queue->piobuf_offset, 868 tx_queue->piobuf); 869 } 870 } 871 } 872 873 return 0; 874 875 fail: 876 while (index--) { 877 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 878 nic_data->pio_write_vi_base + index); 879 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 880 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 881 NULL, 0, NULL); 882 } 883 return rc; 884 } 885 886 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 887 { 888 struct efx_channel *channel; 889 struct efx_tx_queue *tx_queue; 890 891 /* All our existing PIO buffers went away */ 892 efx_for_each_channel(channel, efx) 893 efx_for_each_channel_tx_queue(tx_queue, channel) 894 tx_queue->piobuf = NULL; 895 } 896 897 #else /* !EFX_USE_PIO */ 898 899 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 900 { 901 return n == 0 ? 0 : -ENOBUFS; 902 } 903 904 static int efx_ef10_link_piobufs(struct efx_nic *efx) 905 { 906 return 0; 907 } 908 909 static void efx_ef10_free_piobufs(struct efx_nic *efx) 910 { 911 } 912 913 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 914 { 915 } 916 917 #endif /* EFX_USE_PIO */ 918 919 static void efx_ef10_remove(struct efx_nic *efx) 920 { 921 struct efx_ef10_nic_data *nic_data = efx->nic_data; 922 int rc; 923 924 #ifdef CONFIG_SFC_SRIOV 925 struct efx_ef10_nic_data *nic_data_pf; 926 struct pci_dev *pci_dev_pf; 927 struct efx_nic *efx_pf; 928 struct ef10_vf *vf; 929 930 if (efx->pci_dev->is_virtfn) { 931 pci_dev_pf = efx->pci_dev->physfn; 932 if (pci_dev_pf) { 933 efx_pf = pci_get_drvdata(pci_dev_pf); 934 nic_data_pf = efx_pf->nic_data; 935 vf = nic_data_pf->vf + nic_data->vf_index; 936 vf->efx = NULL; 937 } else 938 netif_info(efx, drv, efx->net_dev, 939 "Could not get the PF id from VF\n"); 940 } 941 #endif 942 943 efx_ef10_cleanup_vlans(efx); 944 mutex_destroy(&nic_data->vlan_lock); 945 946 efx_ptp_remove(efx); 947 948 efx_mcdi_mon_remove(efx); 949 950 efx_ef10_rx_free_indir_table(efx); 951 952 if (nic_data->wc_membase) 953 iounmap(nic_data->wc_membase); 954 955 rc = efx_ef10_free_vis(efx); 956 WARN_ON(rc != 0); 957 958 if (!nic_data->must_restore_piobufs) 959 efx_ef10_free_piobufs(efx); 960 961 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 962 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 963 964 efx_mcdi_fini(efx); 965 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 966 kfree(nic_data); 967 } 968 969 static int efx_ef10_probe_pf(struct efx_nic *efx) 970 { 971 return efx_ef10_probe(efx); 972 } 973 974 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id, 975 u32 *port_flags, u32 *vadaptor_flags, 976 unsigned int *vlan_tags) 977 { 978 struct efx_ef10_nic_data *nic_data = efx->nic_data; 979 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN); 980 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN); 981 size_t outlen; 982 int rc; 983 984 if (nic_data->datapath_caps & 985 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) { 986 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID, 987 port_id); 988 989 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf), 990 outbuf, sizeof(outbuf), &outlen); 991 if (rc) 992 return rc; 993 994 if (outlen < sizeof(outbuf)) { 995 rc = -EIO; 996 return rc; 997 } 998 } 999 1000 if (port_flags) 1001 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS); 1002 if (vadaptor_flags) 1003 *vadaptor_flags = 1004 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS); 1005 if (vlan_tags) 1006 *vlan_tags = 1007 MCDI_DWORD(outbuf, 1008 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS); 1009 1010 return 0; 1011 } 1012 1013 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id) 1014 { 1015 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN); 1016 1017 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 1018 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf), 1019 NULL, 0, NULL); 1020 } 1021 1022 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id) 1023 { 1024 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN); 1025 1026 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 1027 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf), 1028 NULL, 0, NULL); 1029 } 1030 1031 int efx_ef10_vport_add_mac(struct efx_nic *efx, 1032 unsigned int port_id, u8 *mac) 1033 { 1034 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN); 1035 1036 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id); 1037 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac); 1038 1039 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf, 1040 sizeof(inbuf), NULL, 0, NULL); 1041 } 1042 1043 int efx_ef10_vport_del_mac(struct efx_nic *efx, 1044 unsigned int port_id, u8 *mac) 1045 { 1046 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN); 1047 1048 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id); 1049 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac); 1050 1051 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf, 1052 sizeof(inbuf), NULL, 0, NULL); 1053 } 1054 1055 #ifdef CONFIG_SFC_SRIOV 1056 static int efx_ef10_probe_vf(struct efx_nic *efx) 1057 { 1058 int rc; 1059 struct pci_dev *pci_dev_pf; 1060 1061 /* If the parent PF has no VF data structure, it doesn't know about this 1062 * VF so fail probe. The VF needs to be re-created. This can happen 1063 * if the PF driver is unloaded while the VF is assigned to a guest. 1064 */ 1065 pci_dev_pf = efx->pci_dev->physfn; 1066 if (pci_dev_pf) { 1067 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 1068 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data; 1069 1070 if (!nic_data_pf->vf) { 1071 netif_info(efx, drv, efx->net_dev, 1072 "The VF cannot link to its parent PF; " 1073 "please destroy and re-create the VF\n"); 1074 return -EBUSY; 1075 } 1076 } 1077 1078 rc = efx_ef10_probe(efx); 1079 if (rc) 1080 return rc; 1081 1082 rc = efx_ef10_get_vf_index(efx); 1083 if (rc) 1084 goto fail; 1085 1086 if (efx->pci_dev->is_virtfn) { 1087 if (efx->pci_dev->physfn) { 1088 struct efx_nic *efx_pf = 1089 pci_get_drvdata(efx->pci_dev->physfn); 1090 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data; 1091 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1092 1093 nic_data_p->vf[nic_data->vf_index].efx = efx; 1094 nic_data_p->vf[nic_data->vf_index].pci_dev = 1095 efx->pci_dev; 1096 } else 1097 netif_info(efx, drv, efx->net_dev, 1098 "Could not get the PF id from VF\n"); 1099 } 1100 1101 return 0; 1102 1103 fail: 1104 efx_ef10_remove(efx); 1105 return rc; 1106 } 1107 #else 1108 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused))) 1109 { 1110 return 0; 1111 } 1112 #endif 1113 1114 static int efx_ef10_alloc_vis(struct efx_nic *efx, 1115 unsigned int min_vis, unsigned int max_vis) 1116 { 1117 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN); 1118 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN); 1119 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1120 size_t outlen; 1121 int rc; 1122 1123 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis); 1124 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis); 1125 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf), 1126 outbuf, sizeof(outbuf), &outlen); 1127 if (rc != 0) 1128 return rc; 1129 1130 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN) 1131 return -EIO; 1132 1133 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n", 1134 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE)); 1135 1136 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE); 1137 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT); 1138 return 0; 1139 } 1140 1141 /* Note that the failure path of this function does not free 1142 * resources, as this will be done by efx_ef10_remove(). 1143 */ 1144 static int efx_ef10_dimension_resources(struct efx_nic *efx) 1145 { 1146 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1147 unsigned int uc_mem_map_size, wc_mem_map_size; 1148 unsigned int min_vis = max(EFX_TXQ_TYPES, 1149 efx_separate_tx_channels ? 2 : 1); 1150 unsigned int channel_vis, pio_write_vi_base, max_vis; 1151 void __iomem *membase; 1152 int rc; 1153 1154 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES); 1155 1156 #ifdef EFX_USE_PIO 1157 /* Try to allocate PIO buffers if wanted and if the full 1158 * number of PIO buffers would be sufficient to allocate one 1159 * copy-buffer per TX channel. Failure is non-fatal, as there 1160 * are only a small number of PIO buffers shared between all 1161 * functions of the controller. 1162 */ 1163 if (efx_piobuf_size != 0 && 1164 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 1165 efx->n_tx_channels) { 1166 unsigned int n_piobufs = 1167 DIV_ROUND_UP(efx->n_tx_channels, 1168 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size); 1169 1170 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 1171 if (rc) 1172 netif_err(efx, probe, efx->net_dev, 1173 "failed to allocate PIO buffers (%d)\n", rc); 1174 else 1175 netif_dbg(efx, probe, efx->net_dev, 1176 "allocated %u PIO buffers\n", n_piobufs); 1177 } 1178 #else 1179 nic_data->n_piobufs = 0; 1180 #endif 1181 1182 /* PIO buffers should be mapped with write-combining enabled, 1183 * and we want to make single UC and WC mappings rather than 1184 * several of each (in fact that's the only option if host 1185 * page size is >4K). So we may allocate some extra VIs just 1186 * for writing PIO buffers through. 1187 * 1188 * The UC mapping contains (channel_vis - 1) complete VIs and the 1189 * first half of the next VI. Then the WC mapping begins with 1190 * the second half of this last VI. 1191 */ 1192 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE + 1193 ER_DZ_TX_PIOBUF); 1194 if (nic_data->n_piobufs) { 1195 /* pio_write_vi_base rounds down to give the number of complete 1196 * VIs inside the UC mapping. 1197 */ 1198 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE; 1199 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 1200 nic_data->n_piobufs) * 1201 EFX_VI_PAGE_SIZE) - 1202 uc_mem_map_size); 1203 max_vis = pio_write_vi_base + nic_data->n_piobufs; 1204 } else { 1205 pio_write_vi_base = 0; 1206 wc_mem_map_size = 0; 1207 max_vis = channel_vis; 1208 } 1209 1210 /* In case the last attached driver failed to free VIs, do it now */ 1211 rc = efx_ef10_free_vis(efx); 1212 if (rc != 0) 1213 return rc; 1214 1215 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 1216 if (rc != 0) 1217 return rc; 1218 1219 if (nic_data->n_allocated_vis < channel_vis) { 1220 netif_info(efx, drv, efx->net_dev, 1221 "Could not allocate enough VIs to satisfy RSS" 1222 " requirements. Performance may not be optimal.\n"); 1223 /* We didn't get the VIs to populate our channels. 1224 * We could keep what we got but then we'd have more 1225 * interrupts than we need. 1226 * Instead calculate new max_channels and restart 1227 */ 1228 efx->max_channels = nic_data->n_allocated_vis; 1229 efx->max_tx_channels = 1230 nic_data->n_allocated_vis / EFX_TXQ_TYPES; 1231 1232 efx_ef10_free_vis(efx); 1233 return -EAGAIN; 1234 } 1235 1236 /* If we didn't get enough VIs to map all the PIO buffers, free the 1237 * PIO buffers 1238 */ 1239 if (nic_data->n_piobufs && 1240 nic_data->n_allocated_vis < 1241 pio_write_vi_base + nic_data->n_piobufs) { 1242 netif_dbg(efx, probe, efx->net_dev, 1243 "%u VIs are not sufficient to map %u PIO buffers\n", 1244 nic_data->n_allocated_vis, nic_data->n_piobufs); 1245 efx_ef10_free_piobufs(efx); 1246 } 1247 1248 /* Shrink the original UC mapping of the memory BAR */ 1249 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size); 1250 if (!membase) { 1251 netif_err(efx, probe, efx->net_dev, 1252 "could not shrink memory BAR to %x\n", 1253 uc_mem_map_size); 1254 return -ENOMEM; 1255 } 1256 iounmap(efx->membase); 1257 efx->membase = membase; 1258 1259 /* Set up the WC mapping if needed */ 1260 if (wc_mem_map_size) { 1261 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 1262 uc_mem_map_size, 1263 wc_mem_map_size); 1264 if (!nic_data->wc_membase) { 1265 netif_err(efx, probe, efx->net_dev, 1266 "could not allocate WC mapping of size %x\n", 1267 wc_mem_map_size); 1268 return -ENOMEM; 1269 } 1270 nic_data->pio_write_vi_base = pio_write_vi_base; 1271 nic_data->pio_write_base = 1272 nic_data->wc_membase + 1273 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF - 1274 uc_mem_map_size); 1275 1276 rc = efx_ef10_link_piobufs(efx); 1277 if (rc) 1278 efx_ef10_free_piobufs(efx); 1279 } 1280 1281 netif_dbg(efx, probe, efx->net_dev, 1282 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 1283 &efx->membase_phys, efx->membase, uc_mem_map_size, 1284 nic_data->wc_membase, wc_mem_map_size); 1285 1286 return 0; 1287 } 1288 1289 static int efx_ef10_init_nic(struct efx_nic *efx) 1290 { 1291 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1292 int rc; 1293 1294 if (nic_data->must_check_datapath_caps) { 1295 rc = efx_ef10_init_datapath_caps(efx); 1296 if (rc) 1297 return rc; 1298 nic_data->must_check_datapath_caps = false; 1299 } 1300 1301 if (nic_data->must_realloc_vis) { 1302 /* We cannot let the number of VIs change now */ 1303 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 1304 nic_data->n_allocated_vis); 1305 if (rc) 1306 return rc; 1307 nic_data->must_realloc_vis = false; 1308 } 1309 1310 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 1311 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 1312 if (rc == 0) { 1313 rc = efx_ef10_link_piobufs(efx); 1314 if (rc) 1315 efx_ef10_free_piobufs(efx); 1316 } 1317 1318 /* Log an error on failure, but this is non-fatal */ 1319 if (rc) 1320 netif_err(efx, drv, efx->net_dev, 1321 "failed to restore PIO buffers (%d)\n", rc); 1322 nic_data->must_restore_piobufs = false; 1323 } 1324 1325 /* don't fail init if RSS setup doesn't work */ 1326 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table); 1327 1328 return 0; 1329 } 1330 1331 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx) 1332 { 1333 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1334 #ifdef CONFIG_SFC_SRIOV 1335 unsigned int i; 1336 #endif 1337 1338 /* All our allocations have been reset */ 1339 nic_data->must_realloc_vis = true; 1340 nic_data->must_restore_filters = true; 1341 nic_data->must_restore_piobufs = true; 1342 efx_ef10_forget_old_piobufs(efx); 1343 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 1344 1345 /* Driver-created vswitches and vports must be re-created */ 1346 nic_data->must_probe_vswitching = true; 1347 nic_data->vport_id = EVB_PORT_ID_ASSIGNED; 1348 #ifdef CONFIG_SFC_SRIOV 1349 if (nic_data->vf) 1350 for (i = 0; i < efx->vf_count; i++) 1351 nic_data->vf[i].vport_id = 0; 1352 #endif 1353 } 1354 1355 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason) 1356 { 1357 if (reason == RESET_TYPE_MC_FAILURE) 1358 return RESET_TYPE_DATAPATH; 1359 1360 return efx_mcdi_map_reset_reason(reason); 1361 } 1362 1363 static int efx_ef10_map_reset_flags(u32 *flags) 1364 { 1365 enum { 1366 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 1367 ETH_RESET_SHARED_SHIFT), 1368 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 1369 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 1370 ETH_RESET_PHY | ETH_RESET_MGMT) << 1371 ETH_RESET_SHARED_SHIFT) 1372 }; 1373 1374 /* We assume for now that our PCI function is permitted to 1375 * reset everything. 1376 */ 1377 1378 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 1379 *flags &= ~EF10_RESET_MC; 1380 return RESET_TYPE_WORLD; 1381 } 1382 1383 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 1384 *flags &= ~EF10_RESET_PORT; 1385 return RESET_TYPE_ALL; 1386 } 1387 1388 /* no invisible reset implemented */ 1389 1390 return -EINVAL; 1391 } 1392 1393 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 1394 { 1395 int rc = efx_mcdi_reset(efx, reset_type); 1396 1397 /* Unprivileged functions return -EPERM, but need to return success 1398 * here so that the datapath is brought back up. 1399 */ 1400 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM) 1401 rc = 0; 1402 1403 /* If it was a port reset, trigger reallocation of MC resources. 1404 * Note that on an MC reset nothing needs to be done now because we'll 1405 * detect the MC reset later and handle it then. 1406 * For an FLR, we never get an MC reset event, but the MC has reset all 1407 * resources assigned to us, so we have to trigger reallocation now. 1408 */ 1409 if ((reset_type == RESET_TYPE_ALL || 1410 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) 1411 efx_ef10_reset_mc_allocations(efx); 1412 return rc; 1413 } 1414 1415 #define EF10_DMA_STAT(ext_name, mcdi_name) \ 1416 [EF10_STAT_ ## ext_name] = \ 1417 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1418 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 1419 [EF10_STAT_ ## int_name] = \ 1420 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1421 #define EF10_OTHER_STAT(ext_name) \ 1422 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1423 #define GENERIC_SW_STAT(ext_name) \ 1424 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1425 1426 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 1427 EF10_DMA_STAT(port_tx_bytes, TX_BYTES), 1428 EF10_DMA_STAT(port_tx_packets, TX_PKTS), 1429 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 1430 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS), 1431 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 1432 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 1433 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 1434 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 1435 EF10_DMA_STAT(port_tx_64, TX_64_PKTS), 1436 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 1437 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 1438 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 1439 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 1440 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 1441 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 1442 EF10_DMA_STAT(port_rx_bytes, RX_BYTES), 1443 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES), 1444 EF10_OTHER_STAT(port_rx_good_bytes), 1445 EF10_OTHER_STAT(port_rx_bad_bytes), 1446 EF10_DMA_STAT(port_rx_packets, RX_PKTS), 1447 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 1448 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 1449 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 1450 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS), 1451 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 1452 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 1453 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 1454 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 1455 EF10_DMA_STAT(port_rx_64, RX_64_PKTS), 1456 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 1457 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 1458 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 1459 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 1460 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 1461 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 1462 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 1463 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 1464 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 1465 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 1466 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 1467 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 1468 GENERIC_SW_STAT(rx_nodesc_trunc), 1469 GENERIC_SW_STAT(rx_noskb_drops), 1470 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 1471 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 1472 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 1473 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 1474 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB), 1475 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB), 1476 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING), 1477 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 1478 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 1479 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 1480 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS), 1481 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS), 1482 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS), 1483 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES), 1484 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS), 1485 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES), 1486 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS), 1487 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES), 1488 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS), 1489 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES), 1490 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW), 1491 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS), 1492 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES), 1493 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS), 1494 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES), 1495 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS), 1496 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES), 1497 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS), 1498 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES), 1499 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW), 1500 }; 1501 1502 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \ 1503 (1ULL << EF10_STAT_port_tx_packets) | \ 1504 (1ULL << EF10_STAT_port_tx_pause) | \ 1505 (1ULL << EF10_STAT_port_tx_unicast) | \ 1506 (1ULL << EF10_STAT_port_tx_multicast) | \ 1507 (1ULL << EF10_STAT_port_tx_broadcast) | \ 1508 (1ULL << EF10_STAT_port_rx_bytes) | \ 1509 (1ULL << \ 1510 EF10_STAT_port_rx_bytes_minus_good_bytes) | \ 1511 (1ULL << EF10_STAT_port_rx_good_bytes) | \ 1512 (1ULL << EF10_STAT_port_rx_bad_bytes) | \ 1513 (1ULL << EF10_STAT_port_rx_packets) | \ 1514 (1ULL << EF10_STAT_port_rx_good) | \ 1515 (1ULL << EF10_STAT_port_rx_bad) | \ 1516 (1ULL << EF10_STAT_port_rx_pause) | \ 1517 (1ULL << EF10_STAT_port_rx_control) | \ 1518 (1ULL << EF10_STAT_port_rx_unicast) | \ 1519 (1ULL << EF10_STAT_port_rx_multicast) | \ 1520 (1ULL << EF10_STAT_port_rx_broadcast) | \ 1521 (1ULL << EF10_STAT_port_rx_lt64) | \ 1522 (1ULL << EF10_STAT_port_rx_64) | \ 1523 (1ULL << EF10_STAT_port_rx_65_to_127) | \ 1524 (1ULL << EF10_STAT_port_rx_128_to_255) | \ 1525 (1ULL << EF10_STAT_port_rx_256_to_511) | \ 1526 (1ULL << EF10_STAT_port_rx_512_to_1023) |\ 1527 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\ 1528 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\ 1529 (1ULL << EF10_STAT_port_rx_gtjumbo) | \ 1530 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\ 1531 (1ULL << EF10_STAT_port_rx_overflow) | \ 1532 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\ 1533 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ 1534 (1ULL << GENERIC_STAT_rx_noskb_drops)) 1535 1536 /* On 7000 series NICs, these statistics are only provided by the 10G MAC. 1537 * For a 10G/40G switchable port we do not expose these because they might 1538 * not include all the packets they should. 1539 * On 8000 series NICs these statistics are always provided. 1540 */ 1541 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \ 1542 (1ULL << EF10_STAT_port_tx_lt64) | \ 1543 (1ULL << EF10_STAT_port_tx_64) | \ 1544 (1ULL << EF10_STAT_port_tx_65_to_127) |\ 1545 (1ULL << EF10_STAT_port_tx_128_to_255) |\ 1546 (1ULL << EF10_STAT_port_tx_256_to_511) |\ 1547 (1ULL << EF10_STAT_port_tx_512_to_1023) |\ 1548 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\ 1549 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo)) 1550 1551 /* These statistics are only provided by the 40G MAC. For a 10G/40G 1552 * switchable port we do expose these because the errors will otherwise 1553 * be silent. 1554 */ 1555 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\ 1556 (1ULL << EF10_STAT_port_rx_length_error)) 1557 1558 /* These statistics are only provided if the firmware supports the 1559 * capability PM_AND_RXDP_COUNTERS. 1560 */ 1561 #define HUNT_PM_AND_RXDP_STAT_MASK ( \ 1562 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \ 1563 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \ 1564 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \ 1565 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \ 1566 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \ 1567 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \ 1568 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \ 1569 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \ 1570 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \ 1571 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \ 1572 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \ 1573 (1ULL << EF10_STAT_port_rx_dp_hlb_wait)) 1574 1575 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 1576 { 1577 u64 raw_mask = HUNT_COMMON_STAT_MASK; 1578 u32 port_caps = efx_mcdi_phy_get_caps(efx); 1579 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1580 1581 if (!(efx->mcdi->fn_flags & 1582 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 1583 return 0; 1584 1585 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) { 1586 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 1587 /* 8000 series have everything even at 40G */ 1588 if (nic_data->datapath_caps2 & 1589 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN)) 1590 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1591 } else { 1592 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1593 } 1594 1595 if (nic_data->datapath_caps & 1596 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 1597 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 1598 1599 return raw_mask; 1600 } 1601 1602 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 1603 { 1604 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1605 u64 raw_mask[2]; 1606 1607 raw_mask[0] = efx_ef10_raw_stat_mask(efx); 1608 1609 /* Only show vadaptor stats when EVB capability is present */ 1610 if (nic_data->datapath_caps & 1611 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) { 1612 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1); 1613 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1; 1614 } else { 1615 raw_mask[1] = 0; 1616 } 1617 1618 #if BITS_PER_LONG == 64 1619 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2); 1620 mask[0] = raw_mask[0]; 1621 mask[1] = raw_mask[1]; 1622 #else 1623 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3); 1624 mask[0] = raw_mask[0] & 0xffffffff; 1625 mask[1] = raw_mask[0] >> 32; 1626 mask[2] = raw_mask[1] & 0xffffffff; 1627 #endif 1628 } 1629 1630 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 1631 { 1632 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1633 1634 efx_ef10_get_stat_mask(efx, mask); 1635 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1636 mask, names); 1637 } 1638 1639 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats, 1640 struct rtnl_link_stats64 *core_stats) 1641 { 1642 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1643 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1644 u64 *stats = nic_data->stats; 1645 size_t stats_count = 0, index; 1646 1647 efx_ef10_get_stat_mask(efx, mask); 1648 1649 if (full_stats) { 1650 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 1651 if (efx_ef10_stat_desc[index].name) { 1652 *full_stats++ = stats[index]; 1653 ++stats_count; 1654 } 1655 } 1656 } 1657 1658 if (!core_stats) 1659 return stats_count; 1660 1661 if (nic_data->datapath_caps & 1662 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) { 1663 /* Use vadaptor stats. */ 1664 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] + 1665 stats[EF10_STAT_rx_multicast] + 1666 stats[EF10_STAT_rx_broadcast]; 1667 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] + 1668 stats[EF10_STAT_tx_multicast] + 1669 stats[EF10_STAT_tx_broadcast]; 1670 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] + 1671 stats[EF10_STAT_rx_multicast_bytes] + 1672 stats[EF10_STAT_rx_broadcast_bytes]; 1673 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] + 1674 stats[EF10_STAT_tx_multicast_bytes] + 1675 stats[EF10_STAT_tx_broadcast_bytes]; 1676 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] + 1677 stats[GENERIC_STAT_rx_noskb_drops]; 1678 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 1679 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 1680 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 1681 core_stats->rx_errors = core_stats->rx_crc_errors; 1682 core_stats->tx_errors = stats[EF10_STAT_tx_bad]; 1683 } else { 1684 /* Use port stats. */ 1685 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets]; 1686 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets]; 1687 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes]; 1688 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes]; 1689 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] + 1690 stats[GENERIC_STAT_rx_nodesc_trunc] + 1691 stats[GENERIC_STAT_rx_noskb_drops]; 1692 core_stats->multicast = stats[EF10_STAT_port_rx_multicast]; 1693 core_stats->rx_length_errors = 1694 stats[EF10_STAT_port_rx_gtjumbo] + 1695 stats[EF10_STAT_port_rx_length_error]; 1696 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad]; 1697 core_stats->rx_frame_errors = 1698 stats[EF10_STAT_port_rx_align_error]; 1699 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow]; 1700 core_stats->rx_errors = (core_stats->rx_length_errors + 1701 core_stats->rx_crc_errors + 1702 core_stats->rx_frame_errors); 1703 } 1704 1705 return stats_count; 1706 } 1707 1708 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx) 1709 { 1710 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1711 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1712 __le64 generation_start, generation_end; 1713 u64 *stats = nic_data->stats; 1714 __le64 *dma_stats; 1715 1716 efx_ef10_get_stat_mask(efx, mask); 1717 1718 dma_stats = efx->stats_buffer.addr; 1719 1720 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; 1721 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) 1722 return 0; 1723 rmb(); 1724 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1725 stats, efx->stats_buffer.addr, false); 1726 rmb(); 1727 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1728 if (generation_end != generation_start) 1729 return -EAGAIN; 1730 1731 /* Update derived statistics */ 1732 efx_nic_fix_nodesc_drop_stat(efx, 1733 &stats[EF10_STAT_port_rx_nodesc_drops]); 1734 stats[EF10_STAT_port_rx_good_bytes] = 1735 stats[EF10_STAT_port_rx_bytes] - 1736 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]; 1737 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes], 1738 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]); 1739 efx_update_sw_stats(efx, stats); 1740 return 0; 1741 } 1742 1743 1744 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats, 1745 struct rtnl_link_stats64 *core_stats) 1746 { 1747 int retry; 1748 1749 /* If we're unlucky enough to read statistics during the DMA, wait 1750 * up to 10ms for it to finish (typically takes <500us) 1751 */ 1752 for (retry = 0; retry < 100; ++retry) { 1753 if (efx_ef10_try_update_nic_stats_pf(efx) == 0) 1754 break; 1755 udelay(100); 1756 } 1757 1758 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1759 } 1760 1761 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx) 1762 { 1763 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN); 1764 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1765 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1766 __le64 generation_start, generation_end; 1767 u64 *stats = nic_data->stats; 1768 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64); 1769 struct efx_buffer stats_buf; 1770 __le64 *dma_stats; 1771 int rc; 1772 1773 spin_unlock_bh(&efx->stats_lock); 1774 1775 if (in_interrupt()) { 1776 /* If in atomic context, cannot update stats. Just update the 1777 * software stats and return so the caller can continue. 1778 */ 1779 spin_lock_bh(&efx->stats_lock); 1780 efx_update_sw_stats(efx, stats); 1781 return 0; 1782 } 1783 1784 efx_ef10_get_stat_mask(efx, mask); 1785 1786 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC); 1787 if (rc) { 1788 spin_lock_bh(&efx->stats_lock); 1789 return rc; 1790 } 1791 1792 dma_stats = stats_buf.addr; 1793 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID; 1794 1795 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr); 1796 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD, 1797 MAC_STATS_IN_DMA, 1); 1798 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len); 1799 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1800 1801 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf), 1802 NULL, 0, NULL); 1803 spin_lock_bh(&efx->stats_lock); 1804 if (rc) { 1805 /* Expect ENOENT if DMA queues have not been set up */ 1806 if (rc != -ENOENT || atomic_read(&efx->active_queues)) 1807 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS, 1808 sizeof(inbuf), NULL, 0, rc); 1809 goto out; 1810 } 1811 1812 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; 1813 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) { 1814 WARN_ON_ONCE(1); 1815 goto out; 1816 } 1817 rmb(); 1818 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1819 stats, stats_buf.addr, false); 1820 rmb(); 1821 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1822 if (generation_end != generation_start) { 1823 rc = -EAGAIN; 1824 goto out; 1825 } 1826 1827 efx_update_sw_stats(efx, stats); 1828 out: 1829 efx_nic_free_buffer(efx, &stats_buf); 1830 return rc; 1831 } 1832 1833 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats, 1834 struct rtnl_link_stats64 *core_stats) 1835 { 1836 if (efx_ef10_try_update_nic_stats_vf(efx)) 1837 return 0; 1838 1839 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1840 } 1841 1842 static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1843 { 1844 struct efx_nic *efx = channel->efx; 1845 unsigned int mode, usecs; 1846 efx_dword_t timer_cmd; 1847 1848 if (channel->irq_moderation_us) { 1849 mode = 3; 1850 usecs = channel->irq_moderation_us; 1851 } else { 1852 mode = 0; 1853 usecs = 0; 1854 } 1855 1856 if (EFX_EF10_WORKAROUND_61265(efx)) { 1857 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN); 1858 unsigned int ns = usecs * 1000; 1859 1860 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE, 1861 channel->channel); 1862 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns); 1863 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns); 1864 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode); 1865 1866 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR, 1867 inbuf, sizeof(inbuf), 0, NULL, 0); 1868 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 1869 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 1870 1871 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 1872 EFE_DD_EVQ_IND_TIMER_FLAGS, 1873 ERF_DD_EVQ_IND_TIMER_MODE, mode, 1874 ERF_DD_EVQ_IND_TIMER_VAL, ticks); 1875 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 1876 channel->channel); 1877 } else { 1878 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 1879 1880 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 1881 ERF_DZ_TC_TIMER_VAL, ticks); 1882 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 1883 channel->channel); 1884 } 1885 } 1886 1887 static void efx_ef10_get_wol_vf(struct efx_nic *efx, 1888 struct ethtool_wolinfo *wol) {} 1889 1890 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type) 1891 { 1892 return -EOPNOTSUPP; 1893 } 1894 1895 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 1896 { 1897 wol->supported = 0; 1898 wol->wolopts = 0; 1899 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1900 } 1901 1902 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 1903 { 1904 if (type != 0) 1905 return -EINVAL; 1906 return 0; 1907 } 1908 1909 static void efx_ef10_mcdi_request(struct efx_nic *efx, 1910 const efx_dword_t *hdr, size_t hdr_len, 1911 const efx_dword_t *sdu, size_t sdu_len) 1912 { 1913 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1914 u8 *pdu = nic_data->mcdi_buf.addr; 1915 1916 memcpy(pdu, hdr, hdr_len); 1917 memcpy(pdu + hdr_len, sdu, sdu_len); 1918 wmb(); 1919 1920 /* The hardware provides 'low' and 'high' (doorbell) registers 1921 * for passing the 64-bit address of an MCDI request to 1922 * firmware. However the dwords are swapped by firmware. The 1923 * least significant bits of the doorbell are then 0 for all 1924 * MCDI requests due to alignment. 1925 */ 1926 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 1927 ER_DZ_MC_DB_LWRD); 1928 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 1929 ER_DZ_MC_DB_HWRD); 1930 } 1931 1932 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 1933 { 1934 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1935 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 1936 1937 rmb(); 1938 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 1939 } 1940 1941 static void 1942 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 1943 size_t offset, size_t outlen) 1944 { 1945 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1946 const u8 *pdu = nic_data->mcdi_buf.addr; 1947 1948 memcpy(outbuf, pdu + offset, outlen); 1949 } 1950 1951 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx) 1952 { 1953 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1954 1955 /* All our allocations have been reset */ 1956 efx_ef10_reset_mc_allocations(efx); 1957 1958 /* The datapath firmware might have been changed */ 1959 nic_data->must_check_datapath_caps = true; 1960 1961 /* MAC statistics have been cleared on the NIC; clear the local 1962 * statistic that we update with efx_update_diff_stat(). 1963 */ 1964 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0; 1965 } 1966 1967 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 1968 { 1969 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1970 int rc; 1971 1972 rc = efx_ef10_get_warm_boot_count(efx); 1973 if (rc < 0) { 1974 /* The firmware is presumably in the process of 1975 * rebooting. However, we are supposed to report each 1976 * reboot just once, so we must only do that once we 1977 * can read and store the updated warm boot count. 1978 */ 1979 return 0; 1980 } 1981 1982 if (rc == nic_data->warm_boot_count) 1983 return 0; 1984 1985 nic_data->warm_boot_count = rc; 1986 efx_ef10_mcdi_reboot_detected(efx); 1987 1988 return -EIO; 1989 } 1990 1991 /* Handle an MSI interrupt 1992 * 1993 * Handle an MSI hardware interrupt. This routine schedules event 1994 * queue processing. No interrupt acknowledgement cycle is necessary. 1995 * Also, we never need to check that the interrupt is for us, since 1996 * MSI interrupts cannot be shared. 1997 */ 1998 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 1999 { 2000 struct efx_msi_context *context = dev_id; 2001 struct efx_nic *efx = context->efx; 2002 2003 netif_vdbg(efx, intr, efx->net_dev, 2004 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 2005 2006 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) { 2007 /* Note test interrupts */ 2008 if (context->index == efx->irq_level) 2009 efx->last_irq_cpu = raw_smp_processor_id(); 2010 2011 /* Schedule processing of the channel */ 2012 efx_schedule_channel_irq(efx->channel[context->index]); 2013 } 2014 2015 return IRQ_HANDLED; 2016 } 2017 2018 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 2019 { 2020 struct efx_nic *efx = dev_id; 2021 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled); 2022 struct efx_channel *channel; 2023 efx_dword_t reg; 2024 u32 queues; 2025 2026 /* Read the ISR which also ACKs the interrupts */ 2027 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 2028 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 2029 2030 if (queues == 0) 2031 return IRQ_NONE; 2032 2033 if (likely(soft_enabled)) { 2034 /* Note test interrupts */ 2035 if (queues & (1U << efx->irq_level)) 2036 efx->last_irq_cpu = raw_smp_processor_id(); 2037 2038 efx_for_each_channel(channel, efx) { 2039 if (queues & 1) 2040 efx_schedule_channel_irq(channel); 2041 queues >>= 1; 2042 } 2043 } 2044 2045 netif_vdbg(efx, intr, efx->net_dev, 2046 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 2047 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 2048 2049 return IRQ_HANDLED; 2050 } 2051 2052 static int efx_ef10_irq_test_generate(struct efx_nic *efx) 2053 { 2054 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 2055 2056 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true, 2057 NULL) == 0) 2058 return -ENOTSUPP; 2059 2060 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 2061 2062 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 2063 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 2064 inbuf, sizeof(inbuf), NULL, 0, NULL); 2065 } 2066 2067 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 2068 { 2069 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 2070 (tx_queue->ptr_mask + 1) * 2071 sizeof(efx_qword_t), 2072 GFP_KERNEL); 2073 } 2074 2075 /* This writes to the TX_DESC_WPTR and also pushes data */ 2076 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 2077 const efx_qword_t *txd) 2078 { 2079 unsigned int write_ptr; 2080 efx_oword_t reg; 2081 2082 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2083 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 2084 reg.qword[0] = *txd; 2085 efx_writeo_page(tx_queue->efx, ®, 2086 ER_DZ_TX_DESC_UPD, tx_queue->queue); 2087 } 2088 2089 /* Add Firmware-Assisted TSO v2 option descriptors to a queue. 2090 */ 2091 static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, 2092 struct sk_buff *skb, 2093 bool *data_mapped) 2094 { 2095 struct efx_tx_buffer *buffer; 2096 struct tcphdr *tcp; 2097 struct iphdr *ip; 2098 2099 u16 ipv4_id; 2100 u32 seqnum; 2101 u32 mss; 2102 2103 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2); 2104 2105 mss = skb_shinfo(skb)->gso_size; 2106 2107 if (unlikely(mss < 4)) { 2108 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss); 2109 return -EINVAL; 2110 } 2111 2112 ip = ip_hdr(skb); 2113 if (ip->version == 4) { 2114 /* Modify IPv4 header if needed. */ 2115 ip->tot_len = 0; 2116 ip->check = 0; 2117 ipv4_id = ip->id; 2118 } else { 2119 /* Modify IPv6 header if needed. */ 2120 struct ipv6hdr *ipv6 = ipv6_hdr(skb); 2121 2122 ipv6->payload_len = 0; 2123 ipv4_id = 0; 2124 } 2125 2126 tcp = tcp_hdr(skb); 2127 seqnum = ntohl(tcp->seq); 2128 2129 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2130 2131 buffer->flags = EFX_TX_BUF_OPTION; 2132 buffer->len = 0; 2133 buffer->unmap_len = 0; 2134 EFX_POPULATE_QWORD_5(buffer->option, 2135 ESF_DZ_TX_DESC_IS_OPT, 1, 2136 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2137 ESF_DZ_TX_TSO_OPTION_TYPE, 2138 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A, 2139 ESF_DZ_TX_TSO_IP_ID, ipv4_id, 2140 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum 2141 ); 2142 ++tx_queue->insert_count; 2143 2144 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2145 2146 buffer->flags = EFX_TX_BUF_OPTION; 2147 buffer->len = 0; 2148 buffer->unmap_len = 0; 2149 EFX_POPULATE_QWORD_4(buffer->option, 2150 ESF_DZ_TX_DESC_IS_OPT, 1, 2151 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2152 ESF_DZ_TX_TSO_OPTION_TYPE, 2153 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B, 2154 ESF_DZ_TX_TSO_TCP_MSS, mss 2155 ); 2156 ++tx_queue->insert_count; 2157 2158 return 0; 2159 } 2160 2161 static u32 efx_ef10_tso_versions(struct efx_nic *efx) 2162 { 2163 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2164 u32 tso_versions = 0; 2165 2166 if (nic_data->datapath_caps & 2167 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) 2168 tso_versions |= BIT(1); 2169 if (nic_data->datapath_caps2 & 2170 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) 2171 tso_versions |= BIT(2); 2172 return tso_versions; 2173 } 2174 2175 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 2176 { 2177 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 2178 EFX_BUF_SIZE)); 2179 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; 2180 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE; 2181 struct efx_channel *channel = tx_queue->channel; 2182 struct efx_nic *efx = tx_queue->efx; 2183 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2184 bool tso_v2 = false; 2185 size_t inlen; 2186 dma_addr_t dma_addr; 2187 efx_qword_t *txd; 2188 int rc; 2189 int i; 2190 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0); 2191 2192 /* TSOv2 is a limited resource that can only be configured on a limited 2193 * number of queues. TSO without checksum offload is not really a thing, 2194 * so we only enable it for those queues. 2195 */ 2196 if (csum_offload && (nic_data->datapath_caps2 & 2197 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))) { 2198 tso_v2 = true; 2199 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n", 2200 channel->channel); 2201 } 2202 2203 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1); 2204 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel); 2205 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue); 2206 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue); 2207 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0); 2208 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id); 2209 2210 dma_addr = tx_queue->txd.buf.dma_addr; 2211 2212 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n", 2213 tx_queue->queue, entries, (u64)dma_addr); 2214 2215 for (i = 0; i < entries; ++i) { 2216 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr); 2217 dma_addr += EFX_BUF_SIZE; 2218 } 2219 2220 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries); 2221 2222 do { 2223 MCDI_POPULATE_DWORD_3(inbuf, INIT_TXQ_IN_FLAGS, 2224 /* This flag was removed from mcdi_pcol.h for 2225 * the non-_EXT version of INIT_TXQ. However, 2226 * firmware still honours it. 2227 */ 2228 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2, 2229 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload, 2230 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload); 2231 2232 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen, 2233 NULL, 0, NULL); 2234 if (rc == -ENOSPC && tso_v2) { 2235 /* Retry without TSOv2 if we're short on contexts. */ 2236 tso_v2 = false; 2237 netif_warn(efx, probe, efx->net_dev, 2238 "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n"); 2239 } else if (rc) { 2240 efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ, 2241 MC_CMD_INIT_TXQ_EXT_IN_LEN, 2242 NULL, 0, rc); 2243 goto fail; 2244 } 2245 } while (rc); 2246 2247 /* A previous user of this TX queue might have set us up the 2248 * bomb by writing a descriptor to the TX push collector but 2249 * not the doorbell. (Each collector belongs to a port, not a 2250 * queue or function, so cannot easily be reset.) We must 2251 * attempt to push a no-op descriptor in its place. 2252 */ 2253 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 2254 tx_queue->insert_count = 1; 2255 txd = efx_tx_desc(tx_queue, 0); 2256 EFX_POPULATE_QWORD_4(*txd, 2257 ESF_DZ_TX_DESC_IS_OPT, true, 2258 ESF_DZ_TX_OPTION_TYPE, 2259 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 2260 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 2261 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload); 2262 tx_queue->write_count = 1; 2263 2264 if (tso_v2) { 2265 tx_queue->handle_tso = efx_ef10_tx_tso_desc; 2266 tx_queue->tso_version = 2; 2267 } else if (nic_data->datapath_caps & 2268 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) { 2269 tx_queue->tso_version = 1; 2270 } 2271 2272 wmb(); 2273 efx_ef10_push_tx_desc(tx_queue, txd); 2274 2275 return; 2276 2277 fail: 2278 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 2279 tx_queue->queue); 2280 } 2281 2282 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue) 2283 { 2284 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN); 2285 MCDI_DECLARE_BUF_ERR(outbuf); 2286 struct efx_nic *efx = tx_queue->efx; 2287 size_t outlen; 2288 int rc; 2289 2290 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE, 2291 tx_queue->queue); 2292 2293 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf), 2294 outbuf, sizeof(outbuf), &outlen); 2295 2296 if (rc && rc != -EALREADY) 2297 goto fail; 2298 2299 return; 2300 2301 fail: 2302 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN, 2303 outbuf, outlen, rc); 2304 } 2305 2306 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue) 2307 { 2308 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf); 2309 } 2310 2311 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 2312 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 2313 { 2314 unsigned int write_ptr; 2315 efx_dword_t reg; 2316 2317 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2318 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 2319 efx_writed_page(tx_queue->efx, ®, 2320 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 2321 } 2322 2323 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff 2324 2325 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue, 2326 dma_addr_t dma_addr, unsigned int len) 2327 { 2328 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) { 2329 /* If we need to break across multiple descriptors we should 2330 * stop at a page boundary. This assumes the length limit is 2331 * greater than the page size. 2332 */ 2333 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN; 2334 2335 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE); 2336 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr; 2337 } 2338 2339 return len; 2340 } 2341 2342 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 2343 { 2344 unsigned int old_write_count = tx_queue->write_count; 2345 struct efx_tx_buffer *buffer; 2346 unsigned int write_ptr; 2347 efx_qword_t *txd; 2348 2349 tx_queue->xmit_more_available = false; 2350 if (unlikely(tx_queue->write_count == tx_queue->insert_count)) 2351 return; 2352 2353 do { 2354 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2355 buffer = &tx_queue->buffer[write_ptr]; 2356 txd = efx_tx_desc(tx_queue, write_ptr); 2357 ++tx_queue->write_count; 2358 2359 /* Create TX descriptor ring entry */ 2360 if (buffer->flags & EFX_TX_BUF_OPTION) { 2361 *txd = buffer->option; 2362 } else { 2363 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 2364 EFX_POPULATE_QWORD_3( 2365 *txd, 2366 ESF_DZ_TX_KER_CONT, 2367 buffer->flags & EFX_TX_BUF_CONT, 2368 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 2369 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 2370 } 2371 } while (tx_queue->write_count != tx_queue->insert_count); 2372 2373 wmb(); /* Ensure descriptors are written before they are fetched */ 2374 2375 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 2376 txd = efx_tx_desc(tx_queue, 2377 old_write_count & tx_queue->ptr_mask); 2378 efx_ef10_push_tx_desc(tx_queue, txd); 2379 ++tx_queue->pushes; 2380 } else { 2381 efx_ef10_notify_tx_desc(tx_queue); 2382 } 2383 } 2384 2385 #define RSS_MODE_HASH_ADDRS (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\ 2386 1 << RSS_MODE_HASH_DST_ADDR_LBN) 2387 #define RSS_MODE_HASH_PORTS (1 << RSS_MODE_HASH_SRC_PORT_LBN |\ 2388 1 << RSS_MODE_HASH_DST_PORT_LBN) 2389 #define RSS_CONTEXT_FLAGS_DEFAULT (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\ 2390 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\ 2391 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\ 2392 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\ 2393 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\ 2394 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\ 2395 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\ 2396 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\ 2397 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\ 2398 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN) 2399 2400 static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags) 2401 { 2402 /* Firmware had a bug (sfc bug 61952) where it would not actually 2403 * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS. 2404 * This meant that it would always contain whatever was previously 2405 * in the MCDI buffer. Fortunately, all firmware versions with 2406 * this bug have the same default flags value for a newly-allocated 2407 * RSS context, and the only time we want to get the flags is just 2408 * after allocating. Moreover, the response has a 32-bit hole 2409 * where the context ID would be in the request, so we can use an 2410 * overlength buffer in the request and pre-fill the flags field 2411 * with what we believe the default to be. Thus if the firmware 2412 * has the bug, it will leave our pre-filled value in the flags 2413 * field of the response, and we will get the right answer. 2414 * 2415 * However, this does mean that this function should NOT be used if 2416 * the RSS context flags might not be their defaults - it is ONLY 2417 * reliably correct for a newly-allocated RSS context. 2418 */ 2419 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN); 2420 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN); 2421 size_t outlen; 2422 int rc; 2423 2424 /* Check we have a hole for the context ID */ 2425 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST); 2426 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context); 2427 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS, 2428 RSS_CONTEXT_FLAGS_DEFAULT); 2429 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf, 2430 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 2431 if (rc == 0) { 2432 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN) 2433 rc = -EIO; 2434 else 2435 *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS); 2436 } 2437 return rc; 2438 } 2439 2440 /* Attempt to enable 4-tuple UDP hashing on the specified RSS context. 2441 * If we fail, we just leave the RSS context at its default hash settings, 2442 * which is safe but may slightly reduce performance. 2443 * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we 2444 * just need to set the UDP ports flags (for both IP versions). 2445 */ 2446 static void efx_ef10_set_rss_flags(struct efx_nic *efx, u32 context) 2447 { 2448 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN); 2449 u32 flags; 2450 2451 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0); 2452 2453 if (efx_ef10_get_rss_flags(efx, context, &flags) != 0) 2454 return; 2455 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, context); 2456 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN; 2457 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN; 2458 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags); 2459 if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf), 2460 NULL, 0, NULL)) 2461 /* Succeeded, so UDP 4-tuple is now enabled */ 2462 efx->rx_hash_udp_4tuple = true; 2463 } 2464 2465 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context, 2466 bool exclusive, unsigned *context_size) 2467 { 2468 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN); 2469 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN); 2470 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2471 size_t outlen; 2472 int rc; 2473 u32 alloc_type = exclusive ? 2474 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE : 2475 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED; 2476 unsigned rss_spread = exclusive ? 2477 efx->rss_spread : 2478 min(rounddown_pow_of_two(efx->rss_spread), 2479 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE); 2480 2481 if (!exclusive && rss_spread == 1) { 2482 *context = EFX_EF10_RSS_CONTEXT_INVALID; 2483 if (context_size) 2484 *context_size = 1; 2485 return 0; 2486 } 2487 2488 if (nic_data->datapath_caps & 2489 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN) 2490 return -EOPNOTSUPP; 2491 2492 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID, 2493 nic_data->vport_id); 2494 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type); 2495 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread); 2496 2497 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf), 2498 outbuf, sizeof(outbuf), &outlen); 2499 if (rc != 0) 2500 return rc; 2501 2502 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) 2503 return -EIO; 2504 2505 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID); 2506 2507 if (context_size) 2508 *context_size = rss_spread; 2509 2510 if (nic_data->datapath_caps & 2511 1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN) 2512 efx_ef10_set_rss_flags(efx, *context); 2513 2514 return 0; 2515 } 2516 2517 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context) 2518 { 2519 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN); 2520 int rc; 2521 2522 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, 2523 context); 2524 2525 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf), 2526 NULL, 0, NULL); 2527 WARN_ON(rc != 0); 2528 } 2529 2530 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context, 2531 const u32 *rx_indir_table) 2532 { 2533 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN); 2534 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN); 2535 int i, rc; 2536 2537 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID, 2538 context); 2539 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) != 2540 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN); 2541 2542 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i) 2543 MCDI_PTR(tablebuf, 2544 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] = 2545 (u8) rx_indir_table[i]; 2546 2547 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf, 2548 sizeof(tablebuf), NULL, 0, NULL); 2549 if (rc != 0) 2550 return rc; 2551 2552 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID, 2553 context); 2554 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) != 2555 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN); 2556 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i) 2557 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = 2558 efx->rx_hash_key[i]; 2559 2560 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf, 2561 sizeof(keybuf), NULL, 0, NULL); 2562 } 2563 2564 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx) 2565 { 2566 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2567 2568 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) 2569 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context); 2570 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 2571 } 2572 2573 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx, 2574 unsigned *context_size) 2575 { 2576 u32 new_rx_rss_context; 2577 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2578 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context, 2579 false, context_size); 2580 2581 if (rc != 0) 2582 return rc; 2583 2584 nic_data->rx_rss_context = new_rx_rss_context; 2585 nic_data->rx_rss_context_exclusive = false; 2586 efx_set_default_rx_indir_table(efx); 2587 return 0; 2588 } 2589 2590 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx, 2591 const u32 *rx_indir_table) 2592 { 2593 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2594 int rc; 2595 u32 new_rx_rss_context; 2596 2597 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID || 2598 !nic_data->rx_rss_context_exclusive) { 2599 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context, 2600 true, NULL); 2601 if (rc == -EOPNOTSUPP) 2602 return rc; 2603 else if (rc != 0) 2604 goto fail1; 2605 } else { 2606 new_rx_rss_context = nic_data->rx_rss_context; 2607 } 2608 2609 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context, 2610 rx_indir_table); 2611 if (rc != 0) 2612 goto fail2; 2613 2614 if (nic_data->rx_rss_context != new_rx_rss_context) 2615 efx_ef10_rx_free_indir_table(efx); 2616 nic_data->rx_rss_context = new_rx_rss_context; 2617 nic_data->rx_rss_context_exclusive = true; 2618 if (rx_indir_table != efx->rx_indir_table) 2619 memcpy(efx->rx_indir_table, rx_indir_table, 2620 sizeof(efx->rx_indir_table)); 2621 return 0; 2622 2623 fail2: 2624 if (new_rx_rss_context != nic_data->rx_rss_context) 2625 efx_ef10_free_rss_context(efx, new_rx_rss_context); 2626 fail1: 2627 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 2628 return rc; 2629 } 2630 2631 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user, 2632 const u32 *rx_indir_table) 2633 { 2634 int rc; 2635 2636 if (efx->rss_spread == 1) 2637 return 0; 2638 2639 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table); 2640 2641 if (rc == -ENOBUFS && !user) { 2642 unsigned context_size; 2643 bool mismatch = false; 2644 size_t i; 2645 2646 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch; 2647 i++) 2648 mismatch = rx_indir_table[i] != 2649 ethtool_rxfh_indir_default(i, efx->rss_spread); 2650 2651 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size); 2652 if (rc == 0) { 2653 if (context_size != efx->rss_spread) 2654 netif_warn(efx, probe, efx->net_dev, 2655 "Could not allocate an exclusive RSS" 2656 " context; allocated a shared one of" 2657 " different size." 2658 " Wanted %u, got %u.\n", 2659 efx->rss_spread, context_size); 2660 else if (mismatch) 2661 netif_warn(efx, probe, efx->net_dev, 2662 "Could not allocate an exclusive RSS" 2663 " context; allocated a shared one but" 2664 " could not apply custom" 2665 " indirection.\n"); 2666 else 2667 netif_info(efx, probe, efx->net_dev, 2668 "Could not allocate an exclusive RSS" 2669 " context; allocated a shared one.\n"); 2670 } 2671 } 2672 return rc; 2673 } 2674 2675 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user, 2676 const u32 *rx_indir_table 2677 __attribute__ ((unused))) 2678 { 2679 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2680 2681 if (user) 2682 return -EOPNOTSUPP; 2683 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) 2684 return 0; 2685 return efx_ef10_rx_push_shared_rss_config(efx, NULL); 2686 } 2687 2688 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue) 2689 { 2690 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf, 2691 (rx_queue->ptr_mask + 1) * 2692 sizeof(efx_qword_t), 2693 GFP_KERNEL); 2694 } 2695 2696 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue) 2697 { 2698 MCDI_DECLARE_BUF(inbuf, 2699 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 2700 EFX_BUF_SIZE)); 2701 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2702 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE; 2703 struct efx_nic *efx = rx_queue->efx; 2704 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2705 size_t inlen; 2706 dma_addr_t dma_addr; 2707 int rc; 2708 int i; 2709 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0); 2710 2711 rx_queue->scatter_n = 0; 2712 rx_queue->scatter_len = 0; 2713 2714 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1); 2715 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel); 2716 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue)); 2717 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE, 2718 efx_rx_queue_index(rx_queue)); 2719 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS, 2720 INIT_RXQ_IN_FLAG_PREFIX, 1, 2721 INIT_RXQ_IN_FLAG_TIMESTAMP, 1); 2722 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0); 2723 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id); 2724 2725 dma_addr = rx_queue->rxd.buf.dma_addr; 2726 2727 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n", 2728 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr); 2729 2730 for (i = 0; i < entries; ++i) { 2731 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr); 2732 dma_addr += EFX_BUF_SIZE; 2733 } 2734 2735 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries); 2736 2737 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen, 2738 NULL, 0, NULL); 2739 if (rc) 2740 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n", 2741 efx_rx_queue_index(rx_queue)); 2742 } 2743 2744 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue) 2745 { 2746 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN); 2747 MCDI_DECLARE_BUF_ERR(outbuf); 2748 struct efx_nic *efx = rx_queue->efx; 2749 size_t outlen; 2750 int rc; 2751 2752 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE, 2753 efx_rx_queue_index(rx_queue)); 2754 2755 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf), 2756 outbuf, sizeof(outbuf), &outlen); 2757 2758 if (rc && rc != -EALREADY) 2759 goto fail; 2760 2761 return; 2762 2763 fail: 2764 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN, 2765 outbuf, outlen, rc); 2766 } 2767 2768 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue) 2769 { 2770 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf); 2771 } 2772 2773 /* This creates an entry in the RX descriptor queue */ 2774 static inline void 2775 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 2776 { 2777 struct efx_rx_buffer *rx_buf; 2778 efx_qword_t *rxd; 2779 2780 rxd = efx_rx_desc(rx_queue, index); 2781 rx_buf = efx_rx_buffer(rx_queue, index); 2782 EFX_POPULATE_QWORD_2(*rxd, 2783 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 2784 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 2785 } 2786 2787 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 2788 { 2789 struct efx_nic *efx = rx_queue->efx; 2790 unsigned int write_count; 2791 efx_dword_t reg; 2792 2793 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 2794 write_count = rx_queue->added_count & ~7; 2795 if (rx_queue->notified_count == write_count) 2796 return; 2797 2798 do 2799 efx_ef10_build_rx_desc( 2800 rx_queue, 2801 rx_queue->notified_count & rx_queue->ptr_mask); 2802 while (++rx_queue->notified_count != write_count); 2803 2804 wmb(); 2805 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 2806 write_count & rx_queue->ptr_mask); 2807 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 2808 efx_rx_queue_index(rx_queue)); 2809 } 2810 2811 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 2812 2813 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 2814 { 2815 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2816 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2817 efx_qword_t event; 2818 2819 EFX_POPULATE_QWORD_2(event, 2820 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2821 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 2822 2823 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2824 2825 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2826 * already swapped the data to little-endian order. 2827 */ 2828 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2829 sizeof(efx_qword_t)); 2830 2831 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 2832 inbuf, sizeof(inbuf), 0, 2833 efx_ef10_rx_defer_refill_complete, 0); 2834 } 2835 2836 static void 2837 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 2838 int rc, efx_dword_t *outbuf, 2839 size_t outlen_actual) 2840 { 2841 /* nothing to do */ 2842 } 2843 2844 static int efx_ef10_ev_probe(struct efx_channel *channel) 2845 { 2846 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, 2847 (channel->eventq_mask + 1) * 2848 sizeof(efx_qword_t), 2849 GFP_KERNEL); 2850 } 2851 2852 static void efx_ef10_ev_fini(struct efx_channel *channel) 2853 { 2854 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN); 2855 MCDI_DECLARE_BUF_ERR(outbuf); 2856 struct efx_nic *efx = channel->efx; 2857 size_t outlen; 2858 int rc; 2859 2860 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel); 2861 2862 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf), 2863 outbuf, sizeof(outbuf), &outlen); 2864 2865 if (rc && rc != -EALREADY) 2866 goto fail; 2867 2868 return; 2869 2870 fail: 2871 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN, 2872 outbuf, outlen, rc); 2873 } 2874 2875 static int efx_ef10_ev_init(struct efx_channel *channel) 2876 { 2877 MCDI_DECLARE_BUF(inbuf, 2878 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 / 2879 EFX_BUF_SIZE)); 2880 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN); 2881 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE; 2882 struct efx_nic *efx = channel->efx; 2883 struct efx_ef10_nic_data *nic_data; 2884 size_t inlen, outlen; 2885 unsigned int enabled, implemented; 2886 dma_addr_t dma_addr; 2887 int rc; 2888 int i; 2889 2890 nic_data = efx->nic_data; 2891 2892 /* Fill event queue with all ones (i.e. empty events) */ 2893 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len); 2894 2895 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1); 2896 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel); 2897 /* INIT_EVQ expects index in vector table, not absolute */ 2898 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel); 2899 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE, 2900 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS); 2901 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0); 2902 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0); 2903 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE, 2904 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS); 2905 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0); 2906 2907 if (nic_data->datapath_caps2 & 2908 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) { 2909 /* Use the new generic approach to specifying event queue 2910 * configuration, requesting lower latency or higher throughput. 2911 * The options that actually get used appear in the output. 2912 */ 2913 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS, 2914 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1, 2915 INIT_EVQ_V2_IN_FLAG_TYPE, 2916 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO); 2917 } else { 2918 bool cut_thru = !(nic_data->datapath_caps & 2919 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 2920 2921 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS, 2922 INIT_EVQ_IN_FLAG_INTERRUPTING, 1, 2923 INIT_EVQ_IN_FLAG_RX_MERGE, 1, 2924 INIT_EVQ_IN_FLAG_TX_MERGE, 1, 2925 INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru); 2926 } 2927 2928 dma_addr = channel->eventq.buf.dma_addr; 2929 for (i = 0; i < entries; ++i) { 2930 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr); 2931 dma_addr += EFX_BUF_SIZE; 2932 } 2933 2934 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries); 2935 2936 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen, 2937 outbuf, sizeof(outbuf), &outlen); 2938 2939 if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN) 2940 netif_dbg(efx, drv, efx->net_dev, 2941 "Channel %d using event queue flags %08x\n", 2942 channel->channel, 2943 MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS)); 2944 2945 /* IRQ return is ignored */ 2946 if (channel->channel || rc) 2947 return rc; 2948 2949 /* Successfully created event queue on channel 0 */ 2950 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 2951 if (rc == -ENOSYS) { 2952 /* GET_WORKAROUNDS was implemented before this workaround, 2953 * thus it must be unavailable in this firmware. 2954 */ 2955 nic_data->workaround_26807 = false; 2956 rc = 0; 2957 } else if (rc) { 2958 goto fail; 2959 } else { 2960 nic_data->workaround_26807 = 2961 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807); 2962 2963 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 && 2964 !nic_data->workaround_26807) { 2965 unsigned int flags; 2966 2967 rc = efx_mcdi_set_workaround(efx, 2968 MC_CMD_WORKAROUND_BUG26807, 2969 true, &flags); 2970 2971 if (!rc) { 2972 if (flags & 2973 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) { 2974 netif_info(efx, drv, efx->net_dev, 2975 "other functions on NIC have been reset\n"); 2976 2977 /* With MCFW v4.6.x and earlier, the 2978 * boot count will have incremented, 2979 * so re-read the warm_boot_count 2980 * value now to ensure this function 2981 * doesn't think it has changed next 2982 * time it checks. 2983 */ 2984 rc = efx_ef10_get_warm_boot_count(efx); 2985 if (rc >= 0) { 2986 nic_data->warm_boot_count = rc; 2987 rc = 0; 2988 } 2989 } 2990 nic_data->workaround_26807 = true; 2991 } else if (rc == -EPERM) { 2992 rc = 0; 2993 } 2994 } 2995 } 2996 2997 if (!rc) 2998 return 0; 2999 3000 fail: 3001 efx_ef10_ev_fini(channel); 3002 return rc; 3003 } 3004 3005 static void efx_ef10_ev_remove(struct efx_channel *channel) 3006 { 3007 efx_nic_free_buffer(channel->efx, &channel->eventq.buf); 3008 } 3009 3010 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 3011 unsigned int rx_queue_label) 3012 { 3013 struct efx_nic *efx = rx_queue->efx; 3014 3015 netif_info(efx, hw, efx->net_dev, 3016 "rx event arrived on queue %d labeled as queue %u\n", 3017 efx_rx_queue_index(rx_queue), rx_queue_label); 3018 3019 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 3020 } 3021 3022 static void 3023 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 3024 unsigned int actual, unsigned int expected) 3025 { 3026 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 3027 struct efx_nic *efx = rx_queue->efx; 3028 3029 netif_info(efx, hw, efx->net_dev, 3030 "dropped %d events (index=%d expected=%d)\n", 3031 dropped, actual, expected); 3032 3033 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 3034 } 3035 3036 /* partially received RX was aborted. clean up. */ 3037 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 3038 { 3039 unsigned int rx_desc_ptr; 3040 3041 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 3042 "scattered RX aborted (dropping %u buffers)\n", 3043 rx_queue->scatter_n); 3044 3045 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 3046 3047 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 3048 0, EFX_RX_PKT_DISCARD); 3049 3050 rx_queue->removed_count += rx_queue->scatter_n; 3051 rx_queue->scatter_n = 0; 3052 rx_queue->scatter_len = 0; 3053 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 3054 } 3055 3056 static int efx_ef10_handle_rx_event(struct efx_channel *channel, 3057 const efx_qword_t *event) 3058 { 3059 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class; 3060 unsigned int n_descs, n_packets, i; 3061 struct efx_nic *efx = channel->efx; 3062 struct efx_rx_queue *rx_queue; 3063 bool rx_cont; 3064 u16 flags = 0; 3065 3066 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 3067 return 0; 3068 3069 /* Basic packet information */ 3070 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 3071 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 3072 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 3073 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS); 3074 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 3075 3076 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 3077 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 3078 EFX_QWORD_FMT "\n", 3079 EFX_QWORD_VAL(*event)); 3080 3081 rx_queue = efx_channel_get_rx_queue(channel); 3082 3083 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 3084 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 3085 3086 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 3087 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 3088 3089 if (n_descs != rx_queue->scatter_n + 1) { 3090 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3091 3092 /* detect rx abort */ 3093 if (unlikely(n_descs == rx_queue->scatter_n)) { 3094 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 3095 netdev_WARN(efx->net_dev, 3096 "invalid RX abort: scatter_n=%u event=" 3097 EFX_QWORD_FMT "\n", 3098 rx_queue->scatter_n, 3099 EFX_QWORD_VAL(*event)); 3100 efx_ef10_handle_rx_abort(rx_queue); 3101 return 0; 3102 } 3103 3104 /* Check that RX completion merging is valid, i.e. 3105 * the current firmware supports it and this is a 3106 * non-scattered packet. 3107 */ 3108 if (!(nic_data->datapath_caps & 3109 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 3110 rx_queue->scatter_n != 0 || rx_cont) { 3111 efx_ef10_handle_rx_bad_lbits( 3112 rx_queue, next_ptr_lbits, 3113 (rx_queue->removed_count + 3114 rx_queue->scatter_n + 1) & 3115 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 3116 return 0; 3117 } 3118 3119 /* Merged completion for multiple non-scattered packets */ 3120 rx_queue->scatter_n = 1; 3121 rx_queue->scatter_len = 0; 3122 n_packets = n_descs; 3123 ++channel->n_rx_merge_events; 3124 channel->n_rx_merge_packets += n_packets; 3125 flags |= EFX_RX_PKT_PREFIX_LEN; 3126 } else { 3127 ++rx_queue->scatter_n; 3128 rx_queue->scatter_len += rx_bytes; 3129 if (rx_cont) 3130 return 0; 3131 n_packets = 1; 3132 } 3133 3134 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR))) 3135 flags |= EFX_RX_PKT_DISCARD; 3136 3137 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) { 3138 channel->n_rx_ip_hdr_chksum_err += n_packets; 3139 } else if (unlikely(EFX_QWORD_FIELD(*event, 3140 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) { 3141 channel->n_rx_tcp_udp_chksum_err += n_packets; 3142 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP || 3143 rx_l4_class == ESE_DZ_L4_CLASS_UDP) { 3144 flags |= EFX_RX_PKT_CSUMMED; 3145 } 3146 3147 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP) 3148 flags |= EFX_RX_PKT_TCP; 3149 3150 channel->irq_mod_score += 2 * n_packets; 3151 3152 /* Handle received packet(s) */ 3153 for (i = 0; i < n_packets; i++) { 3154 efx_rx_packet(rx_queue, 3155 rx_queue->removed_count & rx_queue->ptr_mask, 3156 rx_queue->scatter_n, rx_queue->scatter_len, 3157 flags); 3158 rx_queue->removed_count += rx_queue->scatter_n; 3159 } 3160 3161 rx_queue->scatter_n = 0; 3162 rx_queue->scatter_len = 0; 3163 3164 return n_packets; 3165 } 3166 3167 static int 3168 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 3169 { 3170 struct efx_nic *efx = channel->efx; 3171 struct efx_tx_queue *tx_queue; 3172 unsigned int tx_ev_desc_ptr; 3173 unsigned int tx_ev_q_label; 3174 int tx_descs = 0; 3175 3176 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 3177 return 0; 3178 3179 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 3180 return 0; 3181 3182 /* Transmit completion */ 3183 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 3184 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 3185 tx_queue = efx_channel_get_tx_queue(channel, 3186 tx_ev_q_label % EFX_TXQ_TYPES); 3187 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) & 3188 tx_queue->ptr_mask); 3189 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 3190 3191 return tx_descs; 3192 } 3193 3194 static void 3195 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 3196 { 3197 struct efx_nic *efx = channel->efx; 3198 int subcode; 3199 3200 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 3201 3202 switch (subcode) { 3203 case ESE_DZ_DRV_TIMER_EV: 3204 case ESE_DZ_DRV_WAKE_UP_EV: 3205 break; 3206 case ESE_DZ_DRV_START_UP_EV: 3207 /* event queue init complete. ok. */ 3208 break; 3209 default: 3210 netif_err(efx, hw, efx->net_dev, 3211 "channel %d unknown driver event type %d" 3212 " (data " EFX_QWORD_FMT ")\n", 3213 channel->channel, subcode, 3214 EFX_QWORD_VAL(*event)); 3215 3216 } 3217 } 3218 3219 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 3220 efx_qword_t *event) 3221 { 3222 struct efx_nic *efx = channel->efx; 3223 u32 subcode; 3224 3225 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 3226 3227 switch (subcode) { 3228 case EFX_EF10_TEST: 3229 channel->event_test_cpu = raw_smp_processor_id(); 3230 break; 3231 case EFX_EF10_REFILL: 3232 /* The queue must be empty, so we won't receive any rx 3233 * events, so efx_process_channel() won't refill the 3234 * queue. Refill it here 3235 */ 3236 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 3237 break; 3238 default: 3239 netif_err(efx, hw, efx->net_dev, 3240 "channel %d unknown driver event type %u" 3241 " (data " EFX_QWORD_FMT ")\n", 3242 channel->channel, (unsigned) subcode, 3243 EFX_QWORD_VAL(*event)); 3244 } 3245 } 3246 3247 static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 3248 { 3249 struct efx_nic *efx = channel->efx; 3250 efx_qword_t event, *p_event; 3251 unsigned int read_ptr; 3252 int ev_code; 3253 int tx_descs = 0; 3254 int spent = 0; 3255 3256 if (quota <= 0) 3257 return spent; 3258 3259 read_ptr = channel->eventq_read_ptr; 3260 3261 for (;;) { 3262 p_event = efx_event(channel, read_ptr); 3263 event = *p_event; 3264 3265 if (!efx_event_present(&event)) 3266 break; 3267 3268 EFX_SET_QWORD(*p_event); 3269 3270 ++read_ptr; 3271 3272 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 3273 3274 netif_vdbg(efx, drv, efx->net_dev, 3275 "processing event on %d " EFX_QWORD_FMT "\n", 3276 channel->channel, EFX_QWORD_VAL(event)); 3277 3278 switch (ev_code) { 3279 case ESE_DZ_EV_CODE_MCDI_EV: 3280 efx_mcdi_process_event(channel, &event); 3281 break; 3282 case ESE_DZ_EV_CODE_RX_EV: 3283 spent += efx_ef10_handle_rx_event(channel, &event); 3284 if (spent >= quota) { 3285 /* XXX can we split a merged event to 3286 * avoid going over-quota? 3287 */ 3288 spent = quota; 3289 goto out; 3290 } 3291 break; 3292 case ESE_DZ_EV_CODE_TX_EV: 3293 tx_descs += efx_ef10_handle_tx_event(channel, &event); 3294 if (tx_descs > efx->txq_entries) { 3295 spent = quota; 3296 goto out; 3297 } else if (++spent == quota) { 3298 goto out; 3299 } 3300 break; 3301 case ESE_DZ_EV_CODE_DRIVER_EV: 3302 efx_ef10_handle_driver_event(channel, &event); 3303 if (++spent == quota) 3304 goto out; 3305 break; 3306 case EFX_EF10_DRVGEN_EV: 3307 efx_ef10_handle_driver_generated_event(channel, &event); 3308 break; 3309 default: 3310 netif_err(efx, hw, efx->net_dev, 3311 "channel %d unknown event type %d" 3312 " (data " EFX_QWORD_FMT ")\n", 3313 channel->channel, ev_code, 3314 EFX_QWORD_VAL(event)); 3315 } 3316 } 3317 3318 out: 3319 channel->eventq_read_ptr = read_ptr; 3320 return spent; 3321 } 3322 3323 static void efx_ef10_ev_read_ack(struct efx_channel *channel) 3324 { 3325 struct efx_nic *efx = channel->efx; 3326 efx_dword_t rptr; 3327 3328 if (EFX_EF10_WORKAROUND_35388(efx)) { 3329 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 3330 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 3331 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 3332 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 3333 3334 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3335 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 3336 ERF_DD_EVQ_IND_RPTR, 3337 (channel->eventq_read_ptr & 3338 channel->eventq_mask) >> 3339 ERF_DD_EVQ_IND_RPTR_WIDTH); 3340 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3341 channel->channel); 3342 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3343 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 3344 ERF_DD_EVQ_IND_RPTR, 3345 channel->eventq_read_ptr & 3346 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 3347 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3348 channel->channel); 3349 } else { 3350 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 3351 channel->eventq_read_ptr & 3352 channel->eventq_mask); 3353 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 3354 } 3355 } 3356 3357 static void efx_ef10_ev_test_generate(struct efx_channel *channel) 3358 { 3359 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 3360 struct efx_nic *efx = channel->efx; 3361 efx_qword_t event; 3362 int rc; 3363 3364 EFX_POPULATE_QWORD_2(event, 3365 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 3366 ESF_DZ_EV_DATA, EFX_EF10_TEST); 3367 3368 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 3369 3370 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 3371 * already swapped the data to little-endian order. 3372 */ 3373 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 3374 sizeof(efx_qword_t)); 3375 3376 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 3377 NULL, 0, NULL); 3378 if (rc != 0) 3379 goto fail; 3380 3381 return; 3382 3383 fail: 3384 WARN_ON(true); 3385 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 3386 } 3387 3388 void efx_ef10_handle_drain_event(struct efx_nic *efx) 3389 { 3390 if (atomic_dec_and_test(&efx->active_queues)) 3391 wake_up(&efx->flush_wq); 3392 3393 WARN_ON(atomic_read(&efx->active_queues) < 0); 3394 } 3395 3396 static int efx_ef10_fini_dmaq(struct efx_nic *efx) 3397 { 3398 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3399 struct efx_channel *channel; 3400 struct efx_tx_queue *tx_queue; 3401 struct efx_rx_queue *rx_queue; 3402 int pending; 3403 3404 /* If the MC has just rebooted, the TX/RX queues will have already been 3405 * torn down, but efx->active_queues needs to be set to zero. 3406 */ 3407 if (nic_data->must_realloc_vis) { 3408 atomic_set(&efx->active_queues, 0); 3409 return 0; 3410 } 3411 3412 /* Do not attempt to write to the NIC during EEH recovery */ 3413 if (efx->state != STATE_RECOVERY) { 3414 efx_for_each_channel(channel, efx) { 3415 efx_for_each_channel_rx_queue(rx_queue, channel) 3416 efx_ef10_rx_fini(rx_queue); 3417 efx_for_each_channel_tx_queue(tx_queue, channel) 3418 efx_ef10_tx_fini(tx_queue); 3419 } 3420 3421 wait_event_timeout(efx->flush_wq, 3422 atomic_read(&efx->active_queues) == 0, 3423 msecs_to_jiffies(EFX_MAX_FLUSH_TIME)); 3424 pending = atomic_read(&efx->active_queues); 3425 if (pending) { 3426 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n", 3427 pending); 3428 return -ETIMEDOUT; 3429 } 3430 } 3431 3432 return 0; 3433 } 3434 3435 static void efx_ef10_prepare_flr(struct efx_nic *efx) 3436 { 3437 atomic_set(&efx->active_queues, 0); 3438 } 3439 3440 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left, 3441 const struct efx_filter_spec *right) 3442 { 3443 if ((left->match_flags ^ right->match_flags) | 3444 ((left->flags ^ right->flags) & 3445 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX))) 3446 return false; 3447 3448 return memcmp(&left->outer_vid, &right->outer_vid, 3449 sizeof(struct efx_filter_spec) - 3450 offsetof(struct efx_filter_spec, outer_vid)) == 0; 3451 } 3452 3453 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec) 3454 { 3455 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3); 3456 return jhash2((const u32 *)&spec->outer_vid, 3457 (sizeof(struct efx_filter_spec) - 3458 offsetof(struct efx_filter_spec, outer_vid)) / 4, 3459 0); 3460 /* XXX should we randomise the initval? */ 3461 } 3462 3463 /* Decide whether a filter should be exclusive or else should allow 3464 * delivery to additional recipients. Currently we decide that 3465 * filters for specific local unicast MAC and IP addresses are 3466 * exclusive. 3467 */ 3468 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec) 3469 { 3470 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC && 3471 !is_multicast_ether_addr(spec->loc_mac)) 3472 return true; 3473 3474 if ((spec->match_flags & 3475 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) == 3476 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) { 3477 if (spec->ether_type == htons(ETH_P_IP) && 3478 !ipv4_is_multicast(spec->loc_host[0])) 3479 return true; 3480 if (spec->ether_type == htons(ETH_P_IPV6) && 3481 ((const u8 *)spec->loc_host)[0] != 0xff) 3482 return true; 3483 } 3484 3485 return false; 3486 } 3487 3488 static struct efx_filter_spec * 3489 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table, 3490 unsigned int filter_idx) 3491 { 3492 return (struct efx_filter_spec *)(table->entry[filter_idx].spec & 3493 ~EFX_EF10_FILTER_FLAGS); 3494 } 3495 3496 static unsigned int 3497 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table, 3498 unsigned int filter_idx) 3499 { 3500 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS; 3501 } 3502 3503 static void 3504 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table, 3505 unsigned int filter_idx, 3506 const struct efx_filter_spec *spec, 3507 unsigned int flags) 3508 { 3509 table->entry[filter_idx].spec = (unsigned long)spec | flags; 3510 } 3511 3512 static void efx_ef10_filter_push_prep(struct efx_nic *efx, 3513 const struct efx_filter_spec *spec, 3514 efx_dword_t *inbuf, u64 handle, 3515 bool replacing) 3516 { 3517 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3518 u32 flags = spec->flags; 3519 3520 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN); 3521 3522 /* Remove RSS flag if we don't have an RSS context. */ 3523 if (flags & EFX_FILTER_FLAG_RX_RSS && 3524 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT && 3525 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) 3526 flags &= ~EFX_FILTER_FLAG_RX_RSS; 3527 3528 if (replacing) { 3529 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3530 MC_CMD_FILTER_OP_IN_OP_REPLACE); 3531 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle); 3532 } else { 3533 u32 match_fields = 0; 3534 3535 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3536 efx_ef10_filter_is_exclusive(spec) ? 3537 MC_CMD_FILTER_OP_IN_OP_INSERT : 3538 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE); 3539 3540 /* Convert match flags and values. Unlike almost 3541 * everything else in MCDI, these fields are in 3542 * network byte order. 3543 */ 3544 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) 3545 match_fields |= 3546 is_multicast_ether_addr(spec->loc_mac) ? 3547 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN : 3548 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN; 3549 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \ 3550 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \ 3551 match_fields |= \ 3552 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 3553 mcdi_field ## _LBN; \ 3554 BUILD_BUG_ON( \ 3555 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \ 3556 sizeof(spec->gen_field)); \ 3557 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \ 3558 &spec->gen_field, sizeof(spec->gen_field)); \ 3559 } 3560 COPY_FIELD(REM_HOST, rem_host, SRC_IP); 3561 COPY_FIELD(LOC_HOST, loc_host, DST_IP); 3562 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC); 3563 COPY_FIELD(REM_PORT, rem_port, SRC_PORT); 3564 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC); 3565 COPY_FIELD(LOC_PORT, loc_port, DST_PORT); 3566 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE); 3567 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN); 3568 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN); 3569 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO); 3570 #undef COPY_FIELD 3571 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS, 3572 match_fields); 3573 } 3574 3575 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id); 3576 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST, 3577 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 3578 MC_CMD_FILTER_OP_IN_RX_DEST_DROP : 3579 MC_CMD_FILTER_OP_IN_RX_DEST_HOST); 3580 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0); 3581 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST, 3582 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT); 3583 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE, 3584 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 3585 0 : spec->dmaq_id); 3586 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE, 3587 (flags & EFX_FILTER_FLAG_RX_RSS) ? 3588 MC_CMD_FILTER_OP_IN_RX_MODE_RSS : 3589 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE); 3590 if (flags & EFX_FILTER_FLAG_RX_RSS) 3591 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT, 3592 spec->rss_context != 3593 EFX_FILTER_RSS_CONTEXT_DEFAULT ? 3594 spec->rss_context : nic_data->rx_rss_context); 3595 } 3596 3597 static int efx_ef10_filter_push(struct efx_nic *efx, 3598 const struct efx_filter_spec *spec, 3599 u64 *handle, bool replacing) 3600 { 3601 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3602 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN); 3603 int rc; 3604 3605 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing); 3606 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 3607 outbuf, sizeof(outbuf), NULL); 3608 if (rc == 0) 3609 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 3610 if (rc == -ENOSPC) 3611 rc = -EBUSY; /* to match efx_farch_filter_insert() */ 3612 return rc; 3613 } 3614 3615 static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec) 3616 { 3617 unsigned int match_flags = spec->match_flags; 3618 u32 mcdi_flags = 0; 3619 3620 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) { 3621 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG; 3622 mcdi_flags |= 3623 is_multicast_ether_addr(spec->loc_mac) ? 3624 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN) : 3625 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN); 3626 } 3627 3628 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field) { \ 3629 unsigned int old_match_flags = match_flags; \ 3630 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \ 3631 if (match_flags != old_match_flags) \ 3632 mcdi_flags |= \ 3633 (1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 3634 mcdi_field ## _LBN); \ 3635 } 3636 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP); 3637 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP); 3638 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC); 3639 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT); 3640 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC); 3641 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT); 3642 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE); 3643 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN); 3644 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN); 3645 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO); 3646 #undef MAP_FILTER_TO_MCDI_FLAG 3647 3648 /* Did we map them all? */ 3649 WARN_ON_ONCE(match_flags); 3650 3651 return mcdi_flags; 3652 } 3653 3654 static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table, 3655 const struct efx_filter_spec *spec) 3656 { 3657 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec); 3658 unsigned int match_pri; 3659 3660 for (match_pri = 0; 3661 match_pri < table->rx_match_count; 3662 match_pri++) 3663 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags) 3664 return match_pri; 3665 3666 return -EPROTONOSUPPORT; 3667 } 3668 3669 static s32 efx_ef10_filter_insert(struct efx_nic *efx, 3670 struct efx_filter_spec *spec, 3671 bool replace_equal) 3672 { 3673 struct efx_ef10_filter_table *table = efx->filter_state; 3674 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 3675 struct efx_filter_spec *saved_spec; 3676 unsigned int match_pri, hash; 3677 unsigned int priv_flags; 3678 bool replacing = false; 3679 int ins_index = -1; 3680 DEFINE_WAIT(wait); 3681 bool is_mc_recip; 3682 s32 rc; 3683 3684 /* For now, only support RX filters */ 3685 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) != 3686 EFX_FILTER_FLAG_RX) 3687 return -EINVAL; 3688 3689 rc = efx_ef10_filter_pri(table, spec); 3690 if (rc < 0) 3691 return rc; 3692 match_pri = rc; 3693 3694 hash = efx_ef10_filter_hash(spec); 3695 is_mc_recip = efx_filter_is_mc_recipient(spec); 3696 if (is_mc_recip) 3697 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 3698 3699 /* Find any existing filters with the same match tuple or 3700 * else a free slot to insert at. If any of them are busy, 3701 * we have to wait and retry. 3702 */ 3703 for (;;) { 3704 unsigned int depth = 1; 3705 unsigned int i; 3706 3707 spin_lock_bh(&efx->filter_lock); 3708 3709 for (;;) { 3710 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3711 saved_spec = efx_ef10_filter_entry_spec(table, i); 3712 3713 if (!saved_spec) { 3714 if (ins_index < 0) 3715 ins_index = i; 3716 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 3717 if (table->entry[i].spec & 3718 EFX_EF10_FILTER_FLAG_BUSY) 3719 break; 3720 if (spec->priority < saved_spec->priority && 3721 spec->priority != EFX_FILTER_PRI_AUTO) { 3722 rc = -EPERM; 3723 goto out_unlock; 3724 } 3725 if (!is_mc_recip) { 3726 /* This is the only one */ 3727 if (spec->priority == 3728 saved_spec->priority && 3729 !replace_equal) { 3730 rc = -EEXIST; 3731 goto out_unlock; 3732 } 3733 ins_index = i; 3734 goto found; 3735 } else if (spec->priority > 3736 saved_spec->priority || 3737 (spec->priority == 3738 saved_spec->priority && 3739 replace_equal)) { 3740 if (ins_index < 0) 3741 ins_index = i; 3742 else 3743 __set_bit(depth, mc_rem_map); 3744 } 3745 } 3746 3747 /* Once we reach the maximum search depth, use 3748 * the first suitable slot or return -EBUSY if 3749 * there was none 3750 */ 3751 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 3752 if (ins_index < 0) { 3753 rc = -EBUSY; 3754 goto out_unlock; 3755 } 3756 goto found; 3757 } 3758 3759 ++depth; 3760 } 3761 3762 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 3763 spin_unlock_bh(&efx->filter_lock); 3764 schedule(); 3765 } 3766 3767 found: 3768 /* Create a software table entry if necessary, and mark it 3769 * busy. We might yet fail to insert, but any attempt to 3770 * insert a conflicting filter while we're waiting for the 3771 * firmware must find the busy entry. 3772 */ 3773 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 3774 if (saved_spec) { 3775 if (spec->priority == EFX_FILTER_PRI_AUTO && 3776 saved_spec->priority >= EFX_FILTER_PRI_AUTO) { 3777 /* Just make sure it won't be removed */ 3778 if (saved_spec->priority > EFX_FILTER_PRI_AUTO) 3779 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO; 3780 table->entry[ins_index].spec &= 3781 ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 3782 rc = ins_index; 3783 goto out_unlock; 3784 } 3785 replacing = true; 3786 priv_flags = efx_ef10_filter_entry_flags(table, ins_index); 3787 } else { 3788 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 3789 if (!saved_spec) { 3790 rc = -ENOMEM; 3791 goto out_unlock; 3792 } 3793 *saved_spec = *spec; 3794 priv_flags = 0; 3795 } 3796 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 3797 priv_flags | EFX_EF10_FILTER_FLAG_BUSY); 3798 3799 /* Mark lower-priority multicast recipients busy prior to removal */ 3800 if (is_mc_recip) { 3801 unsigned int depth, i; 3802 3803 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 3804 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3805 if (test_bit(depth, mc_rem_map)) 3806 table->entry[i].spec |= 3807 EFX_EF10_FILTER_FLAG_BUSY; 3808 } 3809 } 3810 3811 spin_unlock_bh(&efx->filter_lock); 3812 3813 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle, 3814 replacing); 3815 3816 /* Finalise the software table entry */ 3817 spin_lock_bh(&efx->filter_lock); 3818 if (rc == 0) { 3819 if (replacing) { 3820 /* Update the fields that may differ */ 3821 if (saved_spec->priority == EFX_FILTER_PRI_AUTO) 3822 saved_spec->flags |= 3823 EFX_FILTER_FLAG_RX_OVER_AUTO; 3824 saved_spec->priority = spec->priority; 3825 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO; 3826 saved_spec->flags |= spec->flags; 3827 saved_spec->rss_context = spec->rss_context; 3828 saved_spec->dmaq_id = spec->dmaq_id; 3829 } 3830 } else if (!replacing) { 3831 kfree(saved_spec); 3832 saved_spec = NULL; 3833 } 3834 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags); 3835 3836 /* Remove and finalise entries for lower-priority multicast 3837 * recipients 3838 */ 3839 if (is_mc_recip) { 3840 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3841 unsigned int depth, i; 3842 3843 memset(inbuf, 0, sizeof(inbuf)); 3844 3845 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 3846 if (!test_bit(depth, mc_rem_map)) 3847 continue; 3848 3849 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3850 saved_spec = efx_ef10_filter_entry_spec(table, i); 3851 priv_flags = efx_ef10_filter_entry_flags(table, i); 3852 3853 if (rc == 0) { 3854 spin_unlock_bh(&efx->filter_lock); 3855 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3856 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3857 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3858 table->entry[i].handle); 3859 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 3860 inbuf, sizeof(inbuf), 3861 NULL, 0, NULL); 3862 spin_lock_bh(&efx->filter_lock); 3863 } 3864 3865 if (rc == 0) { 3866 kfree(saved_spec); 3867 saved_spec = NULL; 3868 priv_flags = 0; 3869 } else { 3870 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY; 3871 } 3872 efx_ef10_filter_set_entry(table, i, saved_spec, 3873 priv_flags); 3874 } 3875 } 3876 3877 /* If successful, return the inserted filter ID */ 3878 if (rc == 0) 3879 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index; 3880 3881 wake_up_all(&table->waitq); 3882 out_unlock: 3883 spin_unlock_bh(&efx->filter_lock); 3884 finish_wait(&table->waitq, &wait); 3885 return rc; 3886 } 3887 3888 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx) 3889 { 3890 /* no need to do anything here on EF10 */ 3891 } 3892 3893 /* Remove a filter. 3894 * If !by_index, remove by ID 3895 * If by_index, remove by index 3896 * Filter ID may come from userland and must be range-checked. 3897 */ 3898 static int efx_ef10_filter_remove_internal(struct efx_nic *efx, 3899 unsigned int priority_mask, 3900 u32 filter_id, bool by_index) 3901 { 3902 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 3903 struct efx_ef10_filter_table *table = efx->filter_state; 3904 MCDI_DECLARE_BUF(inbuf, 3905 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 3906 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 3907 struct efx_filter_spec *spec; 3908 DEFINE_WAIT(wait); 3909 int rc; 3910 3911 /* Find the software table entry and mark it busy. Don't 3912 * remove it yet; any attempt to update while we're waiting 3913 * for the firmware must find the busy entry. 3914 */ 3915 for (;;) { 3916 spin_lock_bh(&efx->filter_lock); 3917 if (!(table->entry[filter_idx].spec & 3918 EFX_EF10_FILTER_FLAG_BUSY)) 3919 break; 3920 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 3921 spin_unlock_bh(&efx->filter_lock); 3922 schedule(); 3923 } 3924 3925 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3926 if (!spec || 3927 (!by_index && 3928 efx_ef10_filter_pri(table, spec) != 3929 filter_id / HUNT_FILTER_TBL_ROWS)) { 3930 rc = -ENOENT; 3931 goto out_unlock; 3932 } 3933 3934 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO && 3935 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) { 3936 /* Just remove flags */ 3937 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO; 3938 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 3939 rc = 0; 3940 goto out_unlock; 3941 } 3942 3943 if (!(priority_mask & (1U << spec->priority))) { 3944 rc = -ENOENT; 3945 goto out_unlock; 3946 } 3947 3948 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3949 spin_unlock_bh(&efx->filter_lock); 3950 3951 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) { 3952 /* Reset to an automatic filter */ 3953 3954 struct efx_filter_spec new_spec = *spec; 3955 3956 new_spec.priority = EFX_FILTER_PRI_AUTO; 3957 new_spec.flags = (EFX_FILTER_FLAG_RX | 3958 (efx_rss_enabled(efx) ? 3959 EFX_FILTER_FLAG_RX_RSS : 0)); 3960 new_spec.dmaq_id = 0; 3961 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT; 3962 rc = efx_ef10_filter_push(efx, &new_spec, 3963 &table->entry[filter_idx].handle, 3964 true); 3965 3966 spin_lock_bh(&efx->filter_lock); 3967 if (rc == 0) 3968 *spec = new_spec; 3969 } else { 3970 /* Really remove the filter */ 3971 3972 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3973 efx_ef10_filter_is_exclusive(spec) ? 3974 MC_CMD_FILTER_OP_IN_OP_REMOVE : 3975 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3976 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3977 table->entry[filter_idx].handle); 3978 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 3979 inbuf, sizeof(inbuf), NULL, 0, NULL); 3980 3981 spin_lock_bh(&efx->filter_lock); 3982 if (rc == 0) { 3983 kfree(spec); 3984 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3985 } 3986 } 3987 3988 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 3989 wake_up_all(&table->waitq); 3990 out_unlock: 3991 spin_unlock_bh(&efx->filter_lock); 3992 finish_wait(&table->waitq, &wait); 3993 return rc; 3994 } 3995 3996 static int efx_ef10_filter_remove_safe(struct efx_nic *efx, 3997 enum efx_filter_priority priority, 3998 u32 filter_id) 3999 { 4000 return efx_ef10_filter_remove_internal(efx, 1U << priority, 4001 filter_id, false); 4002 } 4003 4004 static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id) 4005 { 4006 return filter_id % HUNT_FILTER_TBL_ROWS; 4007 } 4008 4009 static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx, 4010 enum efx_filter_priority priority, 4011 u32 filter_id) 4012 { 4013 if (filter_id == EFX_EF10_FILTER_ID_INVALID) 4014 return; 4015 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true); 4016 } 4017 4018 static int efx_ef10_filter_get_safe(struct efx_nic *efx, 4019 enum efx_filter_priority priority, 4020 u32 filter_id, struct efx_filter_spec *spec) 4021 { 4022 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 4023 struct efx_ef10_filter_table *table = efx->filter_state; 4024 const struct efx_filter_spec *saved_spec; 4025 int rc; 4026 4027 spin_lock_bh(&efx->filter_lock); 4028 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx); 4029 if (saved_spec && saved_spec->priority == priority && 4030 efx_ef10_filter_pri(table, saved_spec) == 4031 filter_id / HUNT_FILTER_TBL_ROWS) { 4032 *spec = *saved_spec; 4033 rc = 0; 4034 } else { 4035 rc = -ENOENT; 4036 } 4037 spin_unlock_bh(&efx->filter_lock); 4038 return rc; 4039 } 4040 4041 static int efx_ef10_filter_clear_rx(struct efx_nic *efx, 4042 enum efx_filter_priority priority) 4043 { 4044 unsigned int priority_mask; 4045 unsigned int i; 4046 int rc; 4047 4048 priority_mask = (((1U << (priority + 1)) - 1) & 4049 ~(1U << EFX_FILTER_PRI_AUTO)); 4050 4051 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 4052 rc = efx_ef10_filter_remove_internal(efx, priority_mask, 4053 i, true); 4054 if (rc && rc != -ENOENT) 4055 return rc; 4056 } 4057 4058 return 0; 4059 } 4060 4061 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx, 4062 enum efx_filter_priority priority) 4063 { 4064 struct efx_ef10_filter_table *table = efx->filter_state; 4065 unsigned int filter_idx; 4066 s32 count = 0; 4067 4068 spin_lock_bh(&efx->filter_lock); 4069 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 4070 if (table->entry[filter_idx].spec && 4071 efx_ef10_filter_entry_spec(table, filter_idx)->priority == 4072 priority) 4073 ++count; 4074 } 4075 spin_unlock_bh(&efx->filter_lock); 4076 return count; 4077 } 4078 4079 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx) 4080 { 4081 struct efx_ef10_filter_table *table = efx->filter_state; 4082 4083 return table->rx_match_count * HUNT_FILTER_TBL_ROWS; 4084 } 4085 4086 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx, 4087 enum efx_filter_priority priority, 4088 u32 *buf, u32 size) 4089 { 4090 struct efx_ef10_filter_table *table = efx->filter_state; 4091 struct efx_filter_spec *spec; 4092 unsigned int filter_idx; 4093 s32 count = 0; 4094 4095 spin_lock_bh(&efx->filter_lock); 4096 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 4097 spec = efx_ef10_filter_entry_spec(table, filter_idx); 4098 if (spec && spec->priority == priority) { 4099 if (count == size) { 4100 count = -EMSGSIZE; 4101 break; 4102 } 4103 buf[count++] = (efx_ef10_filter_pri(table, spec) * 4104 HUNT_FILTER_TBL_ROWS + 4105 filter_idx); 4106 } 4107 } 4108 spin_unlock_bh(&efx->filter_lock); 4109 return count; 4110 } 4111 4112 #ifdef CONFIG_RFS_ACCEL 4113 4114 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete; 4115 4116 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx, 4117 struct efx_filter_spec *spec) 4118 { 4119 struct efx_ef10_filter_table *table = efx->filter_state; 4120 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 4121 struct efx_filter_spec *saved_spec; 4122 unsigned int hash, i, depth = 1; 4123 bool replacing = false; 4124 int ins_index = -1; 4125 u64 cookie; 4126 s32 rc; 4127 4128 /* Must be an RX filter without RSS and not for a multicast 4129 * destination address (RFS only works for connected sockets). 4130 * These restrictions allow us to pass only a tiny amount of 4131 * data through to the completion function. 4132 */ 4133 EFX_WARN_ON_PARANOID(spec->flags != 4134 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER)); 4135 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT); 4136 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec)); 4137 4138 hash = efx_ef10_filter_hash(spec); 4139 4140 spin_lock_bh(&efx->filter_lock); 4141 4142 /* Find any existing filter with the same match tuple or else 4143 * a free slot to insert at. If an existing filter is busy, 4144 * we have to give up. 4145 */ 4146 for (;;) { 4147 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 4148 saved_spec = efx_ef10_filter_entry_spec(table, i); 4149 4150 if (!saved_spec) { 4151 if (ins_index < 0) 4152 ins_index = i; 4153 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 4154 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) { 4155 rc = -EBUSY; 4156 goto fail_unlock; 4157 } 4158 if (spec->priority < saved_spec->priority) { 4159 rc = -EPERM; 4160 goto fail_unlock; 4161 } 4162 ins_index = i; 4163 break; 4164 } 4165 4166 /* Once we reach the maximum search depth, use the 4167 * first suitable slot or return -EBUSY if there was 4168 * none 4169 */ 4170 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 4171 if (ins_index < 0) { 4172 rc = -EBUSY; 4173 goto fail_unlock; 4174 } 4175 break; 4176 } 4177 4178 ++depth; 4179 } 4180 4181 /* Create a software table entry if necessary, and mark it 4182 * busy. We might yet fail to insert, but any attempt to 4183 * insert a conflicting filter while we're waiting for the 4184 * firmware must find the busy entry. 4185 */ 4186 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 4187 if (saved_spec) { 4188 replacing = true; 4189 } else { 4190 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 4191 if (!saved_spec) { 4192 rc = -ENOMEM; 4193 goto fail_unlock; 4194 } 4195 *saved_spec = *spec; 4196 } 4197 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 4198 EFX_EF10_FILTER_FLAG_BUSY); 4199 4200 spin_unlock_bh(&efx->filter_lock); 4201 4202 /* Pack up the variables needed on completion */ 4203 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id; 4204 4205 efx_ef10_filter_push_prep(efx, spec, inbuf, 4206 table->entry[ins_index].handle, replacing); 4207 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 4208 MC_CMD_FILTER_OP_OUT_LEN, 4209 efx_ef10_filter_rfs_insert_complete, cookie); 4210 4211 return ins_index; 4212 4213 fail_unlock: 4214 spin_unlock_bh(&efx->filter_lock); 4215 return rc; 4216 } 4217 4218 static void 4219 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie, 4220 int rc, efx_dword_t *outbuf, 4221 size_t outlen_actual) 4222 { 4223 struct efx_ef10_filter_table *table = efx->filter_state; 4224 unsigned int ins_index, dmaq_id; 4225 struct efx_filter_spec *spec; 4226 bool replacing; 4227 4228 /* Unpack the cookie */ 4229 replacing = cookie >> 31; 4230 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1); 4231 dmaq_id = cookie & 0xffff; 4232 4233 spin_lock_bh(&efx->filter_lock); 4234 spec = efx_ef10_filter_entry_spec(table, ins_index); 4235 if (rc == 0) { 4236 table->entry[ins_index].handle = 4237 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 4238 if (replacing) 4239 spec->dmaq_id = dmaq_id; 4240 } else if (!replacing) { 4241 kfree(spec); 4242 spec = NULL; 4243 } 4244 efx_ef10_filter_set_entry(table, ins_index, spec, 0); 4245 spin_unlock_bh(&efx->filter_lock); 4246 4247 wake_up_all(&table->waitq); 4248 } 4249 4250 static void 4251 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 4252 unsigned long filter_idx, 4253 int rc, efx_dword_t *outbuf, 4254 size_t outlen_actual); 4255 4256 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, 4257 unsigned int filter_idx) 4258 { 4259 struct efx_ef10_filter_table *table = efx->filter_state; 4260 struct efx_filter_spec *spec = 4261 efx_ef10_filter_entry_spec(table, filter_idx); 4262 MCDI_DECLARE_BUF(inbuf, 4263 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 4264 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 4265 4266 if (!spec || 4267 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) || 4268 spec->priority != EFX_FILTER_PRI_HINT || 4269 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id, 4270 flow_id, filter_idx)) 4271 return false; 4272 4273 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 4274 MC_CMD_FILTER_OP_IN_OP_REMOVE); 4275 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 4276 table->entry[filter_idx].handle); 4277 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0, 4278 efx_ef10_filter_rfs_expire_complete, filter_idx)) 4279 return false; 4280 4281 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 4282 return true; 4283 } 4284 4285 static void 4286 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 4287 unsigned long filter_idx, 4288 int rc, efx_dword_t *outbuf, 4289 size_t outlen_actual) 4290 { 4291 struct efx_ef10_filter_table *table = efx->filter_state; 4292 struct efx_filter_spec *spec = 4293 efx_ef10_filter_entry_spec(table, filter_idx); 4294 4295 spin_lock_bh(&efx->filter_lock); 4296 if (rc == 0) { 4297 kfree(spec); 4298 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 4299 } 4300 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 4301 wake_up_all(&table->waitq); 4302 spin_unlock_bh(&efx->filter_lock); 4303 } 4304 4305 #endif /* CONFIG_RFS_ACCEL */ 4306 4307 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags) 4308 { 4309 int match_flags = 0; 4310 4311 #define MAP_FLAG(gen_flag, mcdi_field) { \ 4312 u32 old_mcdi_flags = mcdi_flags; \ 4313 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 4314 mcdi_field ## _LBN); \ 4315 if (mcdi_flags != old_mcdi_flags) \ 4316 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \ 4317 } 4318 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST); 4319 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST); 4320 MAP_FLAG(REM_HOST, SRC_IP); 4321 MAP_FLAG(LOC_HOST, DST_IP); 4322 MAP_FLAG(REM_MAC, SRC_MAC); 4323 MAP_FLAG(REM_PORT, SRC_PORT); 4324 MAP_FLAG(LOC_MAC, DST_MAC); 4325 MAP_FLAG(LOC_PORT, DST_PORT); 4326 MAP_FLAG(ETHER_TYPE, ETHER_TYPE); 4327 MAP_FLAG(INNER_VID, INNER_VLAN); 4328 MAP_FLAG(OUTER_VID, OUTER_VLAN); 4329 MAP_FLAG(IP_PROTO, IP_PROTO); 4330 #undef MAP_FLAG 4331 4332 /* Did we map them all? */ 4333 if (mcdi_flags) 4334 return -EINVAL; 4335 4336 return match_flags; 4337 } 4338 4339 static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx) 4340 { 4341 struct efx_ef10_filter_table *table = efx->filter_state; 4342 struct efx_ef10_filter_vlan *vlan, *next_vlan; 4343 4344 /* See comment in efx_ef10_filter_table_remove() */ 4345 if (!efx_rwsem_assert_write_locked(&efx->filter_sem)) 4346 return; 4347 4348 if (!table) 4349 return; 4350 4351 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list) 4352 efx_ef10_filter_del_vlan_internal(efx, vlan); 4353 } 4354 4355 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table, 4356 enum efx_filter_match_flags match_flags) 4357 { 4358 unsigned int match_pri; 4359 int mf; 4360 4361 for (match_pri = 0; 4362 match_pri < table->rx_match_count; 4363 match_pri++) { 4364 mf = efx_ef10_filter_match_flags_from_mcdi( 4365 table->rx_match_mcdi_flags[match_pri]); 4366 if (mf == match_flags) 4367 return true; 4368 } 4369 4370 return false; 4371 } 4372 4373 static int efx_ef10_filter_table_probe(struct efx_nic *efx) 4374 { 4375 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN); 4376 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX); 4377 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4378 struct net_device *net_dev = efx->net_dev; 4379 unsigned int pd_match_pri, pd_match_count; 4380 struct efx_ef10_filter_table *table; 4381 struct efx_ef10_vlan *vlan; 4382 size_t outlen; 4383 int rc; 4384 4385 if (!efx_rwsem_assert_write_locked(&efx->filter_sem)) 4386 return -EINVAL; 4387 4388 if (efx->filter_state) /* already probed */ 4389 return 0; 4390 4391 table = kzalloc(sizeof(*table), GFP_KERNEL); 4392 if (!table) 4393 return -ENOMEM; 4394 4395 /* Find out which RX filter types are supported, and their priorities */ 4396 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP, 4397 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES); 4398 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO, 4399 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf), 4400 &outlen); 4401 if (rc) 4402 goto fail; 4403 pd_match_count = MCDI_VAR_ARRAY_LEN( 4404 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES); 4405 table->rx_match_count = 0; 4406 4407 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) { 4408 u32 mcdi_flags = 4409 MCDI_ARRAY_DWORD( 4410 outbuf, 4411 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES, 4412 pd_match_pri); 4413 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags); 4414 if (rc < 0) { 4415 netif_dbg(efx, probe, efx->net_dev, 4416 "%s: fw flags %#x pri %u not supported in driver\n", 4417 __func__, mcdi_flags, pd_match_pri); 4418 } else { 4419 netif_dbg(efx, probe, efx->net_dev, 4420 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n", 4421 __func__, mcdi_flags, pd_match_pri, 4422 rc, table->rx_match_count); 4423 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags; 4424 table->rx_match_count++; 4425 } 4426 } 4427 4428 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) && 4429 !(efx_ef10_filter_match_supported(table, 4430 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) && 4431 efx_ef10_filter_match_supported(table, 4432 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) { 4433 netif_info(efx, probe, net_dev, 4434 "VLAN filters are not supported in this firmware variant\n"); 4435 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4436 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4437 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4438 } 4439 4440 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry)); 4441 if (!table->entry) { 4442 rc = -ENOMEM; 4443 goto fail; 4444 } 4445 4446 table->mc_promisc_last = false; 4447 table->vlan_filter = 4448 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER); 4449 INIT_LIST_HEAD(&table->vlan_list); 4450 4451 efx->filter_state = table; 4452 init_waitqueue_head(&table->waitq); 4453 4454 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 4455 rc = efx_ef10_filter_add_vlan(efx, vlan->vid); 4456 if (rc) 4457 goto fail_add_vlan; 4458 } 4459 4460 return 0; 4461 4462 fail_add_vlan: 4463 efx_ef10_filter_cleanup_vlans(efx); 4464 efx->filter_state = NULL; 4465 fail: 4466 kfree(table); 4467 return rc; 4468 } 4469 4470 /* Caller must hold efx->filter_sem for read if race against 4471 * efx_ef10_filter_table_remove() is possible 4472 */ 4473 static void efx_ef10_filter_table_restore(struct efx_nic *efx) 4474 { 4475 struct efx_ef10_filter_table *table = efx->filter_state; 4476 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4477 struct efx_filter_spec *spec; 4478 unsigned int filter_idx; 4479 bool failed = false; 4480 int rc; 4481 4482 WARN_ON(!rwsem_is_locked(&efx->filter_sem)); 4483 4484 if (!nic_data->must_restore_filters) 4485 return; 4486 4487 if (!table) 4488 return; 4489 4490 spin_lock_bh(&efx->filter_lock); 4491 4492 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 4493 spec = efx_ef10_filter_entry_spec(table, filter_idx); 4494 if (!spec) 4495 continue; 4496 4497 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 4498 spin_unlock_bh(&efx->filter_lock); 4499 4500 rc = efx_ef10_filter_push(efx, spec, 4501 &table->entry[filter_idx].handle, 4502 false); 4503 if (rc) 4504 failed = true; 4505 4506 spin_lock_bh(&efx->filter_lock); 4507 if (rc) { 4508 kfree(spec); 4509 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 4510 } else { 4511 table->entry[filter_idx].spec &= 4512 ~EFX_EF10_FILTER_FLAG_BUSY; 4513 } 4514 } 4515 4516 spin_unlock_bh(&efx->filter_lock); 4517 4518 if (failed) 4519 netif_err(efx, hw, efx->net_dev, 4520 "unable to restore all filters\n"); 4521 else 4522 nic_data->must_restore_filters = false; 4523 } 4524 4525 static void efx_ef10_filter_table_remove(struct efx_nic *efx) 4526 { 4527 struct efx_ef10_filter_table *table = efx->filter_state; 4528 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 4529 struct efx_filter_spec *spec; 4530 unsigned int filter_idx; 4531 int rc; 4532 4533 efx_ef10_filter_cleanup_vlans(efx); 4534 efx->filter_state = NULL; 4535 /* If we were called without locking, then it's not safe to free 4536 * the table as others might be using it. So we just WARN, leak 4537 * the memory, and potentially get an inconsistent filter table 4538 * state. 4539 * This should never actually happen. 4540 */ 4541 if (!efx_rwsem_assert_write_locked(&efx->filter_sem)) 4542 return; 4543 4544 if (!table) 4545 return; 4546 4547 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 4548 spec = efx_ef10_filter_entry_spec(table, filter_idx); 4549 if (!spec) 4550 continue; 4551 4552 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 4553 efx_ef10_filter_is_exclusive(spec) ? 4554 MC_CMD_FILTER_OP_IN_OP_REMOVE : 4555 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 4556 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 4557 table->entry[filter_idx].handle); 4558 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf, 4559 sizeof(inbuf), NULL, 0, NULL); 4560 if (rc) 4561 netif_info(efx, drv, efx->net_dev, 4562 "%s: filter %04x remove failed\n", 4563 __func__, filter_idx); 4564 kfree(spec); 4565 } 4566 4567 vfree(table->entry); 4568 kfree(table); 4569 } 4570 4571 static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id) 4572 { 4573 struct efx_ef10_filter_table *table = efx->filter_state; 4574 unsigned int filter_idx; 4575 4576 if (*id != EFX_EF10_FILTER_ID_INVALID) { 4577 filter_idx = efx_ef10_filter_get_unsafe_id(efx, *id); 4578 if (!table->entry[filter_idx].spec) 4579 netif_dbg(efx, drv, efx->net_dev, 4580 "marked null spec old %04x:%04x\n", *id, 4581 filter_idx); 4582 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; 4583 *id = EFX_EF10_FILTER_ID_INVALID; 4584 } 4585 } 4586 4587 /* Mark old per-VLAN filters that may need to be removed */ 4588 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx, 4589 struct efx_ef10_filter_vlan *vlan) 4590 { 4591 struct efx_ef10_filter_table *table = efx->filter_state; 4592 unsigned int i; 4593 4594 for (i = 0; i < table->dev_uc_count; i++) 4595 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]); 4596 for (i = 0; i < table->dev_mc_count; i++) 4597 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]); 4598 efx_ef10_filter_mark_one_old(efx, &vlan->ucdef); 4599 efx_ef10_filter_mark_one_old(efx, &vlan->bcast); 4600 efx_ef10_filter_mark_one_old(efx, &vlan->mcdef); 4601 } 4602 4603 /* Mark old filters that may need to be removed. 4604 * Caller must hold efx->filter_sem for read if race against 4605 * efx_ef10_filter_table_remove() is possible 4606 */ 4607 static void efx_ef10_filter_mark_old(struct efx_nic *efx) 4608 { 4609 struct efx_ef10_filter_table *table = efx->filter_state; 4610 struct efx_ef10_filter_vlan *vlan; 4611 4612 spin_lock_bh(&efx->filter_lock); 4613 list_for_each_entry(vlan, &table->vlan_list, list) 4614 _efx_ef10_filter_vlan_mark_old(efx, vlan); 4615 spin_unlock_bh(&efx->filter_lock); 4616 } 4617 4618 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx) 4619 { 4620 struct efx_ef10_filter_table *table = efx->filter_state; 4621 struct net_device *net_dev = efx->net_dev; 4622 struct netdev_hw_addr *uc; 4623 int addr_count; 4624 unsigned int i; 4625 4626 addr_count = netdev_uc_count(net_dev); 4627 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC); 4628 table->dev_uc_count = 1 + addr_count; 4629 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr); 4630 i = 1; 4631 netdev_for_each_uc_addr(uc, net_dev) { 4632 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) { 4633 table->uc_promisc = true; 4634 break; 4635 } 4636 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr); 4637 i++; 4638 } 4639 } 4640 4641 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx) 4642 { 4643 struct efx_ef10_filter_table *table = efx->filter_state; 4644 struct net_device *net_dev = efx->net_dev; 4645 struct netdev_hw_addr *mc; 4646 unsigned int i, addr_count; 4647 4648 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI)); 4649 4650 addr_count = netdev_mc_count(net_dev); 4651 i = 0; 4652 netdev_for_each_mc_addr(mc, net_dev) { 4653 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) { 4654 table->mc_promisc = true; 4655 break; 4656 } 4657 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr); 4658 i++; 4659 } 4660 4661 table->dev_mc_count = i; 4662 } 4663 4664 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx, 4665 struct efx_ef10_filter_vlan *vlan, 4666 bool multicast, bool rollback) 4667 { 4668 struct efx_ef10_filter_table *table = efx->filter_state; 4669 struct efx_ef10_dev_addr *addr_list; 4670 enum efx_filter_flags filter_flags; 4671 struct efx_filter_spec spec; 4672 u8 baddr[ETH_ALEN]; 4673 unsigned int i, j; 4674 int addr_count; 4675 u16 *ids; 4676 int rc; 4677 4678 if (multicast) { 4679 addr_list = table->dev_mc_list; 4680 addr_count = table->dev_mc_count; 4681 ids = vlan->mc; 4682 } else { 4683 addr_list = table->dev_uc_list; 4684 addr_count = table->dev_uc_count; 4685 ids = vlan->uc; 4686 } 4687 4688 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0; 4689 4690 /* Insert/renew filters */ 4691 for (i = 0; i < addr_count; i++) { 4692 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0); 4693 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr); 4694 rc = efx_ef10_filter_insert(efx, &spec, true); 4695 if (rc < 0) { 4696 if (rollback) { 4697 netif_info(efx, drv, efx->net_dev, 4698 "efx_ef10_filter_insert failed rc=%d\n", 4699 rc); 4700 /* Fall back to promiscuous */ 4701 for (j = 0; j < i; j++) { 4702 efx_ef10_filter_remove_unsafe( 4703 efx, EFX_FILTER_PRI_AUTO, 4704 ids[j]); 4705 ids[j] = EFX_EF10_FILTER_ID_INVALID; 4706 } 4707 return rc; 4708 } else { 4709 /* mark as not inserted, and carry on */ 4710 rc = EFX_EF10_FILTER_ID_INVALID; 4711 } 4712 } 4713 ids[i] = efx_ef10_filter_get_unsafe_id(efx, rc); 4714 } 4715 4716 if (multicast && rollback) { 4717 /* Also need an Ethernet broadcast filter */ 4718 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0); 4719 eth_broadcast_addr(baddr); 4720 efx_filter_set_eth_local(&spec, vlan->vid, baddr); 4721 rc = efx_ef10_filter_insert(efx, &spec, true); 4722 if (rc < 0) { 4723 netif_warn(efx, drv, efx->net_dev, 4724 "Broadcast filter insert failed rc=%d\n", rc); 4725 /* Fall back to promiscuous */ 4726 for (j = 0; j < i; j++) { 4727 efx_ef10_filter_remove_unsafe( 4728 efx, EFX_FILTER_PRI_AUTO, 4729 ids[j]); 4730 ids[j] = EFX_EF10_FILTER_ID_INVALID; 4731 } 4732 return rc; 4733 } else { 4734 EFX_WARN_ON_PARANOID(vlan->bcast != 4735 EFX_EF10_FILTER_ID_INVALID); 4736 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc); 4737 } 4738 } 4739 4740 return 0; 4741 } 4742 4743 static int efx_ef10_filter_insert_def(struct efx_nic *efx, 4744 struct efx_ef10_filter_vlan *vlan, 4745 bool multicast, bool rollback) 4746 { 4747 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4748 enum efx_filter_flags filter_flags; 4749 struct efx_filter_spec spec; 4750 u8 baddr[ETH_ALEN]; 4751 int rc; 4752 4753 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0; 4754 4755 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0); 4756 4757 if (multicast) 4758 efx_filter_set_mc_def(&spec); 4759 else 4760 efx_filter_set_uc_def(&spec); 4761 4762 if (vlan->vid != EFX_FILTER_VID_UNSPEC) 4763 efx_filter_set_eth_local(&spec, vlan->vid, NULL); 4764 4765 rc = efx_ef10_filter_insert(efx, &spec, true); 4766 if (rc < 0) { 4767 netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING, 4768 efx->net_dev, 4769 "%scast mismatch filter insert failed rc=%d\n", 4770 multicast ? "Multi" : "Uni", rc); 4771 } else if (multicast) { 4772 EFX_WARN_ON_PARANOID(vlan->mcdef != EFX_EF10_FILTER_ID_INVALID); 4773 vlan->mcdef = efx_ef10_filter_get_unsafe_id(efx, rc); 4774 if (!nic_data->workaround_26807) { 4775 /* Also need an Ethernet broadcast filter */ 4776 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 4777 filter_flags, 0); 4778 eth_broadcast_addr(baddr); 4779 efx_filter_set_eth_local(&spec, vlan->vid, baddr); 4780 rc = efx_ef10_filter_insert(efx, &spec, true); 4781 if (rc < 0) { 4782 netif_warn(efx, drv, efx->net_dev, 4783 "Broadcast filter insert failed rc=%d\n", 4784 rc); 4785 if (rollback) { 4786 /* Roll back the mc_def filter */ 4787 efx_ef10_filter_remove_unsafe( 4788 efx, EFX_FILTER_PRI_AUTO, 4789 vlan->mcdef); 4790 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID; 4791 return rc; 4792 } 4793 } else { 4794 EFX_WARN_ON_PARANOID(vlan->bcast != 4795 EFX_EF10_FILTER_ID_INVALID); 4796 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc); 4797 } 4798 } 4799 rc = 0; 4800 } else { 4801 EFX_WARN_ON_PARANOID(vlan->ucdef != EFX_EF10_FILTER_ID_INVALID); 4802 vlan->ucdef = rc; 4803 rc = 0; 4804 } 4805 return rc; 4806 } 4807 4808 /* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD 4809 * flag or removes these filters, we don't need to hold the filter_lock while 4810 * scanning for these filters. 4811 */ 4812 static void efx_ef10_filter_remove_old(struct efx_nic *efx) 4813 { 4814 struct efx_ef10_filter_table *table = efx->filter_state; 4815 int remove_failed = 0; 4816 int remove_noent = 0; 4817 int rc; 4818 int i; 4819 4820 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 4821 if (ACCESS_ONCE(table->entry[i].spec) & 4822 EFX_EF10_FILTER_FLAG_AUTO_OLD) { 4823 rc = efx_ef10_filter_remove_internal(efx, 4824 1U << EFX_FILTER_PRI_AUTO, i, true); 4825 if (rc == -ENOENT) 4826 remove_noent++; 4827 else if (rc) 4828 remove_failed++; 4829 } 4830 } 4831 4832 if (remove_failed) 4833 netif_info(efx, drv, efx->net_dev, 4834 "%s: failed to remove %d filters\n", 4835 __func__, remove_failed); 4836 if (remove_noent) 4837 netif_info(efx, drv, efx->net_dev, 4838 "%s: failed to remove %d non-existent filters\n", 4839 __func__, remove_noent); 4840 } 4841 4842 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx) 4843 { 4844 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4845 u8 mac_old[ETH_ALEN]; 4846 int rc, rc2; 4847 4848 /* Only reconfigure a PF-created vport */ 4849 if (is_zero_ether_addr(nic_data->vport_mac)) 4850 return 0; 4851 4852 efx_device_detach_sync(efx); 4853 efx_net_stop(efx->net_dev); 4854 down_write(&efx->filter_sem); 4855 efx_ef10_filter_table_remove(efx); 4856 up_write(&efx->filter_sem); 4857 4858 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id); 4859 if (rc) 4860 goto restore_filters; 4861 4862 ether_addr_copy(mac_old, nic_data->vport_mac); 4863 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id, 4864 nic_data->vport_mac); 4865 if (rc) 4866 goto restore_vadaptor; 4867 4868 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id, 4869 efx->net_dev->dev_addr); 4870 if (!rc) { 4871 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr); 4872 } else { 4873 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old); 4874 if (rc2) { 4875 /* Failed to add original MAC, so clear vport_mac */ 4876 eth_zero_addr(nic_data->vport_mac); 4877 goto reset_nic; 4878 } 4879 } 4880 4881 restore_vadaptor: 4882 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id); 4883 if (rc2) 4884 goto reset_nic; 4885 restore_filters: 4886 down_write(&efx->filter_sem); 4887 rc2 = efx_ef10_filter_table_probe(efx); 4888 up_write(&efx->filter_sem); 4889 if (rc2) 4890 goto reset_nic; 4891 4892 rc2 = efx_net_open(efx->net_dev); 4893 if (rc2) 4894 goto reset_nic; 4895 4896 netif_device_attach(efx->net_dev); 4897 4898 return rc; 4899 4900 reset_nic: 4901 netif_err(efx, drv, efx->net_dev, 4902 "Failed to restore when changing MAC address - scheduling reset\n"); 4903 efx_schedule_reset(efx, RESET_TYPE_DATAPATH); 4904 4905 return rc ? rc : rc2; 4906 } 4907 4908 /* Caller must hold efx->filter_sem for read if race against 4909 * efx_ef10_filter_table_remove() is possible 4910 */ 4911 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx, 4912 struct efx_ef10_filter_vlan *vlan) 4913 { 4914 struct efx_ef10_filter_table *table = efx->filter_state; 4915 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4916 4917 /* Do not install unspecified VID if VLAN filtering is enabled. 4918 * Do not install all specified VIDs if VLAN filtering is disabled. 4919 */ 4920 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter) 4921 return; 4922 4923 /* Insert/renew unicast filters */ 4924 if (table->uc_promisc) { 4925 efx_ef10_filter_insert_def(efx, vlan, false, false); 4926 efx_ef10_filter_insert_addr_list(efx, vlan, false, false); 4927 } else { 4928 /* If any of the filters failed to insert, fall back to 4929 * promiscuous mode - add in the uc_def filter. But keep 4930 * our individual unicast filters. 4931 */ 4932 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false)) 4933 efx_ef10_filter_insert_def(efx, vlan, false, false); 4934 } 4935 4936 /* Insert/renew multicast filters */ 4937 /* If changing promiscuous state with cascaded multicast filters, remove 4938 * old filters first, so that packets are dropped rather than duplicated 4939 */ 4940 if (nic_data->workaround_26807 && 4941 table->mc_promisc_last != table->mc_promisc) 4942 efx_ef10_filter_remove_old(efx); 4943 if (table->mc_promisc) { 4944 if (nic_data->workaround_26807) { 4945 /* If we failed to insert promiscuous filters, rollback 4946 * and fall back to individual multicast filters 4947 */ 4948 if (efx_ef10_filter_insert_def(efx, vlan, true, true)) { 4949 /* Changing promisc state, so remove old filters */ 4950 efx_ef10_filter_remove_old(efx); 4951 efx_ef10_filter_insert_addr_list(efx, vlan, 4952 true, false); 4953 } 4954 } else { 4955 /* If we failed to insert promiscuous filters, don't 4956 * rollback. Regardless, also insert the mc_list 4957 */ 4958 efx_ef10_filter_insert_def(efx, vlan, true, false); 4959 efx_ef10_filter_insert_addr_list(efx, vlan, true, false); 4960 } 4961 } else { 4962 /* If any filters failed to insert, rollback and fall back to 4963 * promiscuous mode - mc_def filter and maybe broadcast. If 4964 * that fails, roll back again and insert as many of our 4965 * individual multicast filters as we can. 4966 */ 4967 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) { 4968 /* Changing promisc state, so remove old filters */ 4969 if (nic_data->workaround_26807) 4970 efx_ef10_filter_remove_old(efx); 4971 if (efx_ef10_filter_insert_def(efx, vlan, true, true)) 4972 efx_ef10_filter_insert_addr_list(efx, vlan, 4973 true, false); 4974 } 4975 } 4976 } 4977 4978 /* Caller must hold efx->filter_sem for read if race against 4979 * efx_ef10_filter_table_remove() is possible 4980 */ 4981 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx) 4982 { 4983 struct efx_ef10_filter_table *table = efx->filter_state; 4984 struct net_device *net_dev = efx->net_dev; 4985 struct efx_ef10_filter_vlan *vlan; 4986 bool vlan_filter; 4987 4988 if (!efx_dev_registered(efx)) 4989 return; 4990 4991 if (!table) 4992 return; 4993 4994 efx_ef10_filter_mark_old(efx); 4995 4996 /* Copy/convert the address lists; add the primary station 4997 * address and broadcast address 4998 */ 4999 netif_addr_lock_bh(net_dev); 5000 efx_ef10_filter_uc_addr_list(efx); 5001 efx_ef10_filter_mc_addr_list(efx); 5002 netif_addr_unlock_bh(net_dev); 5003 5004 /* If VLAN filtering changes, all old filters are finally removed. 5005 * Do it in advance to avoid conflicts for unicast untagged and 5006 * VLAN 0 tagged filters. 5007 */ 5008 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER); 5009 if (table->vlan_filter != vlan_filter) { 5010 table->vlan_filter = vlan_filter; 5011 efx_ef10_filter_remove_old(efx); 5012 } 5013 5014 list_for_each_entry(vlan, &table->vlan_list, list) 5015 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan); 5016 5017 efx_ef10_filter_remove_old(efx); 5018 table->mc_promisc_last = table->mc_promisc; 5019 } 5020 5021 static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid) 5022 { 5023 struct efx_ef10_filter_table *table = efx->filter_state; 5024 struct efx_ef10_filter_vlan *vlan; 5025 5026 WARN_ON(!rwsem_is_locked(&efx->filter_sem)); 5027 5028 list_for_each_entry(vlan, &table->vlan_list, list) { 5029 if (vlan->vid == vid) 5030 return vlan; 5031 } 5032 5033 return NULL; 5034 } 5035 5036 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid) 5037 { 5038 struct efx_ef10_filter_table *table = efx->filter_state; 5039 struct efx_ef10_filter_vlan *vlan; 5040 unsigned int i; 5041 5042 if (!efx_rwsem_assert_write_locked(&efx->filter_sem)) 5043 return -EINVAL; 5044 5045 vlan = efx_ef10_filter_find_vlan(efx, vid); 5046 if (WARN_ON(vlan)) { 5047 netif_err(efx, drv, efx->net_dev, 5048 "VLAN %u already added\n", vid); 5049 return -EALREADY; 5050 } 5051 5052 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 5053 if (!vlan) 5054 return -ENOMEM; 5055 5056 vlan->vid = vid; 5057 5058 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++) 5059 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID; 5060 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++) 5061 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID; 5062 vlan->ucdef = EFX_EF10_FILTER_ID_INVALID; 5063 vlan->bcast = EFX_EF10_FILTER_ID_INVALID; 5064 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID; 5065 5066 list_add_tail(&vlan->list, &table->vlan_list); 5067 5068 if (efx_dev_registered(efx)) 5069 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan); 5070 5071 return 0; 5072 } 5073 5074 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx, 5075 struct efx_ef10_filter_vlan *vlan) 5076 { 5077 unsigned int i; 5078 5079 /* See comment in efx_ef10_filter_table_remove() */ 5080 if (!efx_rwsem_assert_write_locked(&efx->filter_sem)) 5081 return; 5082 5083 list_del(&vlan->list); 5084 5085 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++) 5086 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, 5087 vlan->uc[i]); 5088 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++) 5089 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, 5090 vlan->mc[i]); 5091 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->ucdef); 5092 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->bcast); 5093 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->mcdef); 5094 5095 kfree(vlan); 5096 } 5097 5098 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid) 5099 { 5100 struct efx_ef10_filter_vlan *vlan; 5101 5102 /* See comment in efx_ef10_filter_table_remove() */ 5103 if (!efx_rwsem_assert_write_locked(&efx->filter_sem)) 5104 return; 5105 5106 vlan = efx_ef10_filter_find_vlan(efx, vid); 5107 if (!vlan) { 5108 netif_err(efx, drv, efx->net_dev, 5109 "VLAN %u not found in filter state\n", vid); 5110 return; 5111 } 5112 5113 efx_ef10_filter_del_vlan_internal(efx, vlan); 5114 } 5115 5116 static int efx_ef10_set_mac_address(struct efx_nic *efx) 5117 { 5118 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN); 5119 struct efx_ef10_nic_data *nic_data = efx->nic_data; 5120 bool was_enabled = efx->port_enabled; 5121 int rc; 5122 5123 efx_device_detach_sync(efx); 5124 efx_net_stop(efx->net_dev); 5125 5126 mutex_lock(&efx->mac_lock); 5127 down_write(&efx->filter_sem); 5128 efx_ef10_filter_table_remove(efx); 5129 5130 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR), 5131 efx->net_dev->dev_addr); 5132 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID, 5133 nic_data->vport_id); 5134 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf, 5135 sizeof(inbuf), NULL, 0, NULL); 5136 5137 efx_ef10_filter_table_probe(efx); 5138 up_write(&efx->filter_sem); 5139 mutex_unlock(&efx->mac_lock); 5140 5141 if (was_enabled) 5142 efx_net_open(efx->net_dev); 5143 netif_device_attach(efx->net_dev); 5144 5145 #ifdef CONFIG_SFC_SRIOV 5146 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) { 5147 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 5148 5149 if (rc == -EPERM) { 5150 struct efx_nic *efx_pf; 5151 5152 /* Switch to PF and change MAC address on vport */ 5153 efx_pf = pci_get_drvdata(pci_dev_pf); 5154 5155 rc = efx_ef10_sriov_set_vf_mac(efx_pf, 5156 nic_data->vf_index, 5157 efx->net_dev->dev_addr); 5158 } else if (!rc) { 5159 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 5160 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data; 5161 unsigned int i; 5162 5163 /* MAC address successfully changed by VF (with MAC 5164 * spoofing) so update the parent PF if possible. 5165 */ 5166 for (i = 0; i < efx_pf->vf_count; ++i) { 5167 struct ef10_vf *vf = nic_data->vf + i; 5168 5169 if (vf->efx == efx) { 5170 ether_addr_copy(vf->mac, 5171 efx->net_dev->dev_addr); 5172 return 0; 5173 } 5174 } 5175 } 5176 } else 5177 #endif 5178 if (rc == -EPERM) { 5179 netif_err(efx, drv, efx->net_dev, 5180 "Cannot change MAC address; use sfboot to enable" 5181 " mac-spoofing on this interface\n"); 5182 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) { 5183 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC 5184 * fall-back to the method of changing the MAC address on the 5185 * vport. This only applies to PFs because such versions of 5186 * MCFW do not support VFs. 5187 */ 5188 rc = efx_ef10_vport_set_mac_address(efx); 5189 } else { 5190 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC, 5191 sizeof(inbuf), NULL, 0, rc); 5192 } 5193 5194 return rc; 5195 } 5196 5197 static int efx_ef10_mac_reconfigure(struct efx_nic *efx) 5198 { 5199 efx_ef10_filter_sync_rx_mode(efx); 5200 5201 return efx_mcdi_set_mac(efx); 5202 } 5203 5204 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx) 5205 { 5206 efx_ef10_filter_sync_rx_mode(efx); 5207 5208 return 0; 5209 } 5210 5211 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 5212 { 5213 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 5214 5215 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 5216 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 5217 NULL, 0, NULL); 5218 } 5219 5220 /* MC BISTs follow a different poll mechanism to phy BISTs. 5221 * The BIST is done in the poll handler on the MC, and the MCDI command 5222 * will block until the BIST is done. 5223 */ 5224 static int efx_ef10_poll_bist(struct efx_nic *efx) 5225 { 5226 int rc; 5227 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 5228 size_t outlen; 5229 u32 result; 5230 5231 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 5232 outbuf, sizeof(outbuf), &outlen); 5233 if (rc != 0) 5234 return rc; 5235 5236 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 5237 return -EIO; 5238 5239 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 5240 switch (result) { 5241 case MC_CMD_POLL_BIST_PASSED: 5242 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 5243 return 0; 5244 case MC_CMD_POLL_BIST_TIMEOUT: 5245 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 5246 return -EIO; 5247 case MC_CMD_POLL_BIST_FAILED: 5248 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 5249 return -EIO; 5250 default: 5251 netif_err(efx, hw, efx->net_dev, 5252 "BIST returned unknown result %u", result); 5253 return -EIO; 5254 } 5255 } 5256 5257 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 5258 { 5259 int rc; 5260 5261 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 5262 5263 rc = efx_ef10_start_bist(efx, bist_type); 5264 if (rc != 0) 5265 return rc; 5266 5267 return efx_ef10_poll_bist(efx); 5268 } 5269 5270 static int 5271 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 5272 { 5273 int rc, rc2; 5274 5275 efx_reset_down(efx, RESET_TYPE_WORLD); 5276 5277 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 5278 NULL, 0, NULL, 0, NULL); 5279 if (rc != 0) 5280 goto out; 5281 5282 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 5283 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 5284 5285 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 5286 5287 out: 5288 if (rc == -EPERM) 5289 rc = 0; 5290 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 5291 return rc ? rc : rc2; 5292 } 5293 5294 #ifdef CONFIG_SFC_MTD 5295 5296 struct efx_ef10_nvram_type_info { 5297 u16 type, type_mask; 5298 u8 port; 5299 const char *name; 5300 }; 5301 5302 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 5303 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 5304 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 5305 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 5306 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 5307 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 5308 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 5309 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 5310 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 5311 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 5312 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 5313 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 5314 }; 5315 5316 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 5317 struct efx_mcdi_mtd_partition *part, 5318 unsigned int type) 5319 { 5320 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 5321 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 5322 const struct efx_ef10_nvram_type_info *info; 5323 size_t size, erase_size, outlen; 5324 bool protected; 5325 int rc; 5326 5327 for (info = efx_ef10_nvram_types; ; info++) { 5328 if (info == 5329 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types)) 5330 return -ENODEV; 5331 if ((type & ~info->type_mask) == info->type) 5332 break; 5333 } 5334 if (info->port != efx_port_num(efx)) 5335 return -ENODEV; 5336 5337 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 5338 if (rc) 5339 return rc; 5340 if (protected) 5341 return -ENODEV; /* hide it */ 5342 5343 part->nvram_type = type; 5344 5345 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 5346 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 5347 outbuf, sizeof(outbuf), &outlen); 5348 if (rc) 5349 return rc; 5350 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 5351 return -EIO; 5352 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 5353 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 5354 part->fw_subtype = MCDI_DWORD(outbuf, 5355 NVRAM_METADATA_OUT_SUBTYPE); 5356 5357 part->common.dev_type_name = "EF10 NVRAM manager"; 5358 part->common.type_name = info->name; 5359 5360 part->common.mtd.type = MTD_NORFLASH; 5361 part->common.mtd.flags = MTD_CAP_NORFLASH; 5362 part->common.mtd.size = size; 5363 part->common.mtd.erasesize = erase_size; 5364 5365 return 0; 5366 } 5367 5368 static int efx_ef10_mtd_probe(struct efx_nic *efx) 5369 { 5370 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 5371 struct efx_mcdi_mtd_partition *parts; 5372 size_t outlen, n_parts_total, i, n_parts; 5373 unsigned int type; 5374 int rc; 5375 5376 ASSERT_RTNL(); 5377 5378 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 5379 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 5380 outbuf, sizeof(outbuf), &outlen); 5381 if (rc) 5382 return rc; 5383 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 5384 return -EIO; 5385 5386 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 5387 if (n_parts_total > 5388 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 5389 return -EIO; 5390 5391 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 5392 if (!parts) 5393 return -ENOMEM; 5394 5395 n_parts = 0; 5396 for (i = 0; i < n_parts_total; i++) { 5397 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 5398 i); 5399 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type); 5400 if (rc == 0) 5401 n_parts++; 5402 else if (rc != -ENODEV) 5403 goto fail; 5404 } 5405 5406 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 5407 fail: 5408 if (rc) 5409 kfree(parts); 5410 return rc; 5411 } 5412 5413 #endif /* CONFIG_SFC_MTD */ 5414 5415 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 5416 { 5417 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 5418 } 5419 5420 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx, 5421 u32 host_time) {} 5422 5423 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 5424 bool temp) 5425 { 5426 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 5427 int rc; 5428 5429 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 5430 channel->sync_events_state == SYNC_EVENTS_VALID || 5431 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 5432 return 0; 5433 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 5434 5435 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 5436 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 5437 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 5438 channel->channel); 5439 5440 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 5441 inbuf, sizeof(inbuf), NULL, 0, NULL); 5442 5443 if (rc != 0) 5444 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 5445 SYNC_EVENTS_DISABLED; 5446 5447 return rc; 5448 } 5449 5450 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 5451 bool temp) 5452 { 5453 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 5454 int rc; 5455 5456 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 5457 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 5458 return 0; 5459 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 5460 channel->sync_events_state = SYNC_EVENTS_DISABLED; 5461 return 0; 5462 } 5463 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 5464 SYNC_EVENTS_DISABLED; 5465 5466 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 5467 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 5468 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 5469 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 5470 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 5471 channel->channel); 5472 5473 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 5474 inbuf, sizeof(inbuf), NULL, 0, NULL); 5475 5476 return rc; 5477 } 5478 5479 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 5480 bool temp) 5481 { 5482 int (*set)(struct efx_channel *channel, bool temp); 5483 struct efx_channel *channel; 5484 5485 set = en ? 5486 efx_ef10_rx_enable_timestamping : 5487 efx_ef10_rx_disable_timestamping; 5488 5489 efx_for_each_channel(channel, efx) { 5490 int rc = set(channel, temp); 5491 if (en && rc != 0) { 5492 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 5493 return rc; 5494 } 5495 } 5496 5497 return 0; 5498 } 5499 5500 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx, 5501 struct hwtstamp_config *init) 5502 { 5503 return -EOPNOTSUPP; 5504 } 5505 5506 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 5507 struct hwtstamp_config *init) 5508 { 5509 int rc; 5510 5511 switch (init->rx_filter) { 5512 case HWTSTAMP_FILTER_NONE: 5513 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 5514 /* if TX timestamping is still requested then leave PTP on */ 5515 return efx_ptp_change_mode(efx, 5516 init->tx_type != HWTSTAMP_TX_OFF, 0); 5517 case HWTSTAMP_FILTER_ALL: 5518 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 5519 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 5520 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 5521 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 5522 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 5523 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 5524 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 5525 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 5526 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 5527 case HWTSTAMP_FILTER_PTP_V2_EVENT: 5528 case HWTSTAMP_FILTER_PTP_V2_SYNC: 5529 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 5530 init->rx_filter = HWTSTAMP_FILTER_ALL; 5531 rc = efx_ptp_change_mode(efx, true, 0); 5532 if (!rc) 5533 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 5534 if (rc) 5535 efx_ptp_change_mode(efx, false, 0); 5536 return rc; 5537 default: 5538 return -ERANGE; 5539 } 5540 } 5541 5542 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid) 5543 { 5544 if (proto != htons(ETH_P_8021Q)) 5545 return -EINVAL; 5546 5547 return efx_ef10_add_vlan(efx, vid); 5548 } 5549 5550 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid) 5551 { 5552 if (proto != htons(ETH_P_8021Q)) 5553 return -EINVAL; 5554 5555 return efx_ef10_del_vlan(efx, vid); 5556 } 5557 5558 #define EF10_OFFLOAD_FEATURES \ 5559 (NETIF_F_IP_CSUM | \ 5560 NETIF_F_HW_VLAN_CTAG_FILTER | \ 5561 NETIF_F_IPV6_CSUM | \ 5562 NETIF_F_RXHASH | \ 5563 NETIF_F_NTUPLE) 5564 5565 const struct efx_nic_type efx_hunt_a0_vf_nic_type = { 5566 .is_vf = true, 5567 .mem_bar = EFX_MEM_VF_BAR, 5568 .mem_map_size = efx_ef10_mem_map_size, 5569 .probe = efx_ef10_probe_vf, 5570 .remove = efx_ef10_remove, 5571 .dimension_resources = efx_ef10_dimension_resources, 5572 .init = efx_ef10_init_nic, 5573 .fini = efx_port_dummy_op_void, 5574 .map_reset_reason = efx_ef10_map_reset_reason, 5575 .map_reset_flags = efx_ef10_map_reset_flags, 5576 .reset = efx_ef10_reset, 5577 .probe_port = efx_mcdi_port_probe, 5578 .remove_port = efx_mcdi_port_remove, 5579 .fini_dmaq = efx_ef10_fini_dmaq, 5580 .prepare_flr = efx_ef10_prepare_flr, 5581 .finish_flr = efx_port_dummy_op_void, 5582 .describe_stats = efx_ef10_describe_stats, 5583 .update_stats = efx_ef10_update_stats_vf, 5584 .start_stats = efx_port_dummy_op_void, 5585 .pull_stats = efx_port_dummy_op_void, 5586 .stop_stats = efx_port_dummy_op_void, 5587 .set_id_led = efx_mcdi_set_id_led, 5588 .push_irq_moderation = efx_ef10_push_irq_moderation, 5589 .reconfigure_mac = efx_ef10_mac_reconfigure_vf, 5590 .check_mac_fault = efx_mcdi_mac_check_fault, 5591 .reconfigure_port = efx_mcdi_port_reconfigure, 5592 .get_wol = efx_ef10_get_wol_vf, 5593 .set_wol = efx_ef10_set_wol_vf, 5594 .resume_wol = efx_port_dummy_op_void, 5595 .mcdi_request = efx_ef10_mcdi_request, 5596 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 5597 .mcdi_read_response = efx_ef10_mcdi_read_response, 5598 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 5599 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 5600 .irq_enable_master = efx_port_dummy_op_void, 5601 .irq_test_generate = efx_ef10_irq_test_generate, 5602 .irq_disable_non_ev = efx_port_dummy_op_void, 5603 .irq_handle_msi = efx_ef10_msi_interrupt, 5604 .irq_handle_legacy = efx_ef10_legacy_interrupt, 5605 .tx_probe = efx_ef10_tx_probe, 5606 .tx_init = efx_ef10_tx_init, 5607 .tx_remove = efx_ef10_tx_remove, 5608 .tx_write = efx_ef10_tx_write, 5609 .tx_limit_len = efx_ef10_tx_limit_len, 5610 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config, 5611 .rx_probe = efx_ef10_rx_probe, 5612 .rx_init = efx_ef10_rx_init, 5613 .rx_remove = efx_ef10_rx_remove, 5614 .rx_write = efx_ef10_rx_write, 5615 .rx_defer_refill = efx_ef10_rx_defer_refill, 5616 .ev_probe = efx_ef10_ev_probe, 5617 .ev_init = efx_ef10_ev_init, 5618 .ev_fini = efx_ef10_ev_fini, 5619 .ev_remove = efx_ef10_ev_remove, 5620 .ev_process = efx_ef10_ev_process, 5621 .ev_read_ack = efx_ef10_ev_read_ack, 5622 .ev_test_generate = efx_ef10_ev_test_generate, 5623 .filter_table_probe = efx_ef10_filter_table_probe, 5624 .filter_table_restore = efx_ef10_filter_table_restore, 5625 .filter_table_remove = efx_ef10_filter_table_remove, 5626 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, 5627 .filter_insert = efx_ef10_filter_insert, 5628 .filter_remove_safe = efx_ef10_filter_remove_safe, 5629 .filter_get_safe = efx_ef10_filter_get_safe, 5630 .filter_clear_rx = efx_ef10_filter_clear_rx, 5631 .filter_count_rx_used = efx_ef10_filter_count_rx_used, 5632 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, 5633 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, 5634 #ifdef CONFIG_RFS_ACCEL 5635 .filter_rfs_insert = efx_ef10_filter_rfs_insert, 5636 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, 5637 #endif 5638 #ifdef CONFIG_SFC_MTD 5639 .mtd_probe = efx_port_dummy_op_int, 5640 #endif 5641 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf, 5642 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf, 5643 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 5644 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 5645 #ifdef CONFIG_SFC_SRIOV 5646 .vswitching_probe = efx_ef10_vswitching_probe_vf, 5647 .vswitching_restore = efx_ef10_vswitching_restore_vf, 5648 .vswitching_remove = efx_ef10_vswitching_remove_vf, 5649 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id, 5650 #endif 5651 .get_mac_address = efx_ef10_get_mac_address_vf, 5652 .set_mac_address = efx_ef10_set_mac_address, 5653 5654 .revision = EFX_REV_HUNT_A0, 5655 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 5656 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 5657 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 5658 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 5659 .can_rx_scatter = true, 5660 .always_rx_scatter = true, 5661 .max_interrupt_mode = EFX_INT_MODE_MSIX, 5662 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 5663 .offload_features = EF10_OFFLOAD_FEATURES, 5664 .mcdi_max_ver = 2, 5665 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, 5666 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 5667 1 << HWTSTAMP_FILTER_ALL, 5668 }; 5669 5670 const struct efx_nic_type efx_hunt_a0_nic_type = { 5671 .is_vf = false, 5672 .mem_bar = EFX_MEM_BAR, 5673 .mem_map_size = efx_ef10_mem_map_size, 5674 .probe = efx_ef10_probe_pf, 5675 .remove = efx_ef10_remove, 5676 .dimension_resources = efx_ef10_dimension_resources, 5677 .init = efx_ef10_init_nic, 5678 .fini = efx_port_dummy_op_void, 5679 .map_reset_reason = efx_ef10_map_reset_reason, 5680 .map_reset_flags = efx_ef10_map_reset_flags, 5681 .reset = efx_ef10_reset, 5682 .probe_port = efx_mcdi_port_probe, 5683 .remove_port = efx_mcdi_port_remove, 5684 .fini_dmaq = efx_ef10_fini_dmaq, 5685 .prepare_flr = efx_ef10_prepare_flr, 5686 .finish_flr = efx_port_dummy_op_void, 5687 .describe_stats = efx_ef10_describe_stats, 5688 .update_stats = efx_ef10_update_stats_pf, 5689 .start_stats = efx_mcdi_mac_start_stats, 5690 .pull_stats = efx_mcdi_mac_pull_stats, 5691 .stop_stats = efx_mcdi_mac_stop_stats, 5692 .set_id_led = efx_mcdi_set_id_led, 5693 .push_irq_moderation = efx_ef10_push_irq_moderation, 5694 .reconfigure_mac = efx_ef10_mac_reconfigure, 5695 .check_mac_fault = efx_mcdi_mac_check_fault, 5696 .reconfigure_port = efx_mcdi_port_reconfigure, 5697 .get_wol = efx_ef10_get_wol, 5698 .set_wol = efx_ef10_set_wol, 5699 .resume_wol = efx_port_dummy_op_void, 5700 .test_chip = efx_ef10_test_chip, 5701 .test_nvram = efx_mcdi_nvram_test_all, 5702 .mcdi_request = efx_ef10_mcdi_request, 5703 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 5704 .mcdi_read_response = efx_ef10_mcdi_read_response, 5705 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 5706 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 5707 .irq_enable_master = efx_port_dummy_op_void, 5708 .irq_test_generate = efx_ef10_irq_test_generate, 5709 .irq_disable_non_ev = efx_port_dummy_op_void, 5710 .irq_handle_msi = efx_ef10_msi_interrupt, 5711 .irq_handle_legacy = efx_ef10_legacy_interrupt, 5712 .tx_probe = efx_ef10_tx_probe, 5713 .tx_init = efx_ef10_tx_init, 5714 .tx_remove = efx_ef10_tx_remove, 5715 .tx_write = efx_ef10_tx_write, 5716 .tx_limit_len = efx_ef10_tx_limit_len, 5717 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config, 5718 .rx_probe = efx_ef10_rx_probe, 5719 .rx_init = efx_ef10_rx_init, 5720 .rx_remove = efx_ef10_rx_remove, 5721 .rx_write = efx_ef10_rx_write, 5722 .rx_defer_refill = efx_ef10_rx_defer_refill, 5723 .ev_probe = efx_ef10_ev_probe, 5724 .ev_init = efx_ef10_ev_init, 5725 .ev_fini = efx_ef10_ev_fini, 5726 .ev_remove = efx_ef10_ev_remove, 5727 .ev_process = efx_ef10_ev_process, 5728 .ev_read_ack = efx_ef10_ev_read_ack, 5729 .ev_test_generate = efx_ef10_ev_test_generate, 5730 .filter_table_probe = efx_ef10_filter_table_probe, 5731 .filter_table_restore = efx_ef10_filter_table_restore, 5732 .filter_table_remove = efx_ef10_filter_table_remove, 5733 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, 5734 .filter_insert = efx_ef10_filter_insert, 5735 .filter_remove_safe = efx_ef10_filter_remove_safe, 5736 .filter_get_safe = efx_ef10_filter_get_safe, 5737 .filter_clear_rx = efx_ef10_filter_clear_rx, 5738 .filter_count_rx_used = efx_ef10_filter_count_rx_used, 5739 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, 5740 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, 5741 #ifdef CONFIG_RFS_ACCEL 5742 .filter_rfs_insert = efx_ef10_filter_rfs_insert, 5743 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, 5744 #endif 5745 #ifdef CONFIG_SFC_MTD 5746 .mtd_probe = efx_ef10_mtd_probe, 5747 .mtd_rename = efx_mcdi_mtd_rename, 5748 .mtd_read = efx_mcdi_mtd_read, 5749 .mtd_erase = efx_mcdi_mtd_erase, 5750 .mtd_write = efx_mcdi_mtd_write, 5751 .mtd_sync = efx_mcdi_mtd_sync, 5752 #endif 5753 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 5754 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 5755 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 5756 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 5757 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 5758 #ifdef CONFIG_SFC_SRIOV 5759 .sriov_configure = efx_ef10_sriov_configure, 5760 .sriov_init = efx_ef10_sriov_init, 5761 .sriov_fini = efx_ef10_sriov_fini, 5762 .sriov_wanted = efx_ef10_sriov_wanted, 5763 .sriov_reset = efx_ef10_sriov_reset, 5764 .sriov_flr = efx_ef10_sriov_flr, 5765 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, 5766 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, 5767 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, 5768 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, 5769 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state, 5770 .vswitching_probe = efx_ef10_vswitching_probe_pf, 5771 .vswitching_restore = efx_ef10_vswitching_restore_pf, 5772 .vswitching_remove = efx_ef10_vswitching_remove_pf, 5773 #endif 5774 .get_mac_address = efx_ef10_get_mac_address_pf, 5775 .set_mac_address = efx_ef10_set_mac_address, 5776 .tso_versions = efx_ef10_tso_versions, 5777 5778 .revision = EFX_REV_HUNT_A0, 5779 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 5780 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 5781 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 5782 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 5783 .can_rx_scatter = true, 5784 .always_rx_scatter = true, 5785 .max_interrupt_mode = EFX_INT_MODE_MSIX, 5786 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 5787 .offload_features = EF10_OFFLOAD_FEATURES, 5788 .mcdi_max_ver = 2, 5789 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, 5790 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 5791 1 << HWTSTAMP_FILTER_ALL, 5792 }; 5793