1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2012-2013 Solarflare Communications Inc. 5 */ 6 7 #include "net_driver.h" 8 #include "rx_common.h" 9 #include "tx_common.h" 10 #include "ef10_regs.h" 11 #include "io.h" 12 #include "mcdi.h" 13 #include "mcdi_pcol.h" 14 #include "mcdi_port.h" 15 #include "mcdi_port_common.h" 16 #include "mcdi_functions.h" 17 #include "nic.h" 18 #include "mcdi_filters.h" 19 #include "workarounds.h" 20 #include "selftest.h" 21 #include "ef10_sriov.h" 22 #include <linux/in.h> 23 #include <linux/jhash.h> 24 #include <linux/wait.h> 25 #include <linux/workqueue.h> 26 #include <net/udp_tunnel.h> 27 28 /* Hardware control for EF10 architecture including 'Huntington'. */ 29 30 #define EFX_EF10_DRVGEN_EV 7 31 enum { 32 EFX_EF10_TEST = 1, 33 EFX_EF10_REFILL, 34 }; 35 36 /* VLAN list entry */ 37 struct efx_ef10_vlan { 38 struct list_head list; 39 u16 vid; 40 }; 41 42 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading); 43 static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels; 44 45 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 46 { 47 efx_dword_t reg; 48 49 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 50 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 51 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 52 } 53 54 /* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for 55 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O 56 * bar; PFs use BAR 0/1 for memory. 57 */ 58 static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx) 59 { 60 switch (efx->pci_dev->device) { 61 case 0x0b03: /* SFC9250 PF */ 62 return 0; 63 default: 64 return 2; 65 } 66 } 67 68 /* All VFs use BAR 0/1 for memory */ 69 static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx) 70 { 71 return 0; 72 } 73 74 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 75 { 76 int bar; 77 78 bar = efx->type->mem_bar(efx); 79 return resource_size(&efx->pci_dev->resource[bar]); 80 } 81 82 static bool efx_ef10_is_vf(struct efx_nic *efx) 83 { 84 return efx->type->is_vf; 85 } 86 87 #ifdef CONFIG_SFC_SRIOV 88 static int efx_ef10_get_vf_index(struct efx_nic *efx) 89 { 90 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 91 struct efx_ef10_nic_data *nic_data = efx->nic_data; 92 size_t outlen; 93 int rc; 94 95 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 96 sizeof(outbuf), &outlen); 97 if (rc) 98 return rc; 99 if (outlen < sizeof(outbuf)) 100 return -EIO; 101 102 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF); 103 return 0; 104 } 105 #endif 106 107 static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 108 { 109 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN); 110 struct efx_ef10_nic_data *nic_data = efx->nic_data; 111 size_t outlen; 112 int rc; 113 114 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 115 116 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 117 outbuf, sizeof(outbuf), &outlen); 118 if (rc) 119 return rc; 120 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) { 121 netif_err(efx, drv, efx->net_dev, 122 "unable to read datapath firmware capabilities\n"); 123 return -EIO; 124 } 125 126 nic_data->datapath_caps = 127 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 128 129 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) { 130 nic_data->datapath_caps2 = MCDI_DWORD(outbuf, 131 GET_CAPABILITIES_V2_OUT_FLAGS2); 132 nic_data->piobuf_size = MCDI_WORD(outbuf, 133 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF); 134 } else { 135 nic_data->datapath_caps2 = 0; 136 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE; 137 } 138 139 /* record the DPCPU firmware IDs to determine VEB vswitching support. 140 */ 141 nic_data->rx_dpcpu_fw_id = 142 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); 143 nic_data->tx_dpcpu_fw_id = 144 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); 145 146 if (!(nic_data->datapath_caps & 147 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 148 netif_err(efx, probe, efx->net_dev, 149 "current firmware does not support an RX prefix\n"); 150 return -ENODEV; 151 } 152 153 if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) { 154 u8 vi_window_mode = MCDI_BYTE(outbuf, 155 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); 156 157 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode); 158 if (rc) 159 return rc; 160 } else { 161 /* keep default VI stride */ 162 netif_dbg(efx, probe, efx->net_dev, 163 "firmware did not report VI window mode, assuming vi_stride = %u\n", 164 efx->vi_stride); 165 } 166 167 if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) { 168 efx->num_mac_stats = MCDI_WORD(outbuf, 169 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS); 170 netif_dbg(efx, probe, efx->net_dev, 171 "firmware reports num_mac_stats = %u\n", 172 efx->num_mac_stats); 173 } else { 174 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */ 175 netif_dbg(efx, probe, efx->net_dev, 176 "firmware did not report num_mac_stats, assuming %u\n", 177 efx->num_mac_stats); 178 } 179 180 return 0; 181 } 182 183 static void efx_ef10_read_licensed_features(struct efx_nic *efx) 184 { 185 MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN); 186 MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN); 187 struct efx_ef10_nic_data *nic_data = efx->nic_data; 188 size_t outlen; 189 int rc; 190 191 MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP, 192 MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE); 193 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf, sizeof(inbuf), 194 outbuf, sizeof(outbuf), &outlen); 195 if (rc || (outlen < MC_CMD_LICENSING_V3_OUT_LEN)) 196 return; 197 198 nic_data->licensed_features = MCDI_QWORD(outbuf, 199 LICENSING_V3_OUT_LICENSED_FEATURES); 200 } 201 202 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 203 { 204 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 205 int rc; 206 207 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 208 outbuf, sizeof(outbuf), NULL); 209 if (rc) 210 return rc; 211 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 212 return rc > 0 ? rc : -ERANGE; 213 } 214 215 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx) 216 { 217 struct efx_ef10_nic_data *nic_data = efx->nic_data; 218 unsigned int implemented; 219 unsigned int enabled; 220 int rc; 221 222 nic_data->workaround_35388 = false; 223 nic_data->workaround_61265 = false; 224 225 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 226 227 if (rc == -ENOSYS) { 228 /* Firmware without GET_WORKAROUNDS - not a problem. */ 229 rc = 0; 230 } else if (rc == 0) { 231 /* Bug61265 workaround is always enabled if implemented. */ 232 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265) 233 nic_data->workaround_61265 = true; 234 235 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 236 nic_data->workaround_35388 = true; 237 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 238 /* Workaround is implemented but not enabled. 239 * Try to enable it. 240 */ 241 rc = efx_mcdi_set_workaround(efx, 242 MC_CMD_WORKAROUND_BUG35388, 243 true, NULL); 244 if (rc == 0) 245 nic_data->workaround_35388 = true; 246 /* If we failed to set the workaround just carry on. */ 247 rc = 0; 248 } 249 } 250 251 netif_dbg(efx, probe, efx->net_dev, 252 "workaround for bug 35388 is %sabled\n", 253 nic_data->workaround_35388 ? "en" : "dis"); 254 netif_dbg(efx, probe, efx->net_dev, 255 "workaround for bug 61265 is %sabled\n", 256 nic_data->workaround_61265 ? "en" : "dis"); 257 258 return rc; 259 } 260 261 static void efx_ef10_process_timer_config(struct efx_nic *efx, 262 const efx_dword_t *data) 263 { 264 unsigned int max_count; 265 266 if (EFX_EF10_WORKAROUND_61265(efx)) { 267 efx->timer_quantum_ns = MCDI_DWORD(data, 268 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS); 269 efx->timer_max_ns = MCDI_DWORD(data, 270 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS); 271 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 272 efx->timer_quantum_ns = MCDI_DWORD(data, 273 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT); 274 max_count = MCDI_DWORD(data, 275 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT); 276 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 277 } else { 278 efx->timer_quantum_ns = MCDI_DWORD(data, 279 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT); 280 max_count = MCDI_DWORD(data, 281 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT); 282 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 283 } 284 285 netif_dbg(efx, probe, efx->net_dev, 286 "got timer properties from MC: quantum %u ns; max %u ns\n", 287 efx->timer_quantum_ns, efx->timer_max_ns); 288 } 289 290 static int efx_ef10_get_timer_config(struct efx_nic *efx) 291 { 292 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN); 293 int rc; 294 295 rc = efx_ef10_get_timer_workarounds(efx); 296 if (rc) 297 return rc; 298 299 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0, 300 outbuf, sizeof(outbuf), NULL); 301 302 if (rc == 0) { 303 efx_ef10_process_timer_config(efx, outbuf); 304 } else if (rc == -ENOSYS || rc == -EPERM) { 305 /* Not available - fall back to Huntington defaults. */ 306 unsigned int quantum; 307 308 rc = efx_ef10_get_sysclk_freq(efx); 309 if (rc < 0) 310 return rc; 311 312 quantum = 1536000 / rc; /* 1536 cycles */ 313 efx->timer_quantum_ns = quantum; 314 efx->timer_max_ns = efx->type->timer_period_max * quantum; 315 rc = 0; 316 } else { 317 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, 318 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN, 319 NULL, 0, rc); 320 } 321 322 return rc; 323 } 324 325 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address) 326 { 327 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 328 size_t outlen; 329 int rc; 330 331 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 332 333 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 334 outbuf, sizeof(outbuf), &outlen); 335 if (rc) 336 return rc; 337 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 338 return -EIO; 339 340 ether_addr_copy(mac_address, 341 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 342 return 0; 343 } 344 345 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address) 346 { 347 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN); 348 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 349 size_t outlen; 350 int num_addrs, rc; 351 352 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 353 EVB_PORT_ID_ASSIGNED); 354 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf, 355 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 356 357 if (rc) 358 return rc; 359 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) 360 return -EIO; 361 362 num_addrs = MCDI_DWORD(outbuf, 363 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT); 364 365 WARN_ON(num_addrs != 1); 366 367 ether_addr_copy(mac_address, 368 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR)); 369 370 return 0; 371 } 372 373 static ssize_t efx_ef10_show_link_control_flag(struct device *dev, 374 struct device_attribute *attr, 375 char *buf) 376 { 377 struct efx_nic *efx = dev_get_drvdata(dev); 378 379 return sprintf(buf, "%d\n", 380 ((efx->mcdi->fn_flags) & 381 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 382 ? 1 : 0); 383 } 384 385 static ssize_t efx_ef10_show_primary_flag(struct device *dev, 386 struct device_attribute *attr, 387 char *buf) 388 { 389 struct efx_nic *efx = dev_get_drvdata(dev); 390 391 return sprintf(buf, "%d\n", 392 ((efx->mcdi->fn_flags) & 393 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)) 394 ? 1 : 0); 395 } 396 397 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid) 398 { 399 struct efx_ef10_nic_data *nic_data = efx->nic_data; 400 struct efx_ef10_vlan *vlan; 401 402 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 403 404 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 405 if (vlan->vid == vid) 406 return vlan; 407 } 408 409 return NULL; 410 } 411 412 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid) 413 { 414 struct efx_ef10_nic_data *nic_data = efx->nic_data; 415 struct efx_ef10_vlan *vlan; 416 int rc; 417 418 mutex_lock(&nic_data->vlan_lock); 419 420 vlan = efx_ef10_find_vlan(efx, vid); 421 if (vlan) { 422 /* We add VID 0 on init. 8021q adds it on module init 423 * for all interfaces with VLAN filtring feature. 424 */ 425 if (vid == 0) 426 goto done_unlock; 427 netif_warn(efx, drv, efx->net_dev, 428 "VLAN %u already added\n", vid); 429 rc = -EALREADY; 430 goto fail_exist; 431 } 432 433 rc = -ENOMEM; 434 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 435 if (!vlan) 436 goto fail_alloc; 437 438 vlan->vid = vid; 439 440 list_add_tail(&vlan->list, &nic_data->vlan_list); 441 442 if (efx->filter_state) { 443 mutex_lock(&efx->mac_lock); 444 down_write(&efx->filter_sem); 445 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 446 up_write(&efx->filter_sem); 447 mutex_unlock(&efx->mac_lock); 448 if (rc) 449 goto fail_filter_add_vlan; 450 } 451 452 done_unlock: 453 mutex_unlock(&nic_data->vlan_lock); 454 return 0; 455 456 fail_filter_add_vlan: 457 list_del(&vlan->list); 458 kfree(vlan); 459 fail_alloc: 460 fail_exist: 461 mutex_unlock(&nic_data->vlan_lock); 462 return rc; 463 } 464 465 static void efx_ef10_del_vlan_internal(struct efx_nic *efx, 466 struct efx_ef10_vlan *vlan) 467 { 468 struct efx_ef10_nic_data *nic_data = efx->nic_data; 469 470 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 471 472 if (efx->filter_state) { 473 down_write(&efx->filter_sem); 474 efx_mcdi_filter_del_vlan(efx, vlan->vid); 475 up_write(&efx->filter_sem); 476 } 477 478 list_del(&vlan->list); 479 kfree(vlan); 480 } 481 482 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid) 483 { 484 struct efx_ef10_nic_data *nic_data = efx->nic_data; 485 struct efx_ef10_vlan *vlan; 486 int rc = 0; 487 488 /* 8021q removes VID 0 on module unload for all interfaces 489 * with VLAN filtering feature. We need to keep it to receive 490 * untagged traffic. 491 */ 492 if (vid == 0) 493 return 0; 494 495 mutex_lock(&nic_data->vlan_lock); 496 497 vlan = efx_ef10_find_vlan(efx, vid); 498 if (!vlan) { 499 netif_err(efx, drv, efx->net_dev, 500 "VLAN %u to be deleted not found\n", vid); 501 rc = -ENOENT; 502 } else { 503 efx_ef10_del_vlan_internal(efx, vlan); 504 } 505 506 mutex_unlock(&nic_data->vlan_lock); 507 508 return rc; 509 } 510 511 static void efx_ef10_cleanup_vlans(struct efx_nic *efx) 512 { 513 struct efx_ef10_nic_data *nic_data = efx->nic_data; 514 struct efx_ef10_vlan *vlan, *next_vlan; 515 516 mutex_lock(&nic_data->vlan_lock); 517 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list) 518 efx_ef10_del_vlan_internal(efx, vlan); 519 mutex_unlock(&nic_data->vlan_lock); 520 } 521 522 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag, 523 NULL); 524 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL); 525 526 static int efx_ef10_probe(struct efx_nic *efx) 527 { 528 struct efx_ef10_nic_data *nic_data; 529 int i, rc; 530 531 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 532 if (!nic_data) 533 return -ENOMEM; 534 efx->nic_data = nic_data; 535 536 /* we assume later that we can copy from this buffer in dwords */ 537 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 538 539 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 540 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 541 if (rc) 542 goto fail1; 543 544 /* Get the MC's warm boot count. In case it's rebooting right 545 * now, be prepared to retry. 546 */ 547 i = 0; 548 for (;;) { 549 rc = efx_ef10_get_warm_boot_count(efx); 550 if (rc >= 0) 551 break; 552 if (++i == 5) 553 goto fail2; 554 ssleep(1); 555 } 556 nic_data->warm_boot_count = rc; 557 558 /* In case we're recovering from a crash (kexec), we want to 559 * cancel any outstanding request by the previous user of this 560 * function. We send a special message using the least 561 * significant bits of the 'high' (doorbell) register. 562 */ 563 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 564 565 rc = efx_mcdi_init(efx); 566 if (rc) 567 goto fail2; 568 569 mutex_init(&nic_data->udp_tunnels_lock); 570 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) 571 nic_data->udp_tunnels[i].type = 572 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID; 573 574 /* Reset (most) configuration for this function */ 575 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 576 if (rc) 577 goto fail3; 578 579 /* Enable event logging */ 580 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 581 if (rc) 582 goto fail3; 583 584 rc = device_create_file(&efx->pci_dev->dev, 585 &dev_attr_link_control_flag); 586 if (rc) 587 goto fail3; 588 589 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 590 if (rc) 591 goto fail4; 592 593 rc = efx_get_pf_index(efx, &nic_data->pf_index); 594 if (rc) 595 goto fail5; 596 597 rc = efx_ef10_init_datapath_caps(efx); 598 if (rc < 0) 599 goto fail5; 600 601 efx_ef10_read_licensed_features(efx); 602 603 /* We can have one VI for each vi_stride-byte region. 604 * However, until we use TX option descriptors we need up to four 605 * TX queues per channel for different checksumming combinations. 606 */ 607 if (nic_data->datapath_caps & 608 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)) 609 efx->tx_queues_per_channel = 4; 610 else 611 efx->tx_queues_per_channel = 2; 612 efx->max_vis = efx_ef10_mem_map_size(efx) / efx->vi_stride; 613 if (!efx->max_vis) { 614 netif_err(efx, drv, efx->net_dev, "error determining max VIs\n"); 615 rc = -EIO; 616 goto fail5; 617 } 618 efx->max_channels = min_t(unsigned int, EFX_MAX_CHANNELS, 619 efx->max_vis / efx->tx_queues_per_channel); 620 efx->max_tx_channels = efx->max_channels; 621 if (WARN_ON(efx->max_channels == 0)) { 622 rc = -EIO; 623 goto fail5; 624 } 625 626 efx->rx_packet_len_offset = 627 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 628 629 if (nic_data->datapath_caps & 630 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN)) 631 efx->net_dev->hw_features |= NETIF_F_RXFCS; 632 633 rc = efx_mcdi_port_get_number(efx); 634 if (rc < 0) 635 goto fail5; 636 efx->port_num = rc; 637 638 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr); 639 if (rc) 640 goto fail5; 641 642 rc = efx_ef10_get_timer_config(efx); 643 if (rc < 0) 644 goto fail5; 645 646 rc = efx_mcdi_mon_probe(efx); 647 if (rc && rc != -EPERM) 648 goto fail5; 649 650 efx_ptp_defer_probe_with_channel(efx); 651 652 #ifdef CONFIG_SFC_SRIOV 653 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) { 654 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 655 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 656 657 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id); 658 } else 659 #endif 660 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr); 661 662 INIT_LIST_HEAD(&nic_data->vlan_list); 663 mutex_init(&nic_data->vlan_lock); 664 665 /* Add unspecified VID to support VLAN filtering being disabled */ 666 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC); 667 if (rc) 668 goto fail_add_vid_unspec; 669 670 /* If VLAN filtering is enabled, we need VID 0 to get untagged 671 * traffic. It is added automatically if 8021q module is loaded, 672 * but we can't rely on it since module may be not loaded. 673 */ 674 rc = efx_ef10_add_vlan(efx, 0); 675 if (rc) 676 goto fail_add_vid_0; 677 678 if (nic_data->datapath_caps & 679 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) && 680 efx->mcdi->fn_flags & 681 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)) 682 efx->net_dev->udp_tunnel_nic_info = &efx_ef10_udp_tunnels; 683 684 return 0; 685 686 fail_add_vid_0: 687 efx_ef10_cleanup_vlans(efx); 688 fail_add_vid_unspec: 689 mutex_destroy(&nic_data->vlan_lock); 690 efx_ptp_remove(efx); 691 efx_mcdi_mon_remove(efx); 692 fail5: 693 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 694 fail4: 695 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 696 fail3: 697 efx_mcdi_detach(efx); 698 699 mutex_lock(&nic_data->udp_tunnels_lock); 700 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 701 (void)efx_ef10_set_udp_tnl_ports(efx, true); 702 mutex_unlock(&nic_data->udp_tunnels_lock); 703 mutex_destroy(&nic_data->udp_tunnels_lock); 704 705 efx_mcdi_fini(efx); 706 fail2: 707 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 708 fail1: 709 kfree(nic_data); 710 efx->nic_data = NULL; 711 return rc; 712 } 713 714 #ifdef EFX_USE_PIO 715 716 static void efx_ef10_free_piobufs(struct efx_nic *efx) 717 { 718 struct efx_ef10_nic_data *nic_data = efx->nic_data; 719 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 720 unsigned int i; 721 int rc; 722 723 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 724 725 for (i = 0; i < nic_data->n_piobufs; i++) { 726 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 727 nic_data->piobuf_handle[i]); 728 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 729 NULL, 0, NULL); 730 WARN_ON(rc); 731 } 732 733 nic_data->n_piobufs = 0; 734 } 735 736 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 737 { 738 struct efx_ef10_nic_data *nic_data = efx->nic_data; 739 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 740 unsigned int i; 741 size_t outlen; 742 int rc = 0; 743 744 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 745 746 for (i = 0; i < n; i++) { 747 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 748 outbuf, sizeof(outbuf), &outlen); 749 if (rc) { 750 /* Don't display the MC error if we didn't have space 751 * for a VF. 752 */ 753 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC)) 754 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF, 755 0, outbuf, outlen, rc); 756 break; 757 } 758 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 759 rc = -EIO; 760 break; 761 } 762 nic_data->piobuf_handle[i] = 763 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 764 netif_dbg(efx, probe, efx->net_dev, 765 "allocated PIO buffer %u handle %x\n", i, 766 nic_data->piobuf_handle[i]); 767 } 768 769 nic_data->n_piobufs = i; 770 if (rc) 771 efx_ef10_free_piobufs(efx); 772 return rc; 773 } 774 775 static int efx_ef10_link_piobufs(struct efx_nic *efx) 776 { 777 struct efx_ef10_nic_data *nic_data = efx->nic_data; 778 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN); 779 struct efx_channel *channel; 780 struct efx_tx_queue *tx_queue; 781 unsigned int offset, index; 782 int rc; 783 784 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 785 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 786 787 /* Link a buffer to each VI in the write-combining mapping */ 788 for (index = 0; index < nic_data->n_piobufs; ++index) { 789 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 790 nic_data->piobuf_handle[index]); 791 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 792 nic_data->pio_write_vi_base + index); 793 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 794 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 795 NULL, 0, NULL); 796 if (rc) { 797 netif_err(efx, drv, efx->net_dev, 798 "failed to link VI %u to PIO buffer %u (%d)\n", 799 nic_data->pio_write_vi_base + index, index, 800 rc); 801 goto fail; 802 } 803 netif_dbg(efx, probe, efx->net_dev, 804 "linked VI %u to PIO buffer %u\n", 805 nic_data->pio_write_vi_base + index, index); 806 } 807 808 /* Link a buffer to each TX queue */ 809 efx_for_each_channel(channel, efx) { 810 /* Extra channels, even those with TXQs (PTP), do not require 811 * PIO resources. 812 */ 813 if (!channel->type->want_pio || 814 channel->channel >= efx->xdp_channel_offset) 815 continue; 816 817 efx_for_each_channel_tx_queue(tx_queue, channel) { 818 /* We assign the PIO buffers to queues in 819 * reverse order to allow for the following 820 * special case. 821 */ 822 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 823 tx_queue->channel->channel - 1) * 824 efx_piobuf_size); 825 index = offset / nic_data->piobuf_size; 826 offset = offset % nic_data->piobuf_size; 827 828 /* When the host page size is 4K, the first 829 * host page in the WC mapping may be within 830 * the same VI page as the last TX queue. We 831 * can only link one buffer to each VI. 832 */ 833 if (tx_queue->queue == nic_data->pio_write_vi_base) { 834 BUG_ON(index != 0); 835 rc = 0; 836 } else { 837 MCDI_SET_DWORD(inbuf, 838 LINK_PIOBUF_IN_PIOBUF_HANDLE, 839 nic_data->piobuf_handle[index]); 840 MCDI_SET_DWORD(inbuf, 841 LINK_PIOBUF_IN_TXQ_INSTANCE, 842 tx_queue->queue); 843 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 844 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 845 NULL, 0, NULL); 846 } 847 848 if (rc) { 849 /* This is non-fatal; the TX path just 850 * won't use PIO for this queue 851 */ 852 netif_err(efx, drv, efx->net_dev, 853 "failed to link VI %u to PIO buffer %u (%d)\n", 854 tx_queue->queue, index, rc); 855 tx_queue->piobuf = NULL; 856 } else { 857 tx_queue->piobuf = 858 nic_data->pio_write_base + 859 index * efx->vi_stride + offset; 860 tx_queue->piobuf_offset = offset; 861 netif_dbg(efx, probe, efx->net_dev, 862 "linked VI %u to PIO buffer %u offset %x addr %p\n", 863 tx_queue->queue, index, 864 tx_queue->piobuf_offset, 865 tx_queue->piobuf); 866 } 867 } 868 } 869 870 return 0; 871 872 fail: 873 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same 874 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter. 875 */ 876 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN); 877 while (index--) { 878 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 879 nic_data->pio_write_vi_base + index); 880 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 881 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 882 NULL, 0, NULL); 883 } 884 return rc; 885 } 886 887 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 888 { 889 struct efx_channel *channel; 890 struct efx_tx_queue *tx_queue; 891 892 /* All our existing PIO buffers went away */ 893 efx_for_each_channel(channel, efx) 894 efx_for_each_channel_tx_queue(tx_queue, channel) 895 tx_queue->piobuf = NULL; 896 } 897 898 #else /* !EFX_USE_PIO */ 899 900 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 901 { 902 return n == 0 ? 0 : -ENOBUFS; 903 } 904 905 static int efx_ef10_link_piobufs(struct efx_nic *efx) 906 { 907 return 0; 908 } 909 910 static void efx_ef10_free_piobufs(struct efx_nic *efx) 911 { 912 } 913 914 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 915 { 916 } 917 918 #endif /* EFX_USE_PIO */ 919 920 static void efx_ef10_remove(struct efx_nic *efx) 921 { 922 struct efx_ef10_nic_data *nic_data = efx->nic_data; 923 int rc; 924 925 #ifdef CONFIG_SFC_SRIOV 926 struct efx_ef10_nic_data *nic_data_pf; 927 struct pci_dev *pci_dev_pf; 928 struct efx_nic *efx_pf; 929 struct ef10_vf *vf; 930 931 if (efx->pci_dev->is_virtfn) { 932 pci_dev_pf = efx->pci_dev->physfn; 933 if (pci_dev_pf) { 934 efx_pf = pci_get_drvdata(pci_dev_pf); 935 nic_data_pf = efx_pf->nic_data; 936 vf = nic_data_pf->vf + nic_data->vf_index; 937 vf->efx = NULL; 938 } else 939 netif_info(efx, drv, efx->net_dev, 940 "Could not get the PF id from VF\n"); 941 } 942 #endif 943 944 efx_ef10_cleanup_vlans(efx); 945 mutex_destroy(&nic_data->vlan_lock); 946 947 efx_ptp_remove(efx); 948 949 efx_mcdi_mon_remove(efx); 950 951 efx_mcdi_rx_free_indir_table(efx); 952 953 if (nic_data->wc_membase) 954 iounmap(nic_data->wc_membase); 955 956 rc = efx_mcdi_free_vis(efx); 957 WARN_ON(rc != 0); 958 959 if (!nic_data->must_restore_piobufs) 960 efx_ef10_free_piobufs(efx); 961 962 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 963 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 964 965 efx_mcdi_detach(efx); 966 967 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 968 mutex_lock(&nic_data->udp_tunnels_lock); 969 (void)efx_ef10_set_udp_tnl_ports(efx, true); 970 mutex_unlock(&nic_data->udp_tunnels_lock); 971 972 mutex_destroy(&nic_data->udp_tunnels_lock); 973 974 efx_mcdi_fini(efx); 975 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 976 kfree(nic_data); 977 } 978 979 static int efx_ef10_probe_pf(struct efx_nic *efx) 980 { 981 return efx_ef10_probe(efx); 982 } 983 984 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id, 985 u32 *port_flags, u32 *vadaptor_flags, 986 unsigned int *vlan_tags) 987 { 988 struct efx_ef10_nic_data *nic_data = efx->nic_data; 989 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN); 990 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN); 991 size_t outlen; 992 int rc; 993 994 if (nic_data->datapath_caps & 995 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) { 996 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID, 997 port_id); 998 999 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf), 1000 outbuf, sizeof(outbuf), &outlen); 1001 if (rc) 1002 return rc; 1003 1004 if (outlen < sizeof(outbuf)) { 1005 rc = -EIO; 1006 return rc; 1007 } 1008 } 1009 1010 if (port_flags) 1011 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS); 1012 if (vadaptor_flags) 1013 *vadaptor_flags = 1014 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS); 1015 if (vlan_tags) 1016 *vlan_tags = 1017 MCDI_DWORD(outbuf, 1018 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS); 1019 1020 return 0; 1021 } 1022 1023 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id) 1024 { 1025 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN); 1026 1027 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 1028 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf), 1029 NULL, 0, NULL); 1030 } 1031 1032 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id) 1033 { 1034 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN); 1035 1036 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 1037 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf), 1038 NULL, 0, NULL); 1039 } 1040 1041 int efx_ef10_vport_add_mac(struct efx_nic *efx, 1042 unsigned int port_id, u8 *mac) 1043 { 1044 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN); 1045 1046 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id); 1047 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac); 1048 1049 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf, 1050 sizeof(inbuf), NULL, 0, NULL); 1051 } 1052 1053 int efx_ef10_vport_del_mac(struct efx_nic *efx, 1054 unsigned int port_id, u8 *mac) 1055 { 1056 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN); 1057 1058 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id); 1059 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac); 1060 1061 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf, 1062 sizeof(inbuf), NULL, 0, NULL); 1063 } 1064 1065 #ifdef CONFIG_SFC_SRIOV 1066 static int efx_ef10_probe_vf(struct efx_nic *efx) 1067 { 1068 int rc; 1069 struct pci_dev *pci_dev_pf; 1070 1071 /* If the parent PF has no VF data structure, it doesn't know about this 1072 * VF so fail probe. The VF needs to be re-created. This can happen 1073 * if the PF driver is unloaded while the VF is assigned to a guest. 1074 */ 1075 pci_dev_pf = efx->pci_dev->physfn; 1076 if (pci_dev_pf) { 1077 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 1078 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data; 1079 1080 if (!nic_data_pf->vf) { 1081 netif_info(efx, drv, efx->net_dev, 1082 "The VF cannot link to its parent PF; " 1083 "please destroy and re-create the VF\n"); 1084 return -EBUSY; 1085 } 1086 } 1087 1088 rc = efx_ef10_probe(efx); 1089 if (rc) 1090 return rc; 1091 1092 rc = efx_ef10_get_vf_index(efx); 1093 if (rc) 1094 goto fail; 1095 1096 if (efx->pci_dev->is_virtfn) { 1097 if (efx->pci_dev->physfn) { 1098 struct efx_nic *efx_pf = 1099 pci_get_drvdata(efx->pci_dev->physfn); 1100 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data; 1101 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1102 1103 nic_data_p->vf[nic_data->vf_index].efx = efx; 1104 nic_data_p->vf[nic_data->vf_index].pci_dev = 1105 efx->pci_dev; 1106 } else 1107 netif_info(efx, drv, efx->net_dev, 1108 "Could not get the PF id from VF\n"); 1109 } 1110 1111 return 0; 1112 1113 fail: 1114 efx_ef10_remove(efx); 1115 return rc; 1116 } 1117 #else 1118 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused))) 1119 { 1120 return 0; 1121 } 1122 #endif 1123 1124 static int efx_ef10_alloc_vis(struct efx_nic *efx, 1125 unsigned int min_vis, unsigned int max_vis) 1126 { 1127 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1128 1129 return efx_mcdi_alloc_vis(efx, min_vis, max_vis, &nic_data->vi_base, 1130 &nic_data->n_allocated_vis); 1131 } 1132 1133 /* Note that the failure path of this function does not free 1134 * resources, as this will be done by efx_ef10_remove(). 1135 */ 1136 static int efx_ef10_dimension_resources(struct efx_nic *efx) 1137 { 1138 unsigned int min_vis = max_t(unsigned int, efx->tx_queues_per_channel, 1139 efx_separate_tx_channels ? 2 : 1); 1140 unsigned int channel_vis, pio_write_vi_base, max_vis; 1141 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1142 unsigned int uc_mem_map_size, wc_mem_map_size; 1143 void __iomem *membase; 1144 int rc; 1145 1146 channel_vis = max(efx->n_channels, 1147 ((efx->n_tx_channels + efx->n_extra_tx_channels) * 1148 efx->tx_queues_per_channel) + 1149 efx->n_xdp_channels * efx->xdp_tx_per_channel); 1150 if (efx->max_vis && efx->max_vis < channel_vis) { 1151 netif_dbg(efx, drv, efx->net_dev, 1152 "Reducing channel VIs from %u to %u\n", 1153 channel_vis, efx->max_vis); 1154 channel_vis = efx->max_vis; 1155 } 1156 1157 #ifdef EFX_USE_PIO 1158 /* Try to allocate PIO buffers if wanted and if the full 1159 * number of PIO buffers would be sufficient to allocate one 1160 * copy-buffer per TX channel. Failure is non-fatal, as there 1161 * are only a small number of PIO buffers shared between all 1162 * functions of the controller. 1163 */ 1164 if (efx_piobuf_size != 0 && 1165 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 1166 efx->n_tx_channels) { 1167 unsigned int n_piobufs = 1168 DIV_ROUND_UP(efx->n_tx_channels, 1169 nic_data->piobuf_size / efx_piobuf_size); 1170 1171 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 1172 if (rc == -ENOSPC) 1173 netif_dbg(efx, probe, efx->net_dev, 1174 "out of PIO buffers; cannot allocate more\n"); 1175 else if (rc == -EPERM) 1176 netif_dbg(efx, probe, efx->net_dev, 1177 "not permitted to allocate PIO buffers\n"); 1178 else if (rc) 1179 netif_err(efx, probe, efx->net_dev, 1180 "failed to allocate PIO buffers (%d)\n", rc); 1181 else 1182 netif_dbg(efx, probe, efx->net_dev, 1183 "allocated %u PIO buffers\n", n_piobufs); 1184 } 1185 #else 1186 nic_data->n_piobufs = 0; 1187 #endif 1188 1189 /* PIO buffers should be mapped with write-combining enabled, 1190 * and we want to make single UC and WC mappings rather than 1191 * several of each (in fact that's the only option if host 1192 * page size is >4K). So we may allocate some extra VIs just 1193 * for writing PIO buffers through. 1194 * 1195 * The UC mapping contains (channel_vis - 1) complete VIs and the 1196 * first 4K of the next VI. Then the WC mapping begins with 1197 * the remainder of this last VI. 1198 */ 1199 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride + 1200 ER_DZ_TX_PIOBUF); 1201 if (nic_data->n_piobufs) { 1202 /* pio_write_vi_base rounds down to give the number of complete 1203 * VIs inside the UC mapping. 1204 */ 1205 pio_write_vi_base = uc_mem_map_size / efx->vi_stride; 1206 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 1207 nic_data->n_piobufs) * 1208 efx->vi_stride) - 1209 uc_mem_map_size); 1210 max_vis = pio_write_vi_base + nic_data->n_piobufs; 1211 } else { 1212 pio_write_vi_base = 0; 1213 wc_mem_map_size = 0; 1214 max_vis = channel_vis; 1215 } 1216 1217 /* In case the last attached driver failed to free VIs, do it now */ 1218 rc = efx_mcdi_free_vis(efx); 1219 if (rc != 0) 1220 return rc; 1221 1222 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 1223 if (rc != 0) 1224 return rc; 1225 1226 if (nic_data->n_allocated_vis < channel_vis) { 1227 netif_info(efx, drv, efx->net_dev, 1228 "Could not allocate enough VIs to satisfy RSS" 1229 " requirements. Performance may not be optimal.\n"); 1230 /* We didn't get the VIs to populate our channels. 1231 * We could keep what we got but then we'd have more 1232 * interrupts than we need. 1233 * Instead calculate new max_channels and restart 1234 */ 1235 efx->max_channels = nic_data->n_allocated_vis; 1236 efx->max_tx_channels = 1237 nic_data->n_allocated_vis / efx->tx_queues_per_channel; 1238 1239 efx_mcdi_free_vis(efx); 1240 return -EAGAIN; 1241 } 1242 1243 /* If we didn't get enough VIs to map all the PIO buffers, free the 1244 * PIO buffers 1245 */ 1246 if (nic_data->n_piobufs && 1247 nic_data->n_allocated_vis < 1248 pio_write_vi_base + nic_data->n_piobufs) { 1249 netif_dbg(efx, probe, efx->net_dev, 1250 "%u VIs are not sufficient to map %u PIO buffers\n", 1251 nic_data->n_allocated_vis, nic_data->n_piobufs); 1252 efx_ef10_free_piobufs(efx); 1253 } 1254 1255 /* Shrink the original UC mapping of the memory BAR */ 1256 membase = ioremap(efx->membase_phys, uc_mem_map_size); 1257 if (!membase) { 1258 netif_err(efx, probe, efx->net_dev, 1259 "could not shrink memory BAR to %x\n", 1260 uc_mem_map_size); 1261 return -ENOMEM; 1262 } 1263 iounmap(efx->membase); 1264 efx->membase = membase; 1265 1266 /* Set up the WC mapping if needed */ 1267 if (wc_mem_map_size) { 1268 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 1269 uc_mem_map_size, 1270 wc_mem_map_size); 1271 if (!nic_data->wc_membase) { 1272 netif_err(efx, probe, efx->net_dev, 1273 "could not allocate WC mapping of size %x\n", 1274 wc_mem_map_size); 1275 return -ENOMEM; 1276 } 1277 nic_data->pio_write_vi_base = pio_write_vi_base; 1278 nic_data->pio_write_base = 1279 nic_data->wc_membase + 1280 (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF - 1281 uc_mem_map_size); 1282 1283 rc = efx_ef10_link_piobufs(efx); 1284 if (rc) 1285 efx_ef10_free_piobufs(efx); 1286 } 1287 1288 netif_dbg(efx, probe, efx->net_dev, 1289 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 1290 &efx->membase_phys, efx->membase, uc_mem_map_size, 1291 nic_data->wc_membase, wc_mem_map_size); 1292 1293 return 0; 1294 } 1295 1296 static void efx_ef10_fini_nic(struct efx_nic *efx) 1297 { 1298 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1299 1300 kfree(nic_data->mc_stats); 1301 nic_data->mc_stats = NULL; 1302 } 1303 1304 static int efx_ef10_init_nic(struct efx_nic *efx) 1305 { 1306 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1307 netdev_features_t hw_enc_features = 0; 1308 int rc; 1309 1310 if (nic_data->must_check_datapath_caps) { 1311 rc = efx_ef10_init_datapath_caps(efx); 1312 if (rc) 1313 return rc; 1314 nic_data->must_check_datapath_caps = false; 1315 } 1316 1317 if (efx->must_realloc_vis) { 1318 /* We cannot let the number of VIs change now */ 1319 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 1320 nic_data->n_allocated_vis); 1321 if (rc) 1322 return rc; 1323 efx->must_realloc_vis = false; 1324 } 1325 1326 nic_data->mc_stats = kmalloc(efx->num_mac_stats * sizeof(__le64), 1327 GFP_KERNEL); 1328 if (!nic_data->mc_stats) 1329 return -ENOMEM; 1330 1331 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 1332 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 1333 if (rc == 0) { 1334 rc = efx_ef10_link_piobufs(efx); 1335 if (rc) 1336 efx_ef10_free_piobufs(efx); 1337 } 1338 1339 /* Log an error on failure, but this is non-fatal. 1340 * Permission errors are less important - we've presumably 1341 * had the PIO buffer licence removed. 1342 */ 1343 if (rc == -EPERM) 1344 netif_dbg(efx, drv, efx->net_dev, 1345 "not permitted to restore PIO buffers\n"); 1346 else if (rc) 1347 netif_err(efx, drv, efx->net_dev, 1348 "failed to restore PIO buffers (%d)\n", rc); 1349 nic_data->must_restore_piobufs = false; 1350 } 1351 1352 /* add encapsulated checksum offload features */ 1353 if (efx_has_cap(efx, VXLAN_NVGRE) && !efx_ef10_is_vf(efx)) 1354 hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1355 /* add encapsulated TSO features */ 1356 if (efx_has_cap(efx, TX_TSO_V2_ENCAP)) { 1357 netdev_features_t encap_tso_features; 1358 1359 encap_tso_features = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 1360 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM; 1361 1362 hw_enc_features |= encap_tso_features | NETIF_F_TSO; 1363 efx->net_dev->features |= encap_tso_features; 1364 } 1365 efx->net_dev->hw_enc_features = hw_enc_features; 1366 1367 /* don't fail init if RSS setup doesn't work */ 1368 rc = efx->type->rx_push_rss_config(efx, false, 1369 efx->rss_context.rx_indir_table, NULL); 1370 1371 return 0; 1372 } 1373 1374 static void efx_ef10_table_reset_mc_allocations(struct efx_nic *efx) 1375 { 1376 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1377 #ifdef CONFIG_SFC_SRIOV 1378 unsigned int i; 1379 #endif 1380 1381 /* All our allocations have been reset */ 1382 efx->must_realloc_vis = true; 1383 efx_mcdi_filter_table_reset_mc_allocations(efx); 1384 nic_data->must_restore_piobufs = true; 1385 efx_ef10_forget_old_piobufs(efx); 1386 efx->rss_context.context_id = EFX_MCDI_RSS_CONTEXT_INVALID; 1387 1388 /* Driver-created vswitches and vports must be re-created */ 1389 nic_data->must_probe_vswitching = true; 1390 efx->vport_id = EVB_PORT_ID_ASSIGNED; 1391 #ifdef CONFIG_SFC_SRIOV 1392 if (nic_data->vf) 1393 for (i = 0; i < efx->vf_count; i++) 1394 nic_data->vf[i].vport_id = 0; 1395 #endif 1396 } 1397 1398 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason) 1399 { 1400 if (reason == RESET_TYPE_MC_FAILURE) 1401 return RESET_TYPE_DATAPATH; 1402 1403 return efx_mcdi_map_reset_reason(reason); 1404 } 1405 1406 static int efx_ef10_map_reset_flags(u32 *flags) 1407 { 1408 enum { 1409 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 1410 ETH_RESET_SHARED_SHIFT), 1411 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 1412 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 1413 ETH_RESET_PHY | ETH_RESET_MGMT) << 1414 ETH_RESET_SHARED_SHIFT) 1415 }; 1416 1417 /* We assume for now that our PCI function is permitted to 1418 * reset everything. 1419 */ 1420 1421 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 1422 *flags &= ~EF10_RESET_MC; 1423 return RESET_TYPE_WORLD; 1424 } 1425 1426 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 1427 *flags &= ~EF10_RESET_PORT; 1428 return RESET_TYPE_ALL; 1429 } 1430 1431 /* no invisible reset implemented */ 1432 1433 return -EINVAL; 1434 } 1435 1436 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 1437 { 1438 int rc = efx_mcdi_reset(efx, reset_type); 1439 1440 /* Unprivileged functions return -EPERM, but need to return success 1441 * here so that the datapath is brought back up. 1442 */ 1443 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM) 1444 rc = 0; 1445 1446 /* If it was a port reset, trigger reallocation of MC resources. 1447 * Note that on an MC reset nothing needs to be done now because we'll 1448 * detect the MC reset later and handle it then. 1449 * For an FLR, we never get an MC reset event, but the MC has reset all 1450 * resources assigned to us, so we have to trigger reallocation now. 1451 */ 1452 if ((reset_type == RESET_TYPE_ALL || 1453 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) 1454 efx_ef10_table_reset_mc_allocations(efx); 1455 return rc; 1456 } 1457 1458 #define EF10_DMA_STAT(ext_name, mcdi_name) \ 1459 [EF10_STAT_ ## ext_name] = \ 1460 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1461 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 1462 [EF10_STAT_ ## int_name] = \ 1463 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1464 #define EF10_OTHER_STAT(ext_name) \ 1465 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1466 1467 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 1468 EF10_DMA_STAT(port_tx_bytes, TX_BYTES), 1469 EF10_DMA_STAT(port_tx_packets, TX_PKTS), 1470 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 1471 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS), 1472 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 1473 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 1474 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 1475 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 1476 EF10_DMA_STAT(port_tx_64, TX_64_PKTS), 1477 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 1478 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 1479 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 1480 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 1481 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 1482 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 1483 EF10_DMA_STAT(port_rx_bytes, RX_BYTES), 1484 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES), 1485 EF10_OTHER_STAT(port_rx_good_bytes), 1486 EF10_OTHER_STAT(port_rx_bad_bytes), 1487 EF10_DMA_STAT(port_rx_packets, RX_PKTS), 1488 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 1489 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 1490 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 1491 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS), 1492 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 1493 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 1494 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 1495 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 1496 EF10_DMA_STAT(port_rx_64, RX_64_PKTS), 1497 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 1498 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 1499 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 1500 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 1501 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 1502 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 1503 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 1504 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 1505 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 1506 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 1507 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 1508 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 1509 EFX_GENERIC_SW_STAT(rx_nodesc_trunc), 1510 EFX_GENERIC_SW_STAT(rx_noskb_drops), 1511 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 1512 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 1513 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 1514 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 1515 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB), 1516 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB), 1517 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING), 1518 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 1519 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 1520 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 1521 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS), 1522 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS), 1523 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS), 1524 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES), 1525 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS), 1526 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES), 1527 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS), 1528 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES), 1529 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS), 1530 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES), 1531 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW), 1532 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS), 1533 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES), 1534 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS), 1535 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES), 1536 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS), 1537 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES), 1538 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS), 1539 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES), 1540 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW), 1541 EF10_DMA_STAT(fec_uncorrected_errors, FEC_UNCORRECTED_ERRORS), 1542 EF10_DMA_STAT(fec_corrected_errors, FEC_CORRECTED_ERRORS), 1543 EF10_DMA_STAT(fec_corrected_symbols_lane0, FEC_CORRECTED_SYMBOLS_LANE0), 1544 EF10_DMA_STAT(fec_corrected_symbols_lane1, FEC_CORRECTED_SYMBOLS_LANE1), 1545 EF10_DMA_STAT(fec_corrected_symbols_lane2, FEC_CORRECTED_SYMBOLS_LANE2), 1546 EF10_DMA_STAT(fec_corrected_symbols_lane3, FEC_CORRECTED_SYMBOLS_LANE3), 1547 EF10_DMA_STAT(ctpio_vi_busy_fallback, CTPIO_VI_BUSY_FALLBACK), 1548 EF10_DMA_STAT(ctpio_long_write_success, CTPIO_LONG_WRITE_SUCCESS), 1549 EF10_DMA_STAT(ctpio_missing_dbell_fail, CTPIO_MISSING_DBELL_FAIL), 1550 EF10_DMA_STAT(ctpio_overflow_fail, CTPIO_OVERFLOW_FAIL), 1551 EF10_DMA_STAT(ctpio_underflow_fail, CTPIO_UNDERFLOW_FAIL), 1552 EF10_DMA_STAT(ctpio_timeout_fail, CTPIO_TIMEOUT_FAIL), 1553 EF10_DMA_STAT(ctpio_noncontig_wr_fail, CTPIO_NONCONTIG_WR_FAIL), 1554 EF10_DMA_STAT(ctpio_frm_clobber_fail, CTPIO_FRM_CLOBBER_FAIL), 1555 EF10_DMA_STAT(ctpio_invalid_wr_fail, CTPIO_INVALID_WR_FAIL), 1556 EF10_DMA_STAT(ctpio_vi_clobber_fallback, CTPIO_VI_CLOBBER_FALLBACK), 1557 EF10_DMA_STAT(ctpio_unqualified_fallback, CTPIO_UNQUALIFIED_FALLBACK), 1558 EF10_DMA_STAT(ctpio_runt_fallback, CTPIO_RUNT_FALLBACK), 1559 EF10_DMA_STAT(ctpio_success, CTPIO_SUCCESS), 1560 EF10_DMA_STAT(ctpio_fallback, CTPIO_FALLBACK), 1561 EF10_DMA_STAT(ctpio_poison, CTPIO_POISON), 1562 EF10_DMA_STAT(ctpio_erase, CTPIO_ERASE), 1563 }; 1564 1565 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \ 1566 (1ULL << EF10_STAT_port_tx_packets) | \ 1567 (1ULL << EF10_STAT_port_tx_pause) | \ 1568 (1ULL << EF10_STAT_port_tx_unicast) | \ 1569 (1ULL << EF10_STAT_port_tx_multicast) | \ 1570 (1ULL << EF10_STAT_port_tx_broadcast) | \ 1571 (1ULL << EF10_STAT_port_rx_bytes) | \ 1572 (1ULL << \ 1573 EF10_STAT_port_rx_bytes_minus_good_bytes) | \ 1574 (1ULL << EF10_STAT_port_rx_good_bytes) | \ 1575 (1ULL << EF10_STAT_port_rx_bad_bytes) | \ 1576 (1ULL << EF10_STAT_port_rx_packets) | \ 1577 (1ULL << EF10_STAT_port_rx_good) | \ 1578 (1ULL << EF10_STAT_port_rx_bad) | \ 1579 (1ULL << EF10_STAT_port_rx_pause) | \ 1580 (1ULL << EF10_STAT_port_rx_control) | \ 1581 (1ULL << EF10_STAT_port_rx_unicast) | \ 1582 (1ULL << EF10_STAT_port_rx_multicast) | \ 1583 (1ULL << EF10_STAT_port_rx_broadcast) | \ 1584 (1ULL << EF10_STAT_port_rx_lt64) | \ 1585 (1ULL << EF10_STAT_port_rx_64) | \ 1586 (1ULL << EF10_STAT_port_rx_65_to_127) | \ 1587 (1ULL << EF10_STAT_port_rx_128_to_255) | \ 1588 (1ULL << EF10_STAT_port_rx_256_to_511) | \ 1589 (1ULL << EF10_STAT_port_rx_512_to_1023) |\ 1590 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\ 1591 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\ 1592 (1ULL << EF10_STAT_port_rx_gtjumbo) | \ 1593 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\ 1594 (1ULL << EF10_STAT_port_rx_overflow) | \ 1595 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\ 1596 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ 1597 (1ULL << GENERIC_STAT_rx_noskb_drops)) 1598 1599 /* On 7000 series NICs, these statistics are only provided by the 10G MAC. 1600 * For a 10G/40G switchable port we do not expose these because they might 1601 * not include all the packets they should. 1602 * On 8000 series NICs these statistics are always provided. 1603 */ 1604 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \ 1605 (1ULL << EF10_STAT_port_tx_lt64) | \ 1606 (1ULL << EF10_STAT_port_tx_64) | \ 1607 (1ULL << EF10_STAT_port_tx_65_to_127) |\ 1608 (1ULL << EF10_STAT_port_tx_128_to_255) |\ 1609 (1ULL << EF10_STAT_port_tx_256_to_511) |\ 1610 (1ULL << EF10_STAT_port_tx_512_to_1023) |\ 1611 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\ 1612 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo)) 1613 1614 /* These statistics are only provided by the 40G MAC. For a 10G/40G 1615 * switchable port we do expose these because the errors will otherwise 1616 * be silent. 1617 */ 1618 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\ 1619 (1ULL << EF10_STAT_port_rx_length_error)) 1620 1621 /* These statistics are only provided if the firmware supports the 1622 * capability PM_AND_RXDP_COUNTERS. 1623 */ 1624 #define HUNT_PM_AND_RXDP_STAT_MASK ( \ 1625 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \ 1626 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \ 1627 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \ 1628 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \ 1629 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \ 1630 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \ 1631 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \ 1632 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \ 1633 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \ 1634 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \ 1635 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \ 1636 (1ULL << EF10_STAT_port_rx_dp_hlb_wait)) 1637 1638 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V2, 1639 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V2 in 1640 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1641 * These bits are in the second u64 of the raw mask. 1642 */ 1643 #define EF10_FEC_STAT_MASK ( \ 1644 (1ULL << (EF10_STAT_fec_uncorrected_errors - 64)) | \ 1645 (1ULL << (EF10_STAT_fec_corrected_errors - 64)) | \ 1646 (1ULL << (EF10_STAT_fec_corrected_symbols_lane0 - 64)) | \ 1647 (1ULL << (EF10_STAT_fec_corrected_symbols_lane1 - 64)) | \ 1648 (1ULL << (EF10_STAT_fec_corrected_symbols_lane2 - 64)) | \ 1649 (1ULL << (EF10_STAT_fec_corrected_symbols_lane3 - 64))) 1650 1651 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V3, 1652 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V3 in 1653 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1654 * These bits are in the second u64 of the raw mask. 1655 */ 1656 #define EF10_CTPIO_STAT_MASK ( \ 1657 (1ULL << (EF10_STAT_ctpio_vi_busy_fallback - 64)) | \ 1658 (1ULL << (EF10_STAT_ctpio_long_write_success - 64)) | \ 1659 (1ULL << (EF10_STAT_ctpio_missing_dbell_fail - 64)) | \ 1660 (1ULL << (EF10_STAT_ctpio_overflow_fail - 64)) | \ 1661 (1ULL << (EF10_STAT_ctpio_underflow_fail - 64)) | \ 1662 (1ULL << (EF10_STAT_ctpio_timeout_fail - 64)) | \ 1663 (1ULL << (EF10_STAT_ctpio_noncontig_wr_fail - 64)) | \ 1664 (1ULL << (EF10_STAT_ctpio_frm_clobber_fail - 64)) | \ 1665 (1ULL << (EF10_STAT_ctpio_invalid_wr_fail - 64)) | \ 1666 (1ULL << (EF10_STAT_ctpio_vi_clobber_fallback - 64)) | \ 1667 (1ULL << (EF10_STAT_ctpio_unqualified_fallback - 64)) | \ 1668 (1ULL << (EF10_STAT_ctpio_runt_fallback - 64)) | \ 1669 (1ULL << (EF10_STAT_ctpio_success - 64)) | \ 1670 (1ULL << (EF10_STAT_ctpio_fallback - 64)) | \ 1671 (1ULL << (EF10_STAT_ctpio_poison - 64)) | \ 1672 (1ULL << (EF10_STAT_ctpio_erase - 64))) 1673 1674 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 1675 { 1676 u64 raw_mask = HUNT_COMMON_STAT_MASK; 1677 u32 port_caps = efx_mcdi_phy_get_caps(efx); 1678 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1679 1680 if (!(efx->mcdi->fn_flags & 1681 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 1682 return 0; 1683 1684 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) { 1685 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 1686 /* 8000 series have everything even at 40G */ 1687 if (nic_data->datapath_caps2 & 1688 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN)) 1689 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1690 } else { 1691 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1692 } 1693 1694 if (nic_data->datapath_caps & 1695 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 1696 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 1697 1698 return raw_mask; 1699 } 1700 1701 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 1702 { 1703 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1704 u64 raw_mask[2]; 1705 1706 raw_mask[0] = efx_ef10_raw_stat_mask(efx); 1707 1708 /* Only show vadaptor stats when EVB capability is present */ 1709 if (nic_data->datapath_caps & 1710 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) { 1711 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1); 1712 raw_mask[1] = (1ULL << (EF10_STAT_V1_COUNT - 64)) - 1; 1713 } else { 1714 raw_mask[1] = 0; 1715 } 1716 /* Only show FEC stats when NIC supports MC_CMD_MAC_STATS_V2 */ 1717 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V2) 1718 raw_mask[1] |= EF10_FEC_STAT_MASK; 1719 1720 /* CTPIO stats appear in V3. Only show them on devices that actually 1721 * support CTPIO. Although this driver doesn't use CTPIO others might, 1722 * and we may be reporting the stats for the underlying port. 1723 */ 1724 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V3 && 1725 (nic_data->datapath_caps2 & 1726 (1 << MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN))) 1727 raw_mask[1] |= EF10_CTPIO_STAT_MASK; 1728 1729 #if BITS_PER_LONG == 64 1730 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2); 1731 mask[0] = raw_mask[0]; 1732 mask[1] = raw_mask[1]; 1733 #else 1734 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3); 1735 mask[0] = raw_mask[0] & 0xffffffff; 1736 mask[1] = raw_mask[0] >> 32; 1737 mask[2] = raw_mask[1] & 0xffffffff; 1738 #endif 1739 } 1740 1741 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 1742 { 1743 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1744 1745 efx_ef10_get_stat_mask(efx, mask); 1746 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1747 mask, names); 1748 } 1749 1750 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats, 1751 struct rtnl_link_stats64 *core_stats) 1752 { 1753 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1754 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1755 u64 *stats = nic_data->stats; 1756 size_t stats_count = 0, index; 1757 1758 efx_ef10_get_stat_mask(efx, mask); 1759 1760 if (full_stats) { 1761 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 1762 if (efx_ef10_stat_desc[index].name) { 1763 *full_stats++ = stats[index]; 1764 ++stats_count; 1765 } 1766 } 1767 } 1768 1769 if (!core_stats) 1770 return stats_count; 1771 1772 if (nic_data->datapath_caps & 1773 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) { 1774 /* Use vadaptor stats. */ 1775 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] + 1776 stats[EF10_STAT_rx_multicast] + 1777 stats[EF10_STAT_rx_broadcast]; 1778 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] + 1779 stats[EF10_STAT_tx_multicast] + 1780 stats[EF10_STAT_tx_broadcast]; 1781 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] + 1782 stats[EF10_STAT_rx_multicast_bytes] + 1783 stats[EF10_STAT_rx_broadcast_bytes]; 1784 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] + 1785 stats[EF10_STAT_tx_multicast_bytes] + 1786 stats[EF10_STAT_tx_broadcast_bytes]; 1787 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] + 1788 stats[GENERIC_STAT_rx_noskb_drops]; 1789 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 1790 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 1791 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 1792 core_stats->rx_errors = core_stats->rx_crc_errors; 1793 core_stats->tx_errors = stats[EF10_STAT_tx_bad]; 1794 } else { 1795 /* Use port stats. */ 1796 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets]; 1797 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets]; 1798 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes]; 1799 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes]; 1800 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] + 1801 stats[GENERIC_STAT_rx_nodesc_trunc] + 1802 stats[GENERIC_STAT_rx_noskb_drops]; 1803 core_stats->multicast = stats[EF10_STAT_port_rx_multicast]; 1804 core_stats->rx_length_errors = 1805 stats[EF10_STAT_port_rx_gtjumbo] + 1806 stats[EF10_STAT_port_rx_length_error]; 1807 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad]; 1808 core_stats->rx_frame_errors = 1809 stats[EF10_STAT_port_rx_align_error]; 1810 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow]; 1811 core_stats->rx_errors = (core_stats->rx_length_errors + 1812 core_stats->rx_crc_errors + 1813 core_stats->rx_frame_errors); 1814 } 1815 1816 return stats_count; 1817 } 1818 1819 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats, 1820 struct rtnl_link_stats64 *core_stats) 1821 { 1822 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1823 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1824 u64 *stats = nic_data->stats; 1825 1826 efx_ef10_get_stat_mask(efx, mask); 1827 1828 efx_nic_copy_stats(efx, nic_data->mc_stats); 1829 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1830 mask, stats, nic_data->mc_stats, false); 1831 1832 /* Update derived statistics */ 1833 efx_nic_fix_nodesc_drop_stat(efx, 1834 &stats[EF10_STAT_port_rx_nodesc_drops]); 1835 /* MC Firmware reads RX_BYTES and RX_GOOD_BYTES from the MAC. 1836 * It then calculates RX_BAD_BYTES and DMAs it to us with RX_BYTES. 1837 * We report these as port_rx_ stats. We are not given RX_GOOD_BYTES. 1838 * Here we calculate port_rx_good_bytes. 1839 */ 1840 stats[EF10_STAT_port_rx_good_bytes] = 1841 stats[EF10_STAT_port_rx_bytes] - 1842 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]; 1843 1844 /* The asynchronous reads used to calculate RX_BAD_BYTES in 1845 * MC Firmware are done such that we should not see an increase in 1846 * RX_BAD_BYTES when a good packet has arrived. Unfortunately this 1847 * does mean that the stat can decrease at times. Here we do not 1848 * update the stat unless it has increased or has gone to zero 1849 * (In the case of the NIC rebooting). 1850 * Please see Bug 33781 for a discussion of why things work this way. 1851 */ 1852 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes], 1853 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]); 1854 efx_update_sw_stats(efx, stats); 1855 1856 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1857 } 1858 1859 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx) 1860 __must_hold(&efx->stats_lock) 1861 { 1862 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN); 1863 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1864 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1865 __le64 generation_start, generation_end; 1866 u64 *stats = nic_data->stats; 1867 u32 dma_len = efx->num_mac_stats * sizeof(u64); 1868 struct efx_buffer stats_buf; 1869 __le64 *dma_stats; 1870 int rc; 1871 1872 spin_unlock_bh(&efx->stats_lock); 1873 1874 if (in_interrupt()) { 1875 /* If in atomic context, cannot update stats. Just update the 1876 * software stats and return so the caller can continue. 1877 */ 1878 spin_lock_bh(&efx->stats_lock); 1879 efx_update_sw_stats(efx, stats); 1880 return 0; 1881 } 1882 1883 efx_ef10_get_stat_mask(efx, mask); 1884 1885 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC); 1886 if (rc) { 1887 spin_lock_bh(&efx->stats_lock); 1888 return rc; 1889 } 1890 1891 dma_stats = stats_buf.addr; 1892 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID; 1893 1894 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr); 1895 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD, 1896 MAC_STATS_IN_DMA, 1); 1897 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len); 1898 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1899 1900 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf), 1901 NULL, 0, NULL); 1902 spin_lock_bh(&efx->stats_lock); 1903 if (rc) { 1904 /* Expect ENOENT if DMA queues have not been set up */ 1905 if (rc != -ENOENT || atomic_read(&efx->active_queues)) 1906 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS, 1907 sizeof(inbuf), NULL, 0, rc); 1908 goto out; 1909 } 1910 1911 generation_end = dma_stats[efx->num_mac_stats - 1]; 1912 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) { 1913 WARN_ON_ONCE(1); 1914 goto out; 1915 } 1916 rmb(); 1917 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1918 stats, stats_buf.addr, false); 1919 rmb(); 1920 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1921 if (generation_end != generation_start) { 1922 rc = -EAGAIN; 1923 goto out; 1924 } 1925 1926 efx_update_sw_stats(efx, stats); 1927 out: 1928 efx_nic_free_buffer(efx, &stats_buf); 1929 return rc; 1930 } 1931 1932 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats, 1933 struct rtnl_link_stats64 *core_stats) 1934 { 1935 if (efx_ef10_try_update_nic_stats_vf(efx)) 1936 return 0; 1937 1938 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1939 } 1940 1941 static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1942 { 1943 struct efx_nic *efx = channel->efx; 1944 unsigned int mode, usecs; 1945 efx_dword_t timer_cmd; 1946 1947 if (channel->irq_moderation_us) { 1948 mode = 3; 1949 usecs = channel->irq_moderation_us; 1950 } else { 1951 mode = 0; 1952 usecs = 0; 1953 } 1954 1955 if (EFX_EF10_WORKAROUND_61265(efx)) { 1956 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN); 1957 unsigned int ns = usecs * 1000; 1958 1959 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE, 1960 channel->channel); 1961 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns); 1962 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns); 1963 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode); 1964 1965 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR, 1966 inbuf, sizeof(inbuf), 0, NULL, 0); 1967 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 1968 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 1969 1970 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 1971 EFE_DD_EVQ_IND_TIMER_FLAGS, 1972 ERF_DD_EVQ_IND_TIMER_MODE, mode, 1973 ERF_DD_EVQ_IND_TIMER_VAL, ticks); 1974 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 1975 channel->channel); 1976 } else { 1977 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 1978 1979 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 1980 ERF_DZ_TC_TIMER_VAL, ticks, 1981 ERF_FZ_TC_TMR_REL_VAL, ticks); 1982 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 1983 channel->channel); 1984 } 1985 } 1986 1987 static void efx_ef10_get_wol_vf(struct efx_nic *efx, 1988 struct ethtool_wolinfo *wol) {} 1989 1990 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type) 1991 { 1992 return -EOPNOTSUPP; 1993 } 1994 1995 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 1996 { 1997 wol->supported = 0; 1998 wol->wolopts = 0; 1999 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2000 } 2001 2002 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 2003 { 2004 if (type != 0) 2005 return -EINVAL; 2006 return 0; 2007 } 2008 2009 static void efx_ef10_mcdi_request(struct efx_nic *efx, 2010 const efx_dword_t *hdr, size_t hdr_len, 2011 const efx_dword_t *sdu, size_t sdu_len) 2012 { 2013 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2014 u8 *pdu = nic_data->mcdi_buf.addr; 2015 2016 memcpy(pdu, hdr, hdr_len); 2017 memcpy(pdu + hdr_len, sdu, sdu_len); 2018 wmb(); 2019 2020 /* The hardware provides 'low' and 'high' (doorbell) registers 2021 * for passing the 64-bit address of an MCDI request to 2022 * firmware. However the dwords are swapped by firmware. The 2023 * least significant bits of the doorbell are then 0 for all 2024 * MCDI requests due to alignment. 2025 */ 2026 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 2027 ER_DZ_MC_DB_LWRD); 2028 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 2029 ER_DZ_MC_DB_HWRD); 2030 } 2031 2032 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 2033 { 2034 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2035 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 2036 2037 rmb(); 2038 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 2039 } 2040 2041 static void 2042 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 2043 size_t offset, size_t outlen) 2044 { 2045 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2046 const u8 *pdu = nic_data->mcdi_buf.addr; 2047 2048 memcpy(outbuf, pdu + offset, outlen); 2049 } 2050 2051 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx) 2052 { 2053 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2054 2055 /* All our allocations have been reset */ 2056 efx_ef10_table_reset_mc_allocations(efx); 2057 2058 /* The datapath firmware might have been changed */ 2059 nic_data->must_check_datapath_caps = true; 2060 2061 /* MAC statistics have been cleared on the NIC; clear the local 2062 * statistic that we update with efx_update_diff_stat(). 2063 */ 2064 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0; 2065 } 2066 2067 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 2068 { 2069 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2070 int rc; 2071 2072 rc = efx_ef10_get_warm_boot_count(efx); 2073 if (rc < 0) { 2074 /* The firmware is presumably in the process of 2075 * rebooting. However, we are supposed to report each 2076 * reboot just once, so we must only do that once we 2077 * can read and store the updated warm boot count. 2078 */ 2079 return 0; 2080 } 2081 2082 if (rc == nic_data->warm_boot_count) 2083 return 0; 2084 2085 nic_data->warm_boot_count = rc; 2086 efx_ef10_mcdi_reboot_detected(efx); 2087 2088 return -EIO; 2089 } 2090 2091 /* Handle an MSI interrupt 2092 * 2093 * Handle an MSI hardware interrupt. This routine schedules event 2094 * queue processing. No interrupt acknowledgement cycle is necessary. 2095 * Also, we never need to check that the interrupt is for us, since 2096 * MSI interrupts cannot be shared. 2097 */ 2098 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 2099 { 2100 struct efx_msi_context *context = dev_id; 2101 struct efx_nic *efx = context->efx; 2102 2103 netif_vdbg(efx, intr, efx->net_dev, 2104 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 2105 2106 if (likely(READ_ONCE(efx->irq_soft_enabled))) { 2107 /* Note test interrupts */ 2108 if (context->index == efx->irq_level) 2109 efx->last_irq_cpu = raw_smp_processor_id(); 2110 2111 /* Schedule processing of the channel */ 2112 efx_schedule_channel_irq(efx->channel[context->index]); 2113 } 2114 2115 return IRQ_HANDLED; 2116 } 2117 2118 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 2119 { 2120 struct efx_nic *efx = dev_id; 2121 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled); 2122 struct efx_channel *channel; 2123 efx_dword_t reg; 2124 u32 queues; 2125 2126 /* Read the ISR which also ACKs the interrupts */ 2127 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 2128 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 2129 2130 if (queues == 0) 2131 return IRQ_NONE; 2132 2133 if (likely(soft_enabled)) { 2134 /* Note test interrupts */ 2135 if (queues & (1U << efx->irq_level)) 2136 efx->last_irq_cpu = raw_smp_processor_id(); 2137 2138 efx_for_each_channel(channel, efx) { 2139 if (queues & 1) 2140 efx_schedule_channel_irq(channel); 2141 queues >>= 1; 2142 } 2143 } 2144 2145 netif_vdbg(efx, intr, efx->net_dev, 2146 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 2147 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 2148 2149 return IRQ_HANDLED; 2150 } 2151 2152 static int efx_ef10_irq_test_generate(struct efx_nic *efx) 2153 { 2154 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 2155 2156 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true, 2157 NULL) == 0) 2158 return -ENOTSUPP; 2159 2160 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 2161 2162 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 2163 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 2164 inbuf, sizeof(inbuf), NULL, 0, NULL); 2165 } 2166 2167 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 2168 { 2169 /* low two bits of label are what we want for type */ 2170 BUILD_BUG_ON((EFX_TXQ_TYPE_OUTER_CSUM | EFX_TXQ_TYPE_INNER_CSUM) != 3); 2171 tx_queue->type = tx_queue->label & 3; 2172 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 2173 (tx_queue->ptr_mask + 1) * 2174 sizeof(efx_qword_t), 2175 GFP_KERNEL); 2176 } 2177 2178 /* This writes to the TX_DESC_WPTR and also pushes data */ 2179 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 2180 const efx_qword_t *txd) 2181 { 2182 unsigned int write_ptr; 2183 efx_oword_t reg; 2184 2185 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2186 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 2187 reg.qword[0] = *txd; 2188 efx_writeo_page(tx_queue->efx, ®, 2189 ER_DZ_TX_DESC_UPD, tx_queue->queue); 2190 } 2191 2192 /* Add Firmware-Assisted TSO v2 option descriptors to a queue. 2193 */ 2194 int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb, 2195 bool *data_mapped) 2196 { 2197 struct efx_tx_buffer *buffer; 2198 u16 inner_ipv4_id = 0; 2199 u16 outer_ipv4_id = 0; 2200 struct tcphdr *tcp; 2201 struct iphdr *ip; 2202 u16 ip_tot_len; 2203 u32 seqnum; 2204 u32 mss; 2205 2206 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2); 2207 2208 mss = skb_shinfo(skb)->gso_size; 2209 2210 if (unlikely(mss < 4)) { 2211 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss); 2212 return -EINVAL; 2213 } 2214 2215 if (skb->encapsulation) { 2216 if (!tx_queue->tso_encap) 2217 return -EINVAL; 2218 ip = ip_hdr(skb); 2219 if (ip->version == 4) 2220 outer_ipv4_id = ntohs(ip->id); 2221 2222 ip = inner_ip_hdr(skb); 2223 tcp = inner_tcp_hdr(skb); 2224 } else { 2225 ip = ip_hdr(skb); 2226 tcp = tcp_hdr(skb); 2227 } 2228 2229 /* 8000-series EF10 hardware requires that IP Total Length be 2230 * greater than or equal to the value it will have in each segment 2231 * (which is at most mss + 208 + TCP header length), but also less 2232 * than (0x10000 - inner_network_header). Otherwise the TCP 2233 * checksum calculation will be broken for encapsulated packets. 2234 * We fill in ip->tot_len with 0xff30, which should satisfy the 2235 * first requirement unless the MSS is ridiculously large (which 2236 * should be impossible as the driver max MTU is 9216); it is 2237 * guaranteed to satisfy the second as we only attempt TSO if 2238 * inner_network_header <= 208. 2239 */ 2240 ip_tot_len = -EFX_TSO2_MAX_HDRLEN; 2241 EFX_WARN_ON_ONCE_PARANOID(mss + EFX_TSO2_MAX_HDRLEN + 2242 (tcp->doff << 2u) > ip_tot_len); 2243 2244 if (ip->version == 4) { 2245 ip->tot_len = htons(ip_tot_len); 2246 ip->check = 0; 2247 inner_ipv4_id = ntohs(ip->id); 2248 } else { 2249 ((struct ipv6hdr *)ip)->payload_len = htons(ip_tot_len); 2250 } 2251 2252 seqnum = ntohl(tcp->seq); 2253 2254 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2255 2256 buffer->flags = EFX_TX_BUF_OPTION; 2257 buffer->len = 0; 2258 buffer->unmap_len = 0; 2259 EFX_POPULATE_QWORD_5(buffer->option, 2260 ESF_DZ_TX_DESC_IS_OPT, 1, 2261 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2262 ESF_DZ_TX_TSO_OPTION_TYPE, 2263 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A, 2264 ESF_DZ_TX_TSO_IP_ID, inner_ipv4_id, 2265 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum 2266 ); 2267 ++tx_queue->insert_count; 2268 2269 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2270 2271 buffer->flags = EFX_TX_BUF_OPTION; 2272 buffer->len = 0; 2273 buffer->unmap_len = 0; 2274 EFX_POPULATE_QWORD_5(buffer->option, 2275 ESF_DZ_TX_DESC_IS_OPT, 1, 2276 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2277 ESF_DZ_TX_TSO_OPTION_TYPE, 2278 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B, 2279 ESF_DZ_TX_TSO_OUTER_IPID, outer_ipv4_id, 2280 ESF_DZ_TX_TSO_TCP_MSS, mss 2281 ); 2282 ++tx_queue->insert_count; 2283 2284 return 0; 2285 } 2286 2287 static u32 efx_ef10_tso_versions(struct efx_nic *efx) 2288 { 2289 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2290 u32 tso_versions = 0; 2291 2292 if (nic_data->datapath_caps & 2293 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) 2294 tso_versions |= BIT(1); 2295 if (nic_data->datapath_caps2 & 2296 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) 2297 tso_versions |= BIT(2); 2298 return tso_versions; 2299 } 2300 2301 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 2302 { 2303 bool csum_offload = tx_queue->type & EFX_TXQ_TYPE_OUTER_CSUM; 2304 bool inner_csum = tx_queue->type & EFX_TXQ_TYPE_INNER_CSUM; 2305 struct efx_channel *channel = tx_queue->channel; 2306 struct efx_nic *efx = tx_queue->efx; 2307 struct efx_ef10_nic_data *nic_data; 2308 efx_qword_t *txd; 2309 int rc; 2310 2311 nic_data = efx->nic_data; 2312 2313 /* Only attempt to enable TX timestamping if we have the license for it, 2314 * otherwise TXQ init will fail 2315 */ 2316 if (!(nic_data->licensed_features & 2317 (1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN))) { 2318 tx_queue->timestamping = false; 2319 /* Disable sync events on this channel. */ 2320 if (efx->type->ptp_set_ts_sync_events) 2321 efx->type->ptp_set_ts_sync_events(efx, false, false); 2322 } 2323 2324 /* TSOv2 is a limited resource that can only be configured on a limited 2325 * number of queues. TSO without checksum offload is not really a thing, 2326 * so we only enable it for those queues. 2327 * TSOv2 cannot be used with Hardware timestamping, and is never needed 2328 * for XDP tx. 2329 */ 2330 if (efx_has_cap(efx, TX_TSO_V2)) { 2331 if ((csum_offload || inner_csum) && 2332 !tx_queue->timestamping && !tx_queue->xdp_tx) { 2333 tx_queue->tso_version = 2; 2334 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n", 2335 channel->channel); 2336 } 2337 } else if (efx_has_cap(efx, TX_TSO)) { 2338 tx_queue->tso_version = 1; 2339 } 2340 2341 rc = efx_mcdi_tx_init(tx_queue); 2342 if (rc) 2343 goto fail; 2344 2345 /* A previous user of this TX queue might have set us up the 2346 * bomb by writing a descriptor to the TX push collector but 2347 * not the doorbell. (Each collector belongs to a port, not a 2348 * queue or function, so cannot easily be reset.) We must 2349 * attempt to push a no-op descriptor in its place. 2350 */ 2351 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 2352 tx_queue->insert_count = 1; 2353 txd = efx_tx_desc(tx_queue, 0); 2354 EFX_POPULATE_QWORD_7(*txd, 2355 ESF_DZ_TX_DESC_IS_OPT, true, 2356 ESF_DZ_TX_OPTION_TYPE, 2357 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 2358 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 2359 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload && tx_queue->tso_version != 2, 2360 ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM, inner_csum, 2361 ESF_DZ_TX_OPTION_INNER_IP_CSUM, inner_csum && tx_queue->tso_version != 2, 2362 ESF_DZ_TX_TIMESTAMP, tx_queue->timestamping); 2363 tx_queue->write_count = 1; 2364 2365 if (tx_queue->tso_version == 2 && efx_has_cap(efx, TX_TSO_V2_ENCAP)) 2366 tx_queue->tso_encap = true; 2367 2368 wmb(); 2369 efx_ef10_push_tx_desc(tx_queue, txd); 2370 2371 return; 2372 2373 fail: 2374 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 2375 tx_queue->queue); 2376 } 2377 2378 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 2379 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 2380 { 2381 unsigned int write_ptr; 2382 efx_dword_t reg; 2383 2384 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2385 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 2386 efx_writed_page(tx_queue->efx, ®, 2387 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 2388 } 2389 2390 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff 2391 2392 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue, 2393 dma_addr_t dma_addr, unsigned int len) 2394 { 2395 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) { 2396 /* If we need to break across multiple descriptors we should 2397 * stop at a page boundary. This assumes the length limit is 2398 * greater than the page size. 2399 */ 2400 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN; 2401 2402 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE); 2403 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr; 2404 } 2405 2406 return len; 2407 } 2408 2409 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 2410 { 2411 unsigned int old_write_count = tx_queue->write_count; 2412 struct efx_tx_buffer *buffer; 2413 unsigned int write_ptr; 2414 efx_qword_t *txd; 2415 2416 tx_queue->xmit_pending = false; 2417 if (unlikely(tx_queue->write_count == tx_queue->insert_count)) 2418 return; 2419 2420 do { 2421 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2422 buffer = &tx_queue->buffer[write_ptr]; 2423 txd = efx_tx_desc(tx_queue, write_ptr); 2424 ++tx_queue->write_count; 2425 2426 /* Create TX descriptor ring entry */ 2427 if (buffer->flags & EFX_TX_BUF_OPTION) { 2428 *txd = buffer->option; 2429 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1) 2430 /* PIO descriptor */ 2431 tx_queue->packet_write_count = tx_queue->write_count; 2432 } else { 2433 tx_queue->packet_write_count = tx_queue->write_count; 2434 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 2435 EFX_POPULATE_QWORD_3( 2436 *txd, 2437 ESF_DZ_TX_KER_CONT, 2438 buffer->flags & EFX_TX_BUF_CONT, 2439 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 2440 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 2441 } 2442 } while (tx_queue->write_count != tx_queue->insert_count); 2443 2444 wmb(); /* Ensure descriptors are written before they are fetched */ 2445 2446 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 2447 txd = efx_tx_desc(tx_queue, 2448 old_write_count & tx_queue->ptr_mask); 2449 efx_ef10_push_tx_desc(tx_queue, txd); 2450 ++tx_queue->pushes; 2451 } else { 2452 efx_ef10_notify_tx_desc(tx_queue); 2453 } 2454 } 2455 2456 static int efx_ef10_probe_multicast_chaining(struct efx_nic *efx) 2457 { 2458 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2459 unsigned int enabled, implemented; 2460 bool want_workaround_26807; 2461 int rc; 2462 2463 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 2464 if (rc == -ENOSYS) { 2465 /* GET_WORKAROUNDS was implemented before this workaround, 2466 * thus it must be unavailable in this firmware. 2467 */ 2468 nic_data->workaround_26807 = false; 2469 return 0; 2470 } 2471 if (rc) 2472 return rc; 2473 want_workaround_26807 = 2474 implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807; 2475 nic_data->workaround_26807 = 2476 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807); 2477 2478 if (want_workaround_26807 && !nic_data->workaround_26807) { 2479 unsigned int flags; 2480 2481 rc = efx_mcdi_set_workaround(efx, 2482 MC_CMD_WORKAROUND_BUG26807, 2483 true, &flags); 2484 if (!rc) { 2485 if (flags & 2486 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) { 2487 netif_info(efx, drv, efx->net_dev, 2488 "other functions on NIC have been reset\n"); 2489 2490 /* With MCFW v4.6.x and earlier, the 2491 * boot count will have incremented, 2492 * so re-read the warm_boot_count 2493 * value now to ensure this function 2494 * doesn't think it has changed next 2495 * time it checks. 2496 */ 2497 rc = efx_ef10_get_warm_boot_count(efx); 2498 if (rc >= 0) { 2499 nic_data->warm_boot_count = rc; 2500 rc = 0; 2501 } 2502 } 2503 nic_data->workaround_26807 = true; 2504 } else if (rc == -EPERM) { 2505 rc = 0; 2506 } 2507 } 2508 return rc; 2509 } 2510 2511 static int efx_ef10_filter_table_probe(struct efx_nic *efx) 2512 { 2513 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2514 int rc = efx_ef10_probe_multicast_chaining(efx); 2515 struct efx_mcdi_filter_vlan *vlan; 2516 2517 if (rc) 2518 return rc; 2519 rc = efx_mcdi_filter_table_probe(efx, nic_data->workaround_26807); 2520 2521 if (rc) 2522 return rc; 2523 2524 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 2525 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 2526 if (rc) 2527 goto fail_add_vlan; 2528 } 2529 return 0; 2530 2531 fail_add_vlan: 2532 efx_mcdi_filter_table_remove(efx); 2533 return rc; 2534 } 2535 2536 /* This creates an entry in the RX descriptor queue */ 2537 static inline void 2538 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 2539 { 2540 struct efx_rx_buffer *rx_buf; 2541 efx_qword_t *rxd; 2542 2543 rxd = efx_rx_desc(rx_queue, index); 2544 rx_buf = efx_rx_buffer(rx_queue, index); 2545 EFX_POPULATE_QWORD_2(*rxd, 2546 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 2547 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 2548 } 2549 2550 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 2551 { 2552 struct efx_nic *efx = rx_queue->efx; 2553 unsigned int write_count; 2554 efx_dword_t reg; 2555 2556 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 2557 write_count = rx_queue->added_count & ~7; 2558 if (rx_queue->notified_count == write_count) 2559 return; 2560 2561 do 2562 efx_ef10_build_rx_desc( 2563 rx_queue, 2564 rx_queue->notified_count & rx_queue->ptr_mask); 2565 while (++rx_queue->notified_count != write_count); 2566 2567 wmb(); 2568 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 2569 write_count & rx_queue->ptr_mask); 2570 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 2571 efx_rx_queue_index(rx_queue)); 2572 } 2573 2574 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 2575 2576 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 2577 { 2578 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2579 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2580 efx_qword_t event; 2581 2582 EFX_POPULATE_QWORD_2(event, 2583 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2584 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 2585 2586 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2587 2588 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2589 * already swapped the data to little-endian order. 2590 */ 2591 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2592 sizeof(efx_qword_t)); 2593 2594 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 2595 inbuf, sizeof(inbuf), 0, 2596 efx_ef10_rx_defer_refill_complete, 0); 2597 } 2598 2599 static void 2600 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 2601 int rc, efx_dword_t *outbuf, 2602 size_t outlen_actual) 2603 { 2604 /* nothing to do */ 2605 } 2606 2607 static int efx_ef10_ev_init(struct efx_channel *channel) 2608 { 2609 struct efx_nic *efx = channel->efx; 2610 struct efx_ef10_nic_data *nic_data; 2611 bool use_v2, cut_thru; 2612 2613 nic_data = efx->nic_data; 2614 use_v2 = nic_data->datapath_caps2 & 2615 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN; 2616 cut_thru = !(nic_data->datapath_caps & 2617 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 2618 return efx_mcdi_ev_init(channel, cut_thru, use_v2); 2619 } 2620 2621 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 2622 unsigned int rx_queue_label) 2623 { 2624 struct efx_nic *efx = rx_queue->efx; 2625 2626 netif_info(efx, hw, efx->net_dev, 2627 "rx event arrived on queue %d labeled as queue %u\n", 2628 efx_rx_queue_index(rx_queue), rx_queue_label); 2629 2630 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2631 } 2632 2633 static void 2634 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 2635 unsigned int actual, unsigned int expected) 2636 { 2637 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 2638 struct efx_nic *efx = rx_queue->efx; 2639 2640 netif_info(efx, hw, efx->net_dev, 2641 "dropped %d events (index=%d expected=%d)\n", 2642 dropped, actual, expected); 2643 2644 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2645 } 2646 2647 /* partially received RX was aborted. clean up. */ 2648 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 2649 { 2650 unsigned int rx_desc_ptr; 2651 2652 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 2653 "scattered RX aborted (dropping %u buffers)\n", 2654 rx_queue->scatter_n); 2655 2656 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 2657 2658 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 2659 0, EFX_RX_PKT_DISCARD); 2660 2661 rx_queue->removed_count += rx_queue->scatter_n; 2662 rx_queue->scatter_n = 0; 2663 rx_queue->scatter_len = 0; 2664 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 2665 } 2666 2667 static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel, 2668 unsigned int n_packets, 2669 unsigned int rx_encap_hdr, 2670 unsigned int rx_l3_class, 2671 unsigned int rx_l4_class, 2672 const efx_qword_t *event) 2673 { 2674 struct efx_nic *efx = channel->efx; 2675 bool handled = false; 2676 2677 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) { 2678 if (!(efx->net_dev->features & NETIF_F_RXALL)) { 2679 if (!efx->loopback_selftest) 2680 channel->n_rx_eth_crc_err += n_packets; 2681 return EFX_RX_PKT_DISCARD; 2682 } 2683 handled = true; 2684 } 2685 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) { 2686 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2687 rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2688 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2689 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2690 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2691 netdev_WARN(efx->net_dev, 2692 "invalid class for RX_IPCKSUM_ERR: event=" 2693 EFX_QWORD_FMT "\n", 2694 EFX_QWORD_VAL(*event)); 2695 if (!efx->loopback_selftest) 2696 *(rx_encap_hdr ? 2697 &channel->n_rx_outer_ip_hdr_chksum_err : 2698 &channel->n_rx_ip_hdr_chksum_err) += n_packets; 2699 return 0; 2700 } 2701 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) { 2702 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2703 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2704 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2705 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2706 rx_l4_class != ESE_FZ_L4_CLASS_UDP)))) 2707 netdev_WARN(efx->net_dev, 2708 "invalid class for RX_TCPUDP_CKSUM_ERR: event=" 2709 EFX_QWORD_FMT "\n", 2710 EFX_QWORD_VAL(*event)); 2711 if (!efx->loopback_selftest) 2712 *(rx_encap_hdr ? 2713 &channel->n_rx_outer_tcp_udp_chksum_err : 2714 &channel->n_rx_tcp_udp_chksum_err) += n_packets; 2715 return 0; 2716 } 2717 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) { 2718 if (unlikely(!rx_encap_hdr)) 2719 netdev_WARN(efx->net_dev, 2720 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event=" 2721 EFX_QWORD_FMT "\n", 2722 EFX_QWORD_VAL(*event)); 2723 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2724 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2725 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2726 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2727 netdev_WARN(efx->net_dev, 2728 "invalid class for RX_IP_INNER_CHKSUM_ERR: event=" 2729 EFX_QWORD_FMT "\n", 2730 EFX_QWORD_VAL(*event)); 2731 if (!efx->loopback_selftest) 2732 channel->n_rx_inner_ip_hdr_chksum_err += n_packets; 2733 return 0; 2734 } 2735 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) { 2736 if (unlikely(!rx_encap_hdr)) 2737 netdev_WARN(efx->net_dev, 2738 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2739 EFX_QWORD_FMT "\n", 2740 EFX_QWORD_VAL(*event)); 2741 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2742 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2743 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2744 rx_l4_class != ESE_FZ_L4_CLASS_UDP))) 2745 netdev_WARN(efx->net_dev, 2746 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2747 EFX_QWORD_FMT "\n", 2748 EFX_QWORD_VAL(*event)); 2749 if (!efx->loopback_selftest) 2750 channel->n_rx_inner_tcp_udp_chksum_err += n_packets; 2751 return 0; 2752 } 2753 2754 WARN_ON(!handled); /* No error bits were recognised */ 2755 return 0; 2756 } 2757 2758 static int efx_ef10_handle_rx_event(struct efx_channel *channel, 2759 const efx_qword_t *event) 2760 { 2761 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label; 2762 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr; 2763 unsigned int n_descs, n_packets, i; 2764 struct efx_nic *efx = channel->efx; 2765 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2766 struct efx_rx_queue *rx_queue; 2767 efx_qword_t errors; 2768 bool rx_cont; 2769 u16 flags = 0; 2770 2771 if (unlikely(READ_ONCE(efx->reset_pending))) 2772 return 0; 2773 2774 /* Basic packet information */ 2775 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 2776 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 2777 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 2778 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS); 2779 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS); 2780 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 2781 rx_encap_hdr = 2782 nic_data->datapath_caps & 2783 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ? 2784 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) : 2785 ESE_EZ_ENCAP_HDR_NONE; 2786 2787 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 2788 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 2789 EFX_QWORD_FMT "\n", 2790 EFX_QWORD_VAL(*event)); 2791 2792 rx_queue = efx_channel_get_rx_queue(channel); 2793 2794 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 2795 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 2796 2797 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 2798 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2799 2800 if (n_descs != rx_queue->scatter_n + 1) { 2801 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2802 2803 /* detect rx abort */ 2804 if (unlikely(n_descs == rx_queue->scatter_n)) { 2805 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 2806 netdev_WARN(efx->net_dev, 2807 "invalid RX abort: scatter_n=%u event=" 2808 EFX_QWORD_FMT "\n", 2809 rx_queue->scatter_n, 2810 EFX_QWORD_VAL(*event)); 2811 efx_ef10_handle_rx_abort(rx_queue); 2812 return 0; 2813 } 2814 2815 /* Check that RX completion merging is valid, i.e. 2816 * the current firmware supports it and this is a 2817 * non-scattered packet. 2818 */ 2819 if (!(nic_data->datapath_caps & 2820 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 2821 rx_queue->scatter_n != 0 || rx_cont) { 2822 efx_ef10_handle_rx_bad_lbits( 2823 rx_queue, next_ptr_lbits, 2824 (rx_queue->removed_count + 2825 rx_queue->scatter_n + 1) & 2826 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2827 return 0; 2828 } 2829 2830 /* Merged completion for multiple non-scattered packets */ 2831 rx_queue->scatter_n = 1; 2832 rx_queue->scatter_len = 0; 2833 n_packets = n_descs; 2834 ++channel->n_rx_merge_events; 2835 channel->n_rx_merge_packets += n_packets; 2836 flags |= EFX_RX_PKT_PREFIX_LEN; 2837 } else { 2838 ++rx_queue->scatter_n; 2839 rx_queue->scatter_len += rx_bytes; 2840 if (rx_cont) 2841 return 0; 2842 n_packets = 1; 2843 } 2844 2845 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1, 2846 ESF_DZ_RX_IPCKSUM_ERR, 1, 2847 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1, 2848 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1, 2849 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1); 2850 EFX_AND_QWORD(errors, *event, errors); 2851 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) { 2852 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets, 2853 rx_encap_hdr, 2854 rx_l3_class, rx_l4_class, 2855 event); 2856 } else { 2857 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP || 2858 rx_l4_class == ESE_FZ_L4_CLASS_UDP; 2859 2860 switch (rx_encap_hdr) { 2861 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */ 2862 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */ 2863 if (tcpudp) 2864 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */ 2865 break; 2866 case ESE_EZ_ENCAP_HDR_GRE: 2867 case ESE_EZ_ENCAP_HDR_NONE: 2868 if (tcpudp) 2869 flags |= EFX_RX_PKT_CSUMMED; 2870 break; 2871 default: 2872 netdev_WARN(efx->net_dev, 2873 "unknown encapsulation type: event=" 2874 EFX_QWORD_FMT "\n", 2875 EFX_QWORD_VAL(*event)); 2876 } 2877 } 2878 2879 if (rx_l4_class == ESE_FZ_L4_CLASS_TCP) 2880 flags |= EFX_RX_PKT_TCP; 2881 2882 channel->irq_mod_score += 2 * n_packets; 2883 2884 /* Handle received packet(s) */ 2885 for (i = 0; i < n_packets; i++) { 2886 efx_rx_packet(rx_queue, 2887 rx_queue->removed_count & rx_queue->ptr_mask, 2888 rx_queue->scatter_n, rx_queue->scatter_len, 2889 flags); 2890 rx_queue->removed_count += rx_queue->scatter_n; 2891 } 2892 2893 rx_queue->scatter_n = 0; 2894 rx_queue->scatter_len = 0; 2895 2896 return n_packets; 2897 } 2898 2899 static u32 efx_ef10_extract_event_ts(efx_qword_t *event) 2900 { 2901 u32 tstamp; 2902 2903 tstamp = EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI); 2904 tstamp <<= 16; 2905 tstamp |= EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO); 2906 2907 return tstamp; 2908 } 2909 2910 static void 2911 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 2912 { 2913 struct efx_nic *efx = channel->efx; 2914 struct efx_tx_queue *tx_queue; 2915 unsigned int tx_ev_desc_ptr; 2916 unsigned int tx_ev_q_label; 2917 unsigned int tx_ev_type; 2918 u64 ts_part; 2919 2920 if (unlikely(READ_ONCE(efx->reset_pending))) 2921 return; 2922 2923 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 2924 return; 2925 2926 /* Get the transmit queue */ 2927 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 2928 tx_queue = efx_channel_get_tx_queue(channel, 2929 tx_ev_q_label % EFX_MAX_TXQ_PER_CHANNEL); 2930 2931 if (!tx_queue->timestamping) { 2932 /* Transmit completion */ 2933 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 2934 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 2935 return; 2936 } 2937 2938 /* Transmit timestamps are only available for 8XXX series. They result 2939 * in up to three events per packet. These occur in order, and are: 2940 * - the normal completion event (may be omitted) 2941 * - the low part of the timestamp 2942 * - the high part of the timestamp 2943 * 2944 * It's possible for multiple completion events to appear before the 2945 * corresponding timestamps. So we can for example get: 2946 * COMP N 2947 * COMP N+1 2948 * TS_LO N 2949 * TS_HI N 2950 * TS_LO N+1 2951 * TS_HI N+1 2952 * 2953 * In addition it's also possible for the adjacent completions to be 2954 * merged, so we may not see COMP N above. As such, the completion 2955 * events are not very useful here. 2956 * 2957 * Each part of the timestamp is itself split across two 16 bit 2958 * fields in the event. 2959 */ 2960 tx_ev_type = EFX_QWORD_FIELD(*event, ESF_EZ_TX_SOFT1); 2961 2962 switch (tx_ev_type) { 2963 case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION: 2964 /* Ignore this event - see above. */ 2965 break; 2966 2967 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO: 2968 ts_part = efx_ef10_extract_event_ts(event); 2969 tx_queue->completed_timestamp_minor = ts_part; 2970 break; 2971 2972 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI: 2973 ts_part = efx_ef10_extract_event_ts(event); 2974 tx_queue->completed_timestamp_major = ts_part; 2975 2976 efx_xmit_done_single(tx_queue); 2977 break; 2978 2979 default: 2980 netif_err(efx, hw, efx->net_dev, 2981 "channel %d unknown tx event type %d (data " 2982 EFX_QWORD_FMT ")\n", 2983 channel->channel, tx_ev_type, 2984 EFX_QWORD_VAL(*event)); 2985 break; 2986 } 2987 } 2988 2989 static void 2990 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 2991 { 2992 struct efx_nic *efx = channel->efx; 2993 int subcode; 2994 2995 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 2996 2997 switch (subcode) { 2998 case ESE_DZ_DRV_TIMER_EV: 2999 case ESE_DZ_DRV_WAKE_UP_EV: 3000 break; 3001 case ESE_DZ_DRV_START_UP_EV: 3002 /* event queue init complete. ok. */ 3003 break; 3004 default: 3005 netif_err(efx, hw, efx->net_dev, 3006 "channel %d unknown driver event type %d" 3007 " (data " EFX_QWORD_FMT ")\n", 3008 channel->channel, subcode, 3009 EFX_QWORD_VAL(*event)); 3010 3011 } 3012 } 3013 3014 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 3015 efx_qword_t *event) 3016 { 3017 struct efx_nic *efx = channel->efx; 3018 u32 subcode; 3019 3020 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 3021 3022 switch (subcode) { 3023 case EFX_EF10_TEST: 3024 channel->event_test_cpu = raw_smp_processor_id(); 3025 break; 3026 case EFX_EF10_REFILL: 3027 /* The queue must be empty, so we won't receive any rx 3028 * events, so efx_process_channel() won't refill the 3029 * queue. Refill it here 3030 */ 3031 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 3032 break; 3033 default: 3034 netif_err(efx, hw, efx->net_dev, 3035 "channel %d unknown driver event type %u" 3036 " (data " EFX_QWORD_FMT ")\n", 3037 channel->channel, (unsigned) subcode, 3038 EFX_QWORD_VAL(*event)); 3039 } 3040 } 3041 3042 static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 3043 { 3044 struct efx_nic *efx = channel->efx; 3045 efx_qword_t event, *p_event; 3046 unsigned int read_ptr; 3047 int ev_code; 3048 int spent = 0; 3049 3050 if (quota <= 0) 3051 return spent; 3052 3053 read_ptr = channel->eventq_read_ptr; 3054 3055 for (;;) { 3056 p_event = efx_event(channel, read_ptr); 3057 event = *p_event; 3058 3059 if (!efx_event_present(&event)) 3060 break; 3061 3062 EFX_SET_QWORD(*p_event); 3063 3064 ++read_ptr; 3065 3066 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 3067 3068 netif_vdbg(efx, drv, efx->net_dev, 3069 "processing event on %d " EFX_QWORD_FMT "\n", 3070 channel->channel, EFX_QWORD_VAL(event)); 3071 3072 switch (ev_code) { 3073 case ESE_DZ_EV_CODE_MCDI_EV: 3074 efx_mcdi_process_event(channel, &event); 3075 break; 3076 case ESE_DZ_EV_CODE_RX_EV: 3077 spent += efx_ef10_handle_rx_event(channel, &event); 3078 if (spent >= quota) { 3079 /* XXX can we split a merged event to 3080 * avoid going over-quota? 3081 */ 3082 spent = quota; 3083 goto out; 3084 } 3085 break; 3086 case ESE_DZ_EV_CODE_TX_EV: 3087 efx_ef10_handle_tx_event(channel, &event); 3088 break; 3089 case ESE_DZ_EV_CODE_DRIVER_EV: 3090 efx_ef10_handle_driver_event(channel, &event); 3091 if (++spent == quota) 3092 goto out; 3093 break; 3094 case EFX_EF10_DRVGEN_EV: 3095 efx_ef10_handle_driver_generated_event(channel, &event); 3096 break; 3097 default: 3098 netif_err(efx, hw, efx->net_dev, 3099 "channel %d unknown event type %d" 3100 " (data " EFX_QWORD_FMT ")\n", 3101 channel->channel, ev_code, 3102 EFX_QWORD_VAL(event)); 3103 } 3104 } 3105 3106 out: 3107 channel->eventq_read_ptr = read_ptr; 3108 return spent; 3109 } 3110 3111 static void efx_ef10_ev_read_ack(struct efx_channel *channel) 3112 { 3113 struct efx_nic *efx = channel->efx; 3114 efx_dword_t rptr; 3115 3116 if (EFX_EF10_WORKAROUND_35388(efx)) { 3117 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 3118 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 3119 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 3120 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 3121 3122 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3123 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 3124 ERF_DD_EVQ_IND_RPTR, 3125 (channel->eventq_read_ptr & 3126 channel->eventq_mask) >> 3127 ERF_DD_EVQ_IND_RPTR_WIDTH); 3128 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3129 channel->channel); 3130 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3131 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 3132 ERF_DD_EVQ_IND_RPTR, 3133 channel->eventq_read_ptr & 3134 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 3135 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3136 channel->channel); 3137 } else { 3138 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 3139 channel->eventq_read_ptr & 3140 channel->eventq_mask); 3141 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 3142 } 3143 } 3144 3145 static void efx_ef10_ev_test_generate(struct efx_channel *channel) 3146 { 3147 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 3148 struct efx_nic *efx = channel->efx; 3149 efx_qword_t event; 3150 int rc; 3151 3152 EFX_POPULATE_QWORD_2(event, 3153 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 3154 ESF_DZ_EV_DATA, EFX_EF10_TEST); 3155 3156 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 3157 3158 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 3159 * already swapped the data to little-endian order. 3160 */ 3161 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 3162 sizeof(efx_qword_t)); 3163 3164 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 3165 NULL, 0, NULL); 3166 if (rc != 0) 3167 goto fail; 3168 3169 return; 3170 3171 fail: 3172 WARN_ON(true); 3173 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 3174 } 3175 3176 static void efx_ef10_prepare_flr(struct efx_nic *efx) 3177 { 3178 atomic_set(&efx->active_queues, 0); 3179 } 3180 3181 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx) 3182 { 3183 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3184 u8 mac_old[ETH_ALEN]; 3185 int rc, rc2; 3186 3187 /* Only reconfigure a PF-created vport */ 3188 if (is_zero_ether_addr(nic_data->vport_mac)) 3189 return 0; 3190 3191 efx_device_detach_sync(efx); 3192 efx_net_stop(efx->net_dev); 3193 down_write(&efx->filter_sem); 3194 efx_mcdi_filter_table_remove(efx); 3195 up_write(&efx->filter_sem); 3196 3197 rc = efx_ef10_vadaptor_free(efx, efx->vport_id); 3198 if (rc) 3199 goto restore_filters; 3200 3201 ether_addr_copy(mac_old, nic_data->vport_mac); 3202 rc = efx_ef10_vport_del_mac(efx, efx->vport_id, 3203 nic_data->vport_mac); 3204 if (rc) 3205 goto restore_vadaptor; 3206 3207 rc = efx_ef10_vport_add_mac(efx, efx->vport_id, 3208 efx->net_dev->dev_addr); 3209 if (!rc) { 3210 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr); 3211 } else { 3212 rc2 = efx_ef10_vport_add_mac(efx, efx->vport_id, mac_old); 3213 if (rc2) { 3214 /* Failed to add original MAC, so clear vport_mac */ 3215 eth_zero_addr(nic_data->vport_mac); 3216 goto reset_nic; 3217 } 3218 } 3219 3220 restore_vadaptor: 3221 rc2 = efx_ef10_vadaptor_alloc(efx, efx->vport_id); 3222 if (rc2) 3223 goto reset_nic; 3224 restore_filters: 3225 down_write(&efx->filter_sem); 3226 rc2 = efx_ef10_filter_table_probe(efx); 3227 up_write(&efx->filter_sem); 3228 if (rc2) 3229 goto reset_nic; 3230 3231 rc2 = efx_net_open(efx->net_dev); 3232 if (rc2) 3233 goto reset_nic; 3234 3235 efx_device_attach_if_not_resetting(efx); 3236 3237 return rc; 3238 3239 reset_nic: 3240 netif_err(efx, drv, efx->net_dev, 3241 "Failed to restore when changing MAC address - scheduling reset\n"); 3242 efx_schedule_reset(efx, RESET_TYPE_DATAPATH); 3243 3244 return rc ? rc : rc2; 3245 } 3246 3247 static int efx_ef10_set_mac_address(struct efx_nic *efx) 3248 { 3249 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN); 3250 bool was_enabled = efx->port_enabled; 3251 int rc; 3252 3253 efx_device_detach_sync(efx); 3254 efx_net_stop(efx->net_dev); 3255 3256 mutex_lock(&efx->mac_lock); 3257 down_write(&efx->filter_sem); 3258 efx_mcdi_filter_table_remove(efx); 3259 3260 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR), 3261 efx->net_dev->dev_addr); 3262 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID, 3263 efx->vport_id); 3264 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf, 3265 sizeof(inbuf), NULL, 0, NULL); 3266 3267 efx_ef10_filter_table_probe(efx); 3268 up_write(&efx->filter_sem); 3269 mutex_unlock(&efx->mac_lock); 3270 3271 if (was_enabled) 3272 efx_net_open(efx->net_dev); 3273 efx_device_attach_if_not_resetting(efx); 3274 3275 #ifdef CONFIG_SFC_SRIOV 3276 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) { 3277 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3278 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 3279 3280 if (rc == -EPERM) { 3281 struct efx_nic *efx_pf; 3282 3283 /* Switch to PF and change MAC address on vport */ 3284 efx_pf = pci_get_drvdata(pci_dev_pf); 3285 3286 rc = efx_ef10_sriov_set_vf_mac(efx_pf, 3287 nic_data->vf_index, 3288 efx->net_dev->dev_addr); 3289 } else if (!rc) { 3290 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 3291 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data; 3292 unsigned int i; 3293 3294 /* MAC address successfully changed by VF (with MAC 3295 * spoofing) so update the parent PF if possible. 3296 */ 3297 for (i = 0; i < efx_pf->vf_count; ++i) { 3298 struct ef10_vf *vf = nic_data->vf + i; 3299 3300 if (vf->efx == efx) { 3301 ether_addr_copy(vf->mac, 3302 efx->net_dev->dev_addr); 3303 return 0; 3304 } 3305 } 3306 } 3307 } else 3308 #endif 3309 if (rc == -EPERM) { 3310 netif_err(efx, drv, efx->net_dev, 3311 "Cannot change MAC address; use sfboot to enable" 3312 " mac-spoofing on this interface\n"); 3313 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) { 3314 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC 3315 * fall-back to the method of changing the MAC address on the 3316 * vport. This only applies to PFs because such versions of 3317 * MCFW do not support VFs. 3318 */ 3319 rc = efx_ef10_vport_set_mac_address(efx); 3320 } else if (rc) { 3321 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC, 3322 sizeof(inbuf), NULL, 0, rc); 3323 } 3324 3325 return rc; 3326 } 3327 3328 static int efx_ef10_mac_reconfigure(struct efx_nic *efx, bool mtu_only) 3329 { 3330 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 3331 3332 efx_mcdi_filter_sync_rx_mode(efx); 3333 3334 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED)) 3335 return efx_mcdi_set_mtu(efx); 3336 return efx_mcdi_set_mac(efx); 3337 } 3338 3339 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 3340 { 3341 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 3342 3343 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 3344 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 3345 NULL, 0, NULL); 3346 } 3347 3348 /* MC BISTs follow a different poll mechanism to phy BISTs. 3349 * The BIST is done in the poll handler on the MC, and the MCDI command 3350 * will block until the BIST is done. 3351 */ 3352 static int efx_ef10_poll_bist(struct efx_nic *efx) 3353 { 3354 int rc; 3355 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 3356 size_t outlen; 3357 u32 result; 3358 3359 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 3360 outbuf, sizeof(outbuf), &outlen); 3361 if (rc != 0) 3362 return rc; 3363 3364 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 3365 return -EIO; 3366 3367 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 3368 switch (result) { 3369 case MC_CMD_POLL_BIST_PASSED: 3370 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 3371 return 0; 3372 case MC_CMD_POLL_BIST_TIMEOUT: 3373 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 3374 return -EIO; 3375 case MC_CMD_POLL_BIST_FAILED: 3376 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 3377 return -EIO; 3378 default: 3379 netif_err(efx, hw, efx->net_dev, 3380 "BIST returned unknown result %u", result); 3381 return -EIO; 3382 } 3383 } 3384 3385 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 3386 { 3387 int rc; 3388 3389 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 3390 3391 rc = efx_ef10_start_bist(efx, bist_type); 3392 if (rc != 0) 3393 return rc; 3394 3395 return efx_ef10_poll_bist(efx); 3396 } 3397 3398 static int 3399 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 3400 { 3401 int rc, rc2; 3402 3403 efx_reset_down(efx, RESET_TYPE_WORLD); 3404 3405 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 3406 NULL, 0, NULL, 0, NULL); 3407 if (rc != 0) 3408 goto out; 3409 3410 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 3411 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 3412 3413 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 3414 3415 out: 3416 if (rc == -EPERM) 3417 rc = 0; 3418 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 3419 return rc ? rc : rc2; 3420 } 3421 3422 #ifdef CONFIG_SFC_MTD 3423 3424 struct efx_ef10_nvram_type_info { 3425 u16 type, type_mask; 3426 u8 port; 3427 const char *name; 3428 }; 3429 3430 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 3431 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 3432 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 3433 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 3434 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 3435 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 3436 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 3437 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 3438 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 3439 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 3440 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 3441 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 3442 { NVRAM_PARTITION_TYPE_MUM_FIRMWARE, 0, 0, "sfc_mumfw" }, 3443 { NVRAM_PARTITION_TYPE_EXPANSION_UEFI, 0, 0, "sfc_uefi" }, 3444 { NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS, 0, 0, "sfc_dynamic_cfg_dflt" }, 3445 { NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS, 0, 0, "sfc_exp_rom_cfg_dflt" }, 3446 { NVRAM_PARTITION_TYPE_STATUS, 0, 0, "sfc_status" }, 3447 { NVRAM_PARTITION_TYPE_BUNDLE, 0, 0, "sfc_bundle" }, 3448 { NVRAM_PARTITION_TYPE_BUNDLE_METADATA, 0, 0, "sfc_bundle_metadata" }, 3449 }; 3450 #define EF10_NVRAM_PARTITION_COUNT ARRAY_SIZE(efx_ef10_nvram_types) 3451 3452 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 3453 struct efx_mcdi_mtd_partition *part, 3454 unsigned int type, 3455 unsigned long *found) 3456 { 3457 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 3458 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 3459 const struct efx_ef10_nvram_type_info *info; 3460 size_t size, erase_size, outlen; 3461 int type_idx = 0; 3462 bool protected; 3463 int rc; 3464 3465 for (type_idx = 0; ; type_idx++) { 3466 if (type_idx == EF10_NVRAM_PARTITION_COUNT) 3467 return -ENODEV; 3468 info = efx_ef10_nvram_types + type_idx; 3469 if ((type & ~info->type_mask) == info->type) 3470 break; 3471 } 3472 if (info->port != efx_port_num(efx)) 3473 return -ENODEV; 3474 3475 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 3476 if (rc) 3477 return rc; 3478 if (protected && 3479 (type != NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS && 3480 type != NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS)) 3481 /* Hide protected partitions that don't provide defaults. */ 3482 return -ENODEV; 3483 3484 if (protected) 3485 /* Protected partitions are read only. */ 3486 erase_size = 0; 3487 3488 /* If we've already exposed a partition of this type, hide this 3489 * duplicate. All operations on MTDs are keyed by the type anyway, 3490 * so we can't act on the duplicate. 3491 */ 3492 if (__test_and_set_bit(type_idx, found)) 3493 return -EEXIST; 3494 3495 part->nvram_type = type; 3496 3497 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 3498 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 3499 outbuf, sizeof(outbuf), &outlen); 3500 if (rc) 3501 return rc; 3502 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 3503 return -EIO; 3504 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 3505 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 3506 part->fw_subtype = MCDI_DWORD(outbuf, 3507 NVRAM_METADATA_OUT_SUBTYPE); 3508 3509 part->common.dev_type_name = "EF10 NVRAM manager"; 3510 part->common.type_name = info->name; 3511 3512 part->common.mtd.type = MTD_NORFLASH; 3513 part->common.mtd.flags = MTD_CAP_NORFLASH; 3514 part->common.mtd.size = size; 3515 part->common.mtd.erasesize = erase_size; 3516 /* sfc_status is read-only */ 3517 if (!erase_size) 3518 part->common.mtd.flags |= MTD_NO_ERASE; 3519 3520 return 0; 3521 } 3522 3523 static int efx_ef10_mtd_probe(struct efx_nic *efx) 3524 { 3525 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 3526 DECLARE_BITMAP(found, EF10_NVRAM_PARTITION_COUNT) = { 0 }; 3527 struct efx_mcdi_mtd_partition *parts; 3528 size_t outlen, n_parts_total, i, n_parts; 3529 unsigned int type; 3530 int rc; 3531 3532 ASSERT_RTNL(); 3533 3534 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 3535 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 3536 outbuf, sizeof(outbuf), &outlen); 3537 if (rc) 3538 return rc; 3539 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 3540 return -EIO; 3541 3542 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 3543 if (n_parts_total > 3544 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 3545 return -EIO; 3546 3547 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 3548 if (!parts) 3549 return -ENOMEM; 3550 3551 n_parts = 0; 3552 for (i = 0; i < n_parts_total; i++) { 3553 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 3554 i); 3555 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type, 3556 found); 3557 if (rc == -EEXIST || rc == -ENODEV) 3558 continue; 3559 if (rc) 3560 goto fail; 3561 n_parts++; 3562 } 3563 3564 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 3565 fail: 3566 if (rc) 3567 kfree(parts); 3568 return rc; 3569 } 3570 3571 #endif /* CONFIG_SFC_MTD */ 3572 3573 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 3574 { 3575 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 3576 } 3577 3578 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx, 3579 u32 host_time) {} 3580 3581 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 3582 bool temp) 3583 { 3584 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 3585 int rc; 3586 3587 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 3588 channel->sync_events_state == SYNC_EVENTS_VALID || 3589 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 3590 return 0; 3591 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 3592 3593 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 3594 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3595 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 3596 channel->channel); 3597 3598 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3599 inbuf, sizeof(inbuf), NULL, 0, NULL); 3600 3601 if (rc != 0) 3602 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3603 SYNC_EVENTS_DISABLED; 3604 3605 return rc; 3606 } 3607 3608 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 3609 bool temp) 3610 { 3611 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 3612 int rc; 3613 3614 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 3615 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 3616 return 0; 3617 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 3618 channel->sync_events_state = SYNC_EVENTS_DISABLED; 3619 return 0; 3620 } 3621 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3622 SYNC_EVENTS_DISABLED; 3623 3624 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 3625 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3626 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 3627 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 3628 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 3629 channel->channel); 3630 3631 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3632 inbuf, sizeof(inbuf), NULL, 0, NULL); 3633 3634 return rc; 3635 } 3636 3637 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 3638 bool temp) 3639 { 3640 int (*set)(struct efx_channel *channel, bool temp); 3641 struct efx_channel *channel; 3642 3643 set = en ? 3644 efx_ef10_rx_enable_timestamping : 3645 efx_ef10_rx_disable_timestamping; 3646 3647 channel = efx_ptp_channel(efx); 3648 if (channel) { 3649 int rc = set(channel, temp); 3650 if (en && rc != 0) { 3651 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 3652 return rc; 3653 } 3654 } 3655 3656 return 0; 3657 } 3658 3659 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx, 3660 struct hwtstamp_config *init) 3661 { 3662 return -EOPNOTSUPP; 3663 } 3664 3665 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 3666 struct hwtstamp_config *init) 3667 { 3668 int rc; 3669 3670 switch (init->rx_filter) { 3671 case HWTSTAMP_FILTER_NONE: 3672 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 3673 /* if TX timestamping is still requested then leave PTP on */ 3674 return efx_ptp_change_mode(efx, 3675 init->tx_type != HWTSTAMP_TX_OFF, 0); 3676 case HWTSTAMP_FILTER_ALL: 3677 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3678 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3679 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3680 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3681 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3682 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3683 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3684 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3685 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3686 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3687 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3688 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3689 case HWTSTAMP_FILTER_NTP_ALL: 3690 init->rx_filter = HWTSTAMP_FILTER_ALL; 3691 rc = efx_ptp_change_mode(efx, true, 0); 3692 if (!rc) 3693 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 3694 if (rc) 3695 efx_ptp_change_mode(efx, false, 0); 3696 return rc; 3697 default: 3698 return -ERANGE; 3699 } 3700 } 3701 3702 static int efx_ef10_get_phys_port_id(struct efx_nic *efx, 3703 struct netdev_phys_item_id *ppid) 3704 { 3705 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3706 3707 if (!is_valid_ether_addr(nic_data->port_id)) 3708 return -EOPNOTSUPP; 3709 3710 ppid->id_len = ETH_ALEN; 3711 memcpy(ppid->id, nic_data->port_id, ppid->id_len); 3712 3713 return 0; 3714 } 3715 3716 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3717 { 3718 if (proto != htons(ETH_P_8021Q)) 3719 return -EINVAL; 3720 3721 return efx_ef10_add_vlan(efx, vid); 3722 } 3723 3724 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3725 { 3726 if (proto != htons(ETH_P_8021Q)) 3727 return -EINVAL; 3728 3729 return efx_ef10_del_vlan(efx, vid); 3730 } 3731 3732 /* We rely on the MCDI wiping out our TX rings if it made any changes to the 3733 * ports table, ensuring that any TSO descriptors that were made on a now- 3734 * removed tunnel port will be blown away and won't break things when we try 3735 * to transmit them using the new ports table. 3736 */ 3737 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading) 3738 { 3739 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3740 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX); 3741 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN); 3742 bool will_reset = false; 3743 size_t num_entries = 0; 3744 size_t inlen, outlen; 3745 size_t i; 3746 int rc; 3747 efx_dword_t flags_and_num_entries; 3748 3749 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock)); 3750 3751 nic_data->udp_tunnels_dirty = false; 3752 3753 if (!(nic_data->datapath_caps & 3754 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) { 3755 efx_device_attach_if_not_resetting(efx); 3756 return 0; 3757 } 3758 3759 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) > 3760 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM); 3761 3762 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) { 3763 if (nic_data->udp_tunnels[i].type != 3764 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID) { 3765 efx_dword_t entry; 3766 3767 EFX_POPULATE_DWORD_2(entry, 3768 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT, 3769 ntohs(nic_data->udp_tunnels[i].port), 3770 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL, 3771 nic_data->udp_tunnels[i].type); 3772 *_MCDI_ARRAY_DWORD(inbuf, 3773 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES, 3774 num_entries++) = entry; 3775 } 3776 } 3777 3778 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST - 3779 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 != 3780 EFX_WORD_1_LBN); 3781 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 != 3782 EFX_WORD_1_WIDTH); 3783 EFX_POPULATE_DWORD_2(flags_and_num_entries, 3784 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING, 3785 !!unloading, 3786 EFX_WORD_1, num_entries); 3787 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) = 3788 flags_and_num_entries; 3789 3790 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries); 3791 3792 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS, 3793 inbuf, inlen, outbuf, sizeof(outbuf), &outlen); 3794 if (rc == -EIO) { 3795 /* Most likely the MC rebooted due to another function also 3796 * setting its tunnel port list. Mark the tunnel port list as 3797 * dirty, so it will be pushed upon coming up from the reboot. 3798 */ 3799 nic_data->udp_tunnels_dirty = true; 3800 return 0; 3801 } 3802 3803 if (rc) { 3804 /* expected not available on unprivileged functions */ 3805 if (rc != -EPERM) 3806 netif_warn(efx, drv, efx->net_dev, 3807 "Unable to set UDP tunnel ports; rc=%d.\n", rc); 3808 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) & 3809 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) { 3810 netif_info(efx, drv, efx->net_dev, 3811 "Rebooting MC due to UDP tunnel port list change\n"); 3812 will_reset = true; 3813 if (unloading) 3814 /* Delay for the MC reset to complete. This will make 3815 * unloading other functions a bit smoother. This is a 3816 * race, but the other unload will work whichever way 3817 * it goes, this just avoids an unnecessary error 3818 * message. 3819 */ 3820 msleep(100); 3821 } 3822 if (!will_reset && !unloading) { 3823 /* The caller will have detached, relying on the MC reset to 3824 * trigger a re-attach. Since there won't be an MC reset, we 3825 * have to do the attach ourselves. 3826 */ 3827 efx_device_attach_if_not_resetting(efx); 3828 } 3829 3830 return rc; 3831 } 3832 3833 static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx) 3834 { 3835 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3836 int rc = 0; 3837 3838 mutex_lock(&nic_data->udp_tunnels_lock); 3839 if (nic_data->udp_tunnels_dirty) { 3840 /* Make sure all TX are stopped while we modify the table, else 3841 * we might race against an efx_features_check(). 3842 */ 3843 efx_device_detach_sync(efx); 3844 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3845 } 3846 mutex_unlock(&nic_data->udp_tunnels_lock); 3847 return rc; 3848 } 3849 3850 static int efx_ef10_udp_tnl_set_port(struct net_device *dev, 3851 unsigned int table, unsigned int entry, 3852 struct udp_tunnel_info *ti) 3853 { 3854 struct efx_nic *efx = netdev_priv(dev); 3855 struct efx_ef10_nic_data *nic_data; 3856 int efx_tunnel_type, rc; 3857 3858 if (ti->type == UDP_TUNNEL_TYPE_VXLAN) 3859 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN; 3860 else 3861 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE; 3862 3863 nic_data = efx->nic_data; 3864 if (!(nic_data->datapath_caps & 3865 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3866 return -EOPNOTSUPP; 3867 3868 mutex_lock(&nic_data->udp_tunnels_lock); 3869 /* Make sure all TX are stopped while we add to the table, else we 3870 * might race against an efx_features_check(). 3871 */ 3872 efx_device_detach_sync(efx); 3873 nic_data->udp_tunnels[entry].type = efx_tunnel_type; 3874 nic_data->udp_tunnels[entry].port = ti->port; 3875 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3876 mutex_unlock(&nic_data->udp_tunnels_lock); 3877 3878 return rc; 3879 } 3880 3881 /* Called under the TX lock with the TX queue running, hence no-one can be 3882 * in the middle of updating the UDP tunnels table. However, they could 3883 * have tried and failed the MCDI, in which case they'll have set the dirty 3884 * flag before dropping their locks. 3885 */ 3886 static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port) 3887 { 3888 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3889 size_t i; 3890 3891 if (!(nic_data->datapath_caps & 3892 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3893 return false; 3894 3895 if (nic_data->udp_tunnels_dirty) 3896 /* SW table may not match HW state, so just assume we can't 3897 * use any UDP tunnel offloads. 3898 */ 3899 return false; 3900 3901 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) 3902 if (nic_data->udp_tunnels[i].type != 3903 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID && 3904 nic_data->udp_tunnels[i].port == port) 3905 return true; 3906 3907 return false; 3908 } 3909 3910 static int efx_ef10_udp_tnl_unset_port(struct net_device *dev, 3911 unsigned int table, unsigned int entry, 3912 struct udp_tunnel_info *ti) 3913 { 3914 struct efx_nic *efx = netdev_priv(dev); 3915 struct efx_ef10_nic_data *nic_data; 3916 int rc; 3917 3918 nic_data = efx->nic_data; 3919 3920 mutex_lock(&nic_data->udp_tunnels_lock); 3921 /* Make sure all TX are stopped while we remove from the table, else we 3922 * might race against an efx_features_check(). 3923 */ 3924 efx_device_detach_sync(efx); 3925 nic_data->udp_tunnels[entry].type = TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID; 3926 nic_data->udp_tunnels[entry].port = 0; 3927 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3928 mutex_unlock(&nic_data->udp_tunnels_lock); 3929 3930 return rc; 3931 } 3932 3933 static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels = { 3934 .set_port = efx_ef10_udp_tnl_set_port, 3935 .unset_port = efx_ef10_udp_tnl_unset_port, 3936 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP, 3937 .tables = { 3938 { 3939 .n_entries = 16, 3940 .tunnel_types = UDP_TUNNEL_TYPE_VXLAN | 3941 UDP_TUNNEL_TYPE_GENEVE, 3942 }, 3943 }, 3944 }; 3945 3946 /* EF10 may have multiple datapath firmware variants within a 3947 * single version. Report which variants are running. 3948 */ 3949 static size_t efx_ef10_print_additional_fwver(struct efx_nic *efx, char *buf, 3950 size_t len) 3951 { 3952 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3953 3954 return scnprintf(buf, len, " rx%x tx%x", 3955 nic_data->rx_dpcpu_fw_id, 3956 nic_data->tx_dpcpu_fw_id); 3957 } 3958 3959 static unsigned int ef10_check_caps(const struct efx_nic *efx, 3960 u8 flag, 3961 u32 offset) 3962 { 3963 const struct efx_ef10_nic_data *nic_data = efx->nic_data; 3964 3965 switch (offset) { 3966 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST): 3967 return nic_data->datapath_caps & BIT_ULL(flag); 3968 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST): 3969 return nic_data->datapath_caps2 & BIT_ULL(flag); 3970 default: 3971 return 0; 3972 } 3973 } 3974 3975 #define EF10_OFFLOAD_FEATURES \ 3976 (NETIF_F_IP_CSUM | \ 3977 NETIF_F_HW_VLAN_CTAG_FILTER | \ 3978 NETIF_F_IPV6_CSUM | \ 3979 NETIF_F_RXHASH | \ 3980 NETIF_F_NTUPLE) 3981 3982 const struct efx_nic_type efx_hunt_a0_vf_nic_type = { 3983 .is_vf = true, 3984 .mem_bar = efx_ef10_vf_mem_bar, 3985 .mem_map_size = efx_ef10_mem_map_size, 3986 .probe = efx_ef10_probe_vf, 3987 .remove = efx_ef10_remove, 3988 .dimension_resources = efx_ef10_dimension_resources, 3989 .init = efx_ef10_init_nic, 3990 .fini = efx_ef10_fini_nic, 3991 .map_reset_reason = efx_ef10_map_reset_reason, 3992 .map_reset_flags = efx_ef10_map_reset_flags, 3993 .reset = efx_ef10_reset, 3994 .probe_port = efx_mcdi_port_probe, 3995 .remove_port = efx_mcdi_port_remove, 3996 .fini_dmaq = efx_fini_dmaq, 3997 .prepare_flr = efx_ef10_prepare_flr, 3998 .finish_flr = efx_port_dummy_op_void, 3999 .describe_stats = efx_ef10_describe_stats, 4000 .update_stats = efx_ef10_update_stats_vf, 4001 .start_stats = efx_port_dummy_op_void, 4002 .pull_stats = efx_port_dummy_op_void, 4003 .stop_stats = efx_port_dummy_op_void, 4004 .push_irq_moderation = efx_ef10_push_irq_moderation, 4005 .reconfigure_mac = efx_ef10_mac_reconfigure, 4006 .check_mac_fault = efx_mcdi_mac_check_fault, 4007 .reconfigure_port = efx_mcdi_port_reconfigure, 4008 .get_wol = efx_ef10_get_wol_vf, 4009 .set_wol = efx_ef10_set_wol_vf, 4010 .resume_wol = efx_port_dummy_op_void, 4011 .mcdi_request = efx_ef10_mcdi_request, 4012 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4013 .mcdi_read_response = efx_ef10_mcdi_read_response, 4014 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4015 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4016 .irq_enable_master = efx_port_dummy_op_void, 4017 .irq_test_generate = efx_ef10_irq_test_generate, 4018 .irq_disable_non_ev = efx_port_dummy_op_void, 4019 .irq_handle_msi = efx_ef10_msi_interrupt, 4020 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4021 .tx_probe = efx_ef10_tx_probe, 4022 .tx_init = efx_ef10_tx_init, 4023 .tx_remove = efx_mcdi_tx_remove, 4024 .tx_write = efx_ef10_tx_write, 4025 .tx_limit_len = efx_ef10_tx_limit_len, 4026 .tx_enqueue = __efx_enqueue_skb, 4027 .rx_push_rss_config = efx_mcdi_vf_rx_push_rss_config, 4028 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 4029 .rx_probe = efx_mcdi_rx_probe, 4030 .rx_init = efx_mcdi_rx_init, 4031 .rx_remove = efx_mcdi_rx_remove, 4032 .rx_write = efx_ef10_rx_write, 4033 .rx_defer_refill = efx_ef10_rx_defer_refill, 4034 .rx_packet = __efx_rx_packet, 4035 .ev_probe = efx_mcdi_ev_probe, 4036 .ev_init = efx_ef10_ev_init, 4037 .ev_fini = efx_mcdi_ev_fini, 4038 .ev_remove = efx_mcdi_ev_remove, 4039 .ev_process = efx_ef10_ev_process, 4040 .ev_read_ack = efx_ef10_ev_read_ack, 4041 .ev_test_generate = efx_ef10_ev_test_generate, 4042 .filter_table_probe = efx_ef10_filter_table_probe, 4043 .filter_table_restore = efx_mcdi_filter_table_restore, 4044 .filter_table_remove = efx_mcdi_filter_table_remove, 4045 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 4046 .filter_insert = efx_mcdi_filter_insert, 4047 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4048 .filter_get_safe = efx_mcdi_filter_get_safe, 4049 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4050 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4051 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4052 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4053 #ifdef CONFIG_RFS_ACCEL 4054 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4055 #endif 4056 #ifdef CONFIG_SFC_MTD 4057 .mtd_probe = efx_port_dummy_op_int, 4058 #endif 4059 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf, 4060 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf, 4061 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4062 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4063 #ifdef CONFIG_SFC_SRIOV 4064 .vswitching_probe = efx_ef10_vswitching_probe_vf, 4065 .vswitching_restore = efx_ef10_vswitching_restore_vf, 4066 .vswitching_remove = efx_ef10_vswitching_remove_vf, 4067 #endif 4068 .get_mac_address = efx_ef10_get_mac_address_vf, 4069 .set_mac_address = efx_ef10_set_mac_address, 4070 4071 .get_phys_port_id = efx_ef10_get_phys_port_id, 4072 .revision = EFX_REV_HUNT_A0, 4073 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4074 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4075 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4076 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4077 .can_rx_scatter = true, 4078 .always_rx_scatter = true, 4079 .min_interrupt_mode = EFX_INT_MODE_MSIX, 4080 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4081 .offload_features = EF10_OFFLOAD_FEATURES, 4082 .mcdi_max_ver = 2, 4083 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4084 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4085 1 << HWTSTAMP_FILTER_ALL, 4086 .rx_hash_key_size = 40, 4087 .check_caps = ef10_check_caps, 4088 .print_additional_fwver = efx_ef10_print_additional_fwver, 4089 .sensor_event = efx_mcdi_sensor_event, 4090 }; 4091 4092 const struct efx_nic_type efx_hunt_a0_nic_type = { 4093 .is_vf = false, 4094 .mem_bar = efx_ef10_pf_mem_bar, 4095 .mem_map_size = efx_ef10_mem_map_size, 4096 .probe = efx_ef10_probe_pf, 4097 .remove = efx_ef10_remove, 4098 .dimension_resources = efx_ef10_dimension_resources, 4099 .init = efx_ef10_init_nic, 4100 .fini = efx_ef10_fini_nic, 4101 .map_reset_reason = efx_ef10_map_reset_reason, 4102 .map_reset_flags = efx_ef10_map_reset_flags, 4103 .reset = efx_ef10_reset, 4104 .probe_port = efx_mcdi_port_probe, 4105 .remove_port = efx_mcdi_port_remove, 4106 .fini_dmaq = efx_fini_dmaq, 4107 .prepare_flr = efx_ef10_prepare_flr, 4108 .finish_flr = efx_port_dummy_op_void, 4109 .describe_stats = efx_ef10_describe_stats, 4110 .update_stats = efx_ef10_update_stats_pf, 4111 .start_stats = efx_mcdi_mac_start_stats, 4112 .pull_stats = efx_mcdi_mac_pull_stats, 4113 .stop_stats = efx_mcdi_mac_stop_stats, 4114 .push_irq_moderation = efx_ef10_push_irq_moderation, 4115 .reconfigure_mac = efx_ef10_mac_reconfigure, 4116 .check_mac_fault = efx_mcdi_mac_check_fault, 4117 .reconfigure_port = efx_mcdi_port_reconfigure, 4118 .get_wol = efx_ef10_get_wol, 4119 .set_wol = efx_ef10_set_wol, 4120 .resume_wol = efx_port_dummy_op_void, 4121 .test_chip = efx_ef10_test_chip, 4122 .test_nvram = efx_mcdi_nvram_test_all, 4123 .mcdi_request = efx_ef10_mcdi_request, 4124 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4125 .mcdi_read_response = efx_ef10_mcdi_read_response, 4126 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4127 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4128 .irq_enable_master = efx_port_dummy_op_void, 4129 .irq_test_generate = efx_ef10_irq_test_generate, 4130 .irq_disable_non_ev = efx_port_dummy_op_void, 4131 .irq_handle_msi = efx_ef10_msi_interrupt, 4132 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4133 .tx_probe = efx_ef10_tx_probe, 4134 .tx_init = efx_ef10_tx_init, 4135 .tx_remove = efx_mcdi_tx_remove, 4136 .tx_write = efx_ef10_tx_write, 4137 .tx_limit_len = efx_ef10_tx_limit_len, 4138 .tx_enqueue = __efx_enqueue_skb, 4139 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 4140 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 4141 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config, 4142 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config, 4143 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 4144 .rx_probe = efx_mcdi_rx_probe, 4145 .rx_init = efx_mcdi_rx_init, 4146 .rx_remove = efx_mcdi_rx_remove, 4147 .rx_write = efx_ef10_rx_write, 4148 .rx_defer_refill = efx_ef10_rx_defer_refill, 4149 .rx_packet = __efx_rx_packet, 4150 .ev_probe = efx_mcdi_ev_probe, 4151 .ev_init = efx_ef10_ev_init, 4152 .ev_fini = efx_mcdi_ev_fini, 4153 .ev_remove = efx_mcdi_ev_remove, 4154 .ev_process = efx_ef10_ev_process, 4155 .ev_read_ack = efx_ef10_ev_read_ack, 4156 .ev_test_generate = efx_ef10_ev_test_generate, 4157 .filter_table_probe = efx_ef10_filter_table_probe, 4158 .filter_table_restore = efx_mcdi_filter_table_restore, 4159 .filter_table_remove = efx_mcdi_filter_table_remove, 4160 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 4161 .filter_insert = efx_mcdi_filter_insert, 4162 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4163 .filter_get_safe = efx_mcdi_filter_get_safe, 4164 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4165 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4166 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4167 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4168 #ifdef CONFIG_RFS_ACCEL 4169 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4170 #endif 4171 #ifdef CONFIG_SFC_MTD 4172 .mtd_probe = efx_ef10_mtd_probe, 4173 .mtd_rename = efx_mcdi_mtd_rename, 4174 .mtd_read = efx_mcdi_mtd_read, 4175 .mtd_erase = efx_mcdi_mtd_erase, 4176 .mtd_write = efx_mcdi_mtd_write, 4177 .mtd_sync = efx_mcdi_mtd_sync, 4178 #endif 4179 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 4180 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 4181 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 4182 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4183 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4184 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports, 4185 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port, 4186 #ifdef CONFIG_SFC_SRIOV 4187 .sriov_configure = efx_ef10_sriov_configure, 4188 .sriov_init = efx_ef10_sriov_init, 4189 .sriov_fini = efx_ef10_sriov_fini, 4190 .sriov_wanted = efx_ef10_sriov_wanted, 4191 .sriov_reset = efx_ef10_sriov_reset, 4192 .sriov_flr = efx_ef10_sriov_flr, 4193 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, 4194 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, 4195 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, 4196 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, 4197 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state, 4198 .vswitching_probe = efx_ef10_vswitching_probe_pf, 4199 .vswitching_restore = efx_ef10_vswitching_restore_pf, 4200 .vswitching_remove = efx_ef10_vswitching_remove_pf, 4201 #endif 4202 .get_mac_address = efx_ef10_get_mac_address_pf, 4203 .set_mac_address = efx_ef10_set_mac_address, 4204 .tso_versions = efx_ef10_tso_versions, 4205 4206 .get_phys_port_id = efx_ef10_get_phys_port_id, 4207 .revision = EFX_REV_HUNT_A0, 4208 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4209 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4210 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4211 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4212 .can_rx_scatter = true, 4213 .always_rx_scatter = true, 4214 .option_descriptors = true, 4215 .min_interrupt_mode = EFX_INT_MODE_LEGACY, 4216 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4217 .offload_features = EF10_OFFLOAD_FEATURES, 4218 .mcdi_max_ver = 2, 4219 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4220 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4221 1 << HWTSTAMP_FILTER_ALL, 4222 .rx_hash_key_size = 40, 4223 .check_caps = ef10_check_caps, 4224 .print_additional_fwver = efx_ef10_print_additional_fwver, 4225 .sensor_event = efx_mcdi_sensor_event, 4226 }; 4227