1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 10G controller driver for Samsung SoCs 3 * 4 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * Author: Siva Reddy Kallam <siva.kallam@samsung.com> 8 */ 9 #ifndef __SXGBE_REGMAP_H__ 10 #define __SXGBE_REGMAP_H__ 11 12 /* SXGBE MAC Registers */ 13 #define SXGBE_CORE_TX_CONFIG_REG 0x0000 14 #define SXGBE_CORE_RX_CONFIG_REG 0x0004 15 #define SXGBE_CORE_PKT_FILTER_REG 0x0008 16 #define SXGBE_CORE_WATCHDOG_TIMEOUT_REG 0x000C 17 #define SXGBE_CORE_HASH_TABLE_REG0 0x0010 18 #define SXGBE_CORE_HASH_TABLE_REG1 0x0014 19 #define SXGBE_CORE_HASH_TABLE_REG2 0x0018 20 #define SXGBE_CORE_HASH_TABLE_REG3 0x001C 21 #define SXGBE_CORE_HASH_TABLE_REG4 0x0020 22 #define SXGBE_CORE_HASH_TABLE_REG5 0x0024 23 #define SXGBE_CORE_HASH_TABLE_REG6 0x0028 24 #define SXGBE_CORE_HASH_TABLE_REG7 0x002C 25 26 /* EEE-LPI Registers */ 27 #define SXGBE_CORE_LPI_CTRL_STATUS 0x00D0 28 #define SXGBE_CORE_LPI_TIMER_CTRL 0x00D4 29 30 /* VLAN Specific Registers */ 31 #define SXGBE_CORE_VLAN_TAG_REG 0x0050 32 #define SXGBE_CORE_VLAN_HASHTAB_REG 0x0058 33 #define SXGBE_CORE_VLAN_INSCTL_REG 0x0060 34 #define SXGBE_CORE_VLAN_INNERCTL_REG 0x0064 35 #define SXGBE_CORE_RX_ETHTYPE_MATCH_REG 0x006C 36 37 /* Flow Contol Registers */ 38 #define SXGBE_CORE_TX_Q0_FLOWCTL_REG 0x0070 39 #define SXGBE_CORE_TX_Q1_FLOWCTL_REG 0x0074 40 #define SXGBE_CORE_TX_Q2_FLOWCTL_REG 0x0078 41 #define SXGBE_CORE_TX_Q3_FLOWCTL_REG 0x007C 42 #define SXGBE_CORE_TX_Q4_FLOWCTL_REG 0x0080 43 #define SXGBE_CORE_TX_Q5_FLOWCTL_REG 0x0084 44 #define SXGBE_CORE_TX_Q6_FLOWCTL_REG 0x0088 45 #define SXGBE_CORE_TX_Q7_FLOWCTL_REG 0x008C 46 #define SXGBE_CORE_RX_FLOWCTL_REG 0x0090 47 #define SXGBE_CORE_RX_CTL0_REG 0x00A0 48 #define SXGBE_CORE_RX_CTL1_REG 0x00A4 49 #define SXGBE_CORE_RX_CTL2_REG 0x00A8 50 #define SXGBE_CORE_RX_CTL3_REG 0x00AC 51 52 #define SXGBE_CORE_RXQ_ENABLE_MASK 0x0003 53 #define SXGBE_CORE_RXQ_ENABLE 0x0002 54 #define SXGBE_CORE_RXQ_DISABLE 0x0000 55 56 /* Interrupt Registers */ 57 #define SXGBE_CORE_INT_STATUS_REG 0x00B0 58 #define SXGBE_CORE_INT_ENABLE_REG 0x00B4 59 #define SXGBE_CORE_RXTX_ERR_STATUS_REG 0x00B8 60 #define SXGBE_CORE_PMT_CTL_STATUS_REG 0x00C0 61 #define SXGBE_CORE_RWK_PKT_FILTER_REG 0x00C4 62 #define SXGBE_CORE_VERSION_REG 0x0110 63 #define SXGBE_CORE_DEBUG_REG 0x0114 64 #define SXGBE_CORE_HW_FEA_REG(index) (0x011C + index * 4) 65 66 /* SMA(MDIO) module registers */ 67 #define SXGBE_MDIO_SCMD_ADD_REG 0x0200 68 #define SXGBE_MDIO_SCMD_DATA_REG 0x0204 69 #define SXGBE_MDIO_CCMD_WADD_REG 0x0208 70 #define SXGBE_MDIO_CCMD_WDATA_REG 0x020C 71 #define SXGBE_MDIO_CSCAN_PORT_REG 0x0210 72 #define SXGBE_MDIO_INT_STATUS_REG 0x0214 73 #define SXGBE_MDIO_INT_ENABLE_REG 0x0218 74 #define SXGBE_MDIO_PORT_CONDCON_REG 0x021C 75 #define SXGBE_MDIO_CLAUSE22_PORT_REG 0x0220 76 77 /* port specific, addr = 0-3 */ 78 #define SXGBE_MDIO_DEV_BASE_REG 0x0230 79 #define SXGBE_MDIO_PORT_DEV_REG(addr) \ 80 (SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x0) 81 #define SXGBE_MDIO_PORT_LSTATUS_REG(addr) \ 82 (SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x4) 83 #define SXGBE_MDIO_PORT_ALIVE_REG(addr) \ 84 (SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x8) 85 86 #define SXGBE_CORE_GPIO_CTL_REG 0x0278 87 #define SXGBE_CORE_GPIO_STATUS_REG 0x027C 88 89 /* Address registers for filtering */ 90 #define SXGBE_CORE_ADD_BASE_REG 0x0300 91 92 /* addr = 0-31 */ 93 #define SXGBE_CORE_ADD_HIGHOFFSET(addr) \ 94 (SXGBE_CORE_ADD_BASE_REG + (0x8 * addr) + 0x0) 95 #define SXGBE_CORE_ADD_LOWOFFSET(addr) \ 96 (SXGBE_CORE_ADD_BASE_REG + (0x8 * addr) + 0x4) 97 98 /* SXGBE MMC registers */ 99 #define SXGBE_MMC_CTL_REG 0x0800 100 #define SXGBE_MMC_RXINT_STATUS_REG 0x0804 101 #define SXGBE_MMC_TXINT_STATUS_REG 0x0808 102 #define SXGBE_MMC_RXINT_ENABLE_REG 0x080C 103 #define SXGBE_MMC_TXINT_ENABLE_REG 0x0810 104 105 /* TX specific counters */ 106 #define SXGBE_MMC_TXOCTETHI_GBCNT_REG 0x0814 107 #define SXGBE_MMC_TXOCTETLO_GBCNT_REG 0x0818 108 #define SXGBE_MMC_TXFRAMELO_GBCNT_REG 0x081C 109 #define SXGBE_MMC_TXFRAMEHI_GBCNT_REG 0x0820 110 #define SXGBE_MMC_TXBROADLO_GCNT_REG 0x0824 111 #define SXGBE_MMC_TXBROADHI_GCNT_REG 0x0828 112 #define SXGBE_MMC_TXMULTILO_GCNT_REG 0x082C 113 #define SXGBE_MMC_TXMULTIHI_GCNT_REG 0x0830 114 #define SXGBE_MMC_TX64LO_GBCNT_REG 0x0834 115 #define SXGBE_MMC_TX64HI_GBCNT_REG 0x0838 116 #define SXGBE_MMC_TX65TO127LO_GBCNT_REG 0x083C 117 #define SXGBE_MMC_TX65TO127HI_GBCNT_REG 0x0840 118 #define SXGBE_MMC_TX128TO255LO_GBCNT_REG 0x0844 119 #define SXGBE_MMC_TX128TO255HI_GBCNT_REG 0x0848 120 #define SXGBE_MMC_TX256TO511LO_GBCNT_REG 0x084C 121 #define SXGBE_MMC_TX256TO511HI_GBCNT_REG 0x0850 122 #define SXGBE_MMC_TX512TO1023LO_GBCNT_REG 0x0854 123 #define SXGBE_MMC_TX512TO1023HI_GBCNT_REG 0x0858 124 #define SXGBE_MMC_TX1023TOMAXLO_GBCNT_REG 0x085C 125 #define SXGBE_MMC_TX1023TOMAXHI_GBCNT_REG 0x0860 126 #define SXGBE_MMC_TXUNICASTLO_GBCNT_REG 0x0864 127 #define SXGBE_MMC_TXUNICASTHI_GBCNT_REG 0x0868 128 #define SXGBE_MMC_TXMULTILO_GBCNT_REG 0x086C 129 #define SXGBE_MMC_TXMULTIHI_GBCNT_REG 0x0870 130 #define SXGBE_MMC_TXBROADLO_GBCNT_REG 0x0874 131 #define SXGBE_MMC_TXBROADHI_GBCNT_REG 0x0878 132 #define SXGBE_MMC_TXUFLWLO_GBCNT_REG 0x087C 133 #define SXGBE_MMC_TXUFLWHI_GBCNT_REG 0x0880 134 #define SXGBE_MMC_TXOCTETLO_GCNT_REG 0x0884 135 #define SXGBE_MMC_TXOCTETHI_GCNT_REG 0x0888 136 #define SXGBE_MMC_TXFRAMELO_GCNT_REG 0x088C 137 #define SXGBE_MMC_TXFRAMEHI_GCNT_REG 0x0890 138 #define SXGBE_MMC_TXPAUSELO_CNT_REG 0x0894 139 #define SXGBE_MMC_TXPAUSEHI_CNT_REG 0x0898 140 #define SXGBE_MMC_TXVLANLO_GCNT_REG 0x089C 141 #define SXGBE_MMC_TXVLANHI_GCNT_REG 0x08A0 142 143 /* RX specific counters */ 144 #define SXGBE_MMC_RXFRAMELO_GBCNT_REG 0x0900 145 #define SXGBE_MMC_RXFRAMEHI_GBCNT_REG 0x0904 146 #define SXGBE_MMC_RXOCTETLO_GBCNT_REG 0x0908 147 #define SXGBE_MMC_RXOCTETHI_GBCNT_REG 0x090C 148 #define SXGBE_MMC_RXOCTETLO_GCNT_REG 0x0910 149 #define SXGBE_MMC_RXOCTETHI_GCNT_REG 0x0914 150 #define SXGBE_MMC_RXBROADLO_GCNT_REG 0x0918 151 #define SXGBE_MMC_RXBROADHI_GCNT_REG 0x091C 152 #define SXGBE_MMC_RXMULTILO_GCNT_REG 0x0920 153 #define SXGBE_MMC_RXMULTIHI_GCNT_REG 0x0924 154 #define SXGBE_MMC_RXCRCERRLO_REG 0x0928 155 #define SXGBE_MMC_RXCRCERRHI_REG 0x092C 156 #define SXGBE_MMC_RXSHORT64BFRAME_ERR_REG 0x0930 157 #define SXGBE_MMC_RXJABBERERR_REG 0x0934 158 #define SXGBE_MMC_RXSHORT64BFRAME_COR_REG 0x0938 159 #define SXGBE_MMC_RXOVERMAXFRAME_COR_REG 0x093C 160 #define SXGBE_MMC_RX64LO_GBCNT_REG 0x0940 161 #define SXGBE_MMC_RX64HI_GBCNT_REG 0x0944 162 #define SXGBE_MMC_RX65TO127LO_GBCNT_REG 0x0948 163 #define SXGBE_MMC_RX65TO127HI_GBCNT_REG 0x094C 164 #define SXGBE_MMC_RX128TO255LO_GBCNT_REG 0x0950 165 #define SXGBE_MMC_RX128TO255HI_GBCNT_REG 0x0954 166 #define SXGBE_MMC_RX256TO511LO_GBCNT_REG 0x0958 167 #define SXGBE_MMC_RX256TO511HI_GBCNT_REG 0x095C 168 #define SXGBE_MMC_RX512TO1023LO_GBCNT_REG 0x0960 169 #define SXGBE_MMC_RX512TO1023HI_GBCNT_REG 0x0964 170 #define SXGBE_MMC_RX1023TOMAXLO_GBCNT_REG 0x0968 171 #define SXGBE_MMC_RX1023TOMAXHI_GBCNT_REG 0x096C 172 #define SXGBE_MMC_RXUNICASTLO_GCNT_REG 0x0970 173 #define SXGBE_MMC_RXUNICASTHI_GCNT_REG 0x0974 174 #define SXGBE_MMC_RXLENERRLO_REG 0x0978 175 #define SXGBE_MMC_RXLENERRHI_REG 0x097C 176 #define SXGBE_MMC_RXOUTOFRANGETYPELO_REG 0x0980 177 #define SXGBE_MMC_RXOUTOFRANGETYPEHI_REG 0x0984 178 #define SXGBE_MMC_RXPAUSELO_CNT_REG 0x0988 179 #define SXGBE_MMC_RXPAUSEHI_CNT_REG 0x098C 180 #define SXGBE_MMC_RXFIFOOVERFLOWLO_GBCNT_REG 0x0990 181 #define SXGBE_MMC_RXFIFOOVERFLOWHI_GBCNT_REG 0x0994 182 #define SXGBE_MMC_RXVLANLO_GBCNT_REG 0x0998 183 #define SXGBE_MMC_RXVLANHI_GBCNT_REG 0x099C 184 #define SXGBE_MMC_RXWATCHDOG_ERR_REG 0x09A0 185 186 /* L3/L4 function registers */ 187 #define SXGBE_CORE_L34_ADDCTL_REG 0x0C00 188 #define SXGBE_CORE_L34_DATA_REG 0x0C04 189 190 /* ARP registers */ 191 #define SXGBE_CORE_ARP_ADD_REG 0x0C10 192 193 /* RSS registers */ 194 #define SXGBE_CORE_RSS_CTL_REG 0x0C80 195 #define SXGBE_CORE_RSS_ADD_REG 0x0C88 196 #define SXGBE_CORE_RSS_DATA_REG 0x0C8C 197 198 /* RSS control register bits */ 199 #define SXGBE_CORE_RSS_CTL_UDP4TE BIT(3) 200 #define SXGBE_CORE_RSS_CTL_TCP4TE BIT(2) 201 #define SXGBE_CORE_RSS_CTL_IP2TE BIT(1) 202 #define SXGBE_CORE_RSS_CTL_RSSE BIT(0) 203 204 /* IEEE 1588 registers */ 205 #define SXGBE_CORE_TSTAMP_CTL_REG 0x0D00 206 #define SXGBE_CORE_SUBSEC_INC_REG 0x0D04 207 #define SXGBE_CORE_SYSTIME_SEC_REG 0x0D0C 208 #define SXGBE_CORE_SYSTIME_NSEC_REG 0x0D10 209 #define SXGBE_CORE_SYSTIME_SECUP_REG 0x0D14 210 #define SXGBE_CORE_TSTAMP_ADD_REG 0x0D18 211 #define SXGBE_CORE_SYSTIME_HWORD_REG 0x0D1C 212 #define SXGBE_CORE_TSTAMP_STATUS_REG 0x0D20 213 #define SXGBE_CORE_TXTIME_STATUSNSEC_REG 0x0D30 214 #define SXGBE_CORE_TXTIME_STATUSSEC_REG 0x0D34 215 216 /* Auxiliary registers */ 217 #define SXGBE_CORE_AUX_CTL_REG 0x0D40 218 #define SXGBE_CORE_AUX_TSTAMP_NSEC_REG 0x0D48 219 #define SXGBE_CORE_AUX_TSTAMP_SEC_REG 0x0D4C 220 #define SXGBE_CORE_AUX_TSTAMP_INGCOR_REG 0x0D50 221 #define SXGBE_CORE_AUX_TSTAMP_ENGCOR_REG 0x0D54 222 #define SXGBE_CORE_AUX_TSTAMP_INGCOR_NSEC_REG 0x0D58 223 #define SXGBE_CORE_AUX_TSTAMP_INGCOR_SUBNSEC_REG 0x0D5C 224 #define SXGBE_CORE_AUX_TSTAMP_ENGCOR_NSEC_REG 0x0D60 225 #define SXGBE_CORE_AUX_TSTAMP_ENGCOR_SUBNSEC_REG 0x0D64 226 227 /* PPS registers */ 228 #define SXGBE_CORE_PPS_CTL_REG 0x0D70 229 #define SXGBE_CORE_PPS_BASE 0x0D80 230 231 /* addr = 0 - 3 */ 232 #define SXGBE_CORE_PPS_TTIME_SEC_REG(addr) \ 233 (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0x0) 234 #define SXGBE_CORE_PPS_TTIME_NSEC_REG(addr) \ 235 (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0x4) 236 #define SXGBE_CORE_PPS_INTERVAL_REG(addr) \ 237 (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0x8) 238 #define SXGBE_CORE_PPS_WIDTH_REG(addr) \ 239 (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0xC) 240 #define SXGBE_CORE_PTO_CTL_REG 0x0DC0 241 #define SXGBE_CORE_SRCPORT_ITY0_REG 0x0DC4 242 #define SXGBE_CORE_SRCPORT_ITY1_REG 0x0DC8 243 #define SXGBE_CORE_SRCPORT_ITY2_REG 0x0DCC 244 #define SXGBE_CORE_LOGMSG_LEVEL_REG 0x0DD0 245 246 /* SXGBE MTL Registers */ 247 #define SXGBE_MTL_BASE_REG 0x1000 248 #define SXGBE_MTL_OP_MODE_REG (SXGBE_MTL_BASE_REG + 0x0000) 249 #define SXGBE_MTL_DEBUG_CTL_REG (SXGBE_MTL_BASE_REG + 0x0008) 250 #define SXGBE_MTL_DEBUG_STATUS_REG (SXGBE_MTL_BASE_REG + 0x000C) 251 #define SXGBE_MTL_FIFO_DEBUGDATA_REG (SXGBE_MTL_BASE_REG + 0x0010) 252 #define SXGBE_MTL_INT_STATUS_REG (SXGBE_MTL_BASE_REG + 0x0020) 253 #define SXGBE_MTL_RXQ_DMAMAP0_REG (SXGBE_MTL_BASE_REG + 0x0030) 254 #define SXGBE_MTL_RXQ_DMAMAP1_REG (SXGBE_MTL_BASE_REG + 0x0034) 255 #define SXGBE_MTL_RXQ_DMAMAP2_REG (SXGBE_MTL_BASE_REG + 0x0038) 256 #define SXGBE_MTL_TX_PRTYMAP0_REG (SXGBE_MTL_BASE_REG + 0x0040) 257 #define SXGBE_MTL_TX_PRTYMAP1_REG (SXGBE_MTL_BASE_REG + 0x0044) 258 259 /* TC/Queue registers, qnum=0-15 */ 260 #define SXGBE_MTL_TC_TXBASE_REG (SXGBE_MTL_BASE_REG + 0x0100) 261 #define SXGBE_MTL_TXQ_OPMODE_REG(qnum) \ 262 (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x00) 263 #define SXGBE_MTL_SFMODE BIT(1) 264 #define SXGBE_MTL_FIFO_LSHIFT 16 265 #define SXGBE_MTL_ENABLE_QUEUE 0x00000008 266 #define SXGBE_MTL_TXQ_UNDERFLOW_REG(qnum) \ 267 (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x04) 268 #define SXGBE_MTL_TXQ_DEBUG_REG(qnum) \ 269 (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x08) 270 #define SXGBE_MTL_TXQ_ETSCTL_REG(qnum) \ 271 (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x10) 272 #define SXGBE_MTL_TXQ_ETSSTATUS_REG(qnum) \ 273 (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x14) 274 #define SXGBE_MTL_TXQ_QUANTWEIGHT_REG(qnum) \ 275 (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x18) 276 277 #define SXGBE_MTL_TC_RXBASE_REG 0x1140 278 #define SXGBE_RX_MTL_SFMODE BIT(5) 279 #define SXGBE_MTL_RXQ_OPMODE_REG(qnum) \ 280 (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x00) 281 #define SXGBE_MTL_RXQ_MISPKTOVERFLOW_REG(qnum) \ 282 (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x04) 283 #define SXGBE_MTL_RXQ_DEBUG_REG(qnum) \ 284 (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x08) 285 #define SXGBE_MTL_RXQ_CTL_REG(qnum) \ 286 (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x0C) 287 #define SXGBE_MTL_RXQ_INTENABLE_REG(qnum) \ 288 (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x30) 289 #define SXGBE_MTL_RXQ_INTSTATUS_REG(qnum) \ 290 (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x34) 291 292 /* SXGBE DMA Registers */ 293 #define SXGBE_DMA_BASE_REG 0x3000 294 #define SXGBE_DMA_MODE_REG (SXGBE_DMA_BASE_REG + 0x0000) 295 #define SXGBE_DMA_SOFT_RESET BIT(0) 296 #define SXGBE_DMA_SYSBUS_MODE_REG (SXGBE_DMA_BASE_REG + 0x0004) 297 #define SXGBE_DMA_AXI_UNDEF_BURST BIT(0) 298 #define SXGBE_DMA_ENHACE_ADDR_MODE BIT(11) 299 #define SXGBE_DMA_INT_STATUS_REG (SXGBE_DMA_BASE_REG + 0x0008) 300 #define SXGBE_DMA_AXI_ARCACHECTL_REG (SXGBE_DMA_BASE_REG + 0x0010) 301 #define SXGBE_DMA_AXI_AWCACHECTL_REG (SXGBE_DMA_BASE_REG + 0x0018) 302 #define SXGBE_DMA_DEBUG_STATUS0_REG (SXGBE_DMA_BASE_REG + 0x0020) 303 #define SXGBE_DMA_DEBUG_STATUS1_REG (SXGBE_DMA_BASE_REG + 0x0024) 304 #define SXGBE_DMA_DEBUG_STATUS2_REG (SXGBE_DMA_BASE_REG + 0x0028) 305 #define SXGBE_DMA_DEBUG_STATUS3_REG (SXGBE_DMA_BASE_REG + 0x002C) 306 #define SXGBE_DMA_DEBUG_STATUS4_REG (SXGBE_DMA_BASE_REG + 0x0030) 307 #define SXGBE_DMA_DEBUG_STATUS5_REG (SXGBE_DMA_BASE_REG + 0x0034) 308 309 /* Channel Registers, cha_num = 0-15 */ 310 #define SXGBE_DMA_CHA_BASE_REG \ 311 (SXGBE_DMA_BASE_REG + 0x0100) 312 #define SXGBE_DMA_CHA_CTL_REG(cha_num) \ 313 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x00) 314 #define SXGBE_DMA_PBL_X8MODE BIT(16) 315 #define SXGBE_DMA_CHA_TXCTL_TSE_ENABLE BIT(12) 316 #define SXGBE_DMA_CHA_TXCTL_REG(cha_num) \ 317 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x04) 318 #define SXGBE_DMA_CHA_RXCTL_REG(cha_num) \ 319 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x08) 320 #define SXGBE_DMA_CHA_TXDESC_HADD_REG(cha_num) \ 321 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x10) 322 #define SXGBE_DMA_CHA_TXDESC_LADD_REG(cha_num) \ 323 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x14) 324 #define SXGBE_DMA_CHA_RXDESC_HADD_REG(cha_num) \ 325 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x18) 326 #define SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num) \ 327 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x1C) 328 #define SXGBE_DMA_CHA_TXDESC_TAILPTR_REG(cha_num) \ 329 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x24) 330 #define SXGBE_DMA_CHA_RXDESC_TAILPTR_REG(cha_num) \ 331 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x2C) 332 #define SXGBE_DMA_CHA_TXDESC_RINGLEN_REG(cha_num) \ 333 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x30) 334 #define SXGBE_DMA_CHA_RXDESC_RINGLEN_REG(cha_num) \ 335 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x34) 336 #define SXGBE_DMA_CHA_INT_ENABLE_REG(cha_num) \ 337 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x38) 338 #define SXGBE_DMA_CHA_INT_RXWATCHTMR_REG(cha_num) \ 339 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x3C) 340 #define SXGBE_DMA_CHA_TXDESC_CURADDLO_REG(cha_num) \ 341 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x44) 342 #define SXGBE_DMA_CHA_RXDESC_CURADDLO_REG(cha_num) \ 343 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x4C) 344 #define SXGBE_DMA_CHA_CURTXBUF_ADDHI_REG(cha_num) \ 345 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x50) 346 #define SXGBE_DMA_CHA_CURTXBUF_ADDLO_REG(cha_num) \ 347 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x54) 348 #define SXGBE_DMA_CHA_CURRXBUF_ADDHI_REG(cha_num) \ 349 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x58) 350 #define SXGBE_DMA_CHA_CURRXBUF_ADDLO_REG(cha_num) \ 351 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x5C) 352 #define SXGBE_DMA_CHA_STATUS_REG(cha_num) \ 353 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x60) 354 355 /* TX DMA control register specific */ 356 #define SXGBE_TX_START_DMA BIT(0) 357 358 /* sxgbe tx configuration register bitfields */ 359 #define SXGBE_SPEED_10G 0x0 360 #define SXGBE_SPEED_2_5G 0x1 361 #define SXGBE_SPEED_1G 0x2 362 #define SXGBE_SPEED_LSHIFT 29 363 364 #define SXGBE_TX_ENABLE BIT(0) 365 #define SXGBE_TX_DISDIC_ALGO BIT(1) 366 #define SXGBE_TX_JABBER_DISABLE BIT(16) 367 368 /* sxgbe rx configuration register bitfields */ 369 #define SXGBE_RX_ENABLE BIT(0) 370 #define SXGBE_RX_ACS_ENABLE BIT(1) 371 #define SXGBE_RX_WATCHDOG_DISABLE BIT(7) 372 #define SXGBE_RX_JUMBPKT_ENABLE BIT(8) 373 #define SXGBE_RX_CSUMOFFLOAD_ENABLE BIT(9) 374 #define SXGBE_RX_LOOPBACK_ENABLE BIT(10) 375 #define SXGBE_RX_ARPOFFLOAD_ENABLE BIT(31) 376 377 /* sxgbe vlan Tag Register bitfields */ 378 #define SXGBE_VLAN_SVLAN_ENABLE BIT(18) 379 #define SXGBE_VLAN_DOUBLEVLAN_ENABLE BIT(26) 380 #define SXGBE_VLAN_INNERVLAN_ENABLE BIT(27) 381 382 /* XMAC VLAN Tag Inclusion Register(0x0060) bitfields 383 * Below fields same for Inner VLAN Tag Inclusion 384 * Register(0x0064) register 385 */ 386 enum vlan_tag_ctl_tx { 387 VLAN_TAG_TX_NOP, 388 VLAN_TAG_TX_DEL, 389 VLAN_TAG_TX_INSERT, 390 VLAN_TAG_TX_REPLACE 391 }; 392 #define SXGBE_VLAN_PRTY_CTL BIT(18) 393 #define SXGBE_VLAN_CSVL_CTL BIT(19) 394 395 /* SXGBE TX Q Flow Control Register bitfields */ 396 #define SXGBE_TX_FLOW_CTL_FCB BIT(0) 397 #define SXGBE_TX_FLOW_CTL_TFB BIT(1) 398 399 /* SXGBE RX Q Flow Control Register bitfields */ 400 #define SXGBE_RX_FLOW_CTL_ENABLE BIT(0) 401 #define SXGBE_RX_UNICAST_DETECT BIT(1) 402 #define SXGBE_RX_PRTYFLOW_CTL_ENABLE BIT(8) 403 404 /* sxgbe rx Q control0 register bitfields */ 405 #define SXGBE_RX_Q_ENABLE 0x2 406 407 /* SXGBE hardware features bitfield specific */ 408 /* Capability Register 0 */ 409 #define SXGBE_HW_FEAT_GMII(cap) ((cap & 0x00000002) >> 1) 410 #define SXGBE_HW_FEAT_VLAN_HASH_FILTER(cap) ((cap & 0x00000010) >> 4) 411 #define SXGBE_HW_FEAT_SMA(cap) ((cap & 0x00000020) >> 5) 412 #define SXGBE_HW_FEAT_PMT_TEMOTE_WOP(cap) ((cap & 0x00000040) >> 6) 413 #define SXGBE_HW_FEAT_PMT_MAGIC_PKT(cap) ((cap & 0x00000080) >> 7) 414 #define SXGBE_HW_FEAT_RMON(cap) ((cap & 0x00000100) >> 8) 415 #define SXGBE_HW_FEAT_ARP_OFFLOAD(cap) ((cap & 0x00000200) >> 9) 416 #define SXGBE_HW_FEAT_IEEE1500_2008(cap) ((cap & 0x00001000) >> 12) 417 #define SXGBE_HW_FEAT_EEE(cap) ((cap & 0x00002000) >> 13) 418 #define SXGBE_HW_FEAT_TX_CSUM_OFFLOAD(cap) ((cap & 0x00004000) >> 14) 419 #define SXGBE_HW_FEAT_RX_CSUM_OFFLOAD(cap) ((cap & 0x00010000) >> 16) 420 #define SXGBE_HW_FEAT_MACADDR_COUNT(cap) ((cap & 0x007C0000) >> 18) 421 #define SXGBE_HW_FEAT_TSTMAP_SRC(cap) ((cap & 0x06000000) >> 25) 422 #define SXGBE_HW_FEAT_SRCADDR_VLAN(cap) ((cap & 0x08000000) >> 27) 423 424 /* Capability Register 1 */ 425 #define SXGBE_HW_FEAT_RX_FIFO_SIZE(cap) ((cap & 0x0000001F)) 426 #define SXGBE_HW_FEAT_TX_FIFO_SIZE(cap) ((cap & 0x000007C0) >> 6) 427 #define SXGBE_HW_FEAT_IEEE1588_HWORD(cap) ((cap & 0x00002000) >> 13) 428 #define SXGBE_HW_FEAT_DCB(cap) ((cap & 0x00010000) >> 16) 429 #define SXGBE_HW_FEAT_SPLIT_HDR(cap) ((cap & 0x00020000) >> 17) 430 #define SXGBE_HW_FEAT_TSO(cap) ((cap & 0x00040000) >> 18) 431 #define SXGBE_HW_FEAT_DEBUG_MEM_IFACE(cap) ((cap & 0x00080000) >> 19) 432 #define SXGBE_HW_FEAT_RSS(cap) ((cap & 0x00100000) >> 20) 433 #define SXGBE_HW_FEAT_HASH_TABLE_SIZE(cap) ((cap & 0x03000000) >> 24) 434 #define SXGBE_HW_FEAT_L3L4_FILTER_NUM(cap) ((cap & 0x78000000) >> 27) 435 436 /* Capability Register 2 */ 437 #define SXGBE_HW_FEAT_RX_MTL_QUEUES(cap) ((cap & 0x0000000F)) 438 #define SXGBE_HW_FEAT_TX_MTL_QUEUES(cap) ((cap & 0x000003C0) >> 6) 439 #define SXGBE_HW_FEAT_RX_DMA_CHANNELS(cap) ((cap & 0x0000F000) >> 12) 440 #define SXGBE_HW_FEAT_TX_DMA_CHANNELS(cap) ((cap & 0x003C0000) >> 18) 441 #define SXGBE_HW_FEAT_PPS_OUTPUTS(cap) ((cap & 0x07000000) >> 24) 442 #define SXGBE_HW_FEAT_AUX_SNAPSHOTS(cap) ((cap & 0x70000000) >> 28) 443 444 /* DMAchannel interrupt enable specific */ 445 /* DMA Normal interrupt */ 446 #define SXGBE_DMA_INT_ENA_NIE BIT(16) /* Normal Summary */ 447 #define SXGBE_DMA_INT_ENA_TIE BIT(0) /* Transmit Interrupt */ 448 #define SXGBE_DMA_INT_ENA_TUE BIT(2) /* Transmit Buffer Unavailable */ 449 #define SXGBE_DMA_INT_ENA_RIE BIT(6) /* Receive Interrupt */ 450 451 #define SXGBE_DMA_INT_NORMAL \ 452 (SXGBE_DMA_INT_ENA_NIE | SXGBE_DMA_INT_ENA_RIE | \ 453 SXGBE_DMA_INT_ENA_TIE | SXGBE_DMA_INT_ENA_TUE) 454 455 /* DMA Abnormal interrupt */ 456 #define SXGBE_DMA_INT_ENA_AIE BIT(15) /* Abnormal Summary */ 457 #define SXGBE_DMA_INT_ENA_TSE BIT(1) /* Transmit Stopped */ 458 #define SXGBE_DMA_INT_ENA_RUE BIT(7) /* Receive Buffer Unavailable */ 459 #define SXGBE_DMA_INT_ENA_RSE BIT(8) /* Receive Stopped */ 460 #define SXGBE_DMA_INT_ENA_FBE BIT(12) /* Fatal Bus Error */ 461 #define SXGBE_DMA_INT_ENA_CDEE BIT(13) /* Context Descriptor Error */ 462 463 #define SXGBE_DMA_INT_ABNORMAL \ 464 (SXGBE_DMA_INT_ENA_AIE | SXGBE_DMA_INT_ENA_TSE | \ 465 SXGBE_DMA_INT_ENA_RUE | SXGBE_DMA_INT_ENA_RSE | \ 466 SXGBE_DMA_INT_ENA_FBE | SXGBE_DMA_INT_ENA_CDEE) 467 468 #define SXGBE_DMA_ENA_INT (SXGBE_DMA_INT_NORMAL | SXGBE_DMA_INT_ABNORMAL) 469 470 /* DMA channel interrupt status specific */ 471 #define SXGBE_DMA_INT_STATUS_REB2 BIT(21) 472 #define SXGBE_DMA_INT_STATUS_REB1 BIT(20) 473 #define SXGBE_DMA_INT_STATUS_REB0 BIT(19) 474 #define SXGBE_DMA_INT_STATUS_TEB2 BIT(18) 475 #define SXGBE_DMA_INT_STATUS_TEB1 BIT(17) 476 #define SXGBE_DMA_INT_STATUS_TEB0 BIT(16) 477 #define SXGBE_DMA_INT_STATUS_NIS BIT(15) 478 #define SXGBE_DMA_INT_STATUS_AIS BIT(14) 479 #define SXGBE_DMA_INT_STATUS_CTXTERR BIT(13) 480 #define SXGBE_DMA_INT_STATUS_FBE BIT(12) 481 #define SXGBE_DMA_INT_STATUS_RPS BIT(8) 482 #define SXGBE_DMA_INT_STATUS_RBU BIT(7) 483 #define SXGBE_DMA_INT_STATUS_RI BIT(6) 484 #define SXGBE_DMA_INT_STATUS_TBU BIT(2) 485 #define SXGBE_DMA_INT_STATUS_TPS BIT(1) 486 #define SXGBE_DMA_INT_STATUS_TI BIT(0) 487 488 #endif /* __SXGBE_REGMAP_H__ */ 489