1 /* SuperH Ethernet device driver 2 * 3 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 4 * Copyright (C) 2008-2012 Renesas Solutions Corp. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * The full GNU General Public License is included in this distribution in 16 * the file called "COPYING". 17 */ 18 19 #ifndef __SH_ETH_H__ 20 #define __SH_ETH_H__ 21 22 #define CARDNAME "sh-eth" 23 #define TX_TIMEOUT (5*HZ) 24 #define TX_RING_SIZE 64 /* Tx ring size */ 25 #define RX_RING_SIZE 64 /* Rx ring size */ 26 #define TX_RING_MIN 64 27 #define RX_RING_MIN 64 28 #define TX_RING_MAX 1024 29 #define RX_RING_MAX 1024 30 #define PKT_BUF_SZ 1538 31 #define SH_ETH_TSU_TIMEOUT_MS 500 32 #define SH_ETH_TSU_CAM_ENTRIES 32 33 34 enum { 35 /* IMPORTANT: To keep ethtool register dump working, add new 36 * register names immediately before SH_ETH_MAX_REGISTER_OFFSET. 37 */ 38 39 /* E-DMAC registers */ 40 EDSR = 0, 41 EDMR, 42 EDTRR, 43 EDRRR, 44 EESR, 45 EESIPR, 46 TDLAR, 47 TDFAR, 48 TDFXR, 49 TDFFR, 50 RDLAR, 51 RDFAR, 52 RDFXR, 53 RDFFR, 54 TRSCER, 55 RMFCR, 56 TFTR, 57 FDR, 58 RMCR, 59 EDOCR, 60 TFUCR, 61 RFOCR, 62 RMIIMODE, 63 FCFTR, 64 RPADIR, 65 TRIMD, 66 RBWAR, 67 TBRAR, 68 69 /* Ether registers */ 70 ECMR, 71 ECSR, 72 ECSIPR, 73 PIR, 74 PSR, 75 RDMLR, 76 PIPR, 77 RFLR, 78 IPGR, 79 APR, 80 MPR, 81 PFTCR, 82 PFRCR, 83 RFCR, 84 RFCF, 85 TPAUSER, 86 TPAUSECR, 87 BCFR, 88 BCFRR, 89 GECMR, 90 BCULR, 91 MAHR, 92 MALR, 93 TROCR, 94 CDCR, 95 LCCR, 96 CNDCR, 97 CEFCR, 98 FRECR, 99 TSFRCR, 100 TLFRCR, 101 CERCR, 102 CEECR, 103 MAFCR, 104 RTRATE, 105 CSMR, 106 RMII_MII, 107 108 /* TSU Absolute address */ 109 ARSTR, 110 TSU_CTRST, 111 TSU_FWEN0, 112 TSU_FWEN1, 113 TSU_FCM, 114 TSU_BSYSL0, 115 TSU_BSYSL1, 116 TSU_PRISL0, 117 TSU_PRISL1, 118 TSU_FWSL0, 119 TSU_FWSL1, 120 TSU_FWSLC, 121 TSU_QTAG0, /* Same as TSU_QTAGM0 */ 122 TSU_QTAG1, /* Same as TSU_QTAGM1 */ 123 TSU_QTAGM0, 124 TSU_QTAGM1, 125 TSU_FWSR, 126 TSU_FWINMK, 127 TSU_ADQT0, 128 TSU_ADQT1, 129 TSU_VTAG0, 130 TSU_VTAG1, 131 TSU_ADSBSY, 132 TSU_TEN, 133 TSU_POST1, 134 TSU_POST2, 135 TSU_POST3, 136 TSU_POST4, 137 TSU_ADRH0, 138 /* TSU_ADR{H,L}{0..31} are assumed to be contiguous */ 139 140 TXNLCR0, 141 TXALCR0, 142 RXNLCR0, 143 RXALCR0, 144 FWNLCR0, 145 FWALCR0, 146 TXNLCR1, 147 TXALCR1, 148 RXNLCR1, 149 RXALCR1, 150 FWNLCR1, 151 FWALCR1, 152 153 /* This value must be written at last. */ 154 SH_ETH_MAX_REGISTER_OFFSET, 155 }; 156 157 enum { 158 SH_ETH_REG_GIGABIT, 159 SH_ETH_REG_FAST_RZ, 160 SH_ETH_REG_FAST_RCAR, 161 SH_ETH_REG_FAST_SH4, 162 SH_ETH_REG_FAST_SH3_SH2 163 }; 164 165 /* Driver's parameters */ 166 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RENESAS) 167 #define SH_ETH_RX_ALIGN 32 168 #else 169 #define SH_ETH_RX_ALIGN 2 170 #endif 171 172 /* Register's bits 173 */ 174 /* EDSR : sh7734, sh7757, sh7763, r8a7740, and r7s72100 only */ 175 enum EDSR_BIT { 176 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 177 }; 178 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 179 180 /* GECMR : sh7734, sh7763 and r8a7740 only */ 181 enum GECMR_BIT { 182 GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01, 183 }; 184 185 /* EDMR */ 186 enum DMAC_M_BIT { 187 EDMR_NBST = 0x80, 188 EDMR_EL = 0x40, /* Litte endian */ 189 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 190 EDMR_SRST_GETHER = 0x03, 191 EDMR_SRST_ETHER = 0x01, 192 }; 193 194 /* EDTRR */ 195 enum DMAC_T_BIT { 196 EDTRR_TRNS_GETHER = 0x03, 197 EDTRR_TRNS_ETHER = 0x01, 198 }; 199 200 /* EDRRR */ 201 enum EDRRR_R_BIT { 202 EDRRR_R = 0x01, 203 }; 204 205 /* TPAUSER */ 206 enum TPAUSER_BIT { 207 TPAUSER_TPAUSE = 0x0000ffff, 208 TPAUSER_UNLIMITED = 0, 209 }; 210 211 /* BCFR */ 212 enum BCFR_BIT { 213 BCFR_RPAUSE = 0x0000ffff, 214 BCFR_UNLIMITED = 0, 215 }; 216 217 /* PIR */ 218 enum PIR_BIT { 219 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 220 }; 221 222 /* PSR */ 223 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 224 225 /* EESR */ 226 enum EESR_BIT { 227 EESR_TWB1 = 0x80000000, 228 EESR_TWB = 0x40000000, /* same as TWB0 */ 229 EESR_TC1 = 0x20000000, 230 EESR_TUC = 0x10000000, 231 EESR_ROC = 0x08000000, 232 EESR_TABT = 0x04000000, 233 EESR_RABT = 0x02000000, 234 EESR_RFRMER = 0x01000000, /* same as RFCOF */ 235 EESR_ADE = 0x00800000, 236 EESR_ECI = 0x00400000, 237 EESR_FTC = 0x00200000, /* same as TC or TC0 */ 238 EESR_TDE = 0x00100000, 239 EESR_TFE = 0x00080000, /* same as TFUF */ 240 EESR_FRC = 0x00040000, /* same as FR */ 241 EESR_RDE = 0x00020000, 242 EESR_RFE = 0x00010000, 243 EESR_CND = 0x00000800, 244 EESR_DLC = 0x00000400, 245 EESR_CD = 0x00000200, 246 EESR_TRO = 0x00000100, 247 EESR_RMAF = 0x00000080, 248 EESR_CEEF = 0x00000040, 249 EESR_CELF = 0x00000020, 250 EESR_RRF = 0x00000010, 251 EESR_RTLF = 0x00000008, 252 EESR_RTSF = 0x00000004, 253 EESR_PRE = 0x00000002, 254 EESR_CERF = 0x00000001, 255 }; 256 257 #define EESR_RX_CHECK (EESR_FRC | /* Frame recv */ \ 258 EESR_RMAF | /* Multicast address recv */ \ 259 EESR_RRF | /* Bit frame recv */ \ 260 EESR_RTLF | /* Long frame recv */ \ 261 EESR_RTSF | /* Short frame recv */ \ 262 EESR_PRE | /* PHY-LSI recv error */ \ 263 EESR_CERF) /* Recv frame CRC error */ 264 265 #define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \ 266 EESR_TRO) 267 #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \ 268 EESR_RDE | EESR_RFRMER | EESR_ADE | \ 269 EESR_TFE | EESR_TDE) 270 271 /* EESIPR */ 272 enum EESIPR_BIT { 273 EESIPR_TWB1IP = 0x80000000, 274 EESIPR_TWBIP = 0x40000000, /* same as TWB0IP */ 275 EESIPR_TC1IP = 0x20000000, 276 EESIPR_TUCIP = 0x10000000, 277 EESIPR_ROCIP = 0x08000000, 278 EESIPR_TABTIP = 0x04000000, 279 EESIPR_RABTIP = 0x02000000, 280 EESIPR_RFCOFIP = 0x01000000, 281 EESIPR_ADEIP = 0x00800000, 282 EESIPR_ECIIP = 0x00400000, 283 EESIPR_FTCIP = 0x00200000, /* same as TC0IP */ 284 EESIPR_TDEIP = 0x00100000, 285 EESIPR_TFUFIP = 0x00080000, 286 EESIPR_FRIP = 0x00040000, 287 EESIPR_RDEIP = 0x00020000, 288 EESIPR_RFOFIP = 0x00010000, 289 EESIPR_CNDIP = 0x00000800, 290 EESIPR_DLCIP = 0x00000400, 291 EESIPR_CDIP = 0x00000200, 292 EESIPR_TROIP = 0x00000100, 293 EESIPR_RMAFIP = 0x00000080, 294 EESIPR_CEEFIP = 0x00000040, 295 EESIPR_CELFIP = 0x00000020, 296 EESIPR_RRFIP = 0x00000010, 297 EESIPR_RTLFIP = 0x00000008, 298 EESIPR_RTSFIP = 0x00000004, 299 EESIPR_PREIP = 0x00000002, 300 EESIPR_CERFIP = 0x00000001, 301 }; 302 303 /* Receive descriptor 0 bits */ 304 enum RD_STS_BIT { 305 RD_RACT = 0x80000000, RD_RDLE = 0x40000000, 306 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 307 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 308 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 309 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 310 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 311 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 312 RD_RFS1 = 0x00000001, 313 }; 314 #define RDF1ST RD_RFP1 315 #define RDFEND RD_RFP0 316 #define RD_RFP (RD_RFP1|RD_RFP0) 317 318 /* Receive descriptor 1 bits */ 319 enum RD_LEN_BIT { 320 RD_RFL = 0x0000ffff, /* receive frame length */ 321 RD_RBL = 0xffff0000, /* receive buffer length */ 322 }; 323 324 /* FCFTR */ 325 enum FCFTR_BIT { 326 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 327 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 328 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 329 }; 330 #define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0) 331 #define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0) 332 333 /* Transmit descriptor 0 bits */ 334 enum TD_STS_BIT { 335 TD_TACT = 0x80000000, TD_TDLE = 0x40000000, 336 TD_TFP1 = 0x20000000, TD_TFP0 = 0x10000000, 337 TD_TFE = 0x08000000, TD_TWBI = 0x04000000, 338 }; 339 #define TDF1ST TD_TFP1 340 #define TDFEND TD_TFP0 341 #define TD_TFP (TD_TFP1|TD_TFP0) 342 343 /* Transmit descriptor 1 bits */ 344 enum TD_LEN_BIT { 345 TD_TBL = 0xffff0000, /* transmit buffer length */ 346 }; 347 348 /* RMCR */ 349 enum RMCR_BIT { 350 RMCR_RNC = 0x00000001, 351 }; 352 353 /* ECMR */ 354 enum FELIC_MODE_BIT { 355 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000, 356 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000, 357 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 358 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 359 ECMR_MPDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 360 ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, 361 ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001, 362 }; 363 364 /* ECSR */ 365 enum ECSR_STATUS_BIT { 366 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 367 ECSR_LCHNG = 0x04, 368 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 369 }; 370 371 #define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \ 372 ECSR_ICD | ECSIPR_MPDIP) 373 374 /* ECSIPR */ 375 enum ECSIPR_STATUS_MASK_BIT { 376 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, 377 ECSIPR_LCHNGIP = 0x04, 378 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01, 379 }; 380 381 #define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \ 382 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 383 384 /* APR */ 385 enum APR_BIT { 386 APR_AP = 0x00000001, 387 }; 388 389 /* MPR */ 390 enum MPR_BIT { 391 MPR_MP = 0x00000001, 392 }; 393 394 /* TRSCER */ 395 enum DESC_I_BIT { 396 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 397 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 398 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 399 DESC_I_RINT1 = 0x0001, 400 }; 401 402 #define DEFAULT_TRSCER_ERR_MASK (DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2) 403 404 /* RPADIR */ 405 enum RPADIR_BIT { 406 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 407 RPADIR_PADR = 0x0003f, 408 }; 409 410 /* FDR */ 411 #define DEFAULT_FDR_INIT 0x00000707 412 413 /* ARSTR */ 414 enum ARSTR_BIT { ARSTR_ARST = 0x00000001, }; 415 416 /* TSU_FWEN0 */ 417 enum TSU_FWEN0_BIT { 418 TSU_FWEN0_0 = 0x00000001, 419 }; 420 421 /* TSU_ADSBSY */ 422 enum TSU_ADSBSY_BIT { 423 TSU_ADSBSY_0 = 0x00000001, 424 }; 425 426 /* TSU_TEN */ 427 enum TSU_TEN_BIT { 428 TSU_TEN_0 = 0x80000000, 429 }; 430 431 /* TSU_FWSL0 */ 432 enum TSU_FWSL0_BIT { 433 TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800, 434 TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200, 435 TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010, 436 }; 437 438 /* TSU_FWSLC */ 439 enum TSU_FWSLC_BIT { 440 TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000, 441 TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040, 442 TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010, 443 TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004, 444 TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001, 445 }; 446 447 /* TSU_VTAGn */ 448 #define TSU_VTAG_ENABLE 0x80000000 449 #define TSU_VTAG_VID_MASK 0x00000fff 450 451 /* The sh ether Tx buffer descriptors. 452 * This structure should be 20 bytes. 453 */ 454 struct sh_eth_txdesc { 455 u32 status; /* TD0 */ 456 u32 len; /* TD1 */ 457 u32 addr; /* TD2 */ 458 u32 pad0; /* padding data */ 459 } __aligned(2) __packed; 460 461 /* The sh ether Rx buffer descriptors. 462 * This structure should be 20 bytes. 463 */ 464 struct sh_eth_rxdesc { 465 u32 status; /* RD0 */ 466 u32 len; /* RD1 */ 467 u32 addr; /* RD2 */ 468 u32 pad0; /* padding data */ 469 } __aligned(2) __packed; 470 471 /* This structure is used by each CPU dependency handling. */ 472 struct sh_eth_cpu_data { 473 /* mandatory functions */ 474 int (*soft_reset)(struct net_device *ndev); 475 476 /* optional functions */ 477 void (*chip_reset)(struct net_device *ndev); 478 void (*set_duplex)(struct net_device *ndev); 479 void (*set_rate)(struct net_device *ndev); 480 481 /* mandatory initialize value */ 482 int register_type; 483 u32 edtrr_trns; 484 u32 eesipr_value; 485 486 /* optional initialize value */ 487 u32 ecsr_value; 488 u32 ecsipr_value; 489 u32 fdr_value; 490 u32 fcftr_value; 491 u32 rpadir_value; 492 493 /* interrupt checking mask */ 494 u32 tx_check; 495 u32 eesr_err_check; 496 497 /* Error mask */ 498 u32 trscer_err_mask; 499 500 /* hardware features */ 501 unsigned long irq_flags; /* IRQ configuration flags */ 502 unsigned no_psr:1; /* EtherC DOES NOT have PSR */ 503 unsigned apr:1; /* EtherC has APR */ 504 unsigned mpr:1; /* EtherC has MPR */ 505 unsigned tpauser:1; /* EtherC has TPAUSER */ 506 unsigned bculr:1; /* EtherC has BCULR */ 507 unsigned tsu:1; /* EtherC has TSU */ 508 unsigned hw_swap:1; /* E-DMAC has DE bit in EDMR */ 509 unsigned nbst:1; /* E-DMAC has NBST bit in EDMR */ 510 unsigned rpadir:1; /* E-DMAC has RPADIR */ 511 unsigned no_trimd:1; /* E-DMAC DOES NOT have TRIMD */ 512 unsigned no_ade:1; /* E-DMAC DOES NOT have ADE bit in EESR */ 513 unsigned no_xdfar:1; /* E-DMAC DOES NOT have RDFAR/TDFAR */ 514 unsigned xdfar_rw:1; /* E-DMAC has writeable RDFAR/TDFAR */ 515 unsigned hw_checksum:1; /* E-DMAC has CSMR */ 516 unsigned select_mii:1; /* EtherC has RMII_MII (MII select register) */ 517 unsigned rmiimode:1; /* EtherC has RMIIMODE register */ 518 unsigned rtrate:1; /* EtherC has RTRATE register */ 519 unsigned magic:1; /* EtherC has ECMR.MPDE and ECSR.MPD */ 520 unsigned no_tx_cntrs:1; /* EtherC DOES NOT have TX error counters */ 521 unsigned cexcr:1; /* EtherC has CERCR/CEECR */ 522 unsigned dual_port:1; /* Dual EtherC/E-DMAC */ 523 }; 524 525 struct sh_eth_private { 526 struct platform_device *pdev; 527 struct sh_eth_cpu_data *cd; 528 const u16 *reg_offset; 529 void __iomem *addr; 530 void __iomem *tsu_addr; 531 struct clk *clk; 532 u32 num_rx_ring; 533 u32 num_tx_ring; 534 dma_addr_t rx_desc_dma; 535 dma_addr_t tx_desc_dma; 536 struct sh_eth_rxdesc *rx_ring; 537 struct sh_eth_txdesc *tx_ring; 538 struct sk_buff **rx_skbuff; 539 struct sk_buff **tx_skbuff; 540 spinlock_t lock; /* Register access lock */ 541 u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */ 542 u32 cur_tx, dirty_tx; 543 u32 rx_buf_sz; /* Based on MTU+slack. */ 544 struct napi_struct napi; 545 bool irq_enabled; 546 /* MII transceiver section. */ 547 u32 phy_id; /* PHY ID */ 548 struct mii_bus *mii_bus; /* MDIO bus control */ 549 int link; 550 phy_interface_t phy_interface; 551 int msg_enable; 552 int speed; 553 int duplex; 554 int port; /* for TSU */ 555 int vlan_num_ids; /* for VLAN tag filter */ 556 557 unsigned no_ether_link:1; 558 unsigned ether_link_active_low:1; 559 unsigned is_opened:1; 560 unsigned wol_enabled:1; 561 }; 562 563 static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp, 564 int enum_index) 565 { 566 return mdp->tsu_addr + mdp->reg_offset[enum_index]; 567 } 568 569 #endif /* #ifndef __SH_ETH_H__ */ 570