1 // SPDX-License-Identifier: GPL-2.0 2 /* SuperH Ethernet device driver 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 6 * Copyright (C) 2008-2014 Renesas Solutions Corp. 7 * Copyright (C) 2013-2017 Cogent Embedded, Inc. 8 * Copyright (C) 2014 Codethink Limited 9 */ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/spinlock.h> 14 #include <linux/interrupt.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/etherdevice.h> 17 #include <linux/delay.h> 18 #include <linux/platform_device.h> 19 #include <linux/mdio-bitbang.h> 20 #include <linux/netdevice.h> 21 #include <linux/of.h> 22 #include <linux/of_net.h> 23 #include <linux/phy.h> 24 #include <linux/cache.h> 25 #include <linux/io.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/slab.h> 28 #include <linux/ethtool.h> 29 #include <linux/if_vlan.h> 30 #include <linux/sh_eth.h> 31 #include <linux/of_mdio.h> 32 33 #include "sh_eth.h" 34 35 #define SH_ETH_DEF_MSG_ENABLE \ 36 (NETIF_MSG_LINK | \ 37 NETIF_MSG_TIMER | \ 38 NETIF_MSG_RX_ERR| \ 39 NETIF_MSG_TX_ERR) 40 41 #define SH_ETH_OFFSET_INVALID ((u16)~0) 42 43 #define SH_ETH_OFFSET_DEFAULTS \ 44 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID 45 46 /* use some intentionally tricky logic here to initialize the whole struct to 47 * 0xffff, but then override certain fields, requiring us to indicate that we 48 * "know" that there are overrides in this structure, and we'll need to disable 49 * that warning from W=1 builds. GCC has supported this option since 4.2.X, but 50 * the macros available to do this only define GCC 8. 51 */ 52 __diag_push(); 53 __diag_ignore_all("-Woverride-init", 54 "logic to initialize all and then override some is OK"); 55 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 56 SH_ETH_OFFSET_DEFAULTS, 57 58 [EDSR] = 0x0000, 59 [EDMR] = 0x0400, 60 [EDTRR] = 0x0408, 61 [EDRRR] = 0x0410, 62 [EESR] = 0x0428, 63 [EESIPR] = 0x0430, 64 [TDLAR] = 0x0010, 65 [TDFAR] = 0x0014, 66 [TDFXR] = 0x0018, 67 [TDFFR] = 0x001c, 68 [RDLAR] = 0x0030, 69 [RDFAR] = 0x0034, 70 [RDFXR] = 0x0038, 71 [RDFFR] = 0x003c, 72 [TRSCER] = 0x0438, 73 [RMFCR] = 0x0440, 74 [TFTR] = 0x0448, 75 [FDR] = 0x0450, 76 [RMCR] = 0x0458, 77 [RPADIR] = 0x0460, 78 [FCFTR] = 0x0468, 79 [CSMR] = 0x04E4, 80 81 [ECMR] = 0x0500, 82 [ECSR] = 0x0510, 83 [ECSIPR] = 0x0518, 84 [PIR] = 0x0520, 85 [PSR] = 0x0528, 86 [PIPR] = 0x052c, 87 [RFLR] = 0x0508, 88 [APR] = 0x0554, 89 [MPR] = 0x0558, 90 [PFTCR] = 0x055c, 91 [PFRCR] = 0x0560, 92 [TPAUSER] = 0x0564, 93 [GECMR] = 0x05b0, 94 [BCULR] = 0x05b4, 95 [MAHR] = 0x05c0, 96 [MALR] = 0x05c8, 97 [TROCR] = 0x0700, 98 [CDCR] = 0x0708, 99 [LCCR] = 0x0710, 100 [CEFCR] = 0x0740, 101 [FRECR] = 0x0748, 102 [TSFRCR] = 0x0750, 103 [TLFRCR] = 0x0758, 104 [RFCR] = 0x0760, 105 [CERCR] = 0x0768, 106 [CEECR] = 0x0770, 107 [MAFCR] = 0x0778, 108 [RMII_MII] = 0x0790, 109 110 [ARSTR] = 0x0000, 111 [TSU_CTRST] = 0x0004, 112 [TSU_FWEN0] = 0x0010, 113 [TSU_FWEN1] = 0x0014, 114 [TSU_FCM] = 0x0018, 115 [TSU_BSYSL0] = 0x0020, 116 [TSU_BSYSL1] = 0x0024, 117 [TSU_PRISL0] = 0x0028, 118 [TSU_PRISL1] = 0x002c, 119 [TSU_FWSL0] = 0x0030, 120 [TSU_FWSL1] = 0x0034, 121 [TSU_FWSLC] = 0x0038, 122 [TSU_QTAGM0] = 0x0040, 123 [TSU_QTAGM1] = 0x0044, 124 [TSU_FWSR] = 0x0050, 125 [TSU_FWINMK] = 0x0054, 126 [TSU_ADQT0] = 0x0048, 127 [TSU_ADQT1] = 0x004c, 128 [TSU_VTAG0] = 0x0058, 129 [TSU_VTAG1] = 0x005c, 130 [TSU_ADSBSY] = 0x0060, 131 [TSU_TEN] = 0x0064, 132 [TSU_POST1] = 0x0070, 133 [TSU_POST2] = 0x0074, 134 [TSU_POST3] = 0x0078, 135 [TSU_POST4] = 0x007c, 136 [TSU_ADRH0] = 0x0100, 137 138 [TXNLCR0] = 0x0080, 139 [TXALCR0] = 0x0084, 140 [RXNLCR0] = 0x0088, 141 [RXALCR0] = 0x008c, 142 [FWNLCR0] = 0x0090, 143 [FWALCR0] = 0x0094, 144 [TXNLCR1] = 0x00a0, 145 [TXALCR1] = 0x00a4, 146 [RXNLCR1] = 0x00a8, 147 [RXALCR1] = 0x00ac, 148 [FWNLCR1] = 0x00b0, 149 [FWALCR1] = 0x00b4, 150 }; 151 152 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 153 SH_ETH_OFFSET_DEFAULTS, 154 155 [ECMR] = 0x0300, 156 [RFLR] = 0x0308, 157 [ECSR] = 0x0310, 158 [ECSIPR] = 0x0318, 159 [PIR] = 0x0320, 160 [PSR] = 0x0328, 161 [RDMLR] = 0x0340, 162 [IPGR] = 0x0350, 163 [APR] = 0x0354, 164 [MPR] = 0x0358, 165 [RFCF] = 0x0360, 166 [TPAUSER] = 0x0364, 167 [TPAUSECR] = 0x0368, 168 [MAHR] = 0x03c0, 169 [MALR] = 0x03c8, 170 [TROCR] = 0x03d0, 171 [CDCR] = 0x03d4, 172 [LCCR] = 0x03d8, 173 [CNDCR] = 0x03dc, 174 [CEFCR] = 0x03e4, 175 [FRECR] = 0x03e8, 176 [TSFRCR] = 0x03ec, 177 [TLFRCR] = 0x03f0, 178 [RFCR] = 0x03f4, 179 [MAFCR] = 0x03f8, 180 181 [EDMR] = 0x0200, 182 [EDTRR] = 0x0208, 183 [EDRRR] = 0x0210, 184 [TDLAR] = 0x0218, 185 [RDLAR] = 0x0220, 186 [EESR] = 0x0228, 187 [EESIPR] = 0x0230, 188 [TRSCER] = 0x0238, 189 [RMFCR] = 0x0240, 190 [TFTR] = 0x0248, 191 [FDR] = 0x0250, 192 [RMCR] = 0x0258, 193 [TFUCR] = 0x0264, 194 [RFOCR] = 0x0268, 195 [RMIIMODE] = 0x026c, 196 [FCFTR] = 0x0270, 197 [TRIMD] = 0x027c, 198 }; 199 200 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 201 SH_ETH_OFFSET_DEFAULTS, 202 203 [ECMR] = 0x0100, 204 [RFLR] = 0x0108, 205 [ECSR] = 0x0110, 206 [ECSIPR] = 0x0118, 207 [PIR] = 0x0120, 208 [PSR] = 0x0128, 209 [RDMLR] = 0x0140, 210 [IPGR] = 0x0150, 211 [APR] = 0x0154, 212 [MPR] = 0x0158, 213 [TPAUSER] = 0x0164, 214 [RFCF] = 0x0160, 215 [TPAUSECR] = 0x0168, 216 [BCFRR] = 0x016c, 217 [MAHR] = 0x01c0, 218 [MALR] = 0x01c8, 219 [TROCR] = 0x01d0, 220 [CDCR] = 0x01d4, 221 [LCCR] = 0x01d8, 222 [CNDCR] = 0x01dc, 223 [CEFCR] = 0x01e4, 224 [FRECR] = 0x01e8, 225 [TSFRCR] = 0x01ec, 226 [TLFRCR] = 0x01f0, 227 [RFCR] = 0x01f4, 228 [MAFCR] = 0x01f8, 229 [RTRATE] = 0x01fc, 230 231 [EDMR] = 0x0000, 232 [EDTRR] = 0x0008, 233 [EDRRR] = 0x0010, 234 [TDLAR] = 0x0018, 235 [RDLAR] = 0x0020, 236 [EESR] = 0x0028, 237 [EESIPR] = 0x0030, 238 [TRSCER] = 0x0038, 239 [RMFCR] = 0x0040, 240 [TFTR] = 0x0048, 241 [FDR] = 0x0050, 242 [RMCR] = 0x0058, 243 [TFUCR] = 0x0064, 244 [RFOCR] = 0x0068, 245 [FCFTR] = 0x0070, 246 [RPADIR] = 0x0078, 247 [TRIMD] = 0x007c, 248 [RBWAR] = 0x00c8, 249 [RDFAR] = 0x00cc, 250 [TBRAR] = 0x00d4, 251 [TDFAR] = 0x00d8, 252 }; 253 254 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 255 SH_ETH_OFFSET_DEFAULTS, 256 257 [EDMR] = 0x0000, 258 [EDTRR] = 0x0004, 259 [EDRRR] = 0x0008, 260 [TDLAR] = 0x000c, 261 [RDLAR] = 0x0010, 262 [EESR] = 0x0014, 263 [EESIPR] = 0x0018, 264 [TRSCER] = 0x001c, 265 [RMFCR] = 0x0020, 266 [TFTR] = 0x0024, 267 [FDR] = 0x0028, 268 [RMCR] = 0x002c, 269 [EDOCR] = 0x0030, 270 [FCFTR] = 0x0034, 271 [RPADIR] = 0x0038, 272 [TRIMD] = 0x003c, 273 [RBWAR] = 0x0040, 274 [RDFAR] = 0x0044, 275 [TBRAR] = 0x004c, 276 [TDFAR] = 0x0050, 277 278 [ECMR] = 0x0160, 279 [ECSR] = 0x0164, 280 [ECSIPR] = 0x0168, 281 [PIR] = 0x016c, 282 [MAHR] = 0x0170, 283 [MALR] = 0x0174, 284 [RFLR] = 0x0178, 285 [PSR] = 0x017c, 286 [TROCR] = 0x0180, 287 [CDCR] = 0x0184, 288 [LCCR] = 0x0188, 289 [CNDCR] = 0x018c, 290 [CEFCR] = 0x0194, 291 [FRECR] = 0x0198, 292 [TSFRCR] = 0x019c, 293 [TLFRCR] = 0x01a0, 294 [RFCR] = 0x01a4, 295 [MAFCR] = 0x01a8, 296 [IPGR] = 0x01b4, 297 [APR] = 0x01b8, 298 [MPR] = 0x01bc, 299 [TPAUSER] = 0x01c4, 300 [BCFR] = 0x01cc, 301 302 [ARSTR] = 0x0000, 303 [TSU_CTRST] = 0x0004, 304 [TSU_FWEN0] = 0x0010, 305 [TSU_FWEN1] = 0x0014, 306 [TSU_FCM] = 0x0018, 307 [TSU_BSYSL0] = 0x0020, 308 [TSU_BSYSL1] = 0x0024, 309 [TSU_PRISL0] = 0x0028, 310 [TSU_PRISL1] = 0x002c, 311 [TSU_FWSL0] = 0x0030, 312 [TSU_FWSL1] = 0x0034, 313 [TSU_FWSLC] = 0x0038, 314 [TSU_QTAGM0] = 0x0040, 315 [TSU_QTAGM1] = 0x0044, 316 [TSU_ADQT0] = 0x0048, 317 [TSU_ADQT1] = 0x004c, 318 [TSU_FWSR] = 0x0050, 319 [TSU_FWINMK] = 0x0054, 320 [TSU_ADSBSY] = 0x0060, 321 [TSU_TEN] = 0x0064, 322 [TSU_POST1] = 0x0070, 323 [TSU_POST2] = 0x0074, 324 [TSU_POST3] = 0x0078, 325 [TSU_POST4] = 0x007c, 326 327 [TXNLCR0] = 0x0080, 328 [TXALCR0] = 0x0084, 329 [RXNLCR0] = 0x0088, 330 [RXALCR0] = 0x008c, 331 [FWNLCR0] = 0x0090, 332 [FWALCR0] = 0x0094, 333 [TXNLCR1] = 0x00a0, 334 [TXALCR1] = 0x00a4, 335 [RXNLCR1] = 0x00a8, 336 [RXALCR1] = 0x00ac, 337 [FWNLCR1] = 0x00b0, 338 [FWALCR1] = 0x00b4, 339 340 [TSU_ADRH0] = 0x0100, 341 }; 342 __diag_pop(); 343 344 static void sh_eth_rcv_snd_disable(struct net_device *ndev); 345 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); 346 347 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) 348 { 349 struct sh_eth_private *mdp = netdev_priv(ndev); 350 u16 offset = mdp->reg_offset[enum_index]; 351 352 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 353 return; 354 355 iowrite32(data, mdp->addr + offset); 356 } 357 358 static u32 sh_eth_read(struct net_device *ndev, int enum_index) 359 { 360 struct sh_eth_private *mdp = netdev_priv(ndev); 361 u16 offset = mdp->reg_offset[enum_index]; 362 363 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 364 return ~0U; 365 366 return ioread32(mdp->addr + offset); 367 } 368 369 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear, 370 u32 set) 371 { 372 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set, 373 enum_index); 374 } 375 376 static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index) 377 { 378 return mdp->reg_offset[enum_index]; 379 } 380 381 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data, 382 int enum_index) 383 { 384 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index); 385 386 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 387 return; 388 389 iowrite32(data, mdp->tsu_addr + offset); 390 } 391 392 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index) 393 { 394 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index); 395 396 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 397 return ~0U; 398 399 return ioread32(mdp->tsu_addr + offset); 400 } 401 402 static void sh_eth_soft_swap(char *src, int len) 403 { 404 #ifdef __LITTLE_ENDIAN 405 u32 *p = (u32 *)src; 406 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32)); 407 408 for (; p < maxp; p++) 409 *p = swab32(*p); 410 #endif 411 } 412 413 static void sh_eth_select_mii(struct net_device *ndev) 414 { 415 struct sh_eth_private *mdp = netdev_priv(ndev); 416 u32 value; 417 418 switch (mdp->phy_interface) { 419 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID: 420 value = 0x3; 421 break; 422 case PHY_INTERFACE_MODE_GMII: 423 value = 0x2; 424 break; 425 case PHY_INTERFACE_MODE_MII: 426 value = 0x1; 427 break; 428 case PHY_INTERFACE_MODE_RMII: 429 value = 0x0; 430 break; 431 default: 432 netdev_warn(ndev, 433 "PHY interface mode was not setup. Set to MII.\n"); 434 value = 0x1; 435 break; 436 } 437 438 sh_eth_write(ndev, value, RMII_MII); 439 } 440 441 static void sh_eth_set_duplex(struct net_device *ndev) 442 { 443 struct sh_eth_private *mdp = netdev_priv(ndev); 444 445 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0); 446 } 447 448 static void sh_eth_chip_reset(struct net_device *ndev) 449 { 450 struct sh_eth_private *mdp = netdev_priv(ndev); 451 452 /* reset device */ 453 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR); 454 mdelay(1); 455 } 456 457 static int sh_eth_soft_reset(struct net_device *ndev) 458 { 459 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER); 460 mdelay(3); 461 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0); 462 463 return 0; 464 } 465 466 static int sh_eth_check_soft_reset(struct net_device *ndev) 467 { 468 int cnt; 469 470 for (cnt = 100; cnt > 0; cnt--) { 471 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER)) 472 return 0; 473 mdelay(1); 474 } 475 476 netdev_err(ndev, "Device reset failed\n"); 477 return -ETIMEDOUT; 478 } 479 480 static int sh_eth_soft_reset_gether(struct net_device *ndev) 481 { 482 struct sh_eth_private *mdp = netdev_priv(ndev); 483 int ret; 484 485 sh_eth_write(ndev, EDSR_ENALL, EDSR); 486 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER); 487 488 ret = sh_eth_check_soft_reset(ndev); 489 if (ret) 490 return ret; 491 492 /* Table Init */ 493 sh_eth_write(ndev, 0, TDLAR); 494 sh_eth_write(ndev, 0, TDFAR); 495 sh_eth_write(ndev, 0, TDFXR); 496 sh_eth_write(ndev, 0, TDFFR); 497 sh_eth_write(ndev, 0, RDLAR); 498 sh_eth_write(ndev, 0, RDFAR); 499 sh_eth_write(ndev, 0, RDFXR); 500 sh_eth_write(ndev, 0, RDFFR); 501 502 /* Reset HW CRC register */ 503 if (mdp->cd->csmr) 504 sh_eth_write(ndev, 0, CSMR); 505 506 /* Select MII mode */ 507 if (mdp->cd->select_mii) 508 sh_eth_select_mii(ndev); 509 510 return ret; 511 } 512 513 static void sh_eth_set_rate_gether(struct net_device *ndev) 514 { 515 struct sh_eth_private *mdp = netdev_priv(ndev); 516 517 if (WARN_ON(!mdp->cd->gecmr)) 518 return; 519 520 switch (mdp->speed) { 521 case 10: /* 10BASE */ 522 sh_eth_write(ndev, GECMR_10, GECMR); 523 break; 524 case 100:/* 100BASE */ 525 sh_eth_write(ndev, GECMR_100, GECMR); 526 break; 527 case 1000: /* 1000BASE */ 528 sh_eth_write(ndev, GECMR_1000, GECMR); 529 break; 530 } 531 } 532 533 #ifdef CONFIG_OF 534 /* R7S72100 */ 535 static struct sh_eth_cpu_data r7s72100_data = { 536 .soft_reset = sh_eth_soft_reset_gether, 537 538 .chip_reset = sh_eth_chip_reset, 539 .set_duplex = sh_eth_set_duplex, 540 541 .register_type = SH_ETH_REG_GIGABIT, 542 543 .edtrr_trns = EDTRR_TRNS_GETHER, 544 .ecsr_value = ECSR_ICD, 545 .ecsipr_value = ECSIPR_ICDIP, 546 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP | 547 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP | 548 EESIPR_ECIIP | 549 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 550 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 551 EESIPR_RMAFIP | EESIPR_RRFIP | 552 EESIPR_RTLFIP | EESIPR_RTSFIP | 553 EESIPR_PREIP | EESIPR_CERFIP, 554 555 .tx_check = EESR_TC1 | EESR_FTC, 556 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 557 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 558 EESR_TDE, 559 .fdr_value = 0x0000070f, 560 561 .trscer_err_mask = TRSCER_RMAFCE | TRSCER_RRFCE, 562 563 .no_psr = 1, 564 .apr = 1, 565 .mpr = 1, 566 .tpauser = 1, 567 .hw_swap = 1, 568 .rpadir = 1, 569 .no_trimd = 1, 570 .no_ade = 1, 571 .xdfar_rw = 1, 572 .csmr = 1, 573 .rx_csum = 1, 574 .tsu = 1, 575 .no_tx_cntrs = 1, 576 }; 577 578 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 579 { 580 sh_eth_chip_reset(ndev); 581 582 sh_eth_select_mii(ndev); 583 } 584 585 /* R8A7740 */ 586 static struct sh_eth_cpu_data r8a7740_data = { 587 .soft_reset = sh_eth_soft_reset_gether, 588 589 .chip_reset = sh_eth_chip_reset_r8a7740, 590 .set_duplex = sh_eth_set_duplex, 591 .set_rate = sh_eth_set_rate_gether, 592 593 .register_type = SH_ETH_REG_GIGABIT, 594 595 .edtrr_trns = EDTRR_TRNS_GETHER, 596 .ecsr_value = ECSR_ICD | ECSR_MPD, 597 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 598 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 599 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 600 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 601 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 602 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 603 EESIPR_CEEFIP | EESIPR_CELFIP | 604 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 605 EESIPR_PREIP | EESIPR_CERFIP, 606 607 .tx_check = EESR_TC1 | EESR_FTC, 608 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 609 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 610 EESR_TDE, 611 .fdr_value = 0x0000070f, 612 613 .apr = 1, 614 .mpr = 1, 615 .tpauser = 1, 616 .gecmr = 1, 617 .bculr = 1, 618 .hw_swap = 1, 619 .rpadir = 1, 620 .no_trimd = 1, 621 .no_ade = 1, 622 .xdfar_rw = 1, 623 .csmr = 1, 624 .rx_csum = 1, 625 .tsu = 1, 626 .select_mii = 1, 627 .magic = 1, 628 .cexcr = 1, 629 }; 630 631 /* There is CPU dependent code */ 632 static void sh_eth_set_rate_rcar(struct net_device *ndev) 633 { 634 struct sh_eth_private *mdp = netdev_priv(ndev); 635 636 switch (mdp->speed) { 637 case 10: /* 10BASE */ 638 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0); 639 break; 640 case 100:/* 100BASE */ 641 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB); 642 break; 643 } 644 } 645 646 /* R-Car Gen1 */ 647 static struct sh_eth_cpu_data rcar_gen1_data = { 648 .soft_reset = sh_eth_soft_reset, 649 650 .set_duplex = sh_eth_set_duplex, 651 .set_rate = sh_eth_set_rate_rcar, 652 653 .register_type = SH_ETH_REG_FAST_RCAR, 654 655 .edtrr_trns = EDTRR_TRNS_ETHER, 656 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 657 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 658 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 659 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 660 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 661 EESIPR_RMAFIP | EESIPR_RRFIP | 662 EESIPR_RTLFIP | EESIPR_RTSFIP | 663 EESIPR_PREIP | EESIPR_CERFIP, 664 665 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 666 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 667 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 668 .fdr_value = 0x00000f0f, 669 670 .apr = 1, 671 .mpr = 1, 672 .tpauser = 1, 673 .hw_swap = 1, 674 .no_xdfar = 1, 675 }; 676 677 /* R-Car Gen2 and RZ/G1 */ 678 static struct sh_eth_cpu_data rcar_gen2_data = { 679 .soft_reset = sh_eth_soft_reset, 680 681 .set_duplex = sh_eth_set_duplex, 682 .set_rate = sh_eth_set_rate_rcar, 683 684 .register_type = SH_ETH_REG_FAST_RCAR, 685 686 .edtrr_trns = EDTRR_TRNS_ETHER, 687 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 688 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 689 ECSIPR_MPDIP, 690 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 691 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 692 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 693 EESIPR_RMAFIP | EESIPR_RRFIP | 694 EESIPR_RTLFIP | EESIPR_RTSFIP | 695 EESIPR_PREIP | EESIPR_CERFIP, 696 697 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 698 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 699 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 700 .fdr_value = 0x00000f0f, 701 702 .trscer_err_mask = TRSCER_RMAFCE, 703 704 .apr = 1, 705 .mpr = 1, 706 .tpauser = 1, 707 .hw_swap = 1, 708 .no_xdfar = 1, 709 .rmiimode = 1, 710 .magic = 1, 711 }; 712 713 /* R8A77980 */ 714 static struct sh_eth_cpu_data r8a77980_data = { 715 .soft_reset = sh_eth_soft_reset_gether, 716 717 .set_duplex = sh_eth_set_duplex, 718 .set_rate = sh_eth_set_rate_gether, 719 720 .register_type = SH_ETH_REG_GIGABIT, 721 722 .edtrr_trns = EDTRR_TRNS_GETHER, 723 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 724 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 725 ECSIPR_MPDIP, 726 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 727 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 728 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 729 EESIPR_RMAFIP | EESIPR_RRFIP | 730 EESIPR_RTLFIP | EESIPR_RTSFIP | 731 EESIPR_PREIP | EESIPR_CERFIP, 732 733 .tx_check = EESR_FTC | EESR_CD | EESR_TRO, 734 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 735 EESR_RFE | EESR_RDE | EESR_RFRMER | 736 EESR_TFE | EESR_TDE | EESR_ECI, 737 .fdr_value = 0x0000070f, 738 739 .apr = 1, 740 .mpr = 1, 741 .tpauser = 1, 742 .gecmr = 1, 743 .bculr = 1, 744 .hw_swap = 1, 745 .nbst = 1, 746 .rpadir = 1, 747 .no_trimd = 1, 748 .no_ade = 1, 749 .xdfar_rw = 1, 750 .csmr = 1, 751 .rx_csum = 1, 752 .select_mii = 1, 753 .magic = 1, 754 .cexcr = 1, 755 }; 756 757 /* R7S9210 */ 758 static struct sh_eth_cpu_data r7s9210_data = { 759 .soft_reset = sh_eth_soft_reset, 760 761 .set_duplex = sh_eth_set_duplex, 762 .set_rate = sh_eth_set_rate_rcar, 763 764 .register_type = SH_ETH_REG_FAST_SH4, 765 766 .edtrr_trns = EDTRR_TRNS_ETHER, 767 .ecsr_value = ECSR_ICD, 768 .ecsipr_value = ECSIPR_ICDIP, 769 .eesipr_value = EESIPR_TWBIP | EESIPR_TABTIP | EESIPR_RABTIP | 770 EESIPR_RFCOFIP | EESIPR_ECIIP | EESIPR_FTCIP | 771 EESIPR_TDEIP | EESIPR_TFUFIP | EESIPR_FRIP | 772 EESIPR_RDEIP | EESIPR_RFOFIP | EESIPR_CNDIP | 773 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 774 EESIPR_RMAFIP | EESIPR_RRFIP | EESIPR_RTLFIP | 775 EESIPR_RTSFIP | EESIPR_PREIP | EESIPR_CERFIP, 776 777 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 778 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 779 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 780 781 .fdr_value = 0x0000070f, 782 783 .trscer_err_mask = TRSCER_RMAFCE | TRSCER_RRFCE, 784 785 .apr = 1, 786 .mpr = 1, 787 .tpauser = 1, 788 .hw_swap = 1, 789 .rpadir = 1, 790 .no_ade = 1, 791 .xdfar_rw = 1, 792 }; 793 #endif /* CONFIG_OF */ 794 795 static void sh_eth_set_rate_sh7724(struct net_device *ndev) 796 { 797 struct sh_eth_private *mdp = netdev_priv(ndev); 798 799 switch (mdp->speed) { 800 case 10: /* 10BASE */ 801 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0); 802 break; 803 case 100:/* 100BASE */ 804 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM); 805 break; 806 } 807 } 808 809 /* SH7724 */ 810 static struct sh_eth_cpu_data sh7724_data = { 811 .soft_reset = sh_eth_soft_reset, 812 813 .set_duplex = sh_eth_set_duplex, 814 .set_rate = sh_eth_set_rate_sh7724, 815 816 .register_type = SH_ETH_REG_FAST_SH4, 817 818 .edtrr_trns = EDTRR_TRNS_ETHER, 819 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 820 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 821 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 822 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 823 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 824 EESIPR_RMAFIP | EESIPR_RRFIP | 825 EESIPR_RTLFIP | EESIPR_RTSFIP | 826 EESIPR_PREIP | EESIPR_CERFIP, 827 828 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 829 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 830 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 831 832 .apr = 1, 833 .mpr = 1, 834 .tpauser = 1, 835 .hw_swap = 1, 836 .rpadir = 1, 837 }; 838 839 static void sh_eth_set_rate_sh7757(struct net_device *ndev) 840 { 841 struct sh_eth_private *mdp = netdev_priv(ndev); 842 843 switch (mdp->speed) { 844 case 10: /* 10BASE */ 845 sh_eth_write(ndev, 0, RTRATE); 846 break; 847 case 100:/* 100BASE */ 848 sh_eth_write(ndev, 1, RTRATE); 849 break; 850 } 851 } 852 853 /* SH7757 */ 854 static struct sh_eth_cpu_data sh7757_data = { 855 .soft_reset = sh_eth_soft_reset, 856 857 .set_duplex = sh_eth_set_duplex, 858 .set_rate = sh_eth_set_rate_sh7757, 859 860 .register_type = SH_ETH_REG_FAST_SH4, 861 862 .edtrr_trns = EDTRR_TRNS_ETHER, 863 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 864 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 865 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 866 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 867 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 868 EESIPR_CEEFIP | EESIPR_CELFIP | 869 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 870 EESIPR_PREIP | EESIPR_CERFIP, 871 872 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 873 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 874 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 875 876 .irq_flags = IRQF_SHARED, 877 .apr = 1, 878 .mpr = 1, 879 .tpauser = 1, 880 .hw_swap = 1, 881 .no_ade = 1, 882 .rpadir = 1, 883 .rtrate = 1, 884 .dual_port = 1, 885 }; 886 887 #define SH_GIGA_ETH_BASE 0xfee00000UL 888 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 889 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 890 static void sh_eth_chip_reset_giga(struct net_device *ndev) 891 { 892 u32 mahr[2], malr[2]; 893 int i; 894 895 /* save MAHR and MALR */ 896 for (i = 0; i < 2; i++) { 897 malr[i] = ioread32((void *)GIGA_MALR(i)); 898 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 899 } 900 901 sh_eth_chip_reset(ndev); 902 903 /* restore MAHR and MALR */ 904 for (i = 0; i < 2; i++) { 905 iowrite32(malr[i], (void *)GIGA_MALR(i)); 906 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 907 } 908 } 909 910 static void sh_eth_set_rate_giga(struct net_device *ndev) 911 { 912 struct sh_eth_private *mdp = netdev_priv(ndev); 913 914 if (WARN_ON(!mdp->cd->gecmr)) 915 return; 916 917 switch (mdp->speed) { 918 case 10: /* 10BASE */ 919 sh_eth_write(ndev, 0x00000000, GECMR); 920 break; 921 case 100:/* 100BASE */ 922 sh_eth_write(ndev, 0x00000010, GECMR); 923 break; 924 case 1000: /* 1000BASE */ 925 sh_eth_write(ndev, 0x00000020, GECMR); 926 break; 927 } 928 } 929 930 /* SH7757(GETHERC) */ 931 static struct sh_eth_cpu_data sh7757_data_giga = { 932 .soft_reset = sh_eth_soft_reset_gether, 933 934 .chip_reset = sh_eth_chip_reset_giga, 935 .set_duplex = sh_eth_set_duplex, 936 .set_rate = sh_eth_set_rate_giga, 937 938 .register_type = SH_ETH_REG_GIGABIT, 939 940 .edtrr_trns = EDTRR_TRNS_GETHER, 941 .ecsr_value = ECSR_ICD | ECSR_MPD, 942 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 943 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 944 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 945 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 946 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 947 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 948 EESIPR_CEEFIP | EESIPR_CELFIP | 949 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 950 EESIPR_PREIP | EESIPR_CERFIP, 951 952 .tx_check = EESR_TC1 | EESR_FTC, 953 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 954 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 955 EESR_TDE, 956 .fdr_value = 0x0000072f, 957 958 .irq_flags = IRQF_SHARED, 959 .apr = 1, 960 .mpr = 1, 961 .tpauser = 1, 962 .gecmr = 1, 963 .bculr = 1, 964 .hw_swap = 1, 965 .rpadir = 1, 966 .no_trimd = 1, 967 .no_ade = 1, 968 .xdfar_rw = 1, 969 .tsu = 1, 970 .cexcr = 1, 971 .dual_port = 1, 972 }; 973 974 /* SH7734 */ 975 static struct sh_eth_cpu_data sh7734_data = { 976 .soft_reset = sh_eth_soft_reset_gether, 977 978 .chip_reset = sh_eth_chip_reset, 979 .set_duplex = sh_eth_set_duplex, 980 .set_rate = sh_eth_set_rate_gether, 981 982 .register_type = SH_ETH_REG_GIGABIT, 983 984 .edtrr_trns = EDTRR_TRNS_GETHER, 985 .ecsr_value = ECSR_ICD | ECSR_MPD, 986 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 987 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 988 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 989 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 990 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 991 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 992 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 993 EESIPR_PREIP | EESIPR_CERFIP, 994 995 .tx_check = EESR_TC1 | EESR_FTC, 996 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 997 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 998 EESR_TDE, 999 1000 .apr = 1, 1001 .mpr = 1, 1002 .tpauser = 1, 1003 .gecmr = 1, 1004 .bculr = 1, 1005 .hw_swap = 1, 1006 .no_trimd = 1, 1007 .no_ade = 1, 1008 .xdfar_rw = 1, 1009 .tsu = 1, 1010 .csmr = 1, 1011 .rx_csum = 1, 1012 .select_mii = 1, 1013 .magic = 1, 1014 .cexcr = 1, 1015 }; 1016 1017 /* SH7763 */ 1018 static struct sh_eth_cpu_data sh7763_data = { 1019 .soft_reset = sh_eth_soft_reset_gether, 1020 1021 .chip_reset = sh_eth_chip_reset, 1022 .set_duplex = sh_eth_set_duplex, 1023 .set_rate = sh_eth_set_rate_gether, 1024 1025 .register_type = SH_ETH_REG_GIGABIT, 1026 1027 .edtrr_trns = EDTRR_TRNS_GETHER, 1028 .ecsr_value = ECSR_ICD | ECSR_MPD, 1029 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 1030 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1031 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1032 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1033 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 1034 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 1035 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1036 EESIPR_PREIP | EESIPR_CERFIP, 1037 1038 .tx_check = EESR_TC1 | EESR_FTC, 1039 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 1040 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 1041 1042 .apr = 1, 1043 .mpr = 1, 1044 .tpauser = 1, 1045 .gecmr = 1, 1046 .bculr = 1, 1047 .hw_swap = 1, 1048 .no_trimd = 1, 1049 .no_ade = 1, 1050 .xdfar_rw = 1, 1051 .tsu = 1, 1052 .irq_flags = IRQF_SHARED, 1053 .magic = 1, 1054 .cexcr = 1, 1055 .rx_csum = 1, 1056 .dual_port = 1, 1057 }; 1058 1059 static struct sh_eth_cpu_data sh7619_data = { 1060 .soft_reset = sh_eth_soft_reset, 1061 1062 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1063 1064 .edtrr_trns = EDTRR_TRNS_ETHER, 1065 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1066 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1067 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1068 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1069 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1070 EESIPR_CEEFIP | EESIPR_CELFIP | 1071 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1072 EESIPR_PREIP | EESIPR_CERFIP, 1073 1074 .apr = 1, 1075 .mpr = 1, 1076 .tpauser = 1, 1077 .hw_swap = 1, 1078 }; 1079 1080 static struct sh_eth_cpu_data sh771x_data = { 1081 .soft_reset = sh_eth_soft_reset, 1082 1083 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1084 1085 .edtrr_trns = EDTRR_TRNS_ETHER, 1086 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1087 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1088 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1089 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1090 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1091 EESIPR_CEEFIP | EESIPR_CELFIP | 1092 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1093 EESIPR_PREIP | EESIPR_CERFIP, 1094 1095 .trscer_err_mask = TRSCER_RMAFCE, 1096 1097 .tsu = 1, 1098 .dual_port = 1, 1099 }; 1100 1101 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 1102 { 1103 if (!cd->ecsr_value) 1104 cd->ecsr_value = DEFAULT_ECSR_INIT; 1105 1106 if (!cd->ecsipr_value) 1107 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 1108 1109 if (!cd->fcftr_value) 1110 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 1111 DEFAULT_FIFO_F_D_RFD; 1112 1113 if (!cd->fdr_value) 1114 cd->fdr_value = DEFAULT_FDR_INIT; 1115 1116 if (!cd->tx_check) 1117 cd->tx_check = DEFAULT_TX_CHECK; 1118 1119 if (!cd->eesr_err_check) 1120 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 1121 1122 if (!cd->trscer_err_mask) 1123 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; 1124 } 1125 1126 static void sh_eth_set_receive_align(struct sk_buff *skb) 1127 { 1128 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); 1129 1130 if (reserve) 1131 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); 1132 } 1133 1134 /* Program the hardware MAC address from dev->dev_addr. */ 1135 static void update_mac_address(struct net_device *ndev) 1136 { 1137 sh_eth_write(ndev, 1138 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 1139 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 1140 sh_eth_write(ndev, 1141 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 1142 } 1143 1144 /* Get MAC address from SuperH MAC address register 1145 * 1146 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 1147 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 1148 * When you want use this device, you must set MAC address in bootloader. 1149 * 1150 */ 1151 static void read_mac_address(struct net_device *ndev, unsigned char *mac) 1152 { 1153 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 1154 eth_hw_addr_set(ndev, mac); 1155 } else { 1156 u32 mahr = sh_eth_read(ndev, MAHR); 1157 u32 malr = sh_eth_read(ndev, MALR); 1158 u8 addr[ETH_ALEN]; 1159 1160 addr[0] = (mahr >> 24) & 0xFF; 1161 addr[1] = (mahr >> 16) & 0xFF; 1162 addr[2] = (mahr >> 8) & 0xFF; 1163 addr[3] = (mahr >> 0) & 0xFF; 1164 addr[4] = (malr >> 8) & 0xFF; 1165 addr[5] = (malr >> 0) & 0xFF; 1166 eth_hw_addr_set(ndev, addr); 1167 } 1168 } 1169 1170 struct bb_info { 1171 void (*set_gate)(void *addr); 1172 struct mdiobb_ctrl ctrl; 1173 void *addr; 1174 }; 1175 1176 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 1177 { 1178 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1179 u32 pir; 1180 1181 if (bitbang->set_gate) 1182 bitbang->set_gate(bitbang->addr); 1183 1184 pir = ioread32(bitbang->addr); 1185 if (set) 1186 pir |= mask; 1187 else 1188 pir &= ~mask; 1189 iowrite32(pir, bitbang->addr); 1190 } 1191 1192 /* Data I/O pin control */ 1193 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1194 { 1195 sh_mdio_ctrl(ctrl, PIR_MMD, bit); 1196 } 1197 1198 /* Set bit data*/ 1199 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1200 { 1201 sh_mdio_ctrl(ctrl, PIR_MDO, bit); 1202 } 1203 1204 /* Get bit data*/ 1205 static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1206 { 1207 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1208 1209 if (bitbang->set_gate) 1210 bitbang->set_gate(bitbang->addr); 1211 1212 return (ioread32(bitbang->addr) & PIR_MDI) != 0; 1213 } 1214 1215 /* MDC pin control */ 1216 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1217 { 1218 sh_mdio_ctrl(ctrl, PIR_MDC, bit); 1219 } 1220 1221 /* mdio bus control struct */ 1222 static const struct mdiobb_ops bb_ops = { 1223 .owner = THIS_MODULE, 1224 .set_mdc = sh_mdc_ctrl, 1225 .set_mdio_dir = sh_mmd_ctrl, 1226 .set_mdio_data = sh_set_mdio, 1227 .get_mdio_data = sh_get_mdio, 1228 }; 1229 1230 /* free Tx skb function */ 1231 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only) 1232 { 1233 struct sh_eth_private *mdp = netdev_priv(ndev); 1234 struct sh_eth_txdesc *txdesc; 1235 int free_num = 0; 1236 int entry; 1237 bool sent; 1238 1239 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1240 entry = mdp->dirty_tx % mdp->num_tx_ring; 1241 txdesc = &mdp->tx_ring[entry]; 1242 sent = !(txdesc->status & cpu_to_le32(TD_TACT)); 1243 if (sent_only && !sent) 1244 break; 1245 /* TACT bit must be checked before all the following reads */ 1246 dma_rmb(); 1247 netif_info(mdp, tx_done, ndev, 1248 "tx entry %d status 0x%08x\n", 1249 entry, le32_to_cpu(txdesc->status)); 1250 /* Free the original skb. */ 1251 if (mdp->tx_skbuff[entry]) { 1252 dma_unmap_single(&mdp->pdev->dev, 1253 le32_to_cpu(txdesc->addr), 1254 le32_to_cpu(txdesc->len) >> 16, 1255 DMA_TO_DEVICE); 1256 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1257 mdp->tx_skbuff[entry] = NULL; 1258 free_num++; 1259 } 1260 txdesc->status = cpu_to_le32(TD_TFP); 1261 if (entry >= mdp->num_tx_ring - 1) 1262 txdesc->status |= cpu_to_le32(TD_TDLE); 1263 1264 if (sent) { 1265 ndev->stats.tx_packets++; 1266 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16; 1267 } 1268 } 1269 return free_num; 1270 } 1271 1272 /* free skb and descriptor buffer */ 1273 static void sh_eth_ring_free(struct net_device *ndev) 1274 { 1275 struct sh_eth_private *mdp = netdev_priv(ndev); 1276 int ringsize, i; 1277 1278 if (mdp->rx_ring) { 1279 for (i = 0; i < mdp->num_rx_ring; i++) { 1280 if (mdp->rx_skbuff[i]) { 1281 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i]; 1282 1283 dma_unmap_single(&mdp->pdev->dev, 1284 le32_to_cpu(rxdesc->addr), 1285 ALIGN(mdp->rx_buf_sz, 32), 1286 DMA_FROM_DEVICE); 1287 } 1288 } 1289 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1290 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring, 1291 mdp->rx_desc_dma); 1292 mdp->rx_ring = NULL; 1293 } 1294 1295 /* Free Rx skb ringbuffer */ 1296 if (mdp->rx_skbuff) { 1297 for (i = 0; i < mdp->num_rx_ring; i++) 1298 dev_kfree_skb(mdp->rx_skbuff[i]); 1299 } 1300 kfree(mdp->rx_skbuff); 1301 mdp->rx_skbuff = NULL; 1302 1303 if (mdp->tx_ring) { 1304 sh_eth_tx_free(ndev, false); 1305 1306 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1307 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring, 1308 mdp->tx_desc_dma); 1309 mdp->tx_ring = NULL; 1310 } 1311 1312 /* Free Tx skb ringbuffer */ 1313 kfree(mdp->tx_skbuff); 1314 mdp->tx_skbuff = NULL; 1315 } 1316 1317 /* format skb and descriptor buffer */ 1318 static void sh_eth_ring_format(struct net_device *ndev) 1319 { 1320 struct sh_eth_private *mdp = netdev_priv(ndev); 1321 int i; 1322 struct sk_buff *skb; 1323 struct sh_eth_rxdesc *rxdesc = NULL; 1324 struct sh_eth_txdesc *txdesc = NULL; 1325 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1326 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1327 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1328 dma_addr_t dma_addr; 1329 u32 buf_len; 1330 1331 mdp->cur_rx = 0; 1332 mdp->cur_tx = 0; 1333 mdp->dirty_rx = 0; 1334 mdp->dirty_tx = 0; 1335 1336 memset(mdp->rx_ring, 0, rx_ringsize); 1337 1338 /* build Rx ring buffer */ 1339 for (i = 0; i < mdp->num_rx_ring; i++) { 1340 /* skb */ 1341 mdp->rx_skbuff[i] = NULL; 1342 skb = netdev_alloc_skb(ndev, skbuff_size); 1343 if (skb == NULL) 1344 break; 1345 sh_eth_set_receive_align(skb); 1346 1347 /* The size of the buffer is a multiple of 32 bytes. */ 1348 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1349 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len, 1350 DMA_FROM_DEVICE); 1351 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1352 kfree_skb(skb); 1353 break; 1354 } 1355 mdp->rx_skbuff[i] = skb; 1356 1357 /* RX descriptor */ 1358 rxdesc = &mdp->rx_ring[i]; 1359 rxdesc->len = cpu_to_le32(buf_len << 16); 1360 rxdesc->addr = cpu_to_le32(dma_addr); 1361 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); 1362 1363 /* Rx descriptor address set */ 1364 if (i == 0) { 1365 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1366 if (mdp->cd->xdfar_rw) 1367 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1368 } 1369 } 1370 1371 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1372 1373 /* Mark the last entry as wrapping the ring. */ 1374 if (rxdesc) 1375 rxdesc->status |= cpu_to_le32(RD_RDLE); 1376 1377 memset(mdp->tx_ring, 0, tx_ringsize); 1378 1379 /* build Tx ring buffer */ 1380 for (i = 0; i < mdp->num_tx_ring; i++) { 1381 mdp->tx_skbuff[i] = NULL; 1382 txdesc = &mdp->tx_ring[i]; 1383 txdesc->status = cpu_to_le32(TD_TFP); 1384 txdesc->len = cpu_to_le32(0); 1385 if (i == 0) { 1386 /* Tx descriptor address set */ 1387 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1388 if (mdp->cd->xdfar_rw) 1389 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1390 } 1391 } 1392 1393 txdesc->status |= cpu_to_le32(TD_TDLE); 1394 } 1395 1396 /* Get skb and descriptor buffer */ 1397 static int sh_eth_ring_init(struct net_device *ndev) 1398 { 1399 struct sh_eth_private *mdp = netdev_priv(ndev); 1400 int rx_ringsize, tx_ringsize; 1401 1402 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1403 * card needs room to do 8 byte alignment, +2 so we can reserve 1404 * the first 2 bytes, and +16 gets room for the status word from the 1405 * card. 1406 */ 1407 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1408 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1409 if (mdp->cd->rpadir) 1410 mdp->rx_buf_sz += NET_IP_ALIGN; 1411 1412 /* Allocate RX and TX skb rings */ 1413 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff), 1414 GFP_KERNEL); 1415 if (!mdp->rx_skbuff) 1416 return -ENOMEM; 1417 1418 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff), 1419 GFP_KERNEL); 1420 if (!mdp->tx_skbuff) 1421 goto ring_free; 1422 1423 /* Allocate all Rx descriptors. */ 1424 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1425 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize, 1426 &mdp->rx_desc_dma, GFP_KERNEL); 1427 if (!mdp->rx_ring) 1428 goto ring_free; 1429 1430 mdp->dirty_rx = 0; 1431 1432 /* Allocate all Tx descriptors. */ 1433 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1434 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize, 1435 &mdp->tx_desc_dma, GFP_KERNEL); 1436 if (!mdp->tx_ring) 1437 goto ring_free; 1438 return 0; 1439 1440 ring_free: 1441 /* Free Rx and Tx skb ring buffer and DMA buffer */ 1442 sh_eth_ring_free(ndev); 1443 1444 return -ENOMEM; 1445 } 1446 1447 static int sh_eth_dev_init(struct net_device *ndev) 1448 { 1449 struct sh_eth_private *mdp = netdev_priv(ndev); 1450 int ret; 1451 1452 /* Soft Reset */ 1453 ret = mdp->cd->soft_reset(ndev); 1454 if (ret) 1455 return ret; 1456 1457 if (mdp->cd->rmiimode) 1458 sh_eth_write(ndev, 0x1, RMIIMODE); 1459 1460 /* Descriptor format */ 1461 sh_eth_ring_format(ndev); 1462 if (mdp->cd->rpadir) 1463 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR); 1464 1465 /* all sh_eth int mask */ 1466 sh_eth_write(ndev, 0, EESIPR); 1467 1468 #if defined(__LITTLE_ENDIAN) 1469 if (mdp->cd->hw_swap) 1470 sh_eth_write(ndev, EDMR_EL, EDMR); 1471 else 1472 #endif 1473 sh_eth_write(ndev, 0, EDMR); 1474 1475 /* FIFO size set */ 1476 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1477 sh_eth_write(ndev, 0, TFTR); 1478 1479 /* Frame recv control (enable multiple-packets per rx irq) */ 1480 sh_eth_write(ndev, RMCR_RNC, RMCR); 1481 1482 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); 1483 1484 /* DMA transfer burst mode */ 1485 if (mdp->cd->nbst) 1486 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST); 1487 1488 /* Burst cycle count upper-limit */ 1489 if (mdp->cd->bculr) 1490 sh_eth_write(ndev, 0x800, BCULR); 1491 1492 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1493 1494 if (!mdp->cd->no_trimd) 1495 sh_eth_write(ndev, 0, TRIMD); 1496 1497 /* Recv frame limit set register */ 1498 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1499 RFLR); 1500 1501 sh_eth_modify(ndev, EESR, 0, 0); 1502 mdp->irq_enabled = true; 1503 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1504 1505 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 1506 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | 1507 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 1508 ECMR_TE | ECMR_RE, ECMR); 1509 1510 if (mdp->cd->set_rate) 1511 mdp->cd->set_rate(ndev); 1512 1513 /* E-MAC Status Register clear */ 1514 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1515 1516 /* E-MAC Interrupt Enable register */ 1517 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1518 1519 /* Set MAC address */ 1520 update_mac_address(ndev); 1521 1522 /* mask reset */ 1523 if (mdp->cd->apr) 1524 sh_eth_write(ndev, 1, APR); 1525 if (mdp->cd->mpr) 1526 sh_eth_write(ndev, 1, MPR); 1527 if (mdp->cd->tpauser) 1528 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1529 1530 /* Setting the Rx mode will start the Rx process. */ 1531 sh_eth_write(ndev, EDRRR_R, EDRRR); 1532 1533 return ret; 1534 } 1535 1536 static void sh_eth_dev_exit(struct net_device *ndev) 1537 { 1538 struct sh_eth_private *mdp = netdev_priv(ndev); 1539 int i; 1540 1541 /* Deactivate all TX descriptors, so DMA should stop at next 1542 * packet boundary if it's currently running 1543 */ 1544 for (i = 0; i < mdp->num_tx_ring; i++) 1545 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT); 1546 1547 /* Disable TX FIFO egress to MAC */ 1548 sh_eth_rcv_snd_disable(ndev); 1549 1550 /* Stop RX DMA at next packet boundary */ 1551 sh_eth_write(ndev, 0, EDRRR); 1552 1553 /* Aside from TX DMA, we can't tell when the hardware is 1554 * really stopped, so we need to reset to make sure. 1555 * Before doing that, wait for long enough to *probably* 1556 * finish transmitting the last packet and poll stats. 1557 */ 1558 msleep(2); /* max frame time at 10 Mbps < 1250 us */ 1559 sh_eth_get_stats(ndev); 1560 mdp->cd->soft_reset(ndev); 1561 1562 /* Set the RMII mode again if required */ 1563 if (mdp->cd->rmiimode) 1564 sh_eth_write(ndev, 0x1, RMIIMODE); 1565 1566 /* Set MAC address again */ 1567 update_mac_address(ndev); 1568 } 1569 1570 static void sh_eth_rx_csum(struct sk_buff *skb) 1571 { 1572 u8 *hw_csum; 1573 1574 /* The hardware checksum is 2 bytes appended to packet data */ 1575 if (unlikely(skb->len < sizeof(__sum16))) 1576 return; 1577 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 1578 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 1579 skb->ip_summed = CHECKSUM_COMPLETE; 1580 skb_trim(skb, skb->len - sizeof(__sum16)); 1581 } 1582 1583 /* Packet receive function */ 1584 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1585 { 1586 struct sh_eth_private *mdp = netdev_priv(ndev); 1587 struct sh_eth_rxdesc *rxdesc; 1588 1589 int entry = mdp->cur_rx % mdp->num_rx_ring; 1590 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1591 int limit; 1592 struct sk_buff *skb; 1593 u32 desc_status; 1594 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1595 dma_addr_t dma_addr; 1596 u16 pkt_len; 1597 u32 buf_len; 1598 1599 boguscnt = min(boguscnt, *quota); 1600 limit = boguscnt; 1601 rxdesc = &mdp->rx_ring[entry]; 1602 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { 1603 /* RACT bit must be checked before all the following reads */ 1604 dma_rmb(); 1605 desc_status = le32_to_cpu(rxdesc->status); 1606 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL; 1607 1608 if (--boguscnt < 0) 1609 break; 1610 1611 netif_info(mdp, rx_status, ndev, 1612 "rx entry %d status 0x%08x len %d\n", 1613 entry, desc_status, pkt_len); 1614 1615 if (!(desc_status & RDFEND)) 1616 ndev->stats.rx_length_errors++; 1617 1618 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1619 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1620 * bit 0. However, in case of the R8A7740 and R7S72100 1621 * the RFS bits are from bit 25 to bit 16. So, the 1622 * driver needs right shifting by 16. 1623 */ 1624 if (mdp->cd->csmr) 1625 desc_status >>= 16; 1626 1627 skb = mdp->rx_skbuff[entry]; 1628 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1629 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1630 ndev->stats.rx_errors++; 1631 if (desc_status & RD_RFS1) 1632 ndev->stats.rx_crc_errors++; 1633 if (desc_status & RD_RFS2) 1634 ndev->stats.rx_frame_errors++; 1635 if (desc_status & RD_RFS3) 1636 ndev->stats.rx_length_errors++; 1637 if (desc_status & RD_RFS4) 1638 ndev->stats.rx_length_errors++; 1639 if (desc_status & RD_RFS6) 1640 ndev->stats.rx_missed_errors++; 1641 if (desc_status & RD_RFS10) 1642 ndev->stats.rx_over_errors++; 1643 } else if (skb) { 1644 dma_addr = le32_to_cpu(rxdesc->addr); 1645 if (!mdp->cd->hw_swap) 1646 sh_eth_soft_swap( 1647 phys_to_virt(ALIGN(dma_addr, 4)), 1648 pkt_len + 2); 1649 mdp->rx_skbuff[entry] = NULL; 1650 if (mdp->cd->rpadir) 1651 skb_reserve(skb, NET_IP_ALIGN); 1652 dma_unmap_single(&mdp->pdev->dev, dma_addr, 1653 ALIGN(mdp->rx_buf_sz, 32), 1654 DMA_FROM_DEVICE); 1655 skb_put(skb, pkt_len); 1656 skb->protocol = eth_type_trans(skb, ndev); 1657 if (ndev->features & NETIF_F_RXCSUM) 1658 sh_eth_rx_csum(skb); 1659 netif_receive_skb(skb); 1660 ndev->stats.rx_packets++; 1661 ndev->stats.rx_bytes += pkt_len; 1662 if (desc_status & RD_RFS8) 1663 ndev->stats.multicast++; 1664 } 1665 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1666 rxdesc = &mdp->rx_ring[entry]; 1667 } 1668 1669 /* Refill the Rx ring buffers. */ 1670 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1671 entry = mdp->dirty_rx % mdp->num_rx_ring; 1672 rxdesc = &mdp->rx_ring[entry]; 1673 /* The size of the buffer is 32 byte boundary. */ 1674 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1675 rxdesc->len = cpu_to_le32(buf_len << 16); 1676 1677 if (mdp->rx_skbuff[entry] == NULL) { 1678 skb = netdev_alloc_skb(ndev, skbuff_size); 1679 if (skb == NULL) 1680 break; /* Better luck next round. */ 1681 sh_eth_set_receive_align(skb); 1682 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, 1683 buf_len, DMA_FROM_DEVICE); 1684 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1685 kfree_skb(skb); 1686 break; 1687 } 1688 mdp->rx_skbuff[entry] = skb; 1689 1690 skb_checksum_none_assert(skb); 1691 rxdesc->addr = cpu_to_le32(dma_addr); 1692 } 1693 dma_wmb(); /* RACT bit must be set after all the above writes */ 1694 if (entry >= mdp->num_rx_ring - 1) 1695 rxdesc->status |= 1696 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE); 1697 else 1698 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP); 1699 } 1700 1701 /* Restart Rx engine if stopped. */ 1702 /* If we don't need to check status, don't. -KDU */ 1703 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1704 /* fix the values for the next receiving if RDE is set */ 1705 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) { 1706 u32 count = (sh_eth_read(ndev, RDFAR) - 1707 sh_eth_read(ndev, RDLAR)) >> 4; 1708 1709 mdp->cur_rx = count; 1710 mdp->dirty_rx = count; 1711 } 1712 sh_eth_write(ndev, EDRRR_R, EDRRR); 1713 } 1714 1715 *quota -= limit - boguscnt - 1; 1716 1717 return *quota <= 0; 1718 } 1719 1720 static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1721 { 1722 /* disable tx and rx */ 1723 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1724 } 1725 1726 static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1727 { 1728 /* enable tx and rx */ 1729 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1730 } 1731 1732 /* E-MAC interrupt handler */ 1733 static void sh_eth_emac_interrupt(struct net_device *ndev) 1734 { 1735 struct sh_eth_private *mdp = netdev_priv(ndev); 1736 u32 felic_stat; 1737 u32 link_stat; 1738 1739 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR); 1740 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1741 if (felic_stat & ECSR_ICD) 1742 ndev->stats.tx_carrier_errors++; 1743 if (felic_stat & ECSR_MPD) 1744 pm_wakeup_event(&mdp->pdev->dev, 0); 1745 if (felic_stat & ECSR_LCHNG) { 1746 /* Link Changed */ 1747 if (mdp->cd->no_psr || mdp->no_ether_link) 1748 return; 1749 link_stat = sh_eth_read(ndev, PSR); 1750 if (mdp->ether_link_active_low) 1751 link_stat = ~link_stat; 1752 if (!(link_stat & PSR_LMON)) { 1753 sh_eth_rcv_snd_disable(ndev); 1754 } else { 1755 /* Link Up */ 1756 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0); 1757 /* clear int */ 1758 sh_eth_modify(ndev, ECSR, 0, 0); 1759 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP); 1760 /* enable tx and rx */ 1761 sh_eth_rcv_snd_enable(ndev); 1762 } 1763 } 1764 } 1765 1766 /* error control function */ 1767 static void sh_eth_error(struct net_device *ndev, u32 intr_status) 1768 { 1769 struct sh_eth_private *mdp = netdev_priv(ndev); 1770 u32 mask; 1771 1772 if (intr_status & EESR_TWB) { 1773 /* Unused write back interrupt */ 1774 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1775 ndev->stats.tx_aborted_errors++; 1776 netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); 1777 } 1778 } 1779 1780 if (intr_status & EESR_RABT) { 1781 /* Receive Abort int */ 1782 if (intr_status & EESR_RFRMER) { 1783 /* Receive Frame Overflow int */ 1784 ndev->stats.rx_frame_errors++; 1785 } 1786 } 1787 1788 if (intr_status & EESR_TDE) { 1789 /* Transmit Descriptor Empty int */ 1790 ndev->stats.tx_fifo_errors++; 1791 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); 1792 } 1793 1794 if (intr_status & EESR_TFE) { 1795 /* FIFO under flow */ 1796 ndev->stats.tx_fifo_errors++; 1797 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); 1798 } 1799 1800 if (intr_status & EESR_RDE) { 1801 /* Receive Descriptor Empty int */ 1802 ndev->stats.rx_over_errors++; 1803 } 1804 1805 if (intr_status & EESR_RFE) { 1806 /* Receive FIFO Overflow int */ 1807 ndev->stats.rx_fifo_errors++; 1808 } 1809 1810 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1811 /* Address Error */ 1812 ndev->stats.tx_fifo_errors++; 1813 netif_err(mdp, tx_err, ndev, "Address Error\n"); 1814 } 1815 1816 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1817 if (mdp->cd->no_ade) 1818 mask &= ~EESR_ADE; 1819 if (intr_status & mask) { 1820 /* Tx error */ 1821 u32 edtrr = sh_eth_read(ndev, EDTRR); 1822 1823 /* dmesg */ 1824 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1825 intr_status, mdp->cur_tx, mdp->dirty_tx, 1826 (u32)ndev->state, edtrr); 1827 /* dirty buffer free */ 1828 sh_eth_tx_free(ndev, true); 1829 1830 /* SH7712 BUG */ 1831 if (edtrr ^ mdp->cd->edtrr_trns) { 1832 /* tx dma start */ 1833 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 1834 } 1835 /* wakeup */ 1836 netif_wake_queue(ndev); 1837 } 1838 } 1839 1840 static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1841 { 1842 struct net_device *ndev = netdev; 1843 struct sh_eth_private *mdp = netdev_priv(ndev); 1844 struct sh_eth_cpu_data *cd = mdp->cd; 1845 irqreturn_t ret = IRQ_NONE; 1846 u32 intr_status, intr_enable; 1847 1848 spin_lock(&mdp->lock); 1849 1850 /* Get interrupt status */ 1851 intr_status = sh_eth_read(ndev, EESR); 1852 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1853 * enabled since it's the one that comes thru regardless of the mask, 1854 * and we need to fully handle it in sh_eth_emac_interrupt() in order 1855 * to quench it as it doesn't get cleared by just writing 1 to the ECI 1856 * bit... 1857 */ 1858 intr_enable = sh_eth_read(ndev, EESIPR); 1859 intr_status &= intr_enable | EESIPR_ECIIP; 1860 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | 1861 cd->eesr_err_check)) 1862 ret = IRQ_HANDLED; 1863 else 1864 goto out; 1865 1866 if (unlikely(!mdp->irq_enabled)) { 1867 sh_eth_write(ndev, 0, EESIPR); 1868 goto out; 1869 } 1870 1871 if (intr_status & EESR_RX_CHECK) { 1872 if (napi_schedule_prep(&mdp->napi)) { 1873 /* Mask Rx interrupts */ 1874 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1875 EESIPR); 1876 __napi_schedule(&mdp->napi); 1877 } else { 1878 netdev_warn(ndev, 1879 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", 1880 intr_status, intr_enable); 1881 } 1882 } 1883 1884 /* Tx Check */ 1885 if (intr_status & cd->tx_check) { 1886 /* Clear Tx interrupts */ 1887 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1888 1889 sh_eth_tx_free(ndev, true); 1890 netif_wake_queue(ndev); 1891 } 1892 1893 /* E-MAC interrupt */ 1894 if (intr_status & EESR_ECI) 1895 sh_eth_emac_interrupt(ndev); 1896 1897 if (intr_status & cd->eesr_err_check) { 1898 /* Clear error interrupts */ 1899 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1900 1901 sh_eth_error(ndev, intr_status); 1902 } 1903 1904 out: 1905 spin_unlock(&mdp->lock); 1906 1907 return ret; 1908 } 1909 1910 static int sh_eth_poll(struct napi_struct *napi, int budget) 1911 { 1912 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1913 napi); 1914 struct net_device *ndev = napi->dev; 1915 int quota = budget; 1916 u32 intr_status; 1917 1918 for (;;) { 1919 intr_status = sh_eth_read(ndev, EESR); 1920 if (!(intr_status & EESR_RX_CHECK)) 1921 break; 1922 /* Clear Rx interrupts */ 1923 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1924 1925 if (sh_eth_rx(ndev, intr_status, "a)) 1926 goto out; 1927 } 1928 1929 napi_complete(napi); 1930 1931 /* Reenable Rx interrupts */ 1932 if (mdp->irq_enabled) 1933 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1934 out: 1935 return budget - quota; 1936 } 1937 1938 /* PHY state control function */ 1939 static void sh_eth_adjust_link(struct net_device *ndev) 1940 { 1941 struct sh_eth_private *mdp = netdev_priv(ndev); 1942 struct phy_device *phydev = ndev->phydev; 1943 unsigned long flags; 1944 int new_state = 0; 1945 1946 spin_lock_irqsave(&mdp->lock, flags); 1947 1948 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1949 if (mdp->cd->no_psr || mdp->no_ether_link) 1950 sh_eth_rcv_snd_disable(ndev); 1951 1952 if (phydev->link) { 1953 if (phydev->duplex != mdp->duplex) { 1954 new_state = 1; 1955 mdp->duplex = phydev->duplex; 1956 if (mdp->cd->set_duplex) 1957 mdp->cd->set_duplex(ndev); 1958 } 1959 1960 if (phydev->speed != mdp->speed) { 1961 new_state = 1; 1962 mdp->speed = phydev->speed; 1963 if (mdp->cd->set_rate) 1964 mdp->cd->set_rate(ndev); 1965 } 1966 if (!mdp->link) { 1967 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0); 1968 new_state = 1; 1969 mdp->link = phydev->link; 1970 } 1971 } else if (mdp->link) { 1972 new_state = 1; 1973 mdp->link = 0; 1974 mdp->speed = 0; 1975 mdp->duplex = -1; 1976 } 1977 1978 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1979 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link) 1980 sh_eth_rcv_snd_enable(ndev); 1981 1982 spin_unlock_irqrestore(&mdp->lock, flags); 1983 1984 if (new_state && netif_msg_link(mdp)) 1985 phy_print_status(phydev); 1986 } 1987 1988 /* PHY init function */ 1989 static int sh_eth_phy_init(struct net_device *ndev) 1990 { 1991 struct device_node *np = ndev->dev.parent->of_node; 1992 struct sh_eth_private *mdp = netdev_priv(ndev); 1993 struct phy_device *phydev; 1994 1995 mdp->link = 0; 1996 mdp->speed = 0; 1997 mdp->duplex = -1; 1998 1999 /* Try connect to PHY */ 2000 if (np) { 2001 struct device_node *pn; 2002 2003 pn = of_parse_phandle(np, "phy-handle", 0); 2004 phydev = of_phy_connect(ndev, pn, 2005 sh_eth_adjust_link, 0, 2006 mdp->phy_interface); 2007 2008 of_node_put(pn); 2009 if (!phydev) 2010 phydev = ERR_PTR(-ENOENT); 2011 } else { 2012 char phy_id[MII_BUS_ID_SIZE + 3]; 2013 2014 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 2015 mdp->mii_bus->id, mdp->phy_id); 2016 2017 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 2018 mdp->phy_interface); 2019 } 2020 2021 if (IS_ERR(phydev)) { 2022 netdev_err(ndev, "failed to connect PHY\n"); 2023 return PTR_ERR(phydev); 2024 } 2025 2026 /* mask with MAC supported features */ 2027 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) 2028 phy_set_max_speed(phydev, SPEED_100); 2029 2030 phy_attached_info(phydev); 2031 2032 return 0; 2033 } 2034 2035 /* PHY control start function */ 2036 static int sh_eth_phy_start(struct net_device *ndev) 2037 { 2038 int ret; 2039 2040 ret = sh_eth_phy_init(ndev); 2041 if (ret) 2042 return ret; 2043 2044 phy_start(ndev->phydev); 2045 2046 return 0; 2047 } 2048 2049 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the 2050 * version must be bumped as well. Just adding registers up to that 2051 * limit is fine, as long as the existing register indices don't 2052 * change. 2053 */ 2054 #define SH_ETH_REG_DUMP_VERSION 1 2055 #define SH_ETH_REG_DUMP_MAX_REGS 256 2056 2057 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 2058 { 2059 struct sh_eth_private *mdp = netdev_priv(ndev); 2060 struct sh_eth_cpu_data *cd = mdp->cd; 2061 u32 *valid_map; 2062 size_t len; 2063 2064 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); 2065 2066 /* Dump starts with a bitmap that tells ethtool which 2067 * registers are defined for this chip. 2068 */ 2069 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); 2070 if (buf) { 2071 valid_map = buf; 2072 buf += len; 2073 } else { 2074 valid_map = NULL; 2075 } 2076 2077 /* Add a register to the dump, if it has a defined offset. 2078 * This automatically skips most undefined registers, but for 2079 * some it is also necessary to check a capability flag in 2080 * struct sh_eth_cpu_data. 2081 */ 2082 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) 2083 #define add_reg_from(reg, read_expr) do { \ 2084 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ 2085 if (buf) { \ 2086 mark_reg_valid(reg); \ 2087 *buf++ = read_expr; \ 2088 } \ 2089 ++len; \ 2090 } \ 2091 } while (0) 2092 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) 2093 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) 2094 2095 add_reg(EDSR); 2096 add_reg(EDMR); 2097 add_reg(EDTRR); 2098 add_reg(EDRRR); 2099 add_reg(EESR); 2100 add_reg(EESIPR); 2101 add_reg(TDLAR); 2102 if (!cd->no_xdfar) 2103 add_reg(TDFAR); 2104 add_reg(TDFXR); 2105 add_reg(TDFFR); 2106 add_reg(RDLAR); 2107 if (!cd->no_xdfar) 2108 add_reg(RDFAR); 2109 add_reg(RDFXR); 2110 add_reg(RDFFR); 2111 add_reg(TRSCER); 2112 add_reg(RMFCR); 2113 add_reg(TFTR); 2114 add_reg(FDR); 2115 add_reg(RMCR); 2116 add_reg(TFUCR); 2117 add_reg(RFOCR); 2118 if (cd->rmiimode) 2119 add_reg(RMIIMODE); 2120 add_reg(FCFTR); 2121 if (cd->rpadir) 2122 add_reg(RPADIR); 2123 if (!cd->no_trimd) 2124 add_reg(TRIMD); 2125 add_reg(ECMR); 2126 add_reg(ECSR); 2127 add_reg(ECSIPR); 2128 add_reg(PIR); 2129 if (!cd->no_psr) 2130 add_reg(PSR); 2131 add_reg(RDMLR); 2132 add_reg(RFLR); 2133 add_reg(IPGR); 2134 if (cd->apr) 2135 add_reg(APR); 2136 if (cd->mpr) 2137 add_reg(MPR); 2138 add_reg(RFCR); 2139 add_reg(RFCF); 2140 if (cd->tpauser) 2141 add_reg(TPAUSER); 2142 add_reg(TPAUSECR); 2143 if (cd->gecmr) 2144 add_reg(GECMR); 2145 if (cd->bculr) 2146 add_reg(BCULR); 2147 add_reg(MAHR); 2148 add_reg(MALR); 2149 if (!cd->no_tx_cntrs) { 2150 add_reg(TROCR); 2151 add_reg(CDCR); 2152 add_reg(LCCR); 2153 add_reg(CNDCR); 2154 } 2155 add_reg(CEFCR); 2156 add_reg(FRECR); 2157 add_reg(TSFRCR); 2158 add_reg(TLFRCR); 2159 if (cd->cexcr) { 2160 add_reg(CERCR); 2161 add_reg(CEECR); 2162 } 2163 add_reg(MAFCR); 2164 if (cd->rtrate) 2165 add_reg(RTRATE); 2166 if (cd->csmr) 2167 add_reg(CSMR); 2168 if (cd->select_mii) 2169 add_reg(RMII_MII); 2170 if (cd->tsu) { 2171 add_tsu_reg(ARSTR); 2172 add_tsu_reg(TSU_CTRST); 2173 if (cd->dual_port) { 2174 add_tsu_reg(TSU_FWEN0); 2175 add_tsu_reg(TSU_FWEN1); 2176 add_tsu_reg(TSU_FCM); 2177 add_tsu_reg(TSU_BSYSL0); 2178 add_tsu_reg(TSU_BSYSL1); 2179 add_tsu_reg(TSU_PRISL0); 2180 add_tsu_reg(TSU_PRISL1); 2181 add_tsu_reg(TSU_FWSL0); 2182 add_tsu_reg(TSU_FWSL1); 2183 } 2184 add_tsu_reg(TSU_FWSLC); 2185 if (cd->dual_port) { 2186 add_tsu_reg(TSU_QTAGM0); 2187 add_tsu_reg(TSU_QTAGM1); 2188 add_tsu_reg(TSU_FWSR); 2189 add_tsu_reg(TSU_FWINMK); 2190 add_tsu_reg(TSU_ADQT0); 2191 add_tsu_reg(TSU_ADQT1); 2192 add_tsu_reg(TSU_VTAG0); 2193 add_tsu_reg(TSU_VTAG1); 2194 } 2195 add_tsu_reg(TSU_ADSBSY); 2196 add_tsu_reg(TSU_TEN); 2197 add_tsu_reg(TSU_POST1); 2198 add_tsu_reg(TSU_POST2); 2199 add_tsu_reg(TSU_POST3); 2200 add_tsu_reg(TSU_POST4); 2201 /* This is the start of a table, not just a single register. */ 2202 if (buf) { 2203 unsigned int i; 2204 2205 mark_reg_valid(TSU_ADRH0); 2206 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) 2207 *buf++ = ioread32(mdp->tsu_addr + 2208 mdp->reg_offset[TSU_ADRH0] + 2209 i * 4); 2210 } 2211 len += SH_ETH_TSU_CAM_ENTRIES * 2; 2212 } 2213 2214 #undef mark_reg_valid 2215 #undef add_reg_from 2216 #undef add_reg 2217 #undef add_tsu_reg 2218 2219 return len * 4; 2220 } 2221 2222 static int sh_eth_get_regs_len(struct net_device *ndev) 2223 { 2224 return __sh_eth_get_regs(ndev, NULL); 2225 } 2226 2227 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, 2228 void *buf) 2229 { 2230 struct sh_eth_private *mdp = netdev_priv(ndev); 2231 2232 regs->version = SH_ETH_REG_DUMP_VERSION; 2233 2234 pm_runtime_get_sync(&mdp->pdev->dev); 2235 __sh_eth_get_regs(ndev, buf); 2236 pm_runtime_put(&mdp->pdev->dev); 2237 } 2238 2239 static u32 sh_eth_get_msglevel(struct net_device *ndev) 2240 { 2241 struct sh_eth_private *mdp = netdev_priv(ndev); 2242 return mdp->msg_enable; 2243 } 2244 2245 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 2246 { 2247 struct sh_eth_private *mdp = netdev_priv(ndev); 2248 mdp->msg_enable = value; 2249 } 2250 2251 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 2252 "rx_current", "tx_current", 2253 "rx_dirty", "tx_dirty", 2254 }; 2255 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 2256 2257 static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 2258 { 2259 switch (sset) { 2260 case ETH_SS_STATS: 2261 return SH_ETH_STATS_LEN; 2262 default: 2263 return -EOPNOTSUPP; 2264 } 2265 } 2266 2267 static void sh_eth_get_ethtool_stats(struct net_device *ndev, 2268 struct ethtool_stats *stats, u64 *data) 2269 { 2270 struct sh_eth_private *mdp = netdev_priv(ndev); 2271 int i = 0; 2272 2273 /* device-specific stats */ 2274 data[i++] = mdp->cur_rx; 2275 data[i++] = mdp->cur_tx; 2276 data[i++] = mdp->dirty_rx; 2277 data[i++] = mdp->dirty_tx; 2278 } 2279 2280 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 2281 { 2282 switch (stringset) { 2283 case ETH_SS_STATS: 2284 memcpy(data, sh_eth_gstrings_stats, 2285 sizeof(sh_eth_gstrings_stats)); 2286 break; 2287 } 2288 } 2289 2290 static void sh_eth_get_ringparam(struct net_device *ndev, 2291 struct ethtool_ringparam *ring, 2292 struct kernel_ethtool_ringparam *kernel_ring, 2293 struct netlink_ext_ack *extack) 2294 { 2295 struct sh_eth_private *mdp = netdev_priv(ndev); 2296 2297 ring->rx_max_pending = RX_RING_MAX; 2298 ring->tx_max_pending = TX_RING_MAX; 2299 ring->rx_pending = mdp->num_rx_ring; 2300 ring->tx_pending = mdp->num_tx_ring; 2301 } 2302 2303 static int sh_eth_set_ringparam(struct net_device *ndev, 2304 struct ethtool_ringparam *ring, 2305 struct kernel_ethtool_ringparam *kernel_ring, 2306 struct netlink_ext_ack *extack) 2307 { 2308 struct sh_eth_private *mdp = netdev_priv(ndev); 2309 int ret; 2310 2311 if (ring->tx_pending > TX_RING_MAX || 2312 ring->rx_pending > RX_RING_MAX || 2313 ring->tx_pending < TX_RING_MIN || 2314 ring->rx_pending < RX_RING_MIN) 2315 return -EINVAL; 2316 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 2317 return -EINVAL; 2318 2319 if (netif_running(ndev)) { 2320 netif_device_detach(ndev); 2321 netif_tx_disable(ndev); 2322 2323 /* Serialise with the interrupt handler and NAPI, then 2324 * disable interrupts. We have to clear the 2325 * irq_enabled flag first to ensure that interrupts 2326 * won't be re-enabled. 2327 */ 2328 mdp->irq_enabled = false; 2329 synchronize_irq(ndev->irq); 2330 napi_synchronize(&mdp->napi); 2331 sh_eth_write(ndev, 0x0000, EESIPR); 2332 2333 sh_eth_dev_exit(ndev); 2334 2335 /* Free all the skbuffs in the Rx queue and the DMA buffers. */ 2336 sh_eth_ring_free(ndev); 2337 } 2338 2339 /* Set new parameters */ 2340 mdp->num_rx_ring = ring->rx_pending; 2341 mdp->num_tx_ring = ring->tx_pending; 2342 2343 if (netif_running(ndev)) { 2344 ret = sh_eth_ring_init(ndev); 2345 if (ret < 0) { 2346 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", 2347 __func__); 2348 return ret; 2349 } 2350 ret = sh_eth_dev_init(ndev); 2351 if (ret < 0) { 2352 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", 2353 __func__); 2354 return ret; 2355 } 2356 2357 netif_device_attach(ndev); 2358 } 2359 2360 return 0; 2361 } 2362 2363 #ifdef CONFIG_PM_SLEEP 2364 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2365 { 2366 struct sh_eth_private *mdp = netdev_priv(ndev); 2367 2368 wol->supported = 0; 2369 wol->wolopts = 0; 2370 2371 if (mdp->cd->magic) { 2372 wol->supported = WAKE_MAGIC; 2373 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0; 2374 } 2375 } 2376 2377 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2378 { 2379 struct sh_eth_private *mdp = netdev_priv(ndev); 2380 2381 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC) 2382 return -EOPNOTSUPP; 2383 2384 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 2385 2386 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled); 2387 2388 return 0; 2389 } 2390 #endif 2391 2392 static const struct ethtool_ops sh_eth_ethtool_ops = { 2393 .get_regs_len = sh_eth_get_regs_len, 2394 .get_regs = sh_eth_get_regs, 2395 .nway_reset = phy_ethtool_nway_reset, 2396 .get_msglevel = sh_eth_get_msglevel, 2397 .set_msglevel = sh_eth_set_msglevel, 2398 .get_link = ethtool_op_get_link, 2399 .get_strings = sh_eth_get_strings, 2400 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2401 .get_sset_count = sh_eth_get_sset_count, 2402 .get_ringparam = sh_eth_get_ringparam, 2403 .set_ringparam = sh_eth_set_ringparam, 2404 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2405 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2406 #ifdef CONFIG_PM_SLEEP 2407 .get_wol = sh_eth_get_wol, 2408 .set_wol = sh_eth_set_wol, 2409 #endif 2410 }; 2411 2412 /* network device open function */ 2413 static int sh_eth_open(struct net_device *ndev) 2414 { 2415 struct sh_eth_private *mdp = netdev_priv(ndev); 2416 int ret; 2417 2418 pm_runtime_get_sync(&mdp->pdev->dev); 2419 2420 napi_enable(&mdp->napi); 2421 2422 ret = request_irq(ndev->irq, sh_eth_interrupt, 2423 mdp->cd->irq_flags, ndev->name, ndev); 2424 if (ret) { 2425 netdev_err(ndev, "Can not assign IRQ number\n"); 2426 goto out_napi_off; 2427 } 2428 2429 /* Descriptor set */ 2430 ret = sh_eth_ring_init(ndev); 2431 if (ret) 2432 goto out_free_irq; 2433 2434 /* device init */ 2435 ret = sh_eth_dev_init(ndev); 2436 if (ret) 2437 goto out_free_irq; 2438 2439 /* PHY control start*/ 2440 ret = sh_eth_phy_start(ndev); 2441 if (ret) 2442 goto out_free_irq; 2443 2444 netif_start_queue(ndev); 2445 2446 mdp->is_opened = 1; 2447 2448 return ret; 2449 2450 out_free_irq: 2451 free_irq(ndev->irq, ndev); 2452 out_napi_off: 2453 napi_disable(&mdp->napi); 2454 pm_runtime_put(&mdp->pdev->dev); 2455 return ret; 2456 } 2457 2458 /* Timeout function */ 2459 static void sh_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue) 2460 { 2461 struct sh_eth_private *mdp = netdev_priv(ndev); 2462 struct sh_eth_rxdesc *rxdesc; 2463 int i; 2464 2465 netif_stop_queue(ndev); 2466 2467 netif_err(mdp, timer, ndev, 2468 "transmit timed out, status %8.8x, resetting...\n", 2469 sh_eth_read(ndev, EESR)); 2470 2471 /* tx_errors count up */ 2472 ndev->stats.tx_errors++; 2473 2474 /* Free all the skbuffs in the Rx queue. */ 2475 for (i = 0; i < mdp->num_rx_ring; i++) { 2476 rxdesc = &mdp->rx_ring[i]; 2477 rxdesc->status = cpu_to_le32(0); 2478 rxdesc->addr = cpu_to_le32(0xBADF00D0); 2479 dev_kfree_skb(mdp->rx_skbuff[i]); 2480 mdp->rx_skbuff[i] = NULL; 2481 } 2482 for (i = 0; i < mdp->num_tx_ring; i++) { 2483 dev_kfree_skb(mdp->tx_skbuff[i]); 2484 mdp->tx_skbuff[i] = NULL; 2485 } 2486 2487 /* device init */ 2488 sh_eth_dev_init(ndev); 2489 2490 netif_start_queue(ndev); 2491 } 2492 2493 /* Packet transmit function */ 2494 static netdev_tx_t sh_eth_start_xmit(struct sk_buff *skb, 2495 struct net_device *ndev) 2496 { 2497 struct sh_eth_private *mdp = netdev_priv(ndev); 2498 struct sh_eth_txdesc *txdesc; 2499 dma_addr_t dma_addr; 2500 u32 entry; 2501 unsigned long flags; 2502 2503 spin_lock_irqsave(&mdp->lock, flags); 2504 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2505 if (!sh_eth_tx_free(ndev, true)) { 2506 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); 2507 netif_stop_queue(ndev); 2508 spin_unlock_irqrestore(&mdp->lock, flags); 2509 return NETDEV_TX_BUSY; 2510 } 2511 } 2512 spin_unlock_irqrestore(&mdp->lock, flags); 2513 2514 if (skb_put_padto(skb, ETH_ZLEN)) 2515 return NETDEV_TX_OK; 2516 2517 entry = mdp->cur_tx % mdp->num_tx_ring; 2518 mdp->tx_skbuff[entry] = skb; 2519 txdesc = &mdp->tx_ring[entry]; 2520 /* soft swap. */ 2521 if (!mdp->cd->hw_swap) 2522 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); 2523 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len, 2524 DMA_TO_DEVICE); 2525 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 2526 kfree_skb(skb); 2527 return NETDEV_TX_OK; 2528 } 2529 txdesc->addr = cpu_to_le32(dma_addr); 2530 txdesc->len = cpu_to_le32(skb->len << 16); 2531 2532 dma_wmb(); /* TACT bit must be set after all the above writes */ 2533 if (entry >= mdp->num_tx_ring - 1) 2534 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); 2535 else 2536 txdesc->status |= cpu_to_le32(TD_TACT); 2537 2538 wmb(); /* cur_tx must be incremented after TACT bit was set */ 2539 mdp->cur_tx++; 2540 2541 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns)) 2542 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 2543 2544 return NETDEV_TX_OK; 2545 } 2546 2547 /* The statistics registers have write-clear behaviour, which means we 2548 * will lose any increment between the read and write. We mitigate 2549 * this by only clearing when we read a non-zero value, so we will 2550 * never falsely report a total of zero. 2551 */ 2552 static void 2553 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) 2554 { 2555 u32 delta = sh_eth_read(ndev, reg); 2556 2557 if (delta) { 2558 *stat += delta; 2559 sh_eth_write(ndev, 0, reg); 2560 } 2561 } 2562 2563 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2564 { 2565 struct sh_eth_private *mdp = netdev_priv(ndev); 2566 2567 if (mdp->cd->no_tx_cntrs) 2568 return &ndev->stats; 2569 2570 if (!mdp->is_opened) 2571 return &ndev->stats; 2572 2573 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); 2574 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); 2575 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); 2576 2577 if (mdp->cd->cexcr) { 2578 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2579 CERCR); 2580 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2581 CEECR); 2582 } else { 2583 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2584 CNDCR); 2585 } 2586 2587 return &ndev->stats; 2588 } 2589 2590 /* device close function */ 2591 static int sh_eth_close(struct net_device *ndev) 2592 { 2593 struct sh_eth_private *mdp = netdev_priv(ndev); 2594 2595 netif_stop_queue(ndev); 2596 2597 /* Serialise with the interrupt handler and NAPI, then disable 2598 * interrupts. We have to clear the irq_enabled flag first to 2599 * ensure that interrupts won't be re-enabled. 2600 */ 2601 mdp->irq_enabled = false; 2602 synchronize_irq(ndev->irq); 2603 napi_disable(&mdp->napi); 2604 sh_eth_write(ndev, 0x0000, EESIPR); 2605 2606 sh_eth_dev_exit(ndev); 2607 2608 /* PHY Disconnect */ 2609 if (ndev->phydev) { 2610 phy_stop(ndev->phydev); 2611 phy_disconnect(ndev->phydev); 2612 } 2613 2614 free_irq(ndev->irq, ndev); 2615 2616 /* Free all the skbuffs in the Rx queue and the DMA buffer. */ 2617 sh_eth_ring_free(ndev); 2618 2619 mdp->is_opened = 0; 2620 2621 pm_runtime_put(&mdp->pdev->dev); 2622 2623 return 0; 2624 } 2625 2626 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu) 2627 { 2628 if (netif_running(ndev)) 2629 return -EBUSY; 2630 2631 WRITE_ONCE(ndev->mtu, new_mtu); 2632 netdev_update_features(ndev); 2633 2634 return 0; 2635 } 2636 2637 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2638 static u32 sh_eth_tsu_get_post_mask(int entry) 2639 { 2640 return 0x0f << (28 - ((entry % 8) * 4)); 2641 } 2642 2643 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2644 { 2645 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2646 } 2647 2648 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2649 int entry) 2650 { 2651 struct sh_eth_private *mdp = netdev_priv(ndev); 2652 int reg = TSU_POST1 + entry / 8; 2653 u32 tmp; 2654 2655 tmp = sh_eth_tsu_read(mdp, reg); 2656 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg); 2657 } 2658 2659 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2660 int entry) 2661 { 2662 struct sh_eth_private *mdp = netdev_priv(ndev); 2663 int reg = TSU_POST1 + entry / 8; 2664 u32 post_mask, ref_mask, tmp; 2665 2666 post_mask = sh_eth_tsu_get_post_mask(entry); 2667 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2668 2669 tmp = sh_eth_tsu_read(mdp, reg); 2670 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg); 2671 2672 /* If other port enables, the function returns "true" */ 2673 return tmp & ref_mask; 2674 } 2675 2676 static int sh_eth_tsu_busy(struct net_device *ndev) 2677 { 2678 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2679 struct sh_eth_private *mdp = netdev_priv(ndev); 2680 2681 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2682 udelay(10); 2683 timeout--; 2684 if (timeout <= 0) { 2685 netdev_err(ndev, "%s: timeout\n", __func__); 2686 return -ETIMEDOUT; 2687 } 2688 } 2689 2690 return 0; 2691 } 2692 2693 static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset, 2694 const u8 *addr) 2695 { 2696 struct sh_eth_private *mdp = netdev_priv(ndev); 2697 u32 val; 2698 2699 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2700 iowrite32(val, mdp->tsu_addr + offset); 2701 if (sh_eth_tsu_busy(ndev) < 0) 2702 return -EBUSY; 2703 2704 val = addr[4] << 8 | addr[5]; 2705 iowrite32(val, mdp->tsu_addr + offset + 4); 2706 if (sh_eth_tsu_busy(ndev) < 0) 2707 return -EBUSY; 2708 2709 return 0; 2710 } 2711 2712 static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr) 2713 { 2714 struct sh_eth_private *mdp = netdev_priv(ndev); 2715 u32 val; 2716 2717 val = ioread32(mdp->tsu_addr + offset); 2718 addr[0] = (val >> 24) & 0xff; 2719 addr[1] = (val >> 16) & 0xff; 2720 addr[2] = (val >> 8) & 0xff; 2721 addr[3] = val & 0xff; 2722 val = ioread32(mdp->tsu_addr + offset + 4); 2723 addr[4] = (val >> 8) & 0xff; 2724 addr[5] = val & 0xff; 2725 } 2726 2727 2728 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2729 { 2730 struct sh_eth_private *mdp = netdev_priv(ndev); 2731 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2732 int i; 2733 u8 c_addr[ETH_ALEN]; 2734 2735 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2736 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr); 2737 if (ether_addr_equal(addr, c_addr)) 2738 return i; 2739 } 2740 2741 return -ENOENT; 2742 } 2743 2744 static int sh_eth_tsu_find_empty(struct net_device *ndev) 2745 { 2746 u8 blank[ETH_ALEN]; 2747 int entry; 2748 2749 memset(blank, 0, sizeof(blank)); 2750 entry = sh_eth_tsu_find_entry(ndev, blank); 2751 return (entry < 0) ? -ENOMEM : entry; 2752 } 2753 2754 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2755 int entry) 2756 { 2757 struct sh_eth_private *mdp = netdev_priv(ndev); 2758 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2759 int ret; 2760 u8 blank[ETH_ALEN]; 2761 2762 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2763 ~(1 << (31 - entry)), TSU_TEN); 2764 2765 memset(blank, 0, sizeof(blank)); 2766 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2767 if (ret < 0) 2768 return ret; 2769 return 0; 2770 } 2771 2772 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2773 { 2774 struct sh_eth_private *mdp = netdev_priv(ndev); 2775 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2776 int i, ret; 2777 2778 if (!mdp->cd->tsu) 2779 return 0; 2780 2781 i = sh_eth_tsu_find_entry(ndev, addr); 2782 if (i < 0) { 2783 /* No entry found, create one */ 2784 i = sh_eth_tsu_find_empty(ndev); 2785 if (i < 0) 2786 return -ENOMEM; 2787 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2788 if (ret < 0) 2789 return ret; 2790 2791 /* Enable the entry */ 2792 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2793 (1 << (31 - i)), TSU_TEN); 2794 } 2795 2796 /* Entry found or created, enable POST */ 2797 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2798 2799 return 0; 2800 } 2801 2802 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2803 { 2804 struct sh_eth_private *mdp = netdev_priv(ndev); 2805 int i, ret; 2806 2807 if (!mdp->cd->tsu) 2808 return 0; 2809 2810 i = sh_eth_tsu_find_entry(ndev, addr); 2811 if (i) { 2812 /* Entry found */ 2813 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2814 goto done; 2815 2816 /* Disable the entry if both ports was disabled */ 2817 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2818 if (ret < 0) 2819 return ret; 2820 } 2821 done: 2822 return 0; 2823 } 2824 2825 static int sh_eth_tsu_purge_all(struct net_device *ndev) 2826 { 2827 struct sh_eth_private *mdp = netdev_priv(ndev); 2828 int i, ret; 2829 2830 if (!mdp->cd->tsu) 2831 return 0; 2832 2833 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2834 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2835 continue; 2836 2837 /* Disable the entry if both ports was disabled */ 2838 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2839 if (ret < 0) 2840 return ret; 2841 } 2842 2843 return 0; 2844 } 2845 2846 static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2847 { 2848 struct sh_eth_private *mdp = netdev_priv(ndev); 2849 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2850 u8 addr[ETH_ALEN]; 2851 int i; 2852 2853 if (!mdp->cd->tsu) 2854 return; 2855 2856 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2857 sh_eth_tsu_read_entry(ndev, reg_offset, addr); 2858 if (is_multicast_ether_addr(addr)) 2859 sh_eth_tsu_del_entry(ndev, addr); 2860 } 2861 } 2862 2863 /* Update promiscuous flag and multicast filter */ 2864 static void sh_eth_set_rx_mode(struct net_device *ndev) 2865 { 2866 struct sh_eth_private *mdp = netdev_priv(ndev); 2867 u32 ecmr_bits; 2868 int mcast_all = 0; 2869 unsigned long flags; 2870 2871 spin_lock_irqsave(&mdp->lock, flags); 2872 /* Initial condition is MCT = 1, PRM = 0. 2873 * Depending on ndev->flags, set PRM or clear MCT 2874 */ 2875 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; 2876 if (mdp->cd->tsu) 2877 ecmr_bits |= ECMR_MCT; 2878 2879 if (!(ndev->flags & IFF_MULTICAST)) { 2880 sh_eth_tsu_purge_mcast(ndev); 2881 mcast_all = 1; 2882 } 2883 if (ndev->flags & IFF_ALLMULTI) { 2884 sh_eth_tsu_purge_mcast(ndev); 2885 ecmr_bits &= ~ECMR_MCT; 2886 mcast_all = 1; 2887 } 2888 2889 if (ndev->flags & IFF_PROMISC) { 2890 sh_eth_tsu_purge_all(ndev); 2891 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2892 } else if (mdp->cd->tsu) { 2893 struct netdev_hw_addr *ha; 2894 netdev_for_each_mc_addr(ha, ndev) { 2895 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2896 continue; 2897 2898 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2899 if (!mcast_all) { 2900 sh_eth_tsu_purge_mcast(ndev); 2901 ecmr_bits &= ~ECMR_MCT; 2902 mcast_all = 1; 2903 } 2904 } 2905 } 2906 } 2907 2908 /* update the ethernet mode */ 2909 sh_eth_write(ndev, ecmr_bits, ECMR); 2910 2911 spin_unlock_irqrestore(&mdp->lock, flags); 2912 } 2913 2914 static void sh_eth_set_rx_csum(struct net_device *ndev, bool enable) 2915 { 2916 struct sh_eth_private *mdp = netdev_priv(ndev); 2917 unsigned long flags; 2918 2919 spin_lock_irqsave(&mdp->lock, flags); 2920 2921 /* Disable TX and RX */ 2922 sh_eth_rcv_snd_disable(ndev); 2923 2924 /* Modify RX Checksum setting */ 2925 sh_eth_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2926 2927 /* Enable TX and RX */ 2928 sh_eth_rcv_snd_enable(ndev); 2929 2930 spin_unlock_irqrestore(&mdp->lock, flags); 2931 } 2932 2933 static int sh_eth_set_features(struct net_device *ndev, 2934 netdev_features_t features) 2935 { 2936 netdev_features_t changed = ndev->features ^ features; 2937 struct sh_eth_private *mdp = netdev_priv(ndev); 2938 2939 if (changed & NETIF_F_RXCSUM && mdp->cd->rx_csum) 2940 sh_eth_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2941 2942 ndev->features = features; 2943 2944 return 0; 2945 } 2946 2947 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2948 { 2949 if (!mdp->port) 2950 return TSU_VTAG0; 2951 else 2952 return TSU_VTAG1; 2953 } 2954 2955 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2956 __be16 proto, u16 vid) 2957 { 2958 struct sh_eth_private *mdp = netdev_priv(ndev); 2959 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2960 2961 if (unlikely(!mdp->cd->tsu)) 2962 return -EPERM; 2963 2964 /* No filtering if vid = 0 */ 2965 if (!vid) 2966 return 0; 2967 2968 mdp->vlan_num_ids++; 2969 2970 /* The controller has one VLAN tag HW filter. So, if the filter is 2971 * already enabled, the driver disables it and the filte 2972 */ 2973 if (mdp->vlan_num_ids > 1) { 2974 /* disable VLAN filter */ 2975 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2976 return 0; 2977 } 2978 2979 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2980 vtag_reg_index); 2981 2982 return 0; 2983 } 2984 2985 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2986 __be16 proto, u16 vid) 2987 { 2988 struct sh_eth_private *mdp = netdev_priv(ndev); 2989 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2990 2991 if (unlikely(!mdp->cd->tsu)) 2992 return -EPERM; 2993 2994 /* No filtering if vid = 0 */ 2995 if (!vid) 2996 return 0; 2997 2998 mdp->vlan_num_ids--; 2999 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 3000 3001 return 0; 3002 } 3003 3004 /* SuperH's TSU register init function */ 3005 static void sh_eth_tsu_init(struct sh_eth_private *mdp) 3006 { 3007 if (!mdp->cd->dual_port) { 3008 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 3009 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, 3010 TSU_FWSLC); /* Enable POST registers */ 3011 return; 3012 } 3013 3014 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 3015 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 3016 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 3017 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 3018 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 3019 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 3020 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 3021 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 3022 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 3023 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 3024 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 3025 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 3026 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 3027 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 3028 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 3029 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 3030 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 3031 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 3032 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 3033 } 3034 3035 /* MDIO bus release function */ 3036 static int sh_mdio_release(struct sh_eth_private *mdp) 3037 { 3038 /* unregister mdio bus */ 3039 mdiobus_unregister(mdp->mii_bus); 3040 3041 /* free bitbang info */ 3042 free_mdio_bitbang(mdp->mii_bus); 3043 3044 return 0; 3045 } 3046 3047 static int sh_mdiobb_read_c22(struct mii_bus *bus, int phy, int reg) 3048 { 3049 int res; 3050 3051 pm_runtime_get_sync(bus->parent); 3052 res = mdiobb_read_c22(bus, phy, reg); 3053 pm_runtime_put(bus->parent); 3054 3055 return res; 3056 } 3057 3058 static int sh_mdiobb_write_c22(struct mii_bus *bus, int phy, int reg, u16 val) 3059 { 3060 int res; 3061 3062 pm_runtime_get_sync(bus->parent); 3063 res = mdiobb_write_c22(bus, phy, reg, val); 3064 pm_runtime_put(bus->parent); 3065 3066 return res; 3067 } 3068 3069 static int sh_mdiobb_read_c45(struct mii_bus *bus, int phy, int devad, int reg) 3070 { 3071 int res; 3072 3073 pm_runtime_get_sync(bus->parent); 3074 res = mdiobb_read_c45(bus, phy, devad, reg); 3075 pm_runtime_put(bus->parent); 3076 3077 return res; 3078 } 3079 3080 static int sh_mdiobb_write_c45(struct mii_bus *bus, int phy, int devad, 3081 int reg, u16 val) 3082 { 3083 int res; 3084 3085 pm_runtime_get_sync(bus->parent); 3086 res = mdiobb_write_c45(bus, phy, devad, reg, val); 3087 pm_runtime_put(bus->parent); 3088 3089 return res; 3090 } 3091 3092 /* MDIO bus init function */ 3093 static int sh_mdio_init(struct sh_eth_private *mdp, 3094 struct sh_eth_plat_data *pd) 3095 { 3096 int ret; 3097 struct bb_info *bitbang; 3098 struct platform_device *pdev = mdp->pdev; 3099 struct device *dev = &mdp->pdev->dev; 3100 struct phy_device *phydev; 3101 struct device_node *pn; 3102 3103 /* create bit control struct for PHY */ 3104 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); 3105 if (!bitbang) 3106 return -ENOMEM; 3107 3108 /* bitbang init */ 3109 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 3110 bitbang->set_gate = pd->set_mdio_gate; 3111 bitbang->ctrl.ops = &bb_ops; 3112 3113 /* MII controller setting */ 3114 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 3115 if (!mdp->mii_bus) 3116 return -ENOMEM; 3117 3118 /* Wrap accessors with Runtime PM-aware ops */ 3119 mdp->mii_bus->read = sh_mdiobb_read_c22; 3120 mdp->mii_bus->write = sh_mdiobb_write_c22; 3121 mdp->mii_bus->read_c45 = sh_mdiobb_read_c45; 3122 mdp->mii_bus->write_c45 = sh_mdiobb_write_c45; 3123 3124 /* Hook up MII support for ethtool */ 3125 mdp->mii_bus->name = "sh_mii"; 3126 mdp->mii_bus->parent = dev; 3127 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 3128 pdev->name, pdev->id); 3129 3130 /* register MDIO bus */ 3131 if (pd->phy_irq > 0) 3132 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 3133 3134 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); 3135 if (ret) 3136 goto out_free_bus; 3137 3138 pn = of_parse_phandle(dev->of_node, "phy-handle", 0); 3139 phydev = of_phy_find_device(pn); 3140 if (phydev) { 3141 phydev->mac_managed_pm = true; 3142 put_device(&phydev->mdio.dev); 3143 } 3144 of_node_put(pn); 3145 3146 return 0; 3147 3148 out_free_bus: 3149 free_mdio_bitbang(mdp->mii_bus); 3150 return ret; 3151 } 3152 3153 static const u16 *sh_eth_get_register_offset(int register_type) 3154 { 3155 const u16 *reg_offset = NULL; 3156 3157 switch (register_type) { 3158 case SH_ETH_REG_GIGABIT: 3159 reg_offset = sh_eth_offset_gigabit; 3160 break; 3161 case SH_ETH_REG_FAST_RCAR: 3162 reg_offset = sh_eth_offset_fast_rcar; 3163 break; 3164 case SH_ETH_REG_FAST_SH4: 3165 reg_offset = sh_eth_offset_fast_sh4; 3166 break; 3167 case SH_ETH_REG_FAST_SH3_SH2: 3168 reg_offset = sh_eth_offset_fast_sh3_sh2; 3169 break; 3170 } 3171 3172 return reg_offset; 3173 } 3174 3175 static const struct net_device_ops sh_eth_netdev_ops = { 3176 .ndo_open = sh_eth_open, 3177 .ndo_stop = sh_eth_close, 3178 .ndo_start_xmit = sh_eth_start_xmit, 3179 .ndo_get_stats = sh_eth_get_stats, 3180 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3181 .ndo_tx_timeout = sh_eth_tx_timeout, 3182 .ndo_eth_ioctl = phy_do_ioctl_running, 3183 .ndo_change_mtu = sh_eth_change_mtu, 3184 .ndo_validate_addr = eth_validate_addr, 3185 .ndo_set_mac_address = eth_mac_addr, 3186 .ndo_set_features = sh_eth_set_features, 3187 }; 3188 3189 static const struct net_device_ops sh_eth_netdev_ops_tsu = { 3190 .ndo_open = sh_eth_open, 3191 .ndo_stop = sh_eth_close, 3192 .ndo_start_xmit = sh_eth_start_xmit, 3193 .ndo_get_stats = sh_eth_get_stats, 3194 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3195 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 3196 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 3197 .ndo_tx_timeout = sh_eth_tx_timeout, 3198 .ndo_eth_ioctl = phy_do_ioctl_running, 3199 .ndo_change_mtu = sh_eth_change_mtu, 3200 .ndo_validate_addr = eth_validate_addr, 3201 .ndo_set_mac_address = eth_mac_addr, 3202 .ndo_set_features = sh_eth_set_features, 3203 }; 3204 3205 #ifdef CONFIG_OF 3206 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3207 { 3208 struct device_node *np = dev->of_node; 3209 struct sh_eth_plat_data *pdata; 3210 phy_interface_t interface; 3211 int ret; 3212 3213 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3214 if (!pdata) 3215 return NULL; 3216 3217 ret = of_get_phy_mode(np, &interface); 3218 if (ret) 3219 return NULL; 3220 pdata->phy_interface = interface; 3221 3222 of_get_mac_address(np, pdata->mac_addr); 3223 3224 pdata->no_ether_link = 3225 of_property_read_bool(np, "renesas,no-ether-link"); 3226 pdata->ether_link_active_low = 3227 of_property_read_bool(np, "renesas,ether-link-active-low"); 3228 3229 return pdata; 3230 } 3231 3232 static const struct of_device_id sh_eth_match_table[] = { 3233 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 3234 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data }, 3235 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data }, 3236 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data }, 3237 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data }, 3238 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data }, 3239 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data }, 3240 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data }, 3241 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data }, 3242 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data }, 3243 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 3244 { .compatible = "renesas,ether-r7s9210", .data = &r7s9210_data }, 3245 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data }, 3246 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data }, 3247 { } 3248 }; 3249 MODULE_DEVICE_TABLE(of, sh_eth_match_table); 3250 #else 3251 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3252 { 3253 return NULL; 3254 } 3255 #endif 3256 3257 static int sh_eth_drv_probe(struct platform_device *pdev) 3258 { 3259 struct resource *res; 3260 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 3261 const struct platform_device_id *id = platform_get_device_id(pdev); 3262 struct sh_eth_private *mdp; 3263 struct net_device *ndev; 3264 int ret; 3265 3266 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 3267 if (!ndev) 3268 return -ENOMEM; 3269 3270 pm_runtime_enable(&pdev->dev); 3271 pm_runtime_get_sync(&pdev->dev); 3272 3273 ret = platform_get_irq(pdev, 0); 3274 if (ret < 0) 3275 goto out_release; 3276 ndev->irq = ret; 3277 3278 SET_NETDEV_DEV(ndev, &pdev->dev); 3279 3280 mdp = netdev_priv(ndev); 3281 mdp->num_tx_ring = TX_RING_SIZE; 3282 mdp->num_rx_ring = RX_RING_SIZE; 3283 mdp->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 3284 if (IS_ERR(mdp->addr)) { 3285 ret = PTR_ERR(mdp->addr); 3286 goto out_release; 3287 } 3288 3289 ndev->base_addr = res->start; 3290 3291 spin_lock_init(&mdp->lock); 3292 mdp->pdev = pdev; 3293 3294 if (pdev->dev.of_node) 3295 pd = sh_eth_parse_dt(&pdev->dev); 3296 if (!pd) { 3297 dev_err(&pdev->dev, "no platform data\n"); 3298 ret = -EINVAL; 3299 goto out_release; 3300 } 3301 3302 /* get PHY ID */ 3303 mdp->phy_id = pd->phy; 3304 mdp->phy_interface = pd->phy_interface; 3305 mdp->no_ether_link = pd->no_ether_link; 3306 mdp->ether_link_active_low = pd->ether_link_active_low; 3307 3308 /* set cpu data */ 3309 if (id) 3310 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 3311 else 3312 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev); 3313 3314 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 3315 if (!mdp->reg_offset) { 3316 dev_err(&pdev->dev, "Unknown register type (%d)\n", 3317 mdp->cd->register_type); 3318 ret = -EINVAL; 3319 goto out_release; 3320 } 3321 sh_eth_set_default_cpu_data(mdp->cd); 3322 3323 /* User's manual states max MTU should be 2048 but due to the 3324 * alignment calculations in sh_eth_ring_init() the practical 3325 * MTU is a bit less. Maybe this can be optimized some more. 3326 */ 3327 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 3328 ndev->min_mtu = ETH_MIN_MTU; 3329 3330 if (mdp->cd->rx_csum) { 3331 ndev->features = NETIF_F_RXCSUM; 3332 ndev->hw_features = NETIF_F_RXCSUM; 3333 } 3334 3335 /* set function */ 3336 if (mdp->cd->tsu) 3337 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 3338 else 3339 ndev->netdev_ops = &sh_eth_netdev_ops; 3340 ndev->ethtool_ops = &sh_eth_ethtool_ops; 3341 ndev->watchdog_timeo = TX_TIMEOUT; 3342 3343 /* debug message level */ 3344 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 3345 3346 /* read and set MAC address */ 3347 read_mac_address(ndev, pd->mac_addr); 3348 if (!is_valid_ether_addr(ndev->dev_addr)) { 3349 dev_warn(&pdev->dev, 3350 "no valid MAC address supplied, using a random one.\n"); 3351 eth_hw_addr_random(ndev); 3352 } 3353 3354 if (mdp->cd->tsu) { 3355 int port = pdev->id < 0 ? 0 : pdev->id % 2; 3356 struct resource *rtsu; 3357 3358 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3359 if (!rtsu) { 3360 dev_err(&pdev->dev, "no TSU resource\n"); 3361 ret = -ENODEV; 3362 goto out_release; 3363 } 3364 /* We can only request the TSU region for the first port 3365 * of the two sharing this TSU for the probe to succeed... 3366 */ 3367 if (port == 0 && 3368 !devm_request_mem_region(&pdev->dev, rtsu->start, 3369 resource_size(rtsu), 3370 dev_name(&pdev->dev))) { 3371 dev_err(&pdev->dev, "can't request TSU resource.\n"); 3372 ret = -EBUSY; 3373 goto out_release; 3374 } 3375 /* ioremap the TSU registers */ 3376 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start, 3377 resource_size(rtsu)); 3378 if (!mdp->tsu_addr) { 3379 dev_err(&pdev->dev, "TSU region ioremap() failed.\n"); 3380 ret = -ENOMEM; 3381 goto out_release; 3382 } 3383 mdp->port = port; 3384 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 3385 3386 /* Need to init only the first port of the two sharing a TSU */ 3387 if (port == 0) { 3388 if (mdp->cd->chip_reset) 3389 mdp->cd->chip_reset(ndev); 3390 3391 /* TSU init (Init only)*/ 3392 sh_eth_tsu_init(mdp); 3393 } 3394 } 3395 3396 if (mdp->cd->rmiimode) 3397 sh_eth_write(ndev, 0x1, RMIIMODE); 3398 3399 /* MDIO bus init */ 3400 ret = sh_mdio_init(mdp, pd); 3401 if (ret) { 3402 dev_err_probe(&pdev->dev, ret, "MDIO init failed\n"); 3403 goto out_release; 3404 } 3405 3406 netif_napi_add(ndev, &mdp->napi, sh_eth_poll); 3407 3408 /* network device register */ 3409 ret = register_netdev(ndev); 3410 if (ret) 3411 goto out_napi_del; 3412 3413 if (mdp->cd->magic) 3414 device_set_wakeup_capable(&pdev->dev, 1); 3415 3416 /* print device information */ 3417 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", 3418 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3419 3420 pm_runtime_put(&pdev->dev); 3421 platform_set_drvdata(pdev, ndev); 3422 3423 return ret; 3424 3425 out_napi_del: 3426 netif_napi_del(&mdp->napi); 3427 sh_mdio_release(mdp); 3428 3429 out_release: 3430 /* net_dev free */ 3431 free_netdev(ndev); 3432 3433 pm_runtime_put(&pdev->dev); 3434 pm_runtime_disable(&pdev->dev); 3435 return ret; 3436 } 3437 3438 static void sh_eth_drv_remove(struct platform_device *pdev) 3439 { 3440 struct net_device *ndev = platform_get_drvdata(pdev); 3441 struct sh_eth_private *mdp = netdev_priv(ndev); 3442 3443 unregister_netdev(ndev); 3444 netif_napi_del(&mdp->napi); 3445 sh_mdio_release(mdp); 3446 pm_runtime_disable(&pdev->dev); 3447 free_netdev(ndev); 3448 } 3449 3450 static int sh_eth_wol_setup(struct net_device *ndev) 3451 { 3452 struct sh_eth_private *mdp = netdev_priv(ndev); 3453 3454 /* Only allow ECI interrupts */ 3455 synchronize_irq(ndev->irq); 3456 napi_disable(&mdp->napi); 3457 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); 3458 3459 /* Enable MagicPacket */ 3460 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3461 3462 return enable_irq_wake(ndev->irq); 3463 } 3464 3465 static int sh_eth_wol_restore(struct net_device *ndev) 3466 { 3467 struct sh_eth_private *mdp = netdev_priv(ndev); 3468 int ret; 3469 3470 napi_enable(&mdp->napi); 3471 3472 /* Disable MagicPacket */ 3473 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0); 3474 3475 /* The device needs to be reset to restore MagicPacket logic 3476 * for next wakeup. If we close and open the device it will 3477 * both be reset and all registers restored. This is what 3478 * happens during suspend and resume without WoL enabled. 3479 */ 3480 sh_eth_close(ndev); 3481 ret = sh_eth_open(ndev); 3482 if (ret < 0) 3483 return ret; 3484 3485 return disable_irq_wake(ndev->irq); 3486 } 3487 3488 static int sh_eth_suspend(struct device *dev) 3489 { 3490 struct net_device *ndev = dev_get_drvdata(dev); 3491 struct sh_eth_private *mdp = netdev_priv(ndev); 3492 int ret; 3493 3494 if (!netif_running(ndev)) 3495 return 0; 3496 3497 netif_device_detach(ndev); 3498 3499 rtnl_lock(); 3500 if (mdp->wol_enabled) 3501 ret = sh_eth_wol_setup(ndev); 3502 else 3503 ret = sh_eth_close(ndev); 3504 rtnl_unlock(); 3505 3506 return ret; 3507 } 3508 3509 static int sh_eth_resume(struct device *dev) 3510 { 3511 struct net_device *ndev = dev_get_drvdata(dev); 3512 struct sh_eth_private *mdp = netdev_priv(ndev); 3513 int ret; 3514 3515 if (!netif_running(ndev)) 3516 return 0; 3517 3518 rtnl_lock(); 3519 if (mdp->wol_enabled) 3520 ret = sh_eth_wol_restore(ndev); 3521 else 3522 ret = sh_eth_open(ndev); 3523 rtnl_unlock(); 3524 3525 if (ret < 0) 3526 return ret; 3527 3528 netif_device_attach(ndev); 3529 3530 return ret; 3531 } 3532 3533 static DEFINE_SIMPLE_DEV_PM_OPS(sh_eth_dev_pm_ops, sh_eth_suspend, sh_eth_resume); 3534 3535 static const struct platform_device_id sh_eth_id_table[] = { 3536 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 3537 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 3538 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 3539 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 3540 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 3541 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 3542 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 3543 { } 3544 }; 3545 MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 3546 3547 static struct platform_driver sh_eth_driver = { 3548 .probe = sh_eth_drv_probe, 3549 .remove = sh_eth_drv_remove, 3550 .id_table = sh_eth_id_table, 3551 .driver = { 3552 .name = CARDNAME, 3553 .pm = pm_sleep_ptr(&sh_eth_dev_pm_ops), 3554 .of_match_table = of_match_ptr(sh_eth_match_table), 3555 }, 3556 }; 3557 3558 module_platform_driver(sh_eth_driver); 3559 3560 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3561 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3562 MODULE_LICENSE("GPL v2"); 3563