1 /* SuperH Ethernet device driver 2 * 3 * Copyright (C) 2014 Renesas Electronics Corporation 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2014 Renesas Solutions Corp. 6 * Copyright (C) 2013-2014 Cogent Embedded, Inc. 7 * Copyright (C) 2014 Codethink Limited 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 */ 21 22 #include <linux/module.h> 23 #include <linux/kernel.h> 24 #include <linux/spinlock.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/etherdevice.h> 28 #include <linux/delay.h> 29 #include <linux/platform_device.h> 30 #include <linux/mdio-bitbang.h> 31 #include <linux/netdevice.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_net.h> 36 #include <linux/phy.h> 37 #include <linux/cache.h> 38 #include <linux/io.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/slab.h> 41 #include <linux/ethtool.h> 42 #include <linux/if_vlan.h> 43 #include <linux/clk.h> 44 #include <linux/sh_eth.h> 45 #include <linux/of_mdio.h> 46 47 #include "sh_eth.h" 48 49 #define SH_ETH_DEF_MSG_ENABLE \ 50 (NETIF_MSG_LINK | \ 51 NETIF_MSG_TIMER | \ 52 NETIF_MSG_RX_ERR| \ 53 NETIF_MSG_TX_ERR) 54 55 #define SH_ETH_OFFSET_DEFAULTS \ 56 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID 57 58 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 59 SH_ETH_OFFSET_DEFAULTS, 60 61 [EDSR] = 0x0000, 62 [EDMR] = 0x0400, 63 [EDTRR] = 0x0408, 64 [EDRRR] = 0x0410, 65 [EESR] = 0x0428, 66 [EESIPR] = 0x0430, 67 [TDLAR] = 0x0010, 68 [TDFAR] = 0x0014, 69 [TDFXR] = 0x0018, 70 [TDFFR] = 0x001c, 71 [RDLAR] = 0x0030, 72 [RDFAR] = 0x0034, 73 [RDFXR] = 0x0038, 74 [RDFFR] = 0x003c, 75 [TRSCER] = 0x0438, 76 [RMFCR] = 0x0440, 77 [TFTR] = 0x0448, 78 [FDR] = 0x0450, 79 [RMCR] = 0x0458, 80 [RPADIR] = 0x0460, 81 [FCFTR] = 0x0468, 82 [CSMR] = 0x04E4, 83 84 [ECMR] = 0x0500, 85 [ECSR] = 0x0510, 86 [ECSIPR] = 0x0518, 87 [PIR] = 0x0520, 88 [PSR] = 0x0528, 89 [PIPR] = 0x052c, 90 [RFLR] = 0x0508, 91 [APR] = 0x0554, 92 [MPR] = 0x0558, 93 [PFTCR] = 0x055c, 94 [PFRCR] = 0x0560, 95 [TPAUSER] = 0x0564, 96 [GECMR] = 0x05b0, 97 [BCULR] = 0x05b4, 98 [MAHR] = 0x05c0, 99 [MALR] = 0x05c8, 100 [TROCR] = 0x0700, 101 [CDCR] = 0x0708, 102 [LCCR] = 0x0710, 103 [CEFCR] = 0x0740, 104 [FRECR] = 0x0748, 105 [TSFRCR] = 0x0750, 106 [TLFRCR] = 0x0758, 107 [RFCR] = 0x0760, 108 [CERCR] = 0x0768, 109 [CEECR] = 0x0770, 110 [MAFCR] = 0x0778, 111 [RMII_MII] = 0x0790, 112 113 [ARSTR] = 0x0000, 114 [TSU_CTRST] = 0x0004, 115 [TSU_FWEN0] = 0x0010, 116 [TSU_FWEN1] = 0x0014, 117 [TSU_FCM] = 0x0018, 118 [TSU_BSYSL0] = 0x0020, 119 [TSU_BSYSL1] = 0x0024, 120 [TSU_PRISL0] = 0x0028, 121 [TSU_PRISL1] = 0x002c, 122 [TSU_FWSL0] = 0x0030, 123 [TSU_FWSL1] = 0x0034, 124 [TSU_FWSLC] = 0x0038, 125 [TSU_QTAG0] = 0x0040, 126 [TSU_QTAG1] = 0x0044, 127 [TSU_FWSR] = 0x0050, 128 [TSU_FWINMK] = 0x0054, 129 [TSU_ADQT0] = 0x0048, 130 [TSU_ADQT1] = 0x004c, 131 [TSU_VTAG0] = 0x0058, 132 [TSU_VTAG1] = 0x005c, 133 [TSU_ADSBSY] = 0x0060, 134 [TSU_TEN] = 0x0064, 135 [TSU_POST1] = 0x0070, 136 [TSU_POST2] = 0x0074, 137 [TSU_POST3] = 0x0078, 138 [TSU_POST4] = 0x007c, 139 [TSU_ADRH0] = 0x0100, 140 141 [TXNLCR0] = 0x0080, 142 [TXALCR0] = 0x0084, 143 [RXNLCR0] = 0x0088, 144 [RXALCR0] = 0x008c, 145 [FWNLCR0] = 0x0090, 146 [FWALCR0] = 0x0094, 147 [TXNLCR1] = 0x00a0, 148 [TXALCR1] = 0x00a0, 149 [RXNLCR1] = 0x00a8, 150 [RXALCR1] = 0x00ac, 151 [FWNLCR1] = 0x00b0, 152 [FWALCR1] = 0x00b4, 153 }; 154 155 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { 156 SH_ETH_OFFSET_DEFAULTS, 157 158 [EDSR] = 0x0000, 159 [EDMR] = 0x0400, 160 [EDTRR] = 0x0408, 161 [EDRRR] = 0x0410, 162 [EESR] = 0x0428, 163 [EESIPR] = 0x0430, 164 [TDLAR] = 0x0010, 165 [TDFAR] = 0x0014, 166 [TDFXR] = 0x0018, 167 [TDFFR] = 0x001c, 168 [RDLAR] = 0x0030, 169 [RDFAR] = 0x0034, 170 [RDFXR] = 0x0038, 171 [RDFFR] = 0x003c, 172 [TRSCER] = 0x0438, 173 [RMFCR] = 0x0440, 174 [TFTR] = 0x0448, 175 [FDR] = 0x0450, 176 [RMCR] = 0x0458, 177 [RPADIR] = 0x0460, 178 [FCFTR] = 0x0468, 179 [CSMR] = 0x04E4, 180 181 [ECMR] = 0x0500, 182 [RFLR] = 0x0508, 183 [ECSR] = 0x0510, 184 [ECSIPR] = 0x0518, 185 [PIR] = 0x0520, 186 [APR] = 0x0554, 187 [MPR] = 0x0558, 188 [PFTCR] = 0x055c, 189 [PFRCR] = 0x0560, 190 [TPAUSER] = 0x0564, 191 [MAHR] = 0x05c0, 192 [MALR] = 0x05c8, 193 [CEFCR] = 0x0740, 194 [FRECR] = 0x0748, 195 [TSFRCR] = 0x0750, 196 [TLFRCR] = 0x0758, 197 [RFCR] = 0x0760, 198 [MAFCR] = 0x0778, 199 200 [ARSTR] = 0x0000, 201 [TSU_CTRST] = 0x0004, 202 [TSU_VTAG0] = 0x0058, 203 [TSU_ADSBSY] = 0x0060, 204 [TSU_TEN] = 0x0064, 205 [TSU_ADRH0] = 0x0100, 206 207 [TXNLCR0] = 0x0080, 208 [TXALCR0] = 0x0084, 209 [RXNLCR0] = 0x0088, 210 [RXALCR0] = 0x008C, 211 }; 212 213 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 214 SH_ETH_OFFSET_DEFAULTS, 215 216 [ECMR] = 0x0300, 217 [RFLR] = 0x0308, 218 [ECSR] = 0x0310, 219 [ECSIPR] = 0x0318, 220 [PIR] = 0x0320, 221 [PSR] = 0x0328, 222 [RDMLR] = 0x0340, 223 [IPGR] = 0x0350, 224 [APR] = 0x0354, 225 [MPR] = 0x0358, 226 [RFCF] = 0x0360, 227 [TPAUSER] = 0x0364, 228 [TPAUSECR] = 0x0368, 229 [MAHR] = 0x03c0, 230 [MALR] = 0x03c8, 231 [TROCR] = 0x03d0, 232 [CDCR] = 0x03d4, 233 [LCCR] = 0x03d8, 234 [CNDCR] = 0x03dc, 235 [CEFCR] = 0x03e4, 236 [FRECR] = 0x03e8, 237 [TSFRCR] = 0x03ec, 238 [TLFRCR] = 0x03f0, 239 [RFCR] = 0x03f4, 240 [MAFCR] = 0x03f8, 241 242 [EDMR] = 0x0200, 243 [EDTRR] = 0x0208, 244 [EDRRR] = 0x0210, 245 [TDLAR] = 0x0218, 246 [RDLAR] = 0x0220, 247 [EESR] = 0x0228, 248 [EESIPR] = 0x0230, 249 [TRSCER] = 0x0238, 250 [RMFCR] = 0x0240, 251 [TFTR] = 0x0248, 252 [FDR] = 0x0250, 253 [RMCR] = 0x0258, 254 [TFUCR] = 0x0264, 255 [RFOCR] = 0x0268, 256 [RMIIMODE] = 0x026c, 257 [FCFTR] = 0x0270, 258 [TRIMD] = 0x027c, 259 }; 260 261 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 262 SH_ETH_OFFSET_DEFAULTS, 263 264 [ECMR] = 0x0100, 265 [RFLR] = 0x0108, 266 [ECSR] = 0x0110, 267 [ECSIPR] = 0x0118, 268 [PIR] = 0x0120, 269 [PSR] = 0x0128, 270 [RDMLR] = 0x0140, 271 [IPGR] = 0x0150, 272 [APR] = 0x0154, 273 [MPR] = 0x0158, 274 [TPAUSER] = 0x0164, 275 [RFCF] = 0x0160, 276 [TPAUSECR] = 0x0168, 277 [BCFRR] = 0x016c, 278 [MAHR] = 0x01c0, 279 [MALR] = 0x01c8, 280 [TROCR] = 0x01d0, 281 [CDCR] = 0x01d4, 282 [LCCR] = 0x01d8, 283 [CNDCR] = 0x01dc, 284 [CEFCR] = 0x01e4, 285 [FRECR] = 0x01e8, 286 [TSFRCR] = 0x01ec, 287 [TLFRCR] = 0x01f0, 288 [RFCR] = 0x01f4, 289 [MAFCR] = 0x01f8, 290 [RTRATE] = 0x01fc, 291 292 [EDMR] = 0x0000, 293 [EDTRR] = 0x0008, 294 [EDRRR] = 0x0010, 295 [TDLAR] = 0x0018, 296 [RDLAR] = 0x0020, 297 [EESR] = 0x0028, 298 [EESIPR] = 0x0030, 299 [TRSCER] = 0x0038, 300 [RMFCR] = 0x0040, 301 [TFTR] = 0x0048, 302 [FDR] = 0x0050, 303 [RMCR] = 0x0058, 304 [TFUCR] = 0x0064, 305 [RFOCR] = 0x0068, 306 [FCFTR] = 0x0070, 307 [RPADIR] = 0x0078, 308 [TRIMD] = 0x007c, 309 [RBWAR] = 0x00c8, 310 [RDFAR] = 0x00cc, 311 [TBRAR] = 0x00d4, 312 [TDFAR] = 0x00d8, 313 }; 314 315 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 316 SH_ETH_OFFSET_DEFAULTS, 317 318 [EDMR] = 0x0000, 319 [EDTRR] = 0x0004, 320 [EDRRR] = 0x0008, 321 [TDLAR] = 0x000c, 322 [RDLAR] = 0x0010, 323 [EESR] = 0x0014, 324 [EESIPR] = 0x0018, 325 [TRSCER] = 0x001c, 326 [RMFCR] = 0x0020, 327 [TFTR] = 0x0024, 328 [FDR] = 0x0028, 329 [RMCR] = 0x002c, 330 [EDOCR] = 0x0030, 331 [FCFTR] = 0x0034, 332 [RPADIR] = 0x0038, 333 [TRIMD] = 0x003c, 334 [RBWAR] = 0x0040, 335 [RDFAR] = 0x0044, 336 [TBRAR] = 0x004c, 337 [TDFAR] = 0x0050, 338 339 [ECMR] = 0x0160, 340 [ECSR] = 0x0164, 341 [ECSIPR] = 0x0168, 342 [PIR] = 0x016c, 343 [MAHR] = 0x0170, 344 [MALR] = 0x0174, 345 [RFLR] = 0x0178, 346 [PSR] = 0x017c, 347 [TROCR] = 0x0180, 348 [CDCR] = 0x0184, 349 [LCCR] = 0x0188, 350 [CNDCR] = 0x018c, 351 [CEFCR] = 0x0194, 352 [FRECR] = 0x0198, 353 [TSFRCR] = 0x019c, 354 [TLFRCR] = 0x01a0, 355 [RFCR] = 0x01a4, 356 [MAFCR] = 0x01a8, 357 [IPGR] = 0x01b4, 358 [APR] = 0x01b8, 359 [MPR] = 0x01bc, 360 [TPAUSER] = 0x01c4, 361 [BCFR] = 0x01cc, 362 363 [ARSTR] = 0x0000, 364 [TSU_CTRST] = 0x0004, 365 [TSU_FWEN0] = 0x0010, 366 [TSU_FWEN1] = 0x0014, 367 [TSU_FCM] = 0x0018, 368 [TSU_BSYSL0] = 0x0020, 369 [TSU_BSYSL1] = 0x0024, 370 [TSU_PRISL0] = 0x0028, 371 [TSU_PRISL1] = 0x002c, 372 [TSU_FWSL0] = 0x0030, 373 [TSU_FWSL1] = 0x0034, 374 [TSU_FWSLC] = 0x0038, 375 [TSU_QTAGM0] = 0x0040, 376 [TSU_QTAGM1] = 0x0044, 377 [TSU_ADQT0] = 0x0048, 378 [TSU_ADQT1] = 0x004c, 379 [TSU_FWSR] = 0x0050, 380 [TSU_FWINMK] = 0x0054, 381 [TSU_ADSBSY] = 0x0060, 382 [TSU_TEN] = 0x0064, 383 [TSU_POST1] = 0x0070, 384 [TSU_POST2] = 0x0074, 385 [TSU_POST3] = 0x0078, 386 [TSU_POST4] = 0x007c, 387 388 [TXNLCR0] = 0x0080, 389 [TXALCR0] = 0x0084, 390 [RXNLCR0] = 0x0088, 391 [RXALCR0] = 0x008c, 392 [FWNLCR0] = 0x0090, 393 [FWALCR0] = 0x0094, 394 [TXNLCR1] = 0x00a0, 395 [TXALCR1] = 0x00a0, 396 [RXNLCR1] = 0x00a8, 397 [RXALCR1] = 0x00ac, 398 [FWNLCR1] = 0x00b0, 399 [FWALCR1] = 0x00b4, 400 401 [TSU_ADRH0] = 0x0100, 402 }; 403 404 static void sh_eth_rcv_snd_disable(struct net_device *ndev); 405 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); 406 407 static bool sh_eth_is_gether(struct sh_eth_private *mdp) 408 { 409 return mdp->reg_offset == sh_eth_offset_gigabit; 410 } 411 412 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp) 413 { 414 return mdp->reg_offset == sh_eth_offset_fast_rz; 415 } 416 417 static void sh_eth_select_mii(struct net_device *ndev) 418 { 419 u32 value = 0x0; 420 struct sh_eth_private *mdp = netdev_priv(ndev); 421 422 switch (mdp->phy_interface) { 423 case PHY_INTERFACE_MODE_GMII: 424 value = 0x2; 425 break; 426 case PHY_INTERFACE_MODE_MII: 427 value = 0x1; 428 break; 429 case PHY_INTERFACE_MODE_RMII: 430 value = 0x0; 431 break; 432 default: 433 netdev_warn(ndev, 434 "PHY interface mode was not setup. Set to MII.\n"); 435 value = 0x1; 436 break; 437 } 438 439 sh_eth_write(ndev, value, RMII_MII); 440 } 441 442 static void sh_eth_set_duplex(struct net_device *ndev) 443 { 444 struct sh_eth_private *mdp = netdev_priv(ndev); 445 446 if (mdp->duplex) /* Full */ 447 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 448 else /* Half */ 449 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 450 } 451 452 /* There is CPU dependent code */ 453 static void sh_eth_set_rate_r8a777x(struct net_device *ndev) 454 { 455 struct sh_eth_private *mdp = netdev_priv(ndev); 456 457 switch (mdp->speed) { 458 case 10: /* 10BASE */ 459 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR); 460 break; 461 case 100:/* 100BASE */ 462 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR); 463 break; 464 default: 465 break; 466 } 467 } 468 469 /* R8A7778/9 */ 470 static struct sh_eth_cpu_data r8a777x_data = { 471 .set_duplex = sh_eth_set_duplex, 472 .set_rate = sh_eth_set_rate_r8a777x, 473 474 .register_type = SH_ETH_REG_FAST_RCAR, 475 476 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 477 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 478 .eesipr_value = 0x01ff009f, 479 480 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 481 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 482 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 483 EESR_ECI, 484 .fdr_value = 0x00000f0f, 485 486 .apr = 1, 487 .mpr = 1, 488 .tpauser = 1, 489 .hw_swap = 1, 490 }; 491 492 /* R8A7790/1 */ 493 static struct sh_eth_cpu_data r8a779x_data = { 494 .set_duplex = sh_eth_set_duplex, 495 .set_rate = sh_eth_set_rate_r8a777x, 496 497 .register_type = SH_ETH_REG_FAST_RCAR, 498 499 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 500 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 501 .eesipr_value = 0x01ff009f, 502 503 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 504 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 505 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 506 EESR_ECI, 507 .fdr_value = 0x00000f0f, 508 509 .trscer_err_mask = DESC_I_RINT8, 510 511 .apr = 1, 512 .mpr = 1, 513 .tpauser = 1, 514 .hw_swap = 1, 515 .rmiimode = 1, 516 }; 517 518 static void sh_eth_set_rate_sh7724(struct net_device *ndev) 519 { 520 struct sh_eth_private *mdp = netdev_priv(ndev); 521 522 switch (mdp->speed) { 523 case 10: /* 10BASE */ 524 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR); 525 break; 526 case 100:/* 100BASE */ 527 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR); 528 break; 529 default: 530 break; 531 } 532 } 533 534 /* SH7724 */ 535 static struct sh_eth_cpu_data sh7724_data = { 536 .set_duplex = sh_eth_set_duplex, 537 .set_rate = sh_eth_set_rate_sh7724, 538 539 .register_type = SH_ETH_REG_FAST_SH4, 540 541 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 542 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 543 .eesipr_value = 0x01ff009f, 544 545 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 546 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 547 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 548 EESR_ECI, 549 550 .apr = 1, 551 .mpr = 1, 552 .tpauser = 1, 553 .hw_swap = 1, 554 .rpadir = 1, 555 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 556 }; 557 558 static void sh_eth_set_rate_sh7757(struct net_device *ndev) 559 { 560 struct sh_eth_private *mdp = netdev_priv(ndev); 561 562 switch (mdp->speed) { 563 case 10: /* 10BASE */ 564 sh_eth_write(ndev, 0, RTRATE); 565 break; 566 case 100:/* 100BASE */ 567 sh_eth_write(ndev, 1, RTRATE); 568 break; 569 default: 570 break; 571 } 572 } 573 574 /* SH7757 */ 575 static struct sh_eth_cpu_data sh7757_data = { 576 .set_duplex = sh_eth_set_duplex, 577 .set_rate = sh_eth_set_rate_sh7757, 578 579 .register_type = SH_ETH_REG_FAST_SH4, 580 581 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 582 583 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 584 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 585 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 586 EESR_ECI, 587 588 .irq_flags = IRQF_SHARED, 589 .apr = 1, 590 .mpr = 1, 591 .tpauser = 1, 592 .hw_swap = 1, 593 .no_ade = 1, 594 .rpadir = 1, 595 .rpadir_value = 2 << 16, 596 .rtrate = 1, 597 }; 598 599 #define SH_GIGA_ETH_BASE 0xfee00000UL 600 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 601 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 602 static void sh_eth_chip_reset_giga(struct net_device *ndev) 603 { 604 int i; 605 u32 mahr[2], malr[2]; 606 607 /* save MAHR and MALR */ 608 for (i = 0; i < 2; i++) { 609 malr[i] = ioread32((void *)GIGA_MALR(i)); 610 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 611 } 612 613 /* reset device */ 614 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800)); 615 mdelay(1); 616 617 /* restore MAHR and MALR */ 618 for (i = 0; i < 2; i++) { 619 iowrite32(malr[i], (void *)GIGA_MALR(i)); 620 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 621 } 622 } 623 624 static void sh_eth_set_rate_giga(struct net_device *ndev) 625 { 626 struct sh_eth_private *mdp = netdev_priv(ndev); 627 628 switch (mdp->speed) { 629 case 10: /* 10BASE */ 630 sh_eth_write(ndev, 0x00000000, GECMR); 631 break; 632 case 100:/* 100BASE */ 633 sh_eth_write(ndev, 0x00000010, GECMR); 634 break; 635 case 1000: /* 1000BASE */ 636 sh_eth_write(ndev, 0x00000020, GECMR); 637 break; 638 default: 639 break; 640 } 641 } 642 643 /* SH7757(GETHERC) */ 644 static struct sh_eth_cpu_data sh7757_data_giga = { 645 .chip_reset = sh_eth_chip_reset_giga, 646 .set_duplex = sh_eth_set_duplex, 647 .set_rate = sh_eth_set_rate_giga, 648 649 .register_type = SH_ETH_REG_GIGABIT, 650 651 .ecsr_value = ECSR_ICD | ECSR_MPD, 652 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 653 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 654 655 .tx_check = EESR_TC1 | EESR_FTC, 656 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 657 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 658 EESR_TDE | EESR_ECI, 659 .fdr_value = 0x0000072f, 660 661 .irq_flags = IRQF_SHARED, 662 .apr = 1, 663 .mpr = 1, 664 .tpauser = 1, 665 .bculr = 1, 666 .hw_swap = 1, 667 .rpadir = 1, 668 .rpadir_value = 2 << 16, 669 .no_trimd = 1, 670 .no_ade = 1, 671 .tsu = 1, 672 }; 673 674 static void sh_eth_chip_reset(struct net_device *ndev) 675 { 676 struct sh_eth_private *mdp = netdev_priv(ndev); 677 678 /* reset device */ 679 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 680 mdelay(1); 681 } 682 683 static void sh_eth_set_rate_gether(struct net_device *ndev) 684 { 685 struct sh_eth_private *mdp = netdev_priv(ndev); 686 687 switch (mdp->speed) { 688 case 10: /* 10BASE */ 689 sh_eth_write(ndev, GECMR_10, GECMR); 690 break; 691 case 100:/* 100BASE */ 692 sh_eth_write(ndev, GECMR_100, GECMR); 693 break; 694 case 1000: /* 1000BASE */ 695 sh_eth_write(ndev, GECMR_1000, GECMR); 696 break; 697 default: 698 break; 699 } 700 } 701 702 /* SH7734 */ 703 static struct sh_eth_cpu_data sh7734_data = { 704 .chip_reset = sh_eth_chip_reset, 705 .set_duplex = sh_eth_set_duplex, 706 .set_rate = sh_eth_set_rate_gether, 707 708 .register_type = SH_ETH_REG_GIGABIT, 709 710 .ecsr_value = ECSR_ICD | ECSR_MPD, 711 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 712 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 713 714 .tx_check = EESR_TC1 | EESR_FTC, 715 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 716 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 717 EESR_TDE | EESR_ECI, 718 719 .apr = 1, 720 .mpr = 1, 721 .tpauser = 1, 722 .bculr = 1, 723 .hw_swap = 1, 724 .no_trimd = 1, 725 .no_ade = 1, 726 .tsu = 1, 727 .hw_crc = 1, 728 .select_mii = 1, 729 }; 730 731 /* SH7763 */ 732 static struct sh_eth_cpu_data sh7763_data = { 733 .chip_reset = sh_eth_chip_reset, 734 .set_duplex = sh_eth_set_duplex, 735 .set_rate = sh_eth_set_rate_gether, 736 737 .register_type = SH_ETH_REG_GIGABIT, 738 739 .ecsr_value = ECSR_ICD | ECSR_MPD, 740 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 741 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 742 743 .tx_check = EESR_TC1 | EESR_FTC, 744 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 745 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 746 EESR_ECI, 747 748 .apr = 1, 749 .mpr = 1, 750 .tpauser = 1, 751 .bculr = 1, 752 .hw_swap = 1, 753 .no_trimd = 1, 754 .no_ade = 1, 755 .tsu = 1, 756 .irq_flags = IRQF_SHARED, 757 }; 758 759 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 760 { 761 struct sh_eth_private *mdp = netdev_priv(ndev); 762 763 /* reset device */ 764 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 765 mdelay(1); 766 767 sh_eth_select_mii(ndev); 768 } 769 770 /* R8A7740 */ 771 static struct sh_eth_cpu_data r8a7740_data = { 772 .chip_reset = sh_eth_chip_reset_r8a7740, 773 .set_duplex = sh_eth_set_duplex, 774 .set_rate = sh_eth_set_rate_gether, 775 776 .register_type = SH_ETH_REG_GIGABIT, 777 778 .ecsr_value = ECSR_ICD | ECSR_MPD, 779 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 780 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 781 782 .tx_check = EESR_TC1 | EESR_FTC, 783 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 784 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 785 EESR_TDE | EESR_ECI, 786 .fdr_value = 0x0000070f, 787 788 .apr = 1, 789 .mpr = 1, 790 .tpauser = 1, 791 .bculr = 1, 792 .hw_swap = 1, 793 .rpadir = 1, 794 .rpadir_value = 2 << 16, 795 .no_trimd = 1, 796 .no_ade = 1, 797 .tsu = 1, 798 .select_mii = 1, 799 .shift_rd0 = 1, 800 }; 801 802 /* R7S72100 */ 803 static struct sh_eth_cpu_data r7s72100_data = { 804 .chip_reset = sh_eth_chip_reset, 805 .set_duplex = sh_eth_set_duplex, 806 807 .register_type = SH_ETH_REG_FAST_RZ, 808 809 .ecsr_value = ECSR_ICD, 810 .ecsipr_value = ECSIPR_ICDIP, 811 .eesipr_value = 0xff7f009f, 812 813 .tx_check = EESR_TC1 | EESR_FTC, 814 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 815 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 816 EESR_TDE | EESR_ECI, 817 .fdr_value = 0x0000070f, 818 819 .no_psr = 1, 820 .apr = 1, 821 .mpr = 1, 822 .tpauser = 1, 823 .hw_swap = 1, 824 .rpadir = 1, 825 .rpadir_value = 2 << 16, 826 .no_trimd = 1, 827 .no_ade = 1, 828 .hw_crc = 1, 829 .tsu = 1, 830 .shift_rd0 = 1, 831 }; 832 833 static struct sh_eth_cpu_data sh7619_data = { 834 .register_type = SH_ETH_REG_FAST_SH3_SH2, 835 836 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 837 838 .apr = 1, 839 .mpr = 1, 840 .tpauser = 1, 841 .hw_swap = 1, 842 }; 843 844 static struct sh_eth_cpu_data sh771x_data = { 845 .register_type = SH_ETH_REG_FAST_SH3_SH2, 846 847 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 848 .tsu = 1, 849 }; 850 851 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 852 { 853 if (!cd->ecsr_value) 854 cd->ecsr_value = DEFAULT_ECSR_INIT; 855 856 if (!cd->ecsipr_value) 857 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 858 859 if (!cd->fcftr_value) 860 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 861 DEFAULT_FIFO_F_D_RFD; 862 863 if (!cd->fdr_value) 864 cd->fdr_value = DEFAULT_FDR_INIT; 865 866 if (!cd->tx_check) 867 cd->tx_check = DEFAULT_TX_CHECK; 868 869 if (!cd->eesr_err_check) 870 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 871 872 if (!cd->trscer_err_mask) 873 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; 874 } 875 876 static int sh_eth_check_reset(struct net_device *ndev) 877 { 878 int ret = 0; 879 int cnt = 100; 880 881 while (cnt > 0) { 882 if (!(sh_eth_read(ndev, EDMR) & 0x3)) 883 break; 884 mdelay(1); 885 cnt--; 886 } 887 if (cnt <= 0) { 888 netdev_err(ndev, "Device reset failed\n"); 889 ret = -ETIMEDOUT; 890 } 891 return ret; 892 } 893 894 static int sh_eth_reset(struct net_device *ndev) 895 { 896 struct sh_eth_private *mdp = netdev_priv(ndev); 897 int ret = 0; 898 899 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) { 900 sh_eth_write(ndev, EDSR_ENALL, EDSR); 901 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, 902 EDMR); 903 904 ret = sh_eth_check_reset(ndev); 905 if (ret) 906 return ret; 907 908 /* Table Init */ 909 sh_eth_write(ndev, 0x0, TDLAR); 910 sh_eth_write(ndev, 0x0, TDFAR); 911 sh_eth_write(ndev, 0x0, TDFXR); 912 sh_eth_write(ndev, 0x0, TDFFR); 913 sh_eth_write(ndev, 0x0, RDLAR); 914 sh_eth_write(ndev, 0x0, RDFAR); 915 sh_eth_write(ndev, 0x0, RDFXR); 916 sh_eth_write(ndev, 0x0, RDFFR); 917 918 /* Reset HW CRC register */ 919 if (mdp->cd->hw_crc) 920 sh_eth_write(ndev, 0x0, CSMR); 921 922 /* Select MII mode */ 923 if (mdp->cd->select_mii) 924 sh_eth_select_mii(ndev); 925 } else { 926 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, 927 EDMR); 928 mdelay(3); 929 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, 930 EDMR); 931 } 932 933 return ret; 934 } 935 936 static void sh_eth_set_receive_align(struct sk_buff *skb) 937 { 938 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); 939 940 if (reserve) 941 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); 942 } 943 944 945 /* CPU <-> EDMAC endian convert */ 946 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x) 947 { 948 switch (mdp->edmac_endian) { 949 case EDMAC_LITTLE_ENDIAN: 950 return cpu_to_le32(x); 951 case EDMAC_BIG_ENDIAN: 952 return cpu_to_be32(x); 953 } 954 return x; 955 } 956 957 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x) 958 { 959 switch (mdp->edmac_endian) { 960 case EDMAC_LITTLE_ENDIAN: 961 return le32_to_cpu(x); 962 case EDMAC_BIG_ENDIAN: 963 return be32_to_cpu(x); 964 } 965 return x; 966 } 967 968 /* Program the hardware MAC address from dev->dev_addr. */ 969 static void update_mac_address(struct net_device *ndev) 970 { 971 sh_eth_write(ndev, 972 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 973 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 974 sh_eth_write(ndev, 975 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 976 } 977 978 /* Get MAC address from SuperH MAC address register 979 * 980 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 981 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 982 * When you want use this device, you must set MAC address in bootloader. 983 * 984 */ 985 static void read_mac_address(struct net_device *ndev, unsigned char *mac) 986 { 987 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 988 memcpy(ndev->dev_addr, mac, ETH_ALEN); 989 } else { 990 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24); 991 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF; 992 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF; 993 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF); 994 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF; 995 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF); 996 } 997 } 998 999 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) 1000 { 1001 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) 1002 return EDTRR_TRNS_GETHER; 1003 else 1004 return EDTRR_TRNS_ETHER; 1005 } 1006 1007 struct bb_info { 1008 void (*set_gate)(void *addr); 1009 struct mdiobb_ctrl ctrl; 1010 void *addr; 1011 u32 mmd_msk;/* MMD */ 1012 u32 mdo_msk; 1013 u32 mdi_msk; 1014 u32 mdc_msk; 1015 }; 1016 1017 /* PHY bit set */ 1018 static void bb_set(void *addr, u32 msk) 1019 { 1020 iowrite32(ioread32(addr) | msk, addr); 1021 } 1022 1023 /* PHY bit clear */ 1024 static void bb_clr(void *addr, u32 msk) 1025 { 1026 iowrite32((ioread32(addr) & ~msk), addr); 1027 } 1028 1029 /* PHY bit read */ 1030 static int bb_read(void *addr, u32 msk) 1031 { 1032 return (ioread32(addr) & msk) != 0; 1033 } 1034 1035 /* Data I/O pin control */ 1036 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1037 { 1038 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1039 1040 if (bitbang->set_gate) 1041 bitbang->set_gate(bitbang->addr); 1042 1043 if (bit) 1044 bb_set(bitbang->addr, bitbang->mmd_msk); 1045 else 1046 bb_clr(bitbang->addr, bitbang->mmd_msk); 1047 } 1048 1049 /* Set bit data*/ 1050 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1051 { 1052 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1053 1054 if (bitbang->set_gate) 1055 bitbang->set_gate(bitbang->addr); 1056 1057 if (bit) 1058 bb_set(bitbang->addr, bitbang->mdo_msk); 1059 else 1060 bb_clr(bitbang->addr, bitbang->mdo_msk); 1061 } 1062 1063 /* Get bit data*/ 1064 static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1065 { 1066 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1067 1068 if (bitbang->set_gate) 1069 bitbang->set_gate(bitbang->addr); 1070 1071 return bb_read(bitbang->addr, bitbang->mdi_msk); 1072 } 1073 1074 /* MDC pin control */ 1075 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1076 { 1077 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1078 1079 if (bitbang->set_gate) 1080 bitbang->set_gate(bitbang->addr); 1081 1082 if (bit) 1083 bb_set(bitbang->addr, bitbang->mdc_msk); 1084 else 1085 bb_clr(bitbang->addr, bitbang->mdc_msk); 1086 } 1087 1088 /* mdio bus control struct */ 1089 static struct mdiobb_ops bb_ops = { 1090 .owner = THIS_MODULE, 1091 .set_mdc = sh_mdc_ctrl, 1092 .set_mdio_dir = sh_mmd_ctrl, 1093 .set_mdio_data = sh_set_mdio, 1094 .get_mdio_data = sh_get_mdio, 1095 }; 1096 1097 /* free skb and descriptor buffer */ 1098 static void sh_eth_ring_free(struct net_device *ndev) 1099 { 1100 struct sh_eth_private *mdp = netdev_priv(ndev); 1101 int i; 1102 1103 /* Free Rx skb ringbuffer */ 1104 if (mdp->rx_skbuff) { 1105 for (i = 0; i < mdp->num_rx_ring; i++) 1106 dev_kfree_skb(mdp->rx_skbuff[i]); 1107 } 1108 kfree(mdp->rx_skbuff); 1109 mdp->rx_skbuff = NULL; 1110 1111 /* Free Tx skb ringbuffer */ 1112 if (mdp->tx_skbuff) { 1113 for (i = 0; i < mdp->num_tx_ring; i++) 1114 dev_kfree_skb(mdp->tx_skbuff[i]); 1115 } 1116 kfree(mdp->tx_skbuff); 1117 mdp->tx_skbuff = NULL; 1118 } 1119 1120 /* format skb and descriptor buffer */ 1121 static void sh_eth_ring_format(struct net_device *ndev) 1122 { 1123 struct sh_eth_private *mdp = netdev_priv(ndev); 1124 int i; 1125 struct sk_buff *skb; 1126 struct sh_eth_rxdesc *rxdesc = NULL; 1127 struct sh_eth_txdesc *txdesc = NULL; 1128 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1129 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1130 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1131 dma_addr_t dma_addr; 1132 1133 mdp->cur_rx = 0; 1134 mdp->cur_tx = 0; 1135 mdp->dirty_rx = 0; 1136 mdp->dirty_tx = 0; 1137 1138 memset(mdp->rx_ring, 0, rx_ringsize); 1139 1140 /* build Rx ring buffer */ 1141 for (i = 0; i < mdp->num_rx_ring; i++) { 1142 /* skb */ 1143 mdp->rx_skbuff[i] = NULL; 1144 skb = netdev_alloc_skb(ndev, skbuff_size); 1145 if (skb == NULL) 1146 break; 1147 sh_eth_set_receive_align(skb); 1148 1149 /* RX descriptor */ 1150 rxdesc = &mdp->rx_ring[i]; 1151 /* The size of the buffer is a multiple of 32 bytes. */ 1152 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32); 1153 dma_addr = dma_map_single(&ndev->dev, skb->data, 1154 rxdesc->buffer_length, 1155 DMA_FROM_DEVICE); 1156 if (dma_mapping_error(&ndev->dev, dma_addr)) { 1157 kfree_skb(skb); 1158 break; 1159 } 1160 mdp->rx_skbuff[i] = skb; 1161 rxdesc->addr = dma_addr; 1162 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1163 1164 /* Rx descriptor address set */ 1165 if (i == 0) { 1166 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1167 if (sh_eth_is_gether(mdp) || 1168 sh_eth_is_rz_fast_ether(mdp)) 1169 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1170 } 1171 } 1172 1173 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1174 1175 /* Mark the last entry as wrapping the ring. */ 1176 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL); 1177 1178 memset(mdp->tx_ring, 0, tx_ringsize); 1179 1180 /* build Tx ring buffer */ 1181 for (i = 0; i < mdp->num_tx_ring; i++) { 1182 mdp->tx_skbuff[i] = NULL; 1183 txdesc = &mdp->tx_ring[i]; 1184 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1185 txdesc->buffer_length = 0; 1186 if (i == 0) { 1187 /* Tx descriptor address set */ 1188 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1189 if (sh_eth_is_gether(mdp) || 1190 sh_eth_is_rz_fast_ether(mdp)) 1191 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1192 } 1193 } 1194 1195 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1196 } 1197 1198 /* Get skb and descriptor buffer */ 1199 static int sh_eth_ring_init(struct net_device *ndev) 1200 { 1201 struct sh_eth_private *mdp = netdev_priv(ndev); 1202 int rx_ringsize, tx_ringsize, ret = 0; 1203 1204 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1205 * card needs room to do 8 byte alignment, +2 so we can reserve 1206 * the first 2 bytes, and +16 gets room for the status word from the 1207 * card. 1208 */ 1209 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1210 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1211 if (mdp->cd->rpadir) 1212 mdp->rx_buf_sz += NET_IP_ALIGN; 1213 1214 /* Allocate RX and TX skb rings */ 1215 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring, 1216 sizeof(*mdp->rx_skbuff), GFP_KERNEL); 1217 if (!mdp->rx_skbuff) { 1218 ret = -ENOMEM; 1219 return ret; 1220 } 1221 1222 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring, 1223 sizeof(*mdp->tx_skbuff), GFP_KERNEL); 1224 if (!mdp->tx_skbuff) { 1225 ret = -ENOMEM; 1226 goto skb_ring_free; 1227 } 1228 1229 /* Allocate all Rx descriptors. */ 1230 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1231 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, 1232 GFP_KERNEL); 1233 if (!mdp->rx_ring) { 1234 ret = -ENOMEM; 1235 goto desc_ring_free; 1236 } 1237 1238 mdp->dirty_rx = 0; 1239 1240 /* Allocate all Tx descriptors. */ 1241 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1242 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, 1243 GFP_KERNEL); 1244 if (!mdp->tx_ring) { 1245 ret = -ENOMEM; 1246 goto desc_ring_free; 1247 } 1248 return ret; 1249 1250 desc_ring_free: 1251 /* free DMA buffer */ 1252 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma); 1253 1254 skb_ring_free: 1255 /* Free Rx and Tx skb ring buffer */ 1256 sh_eth_ring_free(ndev); 1257 mdp->tx_ring = NULL; 1258 mdp->rx_ring = NULL; 1259 1260 return ret; 1261 } 1262 1263 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp) 1264 { 1265 int ringsize; 1266 1267 if (mdp->rx_ring) { 1268 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1269 dma_free_coherent(NULL, ringsize, mdp->rx_ring, 1270 mdp->rx_desc_dma); 1271 mdp->rx_ring = NULL; 1272 } 1273 1274 if (mdp->tx_ring) { 1275 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1276 dma_free_coherent(NULL, ringsize, mdp->tx_ring, 1277 mdp->tx_desc_dma); 1278 mdp->tx_ring = NULL; 1279 } 1280 } 1281 1282 static int sh_eth_dev_init(struct net_device *ndev, bool start) 1283 { 1284 int ret = 0; 1285 struct sh_eth_private *mdp = netdev_priv(ndev); 1286 u32 val; 1287 1288 /* Soft Reset */ 1289 ret = sh_eth_reset(ndev); 1290 if (ret) 1291 return ret; 1292 1293 if (mdp->cd->rmiimode) 1294 sh_eth_write(ndev, 0x1, RMIIMODE); 1295 1296 /* Descriptor format */ 1297 sh_eth_ring_format(ndev); 1298 if (mdp->cd->rpadir) 1299 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); 1300 1301 /* all sh_eth int mask */ 1302 sh_eth_write(ndev, 0, EESIPR); 1303 1304 #if defined(__LITTLE_ENDIAN) 1305 if (mdp->cd->hw_swap) 1306 sh_eth_write(ndev, EDMR_EL, EDMR); 1307 else 1308 #endif 1309 sh_eth_write(ndev, 0, EDMR); 1310 1311 /* FIFO size set */ 1312 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1313 sh_eth_write(ndev, 0, TFTR); 1314 1315 /* Frame recv control (enable multiple-packets per rx irq) */ 1316 sh_eth_write(ndev, RMCR_RNC, RMCR); 1317 1318 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); 1319 1320 if (mdp->cd->bculr) 1321 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ 1322 1323 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1324 1325 if (!mdp->cd->no_trimd) 1326 sh_eth_write(ndev, 0, TRIMD); 1327 1328 /* Recv frame limit set register */ 1329 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1330 RFLR); 1331 1332 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR); 1333 if (start) { 1334 mdp->irq_enabled = true; 1335 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1336 } 1337 1338 /* PAUSE Prohibition */ 1339 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) | 1340 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; 1341 1342 sh_eth_write(ndev, val, ECMR); 1343 1344 if (mdp->cd->set_rate) 1345 mdp->cd->set_rate(ndev); 1346 1347 /* E-MAC Status Register clear */ 1348 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1349 1350 /* E-MAC Interrupt Enable register */ 1351 if (start) 1352 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1353 1354 /* Set MAC address */ 1355 update_mac_address(ndev); 1356 1357 /* mask reset */ 1358 if (mdp->cd->apr) 1359 sh_eth_write(ndev, APR_AP, APR); 1360 if (mdp->cd->mpr) 1361 sh_eth_write(ndev, MPR_MP, MPR); 1362 if (mdp->cd->tpauser) 1363 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1364 1365 if (start) { 1366 /* Setting the Rx mode will start the Rx process. */ 1367 sh_eth_write(ndev, EDRRR_R, EDRRR); 1368 1369 netif_start_queue(ndev); 1370 } 1371 1372 return ret; 1373 } 1374 1375 static void sh_eth_dev_exit(struct net_device *ndev) 1376 { 1377 struct sh_eth_private *mdp = netdev_priv(ndev); 1378 int i; 1379 1380 /* Deactivate all TX descriptors, so DMA should stop at next 1381 * packet boundary if it's currently running 1382 */ 1383 for (i = 0; i < mdp->num_tx_ring; i++) 1384 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT); 1385 1386 /* Disable TX FIFO egress to MAC */ 1387 sh_eth_rcv_snd_disable(ndev); 1388 1389 /* Stop RX DMA at next packet boundary */ 1390 sh_eth_write(ndev, 0, EDRRR); 1391 1392 /* Aside from TX DMA, we can't tell when the hardware is 1393 * really stopped, so we need to reset to make sure. 1394 * Before doing that, wait for long enough to *probably* 1395 * finish transmitting the last packet and poll stats. 1396 */ 1397 msleep(2); /* max frame time at 10 Mbps < 1250 us */ 1398 sh_eth_get_stats(ndev); 1399 sh_eth_reset(ndev); 1400 1401 /* Set MAC address again */ 1402 update_mac_address(ndev); 1403 } 1404 1405 /* free Tx skb function */ 1406 static int sh_eth_txfree(struct net_device *ndev) 1407 { 1408 struct sh_eth_private *mdp = netdev_priv(ndev); 1409 struct sh_eth_txdesc *txdesc; 1410 int free_num = 0; 1411 int entry = 0; 1412 1413 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1414 entry = mdp->dirty_tx % mdp->num_tx_ring; 1415 txdesc = &mdp->tx_ring[entry]; 1416 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) 1417 break; 1418 /* TACT bit must be checked before all the following reads */ 1419 rmb(); 1420 netif_info(mdp, tx_done, ndev, 1421 "tx entry %d status 0x%08x\n", 1422 entry, edmac_to_cpu(mdp, txdesc->status)); 1423 /* Free the original skb. */ 1424 if (mdp->tx_skbuff[entry]) { 1425 dma_unmap_single(&ndev->dev, txdesc->addr, 1426 txdesc->buffer_length, DMA_TO_DEVICE); 1427 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1428 mdp->tx_skbuff[entry] = NULL; 1429 free_num++; 1430 } 1431 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1432 if (entry >= mdp->num_tx_ring - 1) 1433 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1434 1435 ndev->stats.tx_packets++; 1436 ndev->stats.tx_bytes += txdesc->buffer_length; 1437 } 1438 return free_num; 1439 } 1440 1441 /* Packet receive function */ 1442 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1443 { 1444 struct sh_eth_private *mdp = netdev_priv(ndev); 1445 struct sh_eth_rxdesc *rxdesc; 1446 1447 int entry = mdp->cur_rx % mdp->num_rx_ring; 1448 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1449 int limit; 1450 struct sk_buff *skb; 1451 u16 pkt_len = 0; 1452 u32 desc_status; 1453 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1454 dma_addr_t dma_addr; 1455 1456 boguscnt = min(boguscnt, *quota); 1457 limit = boguscnt; 1458 rxdesc = &mdp->rx_ring[entry]; 1459 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { 1460 /* RACT bit must be checked before all the following reads */ 1461 rmb(); 1462 desc_status = edmac_to_cpu(mdp, rxdesc->status); 1463 pkt_len = rxdesc->frame_length; 1464 1465 if (--boguscnt < 0) 1466 break; 1467 1468 netif_info(mdp, rx_status, ndev, 1469 "rx entry %d status 0x%08x len %d\n", 1470 entry, desc_status, pkt_len); 1471 1472 if (!(desc_status & RDFEND)) 1473 ndev->stats.rx_length_errors++; 1474 1475 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1476 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1477 * bit 0. However, in case of the R8A7740 and R7S72100 1478 * the RFS bits are from bit 25 to bit 16. So, the 1479 * driver needs right shifting by 16. 1480 */ 1481 if (mdp->cd->shift_rd0) 1482 desc_status >>= 16; 1483 1484 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1485 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1486 ndev->stats.rx_errors++; 1487 if (desc_status & RD_RFS1) 1488 ndev->stats.rx_crc_errors++; 1489 if (desc_status & RD_RFS2) 1490 ndev->stats.rx_frame_errors++; 1491 if (desc_status & RD_RFS3) 1492 ndev->stats.rx_length_errors++; 1493 if (desc_status & RD_RFS4) 1494 ndev->stats.rx_length_errors++; 1495 if (desc_status & RD_RFS6) 1496 ndev->stats.rx_missed_errors++; 1497 if (desc_status & RD_RFS10) 1498 ndev->stats.rx_over_errors++; 1499 } else { 1500 if (!mdp->cd->hw_swap) 1501 sh_eth_soft_swap( 1502 phys_to_virt(ALIGN(rxdesc->addr, 4)), 1503 pkt_len + 2); 1504 skb = mdp->rx_skbuff[entry]; 1505 mdp->rx_skbuff[entry] = NULL; 1506 if (mdp->cd->rpadir) 1507 skb_reserve(skb, NET_IP_ALIGN); 1508 dma_unmap_single(&ndev->dev, rxdesc->addr, 1509 ALIGN(mdp->rx_buf_sz, 32), 1510 DMA_FROM_DEVICE); 1511 skb_put(skb, pkt_len); 1512 skb->protocol = eth_type_trans(skb, ndev); 1513 netif_receive_skb(skb); 1514 ndev->stats.rx_packets++; 1515 ndev->stats.rx_bytes += pkt_len; 1516 if (desc_status & RD_RFS8) 1517 ndev->stats.multicast++; 1518 } 1519 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1520 rxdesc = &mdp->rx_ring[entry]; 1521 } 1522 1523 /* Refill the Rx ring buffers. */ 1524 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1525 entry = mdp->dirty_rx % mdp->num_rx_ring; 1526 rxdesc = &mdp->rx_ring[entry]; 1527 /* The size of the buffer is 32 byte boundary. */ 1528 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32); 1529 1530 if (mdp->rx_skbuff[entry] == NULL) { 1531 skb = netdev_alloc_skb(ndev, skbuff_size); 1532 if (skb == NULL) 1533 break; /* Better luck next round. */ 1534 sh_eth_set_receive_align(skb); 1535 dma_addr = dma_map_single(&ndev->dev, skb->data, 1536 rxdesc->buffer_length, 1537 DMA_FROM_DEVICE); 1538 if (dma_mapping_error(&ndev->dev, dma_addr)) { 1539 kfree_skb(skb); 1540 break; 1541 } 1542 mdp->rx_skbuff[entry] = skb; 1543 1544 skb_checksum_none_assert(skb); 1545 rxdesc->addr = dma_addr; 1546 } 1547 wmb(); /* RACT bit must be set after all the above writes */ 1548 if (entry >= mdp->num_rx_ring - 1) 1549 rxdesc->status |= 1550 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); 1551 else 1552 rxdesc->status |= 1553 cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1554 } 1555 1556 /* Restart Rx engine if stopped. */ 1557 /* If we don't need to check status, don't. -KDU */ 1558 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1559 /* fix the values for the next receiving if RDE is set */ 1560 if (intr_status & EESR_RDE && 1561 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) { 1562 u32 count = (sh_eth_read(ndev, RDFAR) - 1563 sh_eth_read(ndev, RDLAR)) >> 4; 1564 1565 mdp->cur_rx = count; 1566 mdp->dirty_rx = count; 1567 } 1568 sh_eth_write(ndev, EDRRR_R, EDRRR); 1569 } 1570 1571 *quota -= limit - boguscnt - 1; 1572 1573 return *quota <= 0; 1574 } 1575 1576 static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1577 { 1578 /* disable tx and rx */ 1579 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & 1580 ~(ECMR_RE | ECMR_TE), ECMR); 1581 } 1582 1583 static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1584 { 1585 /* enable tx and rx */ 1586 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | 1587 (ECMR_RE | ECMR_TE), ECMR); 1588 } 1589 1590 /* error control function */ 1591 static void sh_eth_error(struct net_device *ndev, u32 intr_status) 1592 { 1593 struct sh_eth_private *mdp = netdev_priv(ndev); 1594 u32 felic_stat; 1595 u32 link_stat; 1596 u32 mask; 1597 1598 if (intr_status & EESR_ECI) { 1599 felic_stat = sh_eth_read(ndev, ECSR); 1600 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1601 if (felic_stat & ECSR_ICD) 1602 ndev->stats.tx_carrier_errors++; 1603 if (felic_stat & ECSR_LCHNG) { 1604 /* Link Changed */ 1605 if (mdp->cd->no_psr || mdp->no_ether_link) { 1606 goto ignore_link; 1607 } else { 1608 link_stat = (sh_eth_read(ndev, PSR)); 1609 if (mdp->ether_link_active_low) 1610 link_stat = ~link_stat; 1611 } 1612 if (!(link_stat & PHY_ST_LINK)) { 1613 sh_eth_rcv_snd_disable(ndev); 1614 } else { 1615 /* Link Up */ 1616 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) & 1617 ~DMAC_M_ECI, EESIPR); 1618 /* clear int */ 1619 sh_eth_write(ndev, sh_eth_read(ndev, ECSR), 1620 ECSR); 1621 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) | 1622 DMAC_M_ECI, EESIPR); 1623 /* enable tx and rx */ 1624 sh_eth_rcv_snd_enable(ndev); 1625 } 1626 } 1627 } 1628 1629 ignore_link: 1630 if (intr_status & EESR_TWB) { 1631 /* Unused write back interrupt */ 1632 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1633 ndev->stats.tx_aborted_errors++; 1634 netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); 1635 } 1636 } 1637 1638 if (intr_status & EESR_RABT) { 1639 /* Receive Abort int */ 1640 if (intr_status & EESR_RFRMER) { 1641 /* Receive Frame Overflow int */ 1642 ndev->stats.rx_frame_errors++; 1643 } 1644 } 1645 1646 if (intr_status & EESR_TDE) { 1647 /* Transmit Descriptor Empty int */ 1648 ndev->stats.tx_fifo_errors++; 1649 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); 1650 } 1651 1652 if (intr_status & EESR_TFE) { 1653 /* FIFO under flow */ 1654 ndev->stats.tx_fifo_errors++; 1655 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); 1656 } 1657 1658 if (intr_status & EESR_RDE) { 1659 /* Receive Descriptor Empty int */ 1660 ndev->stats.rx_over_errors++; 1661 } 1662 1663 if (intr_status & EESR_RFE) { 1664 /* Receive FIFO Overflow int */ 1665 ndev->stats.rx_fifo_errors++; 1666 } 1667 1668 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1669 /* Address Error */ 1670 ndev->stats.tx_fifo_errors++; 1671 netif_err(mdp, tx_err, ndev, "Address Error\n"); 1672 } 1673 1674 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1675 if (mdp->cd->no_ade) 1676 mask &= ~EESR_ADE; 1677 if (intr_status & mask) { 1678 /* Tx error */ 1679 u32 edtrr = sh_eth_read(ndev, EDTRR); 1680 1681 /* dmesg */ 1682 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1683 intr_status, mdp->cur_tx, mdp->dirty_tx, 1684 (u32)ndev->state, edtrr); 1685 /* dirty buffer free */ 1686 sh_eth_txfree(ndev); 1687 1688 /* SH7712 BUG */ 1689 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { 1690 /* tx dma start */ 1691 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1692 } 1693 /* wakeup */ 1694 netif_wake_queue(ndev); 1695 } 1696 } 1697 1698 static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1699 { 1700 struct net_device *ndev = netdev; 1701 struct sh_eth_private *mdp = netdev_priv(ndev); 1702 struct sh_eth_cpu_data *cd = mdp->cd; 1703 irqreturn_t ret = IRQ_NONE; 1704 u32 intr_status, intr_enable; 1705 1706 spin_lock(&mdp->lock); 1707 1708 /* Get interrupt status */ 1709 intr_status = sh_eth_read(ndev, EESR); 1710 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1711 * enabled since it's the one that comes thru regardless of the mask, 1712 * and we need to fully handle it in sh_eth_error() in order to quench 1713 * it as it doesn't get cleared by just writing 1 to the ECI bit... 1714 */ 1715 intr_enable = sh_eth_read(ndev, EESIPR); 1716 intr_status &= intr_enable | DMAC_M_ECI; 1717 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check)) 1718 ret = IRQ_HANDLED; 1719 else 1720 goto out; 1721 1722 if (!likely(mdp->irq_enabled)) { 1723 sh_eth_write(ndev, 0, EESIPR); 1724 goto out; 1725 } 1726 1727 if (intr_status & EESR_RX_CHECK) { 1728 if (napi_schedule_prep(&mdp->napi)) { 1729 /* Mask Rx interrupts */ 1730 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1731 EESIPR); 1732 __napi_schedule(&mdp->napi); 1733 } else { 1734 netdev_warn(ndev, 1735 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", 1736 intr_status, intr_enable); 1737 } 1738 } 1739 1740 /* Tx Check */ 1741 if (intr_status & cd->tx_check) { 1742 /* Clear Tx interrupts */ 1743 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1744 1745 sh_eth_txfree(ndev); 1746 netif_wake_queue(ndev); 1747 } 1748 1749 if (intr_status & cd->eesr_err_check) { 1750 /* Clear error interrupts */ 1751 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1752 1753 sh_eth_error(ndev, intr_status); 1754 } 1755 1756 out: 1757 spin_unlock(&mdp->lock); 1758 1759 return ret; 1760 } 1761 1762 static int sh_eth_poll(struct napi_struct *napi, int budget) 1763 { 1764 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1765 napi); 1766 struct net_device *ndev = napi->dev; 1767 int quota = budget; 1768 u32 intr_status; 1769 1770 for (;;) { 1771 intr_status = sh_eth_read(ndev, EESR); 1772 if (!(intr_status & EESR_RX_CHECK)) 1773 break; 1774 /* Clear Rx interrupts */ 1775 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1776 1777 if (sh_eth_rx(ndev, intr_status, "a)) 1778 goto out; 1779 } 1780 1781 napi_complete(napi); 1782 1783 /* Reenable Rx interrupts */ 1784 if (mdp->irq_enabled) 1785 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1786 out: 1787 return budget - quota; 1788 } 1789 1790 /* PHY state control function */ 1791 static void sh_eth_adjust_link(struct net_device *ndev) 1792 { 1793 struct sh_eth_private *mdp = netdev_priv(ndev); 1794 struct phy_device *phydev = mdp->phydev; 1795 int new_state = 0; 1796 1797 if (phydev->link) { 1798 if (phydev->duplex != mdp->duplex) { 1799 new_state = 1; 1800 mdp->duplex = phydev->duplex; 1801 if (mdp->cd->set_duplex) 1802 mdp->cd->set_duplex(ndev); 1803 } 1804 1805 if (phydev->speed != mdp->speed) { 1806 new_state = 1; 1807 mdp->speed = phydev->speed; 1808 if (mdp->cd->set_rate) 1809 mdp->cd->set_rate(ndev); 1810 } 1811 if (!mdp->link) { 1812 sh_eth_write(ndev, 1813 sh_eth_read(ndev, ECMR) & ~ECMR_TXF, 1814 ECMR); 1815 new_state = 1; 1816 mdp->link = phydev->link; 1817 if (mdp->cd->no_psr || mdp->no_ether_link) 1818 sh_eth_rcv_snd_enable(ndev); 1819 } 1820 } else if (mdp->link) { 1821 new_state = 1; 1822 mdp->link = 0; 1823 mdp->speed = 0; 1824 mdp->duplex = -1; 1825 if (mdp->cd->no_psr || mdp->no_ether_link) 1826 sh_eth_rcv_snd_disable(ndev); 1827 } 1828 1829 if (new_state && netif_msg_link(mdp)) 1830 phy_print_status(phydev); 1831 } 1832 1833 /* PHY init function */ 1834 static int sh_eth_phy_init(struct net_device *ndev) 1835 { 1836 struct device_node *np = ndev->dev.parent->of_node; 1837 struct sh_eth_private *mdp = netdev_priv(ndev); 1838 struct phy_device *phydev = NULL; 1839 1840 mdp->link = 0; 1841 mdp->speed = 0; 1842 mdp->duplex = -1; 1843 1844 /* Try connect to PHY */ 1845 if (np) { 1846 struct device_node *pn; 1847 1848 pn = of_parse_phandle(np, "phy-handle", 0); 1849 phydev = of_phy_connect(ndev, pn, 1850 sh_eth_adjust_link, 0, 1851 mdp->phy_interface); 1852 1853 if (!phydev) 1854 phydev = ERR_PTR(-ENOENT); 1855 } else { 1856 char phy_id[MII_BUS_ID_SIZE + 3]; 1857 1858 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1859 mdp->mii_bus->id, mdp->phy_id); 1860 1861 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1862 mdp->phy_interface); 1863 } 1864 1865 if (IS_ERR(phydev)) { 1866 netdev_err(ndev, "failed to connect PHY\n"); 1867 return PTR_ERR(phydev); 1868 } 1869 1870 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n", 1871 phydev->addr, phydev->irq, phydev->drv->name); 1872 1873 mdp->phydev = phydev; 1874 1875 return 0; 1876 } 1877 1878 /* PHY control start function */ 1879 static int sh_eth_phy_start(struct net_device *ndev) 1880 { 1881 struct sh_eth_private *mdp = netdev_priv(ndev); 1882 int ret; 1883 1884 ret = sh_eth_phy_init(ndev); 1885 if (ret) 1886 return ret; 1887 1888 phy_start(mdp->phydev); 1889 1890 return 0; 1891 } 1892 1893 static int sh_eth_get_settings(struct net_device *ndev, 1894 struct ethtool_cmd *ecmd) 1895 { 1896 struct sh_eth_private *mdp = netdev_priv(ndev); 1897 unsigned long flags; 1898 int ret; 1899 1900 if (!mdp->phydev) 1901 return -ENODEV; 1902 1903 spin_lock_irqsave(&mdp->lock, flags); 1904 ret = phy_ethtool_gset(mdp->phydev, ecmd); 1905 spin_unlock_irqrestore(&mdp->lock, flags); 1906 1907 return ret; 1908 } 1909 1910 static int sh_eth_set_settings(struct net_device *ndev, 1911 struct ethtool_cmd *ecmd) 1912 { 1913 struct sh_eth_private *mdp = netdev_priv(ndev); 1914 unsigned long flags; 1915 int ret; 1916 1917 if (!mdp->phydev) 1918 return -ENODEV; 1919 1920 spin_lock_irqsave(&mdp->lock, flags); 1921 1922 /* disable tx and rx */ 1923 sh_eth_rcv_snd_disable(ndev); 1924 1925 ret = phy_ethtool_sset(mdp->phydev, ecmd); 1926 if (ret) 1927 goto error_exit; 1928 1929 if (ecmd->duplex == DUPLEX_FULL) 1930 mdp->duplex = 1; 1931 else 1932 mdp->duplex = 0; 1933 1934 if (mdp->cd->set_duplex) 1935 mdp->cd->set_duplex(ndev); 1936 1937 error_exit: 1938 mdelay(1); 1939 1940 /* enable tx and rx */ 1941 sh_eth_rcv_snd_enable(ndev); 1942 1943 spin_unlock_irqrestore(&mdp->lock, flags); 1944 1945 return ret; 1946 } 1947 1948 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the 1949 * version must be bumped as well. Just adding registers up to that 1950 * limit is fine, as long as the existing register indices don't 1951 * change. 1952 */ 1953 #define SH_ETH_REG_DUMP_VERSION 1 1954 #define SH_ETH_REG_DUMP_MAX_REGS 256 1955 1956 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 1957 { 1958 struct sh_eth_private *mdp = netdev_priv(ndev); 1959 struct sh_eth_cpu_data *cd = mdp->cd; 1960 u32 *valid_map; 1961 size_t len; 1962 1963 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); 1964 1965 /* Dump starts with a bitmap that tells ethtool which 1966 * registers are defined for this chip. 1967 */ 1968 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); 1969 if (buf) { 1970 valid_map = buf; 1971 buf += len; 1972 } else { 1973 valid_map = NULL; 1974 } 1975 1976 /* Add a register to the dump, if it has a defined offset. 1977 * This automatically skips most undefined registers, but for 1978 * some it is also necessary to check a capability flag in 1979 * struct sh_eth_cpu_data. 1980 */ 1981 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) 1982 #define add_reg_from(reg, read_expr) do { \ 1983 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ 1984 if (buf) { \ 1985 mark_reg_valid(reg); \ 1986 *buf++ = read_expr; \ 1987 } \ 1988 ++len; \ 1989 } \ 1990 } while (0) 1991 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) 1992 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) 1993 1994 add_reg(EDSR); 1995 add_reg(EDMR); 1996 add_reg(EDTRR); 1997 add_reg(EDRRR); 1998 add_reg(EESR); 1999 add_reg(EESIPR); 2000 add_reg(TDLAR); 2001 add_reg(TDFAR); 2002 add_reg(TDFXR); 2003 add_reg(TDFFR); 2004 add_reg(RDLAR); 2005 add_reg(RDFAR); 2006 add_reg(RDFXR); 2007 add_reg(RDFFR); 2008 add_reg(TRSCER); 2009 add_reg(RMFCR); 2010 add_reg(TFTR); 2011 add_reg(FDR); 2012 add_reg(RMCR); 2013 add_reg(TFUCR); 2014 add_reg(RFOCR); 2015 if (cd->rmiimode) 2016 add_reg(RMIIMODE); 2017 add_reg(FCFTR); 2018 if (cd->rpadir) 2019 add_reg(RPADIR); 2020 if (!cd->no_trimd) 2021 add_reg(TRIMD); 2022 add_reg(ECMR); 2023 add_reg(ECSR); 2024 add_reg(ECSIPR); 2025 add_reg(PIR); 2026 if (!cd->no_psr) 2027 add_reg(PSR); 2028 add_reg(RDMLR); 2029 add_reg(RFLR); 2030 add_reg(IPGR); 2031 if (cd->apr) 2032 add_reg(APR); 2033 if (cd->mpr) 2034 add_reg(MPR); 2035 add_reg(RFCR); 2036 add_reg(RFCF); 2037 if (cd->tpauser) 2038 add_reg(TPAUSER); 2039 add_reg(TPAUSECR); 2040 add_reg(GECMR); 2041 if (cd->bculr) 2042 add_reg(BCULR); 2043 add_reg(MAHR); 2044 add_reg(MALR); 2045 add_reg(TROCR); 2046 add_reg(CDCR); 2047 add_reg(LCCR); 2048 add_reg(CNDCR); 2049 add_reg(CEFCR); 2050 add_reg(FRECR); 2051 add_reg(TSFRCR); 2052 add_reg(TLFRCR); 2053 add_reg(CERCR); 2054 add_reg(CEECR); 2055 add_reg(MAFCR); 2056 if (cd->rtrate) 2057 add_reg(RTRATE); 2058 if (cd->hw_crc) 2059 add_reg(CSMR); 2060 if (cd->select_mii) 2061 add_reg(RMII_MII); 2062 add_reg(ARSTR); 2063 if (cd->tsu) { 2064 add_tsu_reg(TSU_CTRST); 2065 add_tsu_reg(TSU_FWEN0); 2066 add_tsu_reg(TSU_FWEN1); 2067 add_tsu_reg(TSU_FCM); 2068 add_tsu_reg(TSU_BSYSL0); 2069 add_tsu_reg(TSU_BSYSL1); 2070 add_tsu_reg(TSU_PRISL0); 2071 add_tsu_reg(TSU_PRISL1); 2072 add_tsu_reg(TSU_FWSL0); 2073 add_tsu_reg(TSU_FWSL1); 2074 add_tsu_reg(TSU_FWSLC); 2075 add_tsu_reg(TSU_QTAG0); 2076 add_tsu_reg(TSU_QTAG1); 2077 add_tsu_reg(TSU_QTAGM0); 2078 add_tsu_reg(TSU_QTAGM1); 2079 add_tsu_reg(TSU_FWSR); 2080 add_tsu_reg(TSU_FWINMK); 2081 add_tsu_reg(TSU_ADQT0); 2082 add_tsu_reg(TSU_ADQT1); 2083 add_tsu_reg(TSU_VTAG0); 2084 add_tsu_reg(TSU_VTAG1); 2085 add_tsu_reg(TSU_ADSBSY); 2086 add_tsu_reg(TSU_TEN); 2087 add_tsu_reg(TSU_POST1); 2088 add_tsu_reg(TSU_POST2); 2089 add_tsu_reg(TSU_POST3); 2090 add_tsu_reg(TSU_POST4); 2091 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) { 2092 /* This is the start of a table, not just a single 2093 * register. 2094 */ 2095 if (buf) { 2096 unsigned int i; 2097 2098 mark_reg_valid(TSU_ADRH0); 2099 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) 2100 *buf++ = ioread32( 2101 mdp->tsu_addr + 2102 mdp->reg_offset[TSU_ADRH0] + 2103 i * 4); 2104 } 2105 len += SH_ETH_TSU_CAM_ENTRIES * 2; 2106 } 2107 } 2108 2109 #undef mark_reg_valid 2110 #undef add_reg_from 2111 #undef add_reg 2112 #undef add_tsu_reg 2113 2114 return len * 4; 2115 } 2116 2117 static int sh_eth_get_regs_len(struct net_device *ndev) 2118 { 2119 return __sh_eth_get_regs(ndev, NULL); 2120 } 2121 2122 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, 2123 void *buf) 2124 { 2125 struct sh_eth_private *mdp = netdev_priv(ndev); 2126 2127 regs->version = SH_ETH_REG_DUMP_VERSION; 2128 2129 pm_runtime_get_sync(&mdp->pdev->dev); 2130 __sh_eth_get_regs(ndev, buf); 2131 pm_runtime_put_sync(&mdp->pdev->dev); 2132 } 2133 2134 static int sh_eth_nway_reset(struct net_device *ndev) 2135 { 2136 struct sh_eth_private *mdp = netdev_priv(ndev); 2137 unsigned long flags; 2138 int ret; 2139 2140 if (!mdp->phydev) 2141 return -ENODEV; 2142 2143 spin_lock_irqsave(&mdp->lock, flags); 2144 ret = phy_start_aneg(mdp->phydev); 2145 spin_unlock_irqrestore(&mdp->lock, flags); 2146 2147 return ret; 2148 } 2149 2150 static u32 sh_eth_get_msglevel(struct net_device *ndev) 2151 { 2152 struct sh_eth_private *mdp = netdev_priv(ndev); 2153 return mdp->msg_enable; 2154 } 2155 2156 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 2157 { 2158 struct sh_eth_private *mdp = netdev_priv(ndev); 2159 mdp->msg_enable = value; 2160 } 2161 2162 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 2163 "rx_current", "tx_current", 2164 "rx_dirty", "tx_dirty", 2165 }; 2166 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 2167 2168 static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 2169 { 2170 switch (sset) { 2171 case ETH_SS_STATS: 2172 return SH_ETH_STATS_LEN; 2173 default: 2174 return -EOPNOTSUPP; 2175 } 2176 } 2177 2178 static void sh_eth_get_ethtool_stats(struct net_device *ndev, 2179 struct ethtool_stats *stats, u64 *data) 2180 { 2181 struct sh_eth_private *mdp = netdev_priv(ndev); 2182 int i = 0; 2183 2184 /* device-specific stats */ 2185 data[i++] = mdp->cur_rx; 2186 data[i++] = mdp->cur_tx; 2187 data[i++] = mdp->dirty_rx; 2188 data[i++] = mdp->dirty_tx; 2189 } 2190 2191 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 2192 { 2193 switch (stringset) { 2194 case ETH_SS_STATS: 2195 memcpy(data, *sh_eth_gstrings_stats, 2196 sizeof(sh_eth_gstrings_stats)); 2197 break; 2198 } 2199 } 2200 2201 static void sh_eth_get_ringparam(struct net_device *ndev, 2202 struct ethtool_ringparam *ring) 2203 { 2204 struct sh_eth_private *mdp = netdev_priv(ndev); 2205 2206 ring->rx_max_pending = RX_RING_MAX; 2207 ring->tx_max_pending = TX_RING_MAX; 2208 ring->rx_pending = mdp->num_rx_ring; 2209 ring->tx_pending = mdp->num_tx_ring; 2210 } 2211 2212 static int sh_eth_set_ringparam(struct net_device *ndev, 2213 struct ethtool_ringparam *ring) 2214 { 2215 struct sh_eth_private *mdp = netdev_priv(ndev); 2216 int ret; 2217 2218 if (ring->tx_pending > TX_RING_MAX || 2219 ring->rx_pending > RX_RING_MAX || 2220 ring->tx_pending < TX_RING_MIN || 2221 ring->rx_pending < RX_RING_MIN) 2222 return -EINVAL; 2223 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 2224 return -EINVAL; 2225 2226 if (netif_running(ndev)) { 2227 netif_device_detach(ndev); 2228 netif_tx_disable(ndev); 2229 2230 /* Serialise with the interrupt handler and NAPI, then 2231 * disable interrupts. We have to clear the 2232 * irq_enabled flag first to ensure that interrupts 2233 * won't be re-enabled. 2234 */ 2235 mdp->irq_enabled = false; 2236 synchronize_irq(ndev->irq); 2237 napi_synchronize(&mdp->napi); 2238 sh_eth_write(ndev, 0x0000, EESIPR); 2239 2240 sh_eth_dev_exit(ndev); 2241 2242 /* Free all the skbuffs in the Rx queue. */ 2243 sh_eth_ring_free(ndev); 2244 /* Free DMA buffer */ 2245 sh_eth_free_dma_buffer(mdp); 2246 } 2247 2248 /* Set new parameters */ 2249 mdp->num_rx_ring = ring->rx_pending; 2250 mdp->num_tx_ring = ring->tx_pending; 2251 2252 if (netif_running(ndev)) { 2253 ret = sh_eth_ring_init(ndev); 2254 if (ret < 0) { 2255 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", 2256 __func__); 2257 return ret; 2258 } 2259 ret = sh_eth_dev_init(ndev, false); 2260 if (ret < 0) { 2261 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", 2262 __func__); 2263 return ret; 2264 } 2265 2266 mdp->irq_enabled = true; 2267 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 2268 /* Setting the Rx mode will start the Rx process. */ 2269 sh_eth_write(ndev, EDRRR_R, EDRRR); 2270 netif_device_attach(ndev); 2271 } 2272 2273 return 0; 2274 } 2275 2276 static const struct ethtool_ops sh_eth_ethtool_ops = { 2277 .get_settings = sh_eth_get_settings, 2278 .set_settings = sh_eth_set_settings, 2279 .get_regs_len = sh_eth_get_regs_len, 2280 .get_regs = sh_eth_get_regs, 2281 .nway_reset = sh_eth_nway_reset, 2282 .get_msglevel = sh_eth_get_msglevel, 2283 .set_msglevel = sh_eth_set_msglevel, 2284 .get_link = ethtool_op_get_link, 2285 .get_strings = sh_eth_get_strings, 2286 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2287 .get_sset_count = sh_eth_get_sset_count, 2288 .get_ringparam = sh_eth_get_ringparam, 2289 .set_ringparam = sh_eth_set_ringparam, 2290 }; 2291 2292 /* network device open function */ 2293 static int sh_eth_open(struct net_device *ndev) 2294 { 2295 int ret = 0; 2296 struct sh_eth_private *mdp = netdev_priv(ndev); 2297 2298 pm_runtime_get_sync(&mdp->pdev->dev); 2299 2300 napi_enable(&mdp->napi); 2301 2302 ret = request_irq(ndev->irq, sh_eth_interrupt, 2303 mdp->cd->irq_flags, ndev->name, ndev); 2304 if (ret) { 2305 netdev_err(ndev, "Can not assign IRQ number\n"); 2306 goto out_napi_off; 2307 } 2308 2309 /* Descriptor set */ 2310 ret = sh_eth_ring_init(ndev); 2311 if (ret) 2312 goto out_free_irq; 2313 2314 /* device init */ 2315 ret = sh_eth_dev_init(ndev, true); 2316 if (ret) 2317 goto out_free_irq; 2318 2319 /* PHY control start*/ 2320 ret = sh_eth_phy_start(ndev); 2321 if (ret) 2322 goto out_free_irq; 2323 2324 mdp->is_opened = 1; 2325 2326 return ret; 2327 2328 out_free_irq: 2329 free_irq(ndev->irq, ndev); 2330 out_napi_off: 2331 napi_disable(&mdp->napi); 2332 pm_runtime_put_sync(&mdp->pdev->dev); 2333 return ret; 2334 } 2335 2336 /* Timeout function */ 2337 static void sh_eth_tx_timeout(struct net_device *ndev) 2338 { 2339 struct sh_eth_private *mdp = netdev_priv(ndev); 2340 struct sh_eth_rxdesc *rxdesc; 2341 int i; 2342 2343 netif_stop_queue(ndev); 2344 2345 netif_err(mdp, timer, ndev, 2346 "transmit timed out, status %8.8x, resetting...\n", 2347 sh_eth_read(ndev, EESR)); 2348 2349 /* tx_errors count up */ 2350 ndev->stats.tx_errors++; 2351 2352 /* Free all the skbuffs in the Rx queue. */ 2353 for (i = 0; i < mdp->num_rx_ring; i++) { 2354 rxdesc = &mdp->rx_ring[i]; 2355 rxdesc->status = 0; 2356 rxdesc->addr = 0xBADF00D0; 2357 dev_kfree_skb(mdp->rx_skbuff[i]); 2358 mdp->rx_skbuff[i] = NULL; 2359 } 2360 for (i = 0; i < mdp->num_tx_ring; i++) { 2361 dev_kfree_skb(mdp->tx_skbuff[i]); 2362 mdp->tx_skbuff[i] = NULL; 2363 } 2364 2365 /* device init */ 2366 sh_eth_dev_init(ndev, true); 2367 } 2368 2369 /* Packet transmit function */ 2370 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2371 { 2372 struct sh_eth_private *mdp = netdev_priv(ndev); 2373 struct sh_eth_txdesc *txdesc; 2374 u32 entry; 2375 unsigned long flags; 2376 2377 spin_lock_irqsave(&mdp->lock, flags); 2378 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2379 if (!sh_eth_txfree(ndev)) { 2380 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); 2381 netif_stop_queue(ndev); 2382 spin_unlock_irqrestore(&mdp->lock, flags); 2383 return NETDEV_TX_BUSY; 2384 } 2385 } 2386 spin_unlock_irqrestore(&mdp->lock, flags); 2387 2388 if (skb_put_padto(skb, ETH_ZLEN)) 2389 return NETDEV_TX_OK; 2390 2391 entry = mdp->cur_tx % mdp->num_tx_ring; 2392 mdp->tx_skbuff[entry] = skb; 2393 txdesc = &mdp->tx_ring[entry]; 2394 /* soft swap. */ 2395 if (!mdp->cd->hw_swap) 2396 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)), 2397 skb->len + 2); 2398 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len, 2399 DMA_TO_DEVICE); 2400 if (dma_mapping_error(&ndev->dev, txdesc->addr)) { 2401 kfree_skb(skb); 2402 return NETDEV_TX_OK; 2403 } 2404 txdesc->buffer_length = skb->len; 2405 2406 wmb(); /* TACT bit must be set after all the above writes */ 2407 if (entry >= mdp->num_tx_ring - 1) 2408 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); 2409 else 2410 txdesc->status |= cpu_to_edmac(mdp, TD_TACT); 2411 2412 mdp->cur_tx++; 2413 2414 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) 2415 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 2416 2417 return NETDEV_TX_OK; 2418 } 2419 2420 /* The statistics registers have write-clear behaviour, which means we 2421 * will lose any increment between the read and write. We mitigate 2422 * this by only clearing when we read a non-zero value, so we will 2423 * never falsely report a total of zero. 2424 */ 2425 static void 2426 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) 2427 { 2428 u32 delta = sh_eth_read(ndev, reg); 2429 2430 if (delta) { 2431 *stat += delta; 2432 sh_eth_write(ndev, 0, reg); 2433 } 2434 } 2435 2436 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2437 { 2438 struct sh_eth_private *mdp = netdev_priv(ndev); 2439 2440 if (sh_eth_is_rz_fast_ether(mdp)) 2441 return &ndev->stats; 2442 2443 if (!mdp->is_opened) 2444 return &ndev->stats; 2445 2446 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); 2447 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); 2448 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); 2449 2450 if (sh_eth_is_gether(mdp)) { 2451 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2452 CERCR); 2453 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2454 CEECR); 2455 } else { 2456 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2457 CNDCR); 2458 } 2459 2460 return &ndev->stats; 2461 } 2462 2463 /* device close function */ 2464 static int sh_eth_close(struct net_device *ndev) 2465 { 2466 struct sh_eth_private *mdp = netdev_priv(ndev); 2467 2468 netif_stop_queue(ndev); 2469 2470 /* Serialise with the interrupt handler and NAPI, then disable 2471 * interrupts. We have to clear the irq_enabled flag first to 2472 * ensure that interrupts won't be re-enabled. 2473 */ 2474 mdp->irq_enabled = false; 2475 synchronize_irq(ndev->irq); 2476 napi_disable(&mdp->napi); 2477 sh_eth_write(ndev, 0x0000, EESIPR); 2478 2479 sh_eth_dev_exit(ndev); 2480 2481 /* PHY Disconnect */ 2482 if (mdp->phydev) { 2483 phy_stop(mdp->phydev); 2484 phy_disconnect(mdp->phydev); 2485 mdp->phydev = NULL; 2486 } 2487 2488 free_irq(ndev->irq, ndev); 2489 2490 /* Free all the skbuffs in the Rx queue. */ 2491 sh_eth_ring_free(ndev); 2492 2493 /* free DMA buffer */ 2494 sh_eth_free_dma_buffer(mdp); 2495 2496 pm_runtime_put_sync(&mdp->pdev->dev); 2497 2498 mdp->is_opened = 0; 2499 2500 return 0; 2501 } 2502 2503 /* ioctl to device function */ 2504 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2505 { 2506 struct sh_eth_private *mdp = netdev_priv(ndev); 2507 struct phy_device *phydev = mdp->phydev; 2508 2509 if (!netif_running(ndev)) 2510 return -EINVAL; 2511 2512 if (!phydev) 2513 return -ENODEV; 2514 2515 return phy_mii_ioctl(phydev, rq, cmd); 2516 } 2517 2518 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2519 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, 2520 int entry) 2521 { 2522 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4); 2523 } 2524 2525 static u32 sh_eth_tsu_get_post_mask(int entry) 2526 { 2527 return 0x0f << (28 - ((entry % 8) * 4)); 2528 } 2529 2530 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2531 { 2532 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2533 } 2534 2535 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2536 int entry) 2537 { 2538 struct sh_eth_private *mdp = netdev_priv(ndev); 2539 u32 tmp; 2540 void *reg_offset; 2541 2542 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2543 tmp = ioread32(reg_offset); 2544 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); 2545 } 2546 2547 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2548 int entry) 2549 { 2550 struct sh_eth_private *mdp = netdev_priv(ndev); 2551 u32 post_mask, ref_mask, tmp; 2552 void *reg_offset; 2553 2554 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2555 post_mask = sh_eth_tsu_get_post_mask(entry); 2556 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2557 2558 tmp = ioread32(reg_offset); 2559 iowrite32(tmp & ~post_mask, reg_offset); 2560 2561 /* If other port enables, the function returns "true" */ 2562 return tmp & ref_mask; 2563 } 2564 2565 static int sh_eth_tsu_busy(struct net_device *ndev) 2566 { 2567 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2568 struct sh_eth_private *mdp = netdev_priv(ndev); 2569 2570 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2571 udelay(10); 2572 timeout--; 2573 if (timeout <= 0) { 2574 netdev_err(ndev, "%s: timeout\n", __func__); 2575 return -ETIMEDOUT; 2576 } 2577 } 2578 2579 return 0; 2580 } 2581 2582 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 2583 const u8 *addr) 2584 { 2585 u32 val; 2586 2587 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2588 iowrite32(val, reg); 2589 if (sh_eth_tsu_busy(ndev) < 0) 2590 return -EBUSY; 2591 2592 val = addr[4] << 8 | addr[5]; 2593 iowrite32(val, reg + 4); 2594 if (sh_eth_tsu_busy(ndev) < 0) 2595 return -EBUSY; 2596 2597 return 0; 2598 } 2599 2600 static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 2601 { 2602 u32 val; 2603 2604 val = ioread32(reg); 2605 addr[0] = (val >> 24) & 0xff; 2606 addr[1] = (val >> 16) & 0xff; 2607 addr[2] = (val >> 8) & 0xff; 2608 addr[3] = val & 0xff; 2609 val = ioread32(reg + 4); 2610 addr[4] = (val >> 8) & 0xff; 2611 addr[5] = val & 0xff; 2612 } 2613 2614 2615 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2616 { 2617 struct sh_eth_private *mdp = netdev_priv(ndev); 2618 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2619 int i; 2620 u8 c_addr[ETH_ALEN]; 2621 2622 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2623 sh_eth_tsu_read_entry(reg_offset, c_addr); 2624 if (ether_addr_equal(addr, c_addr)) 2625 return i; 2626 } 2627 2628 return -ENOENT; 2629 } 2630 2631 static int sh_eth_tsu_find_empty(struct net_device *ndev) 2632 { 2633 u8 blank[ETH_ALEN]; 2634 int entry; 2635 2636 memset(blank, 0, sizeof(blank)); 2637 entry = sh_eth_tsu_find_entry(ndev, blank); 2638 return (entry < 0) ? -ENOMEM : entry; 2639 } 2640 2641 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2642 int entry) 2643 { 2644 struct sh_eth_private *mdp = netdev_priv(ndev); 2645 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2646 int ret; 2647 u8 blank[ETH_ALEN]; 2648 2649 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2650 ~(1 << (31 - entry)), TSU_TEN); 2651 2652 memset(blank, 0, sizeof(blank)); 2653 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2654 if (ret < 0) 2655 return ret; 2656 return 0; 2657 } 2658 2659 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2660 { 2661 struct sh_eth_private *mdp = netdev_priv(ndev); 2662 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2663 int i, ret; 2664 2665 if (!mdp->cd->tsu) 2666 return 0; 2667 2668 i = sh_eth_tsu_find_entry(ndev, addr); 2669 if (i < 0) { 2670 /* No entry found, create one */ 2671 i = sh_eth_tsu_find_empty(ndev); 2672 if (i < 0) 2673 return -ENOMEM; 2674 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2675 if (ret < 0) 2676 return ret; 2677 2678 /* Enable the entry */ 2679 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2680 (1 << (31 - i)), TSU_TEN); 2681 } 2682 2683 /* Entry found or created, enable POST */ 2684 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2685 2686 return 0; 2687 } 2688 2689 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2690 { 2691 struct sh_eth_private *mdp = netdev_priv(ndev); 2692 int i, ret; 2693 2694 if (!mdp->cd->tsu) 2695 return 0; 2696 2697 i = sh_eth_tsu_find_entry(ndev, addr); 2698 if (i) { 2699 /* Entry found */ 2700 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2701 goto done; 2702 2703 /* Disable the entry if both ports was disabled */ 2704 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2705 if (ret < 0) 2706 return ret; 2707 } 2708 done: 2709 return 0; 2710 } 2711 2712 static int sh_eth_tsu_purge_all(struct net_device *ndev) 2713 { 2714 struct sh_eth_private *mdp = netdev_priv(ndev); 2715 int i, ret; 2716 2717 if (!mdp->cd->tsu) 2718 return 0; 2719 2720 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2721 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2722 continue; 2723 2724 /* Disable the entry if both ports was disabled */ 2725 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2726 if (ret < 0) 2727 return ret; 2728 } 2729 2730 return 0; 2731 } 2732 2733 static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2734 { 2735 struct sh_eth_private *mdp = netdev_priv(ndev); 2736 u8 addr[ETH_ALEN]; 2737 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2738 int i; 2739 2740 if (!mdp->cd->tsu) 2741 return; 2742 2743 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2744 sh_eth_tsu_read_entry(reg_offset, addr); 2745 if (is_multicast_ether_addr(addr)) 2746 sh_eth_tsu_del_entry(ndev, addr); 2747 } 2748 } 2749 2750 /* Update promiscuous flag and multicast filter */ 2751 static void sh_eth_set_rx_mode(struct net_device *ndev) 2752 { 2753 struct sh_eth_private *mdp = netdev_priv(ndev); 2754 u32 ecmr_bits; 2755 int mcast_all = 0; 2756 unsigned long flags; 2757 2758 spin_lock_irqsave(&mdp->lock, flags); 2759 /* Initial condition is MCT = 1, PRM = 0. 2760 * Depending on ndev->flags, set PRM or clear MCT 2761 */ 2762 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; 2763 if (mdp->cd->tsu) 2764 ecmr_bits |= ECMR_MCT; 2765 2766 if (!(ndev->flags & IFF_MULTICAST)) { 2767 sh_eth_tsu_purge_mcast(ndev); 2768 mcast_all = 1; 2769 } 2770 if (ndev->flags & IFF_ALLMULTI) { 2771 sh_eth_tsu_purge_mcast(ndev); 2772 ecmr_bits &= ~ECMR_MCT; 2773 mcast_all = 1; 2774 } 2775 2776 if (ndev->flags & IFF_PROMISC) { 2777 sh_eth_tsu_purge_all(ndev); 2778 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2779 } else if (mdp->cd->tsu) { 2780 struct netdev_hw_addr *ha; 2781 netdev_for_each_mc_addr(ha, ndev) { 2782 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2783 continue; 2784 2785 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2786 if (!mcast_all) { 2787 sh_eth_tsu_purge_mcast(ndev); 2788 ecmr_bits &= ~ECMR_MCT; 2789 mcast_all = 1; 2790 } 2791 } 2792 } 2793 } 2794 2795 /* update the ethernet mode */ 2796 sh_eth_write(ndev, ecmr_bits, ECMR); 2797 2798 spin_unlock_irqrestore(&mdp->lock, flags); 2799 } 2800 2801 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2802 { 2803 if (!mdp->port) 2804 return TSU_VTAG0; 2805 else 2806 return TSU_VTAG1; 2807 } 2808 2809 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2810 __be16 proto, u16 vid) 2811 { 2812 struct sh_eth_private *mdp = netdev_priv(ndev); 2813 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2814 2815 if (unlikely(!mdp->cd->tsu)) 2816 return -EPERM; 2817 2818 /* No filtering if vid = 0 */ 2819 if (!vid) 2820 return 0; 2821 2822 mdp->vlan_num_ids++; 2823 2824 /* The controller has one VLAN tag HW filter. So, if the filter is 2825 * already enabled, the driver disables it and the filte 2826 */ 2827 if (mdp->vlan_num_ids > 1) { 2828 /* disable VLAN filter */ 2829 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2830 return 0; 2831 } 2832 2833 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2834 vtag_reg_index); 2835 2836 return 0; 2837 } 2838 2839 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2840 __be16 proto, u16 vid) 2841 { 2842 struct sh_eth_private *mdp = netdev_priv(ndev); 2843 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2844 2845 if (unlikely(!mdp->cd->tsu)) 2846 return -EPERM; 2847 2848 /* No filtering if vid = 0 */ 2849 if (!vid) 2850 return 0; 2851 2852 mdp->vlan_num_ids--; 2853 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2854 2855 return 0; 2856 } 2857 2858 /* SuperH's TSU register init function */ 2859 static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2860 { 2861 if (sh_eth_is_rz_fast_ether(mdp)) { 2862 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2863 return; 2864 } 2865 2866 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2867 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2868 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2869 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2870 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2871 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2872 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2873 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2874 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 2875 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 2876 if (sh_eth_is_gether(mdp)) { 2877 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ 2878 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ 2879 } else { 2880 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 2881 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 2882 } 2883 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 2884 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 2885 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2886 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 2887 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 2888 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 2889 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 2890 } 2891 2892 /* MDIO bus release function */ 2893 static int sh_mdio_release(struct sh_eth_private *mdp) 2894 { 2895 /* unregister mdio bus */ 2896 mdiobus_unregister(mdp->mii_bus); 2897 2898 /* free bitbang info */ 2899 free_mdio_bitbang(mdp->mii_bus); 2900 2901 return 0; 2902 } 2903 2904 /* MDIO bus init function */ 2905 static int sh_mdio_init(struct sh_eth_private *mdp, 2906 struct sh_eth_plat_data *pd) 2907 { 2908 int ret, i; 2909 struct bb_info *bitbang; 2910 struct platform_device *pdev = mdp->pdev; 2911 struct device *dev = &mdp->pdev->dev; 2912 2913 /* create bit control struct for PHY */ 2914 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); 2915 if (!bitbang) 2916 return -ENOMEM; 2917 2918 /* bitbang init */ 2919 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 2920 bitbang->set_gate = pd->set_mdio_gate; 2921 bitbang->mdi_msk = PIR_MDI; 2922 bitbang->mdo_msk = PIR_MDO; 2923 bitbang->mmd_msk = PIR_MMD; 2924 bitbang->mdc_msk = PIR_MDC; 2925 bitbang->ctrl.ops = &bb_ops; 2926 2927 /* MII controller setting */ 2928 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 2929 if (!mdp->mii_bus) 2930 return -ENOMEM; 2931 2932 /* Hook up MII support for ethtool */ 2933 mdp->mii_bus->name = "sh_mii"; 2934 mdp->mii_bus->parent = dev; 2935 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2936 pdev->name, pdev->id); 2937 2938 /* PHY IRQ */ 2939 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int), 2940 GFP_KERNEL); 2941 if (!mdp->mii_bus->irq) { 2942 ret = -ENOMEM; 2943 goto out_free_bus; 2944 } 2945 2946 /* register MDIO bus */ 2947 if (dev->of_node) { 2948 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); 2949 } else { 2950 for (i = 0; i < PHY_MAX_ADDR; i++) 2951 mdp->mii_bus->irq[i] = PHY_POLL; 2952 if (pd->phy_irq > 0) 2953 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 2954 2955 ret = mdiobus_register(mdp->mii_bus); 2956 } 2957 2958 if (ret) 2959 goto out_free_bus; 2960 2961 return 0; 2962 2963 out_free_bus: 2964 free_mdio_bitbang(mdp->mii_bus); 2965 return ret; 2966 } 2967 2968 static const u16 *sh_eth_get_register_offset(int register_type) 2969 { 2970 const u16 *reg_offset = NULL; 2971 2972 switch (register_type) { 2973 case SH_ETH_REG_GIGABIT: 2974 reg_offset = sh_eth_offset_gigabit; 2975 break; 2976 case SH_ETH_REG_FAST_RZ: 2977 reg_offset = sh_eth_offset_fast_rz; 2978 break; 2979 case SH_ETH_REG_FAST_RCAR: 2980 reg_offset = sh_eth_offset_fast_rcar; 2981 break; 2982 case SH_ETH_REG_FAST_SH4: 2983 reg_offset = sh_eth_offset_fast_sh4; 2984 break; 2985 case SH_ETH_REG_FAST_SH3_SH2: 2986 reg_offset = sh_eth_offset_fast_sh3_sh2; 2987 break; 2988 default: 2989 break; 2990 } 2991 2992 return reg_offset; 2993 } 2994 2995 static const struct net_device_ops sh_eth_netdev_ops = { 2996 .ndo_open = sh_eth_open, 2997 .ndo_stop = sh_eth_close, 2998 .ndo_start_xmit = sh_eth_start_xmit, 2999 .ndo_get_stats = sh_eth_get_stats, 3000 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3001 .ndo_tx_timeout = sh_eth_tx_timeout, 3002 .ndo_do_ioctl = sh_eth_do_ioctl, 3003 .ndo_validate_addr = eth_validate_addr, 3004 .ndo_set_mac_address = eth_mac_addr, 3005 .ndo_change_mtu = eth_change_mtu, 3006 }; 3007 3008 static const struct net_device_ops sh_eth_netdev_ops_tsu = { 3009 .ndo_open = sh_eth_open, 3010 .ndo_stop = sh_eth_close, 3011 .ndo_start_xmit = sh_eth_start_xmit, 3012 .ndo_get_stats = sh_eth_get_stats, 3013 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3014 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 3015 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 3016 .ndo_tx_timeout = sh_eth_tx_timeout, 3017 .ndo_do_ioctl = sh_eth_do_ioctl, 3018 .ndo_validate_addr = eth_validate_addr, 3019 .ndo_set_mac_address = eth_mac_addr, 3020 .ndo_change_mtu = eth_change_mtu, 3021 }; 3022 3023 #ifdef CONFIG_OF 3024 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3025 { 3026 struct device_node *np = dev->of_node; 3027 struct sh_eth_plat_data *pdata; 3028 const char *mac_addr; 3029 3030 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3031 if (!pdata) 3032 return NULL; 3033 3034 pdata->phy_interface = of_get_phy_mode(np); 3035 3036 mac_addr = of_get_mac_address(np); 3037 if (mac_addr) 3038 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); 3039 3040 pdata->no_ether_link = 3041 of_property_read_bool(np, "renesas,no-ether-link"); 3042 pdata->ether_link_active_low = 3043 of_property_read_bool(np, "renesas,ether-link-active-low"); 3044 3045 return pdata; 3046 } 3047 3048 static const struct of_device_id sh_eth_match_table[] = { 3049 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 3050 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data }, 3051 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data }, 3052 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data }, 3053 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data }, 3054 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data }, 3055 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data }, 3056 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 3057 { } 3058 }; 3059 MODULE_DEVICE_TABLE(of, sh_eth_match_table); 3060 #else 3061 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3062 { 3063 return NULL; 3064 } 3065 #endif 3066 3067 static int sh_eth_drv_probe(struct platform_device *pdev) 3068 { 3069 int ret, devno = 0; 3070 struct resource *res; 3071 struct net_device *ndev = NULL; 3072 struct sh_eth_private *mdp = NULL; 3073 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 3074 const struct platform_device_id *id = platform_get_device_id(pdev); 3075 3076 /* get base addr */ 3077 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3078 3079 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 3080 if (!ndev) 3081 return -ENOMEM; 3082 3083 pm_runtime_enable(&pdev->dev); 3084 pm_runtime_get_sync(&pdev->dev); 3085 3086 devno = pdev->id; 3087 if (devno < 0) 3088 devno = 0; 3089 3090 ndev->dma = -1; 3091 ret = platform_get_irq(pdev, 0); 3092 if (ret < 0) 3093 goto out_release; 3094 ndev->irq = ret; 3095 3096 SET_NETDEV_DEV(ndev, &pdev->dev); 3097 3098 mdp = netdev_priv(ndev); 3099 mdp->num_tx_ring = TX_RING_SIZE; 3100 mdp->num_rx_ring = RX_RING_SIZE; 3101 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 3102 if (IS_ERR(mdp->addr)) { 3103 ret = PTR_ERR(mdp->addr); 3104 goto out_release; 3105 } 3106 3107 ndev->base_addr = res->start; 3108 3109 spin_lock_init(&mdp->lock); 3110 mdp->pdev = pdev; 3111 3112 if (pdev->dev.of_node) 3113 pd = sh_eth_parse_dt(&pdev->dev); 3114 if (!pd) { 3115 dev_err(&pdev->dev, "no platform data\n"); 3116 ret = -EINVAL; 3117 goto out_release; 3118 } 3119 3120 /* get PHY ID */ 3121 mdp->phy_id = pd->phy; 3122 mdp->phy_interface = pd->phy_interface; 3123 /* EDMAC endian */ 3124 mdp->edmac_endian = pd->edmac_endian; 3125 mdp->no_ether_link = pd->no_ether_link; 3126 mdp->ether_link_active_low = pd->ether_link_active_low; 3127 3128 /* set cpu data */ 3129 if (id) { 3130 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 3131 } else { 3132 const struct of_device_id *match; 3133 3134 match = of_match_device(of_match_ptr(sh_eth_match_table), 3135 &pdev->dev); 3136 mdp->cd = (struct sh_eth_cpu_data *)match->data; 3137 } 3138 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 3139 if (!mdp->reg_offset) { 3140 dev_err(&pdev->dev, "Unknown register type (%d)\n", 3141 mdp->cd->register_type); 3142 ret = -EINVAL; 3143 goto out_release; 3144 } 3145 sh_eth_set_default_cpu_data(mdp->cd); 3146 3147 /* set function */ 3148 if (mdp->cd->tsu) 3149 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 3150 else 3151 ndev->netdev_ops = &sh_eth_netdev_ops; 3152 ndev->ethtool_ops = &sh_eth_ethtool_ops; 3153 ndev->watchdog_timeo = TX_TIMEOUT; 3154 3155 /* debug message level */ 3156 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 3157 3158 /* read and set MAC address */ 3159 read_mac_address(ndev, pd->mac_addr); 3160 if (!is_valid_ether_addr(ndev->dev_addr)) { 3161 dev_warn(&pdev->dev, 3162 "no valid MAC address supplied, using a random one.\n"); 3163 eth_hw_addr_random(ndev); 3164 } 3165 3166 /* ioremap the TSU registers */ 3167 if (mdp->cd->tsu) { 3168 struct resource *rtsu; 3169 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3170 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu); 3171 if (IS_ERR(mdp->tsu_addr)) { 3172 ret = PTR_ERR(mdp->tsu_addr); 3173 goto out_release; 3174 } 3175 mdp->port = devno % 2; 3176 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 3177 } 3178 3179 /* initialize first or needed device */ 3180 if (!devno || pd->needs_init) { 3181 if (mdp->cd->chip_reset) 3182 mdp->cd->chip_reset(ndev); 3183 3184 if (mdp->cd->tsu) { 3185 /* TSU init (Init only)*/ 3186 sh_eth_tsu_init(mdp); 3187 } 3188 } 3189 3190 if (mdp->cd->rmiimode) 3191 sh_eth_write(ndev, 0x1, RMIIMODE); 3192 3193 /* MDIO bus init */ 3194 ret = sh_mdio_init(mdp, pd); 3195 if (ret) { 3196 dev_err(&ndev->dev, "failed to initialise MDIO\n"); 3197 goto out_release; 3198 } 3199 3200 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 3201 3202 /* network device register */ 3203 ret = register_netdev(ndev); 3204 if (ret) 3205 goto out_napi_del; 3206 3207 /* print device information */ 3208 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", 3209 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3210 3211 pm_runtime_put(&pdev->dev); 3212 platform_set_drvdata(pdev, ndev); 3213 3214 return ret; 3215 3216 out_napi_del: 3217 netif_napi_del(&mdp->napi); 3218 sh_mdio_release(mdp); 3219 3220 out_release: 3221 /* net_dev free */ 3222 if (ndev) 3223 free_netdev(ndev); 3224 3225 pm_runtime_put(&pdev->dev); 3226 pm_runtime_disable(&pdev->dev); 3227 return ret; 3228 } 3229 3230 static int sh_eth_drv_remove(struct platform_device *pdev) 3231 { 3232 struct net_device *ndev = platform_get_drvdata(pdev); 3233 struct sh_eth_private *mdp = netdev_priv(ndev); 3234 3235 unregister_netdev(ndev); 3236 netif_napi_del(&mdp->napi); 3237 sh_mdio_release(mdp); 3238 pm_runtime_disable(&pdev->dev); 3239 free_netdev(ndev); 3240 3241 return 0; 3242 } 3243 3244 #ifdef CONFIG_PM 3245 #ifdef CONFIG_PM_SLEEP 3246 static int sh_eth_suspend(struct device *dev) 3247 { 3248 struct net_device *ndev = dev_get_drvdata(dev); 3249 int ret = 0; 3250 3251 if (netif_running(ndev)) { 3252 netif_device_detach(ndev); 3253 ret = sh_eth_close(ndev); 3254 } 3255 3256 return ret; 3257 } 3258 3259 static int sh_eth_resume(struct device *dev) 3260 { 3261 struct net_device *ndev = dev_get_drvdata(dev); 3262 int ret = 0; 3263 3264 if (netif_running(ndev)) { 3265 ret = sh_eth_open(ndev); 3266 if (ret < 0) 3267 return ret; 3268 netif_device_attach(ndev); 3269 } 3270 3271 return ret; 3272 } 3273 #endif 3274 3275 static int sh_eth_runtime_nop(struct device *dev) 3276 { 3277 /* Runtime PM callback shared between ->runtime_suspend() 3278 * and ->runtime_resume(). Simply returns success. 3279 * 3280 * This driver re-initializes all registers after 3281 * pm_runtime_get_sync() anyway so there is no need 3282 * to save and restore registers here. 3283 */ 3284 return 0; 3285 } 3286 3287 static const struct dev_pm_ops sh_eth_dev_pm_ops = { 3288 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume) 3289 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL) 3290 }; 3291 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 3292 #else 3293 #define SH_ETH_PM_OPS NULL 3294 #endif 3295 3296 static struct platform_device_id sh_eth_id_table[] = { 3297 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 3298 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 3299 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 3300 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 3301 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 3302 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 3303 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 3304 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data }, 3305 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data }, 3306 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data }, 3307 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data }, 3308 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data }, 3309 { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data }, 3310 { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data }, 3311 { } 3312 }; 3313 MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 3314 3315 static struct platform_driver sh_eth_driver = { 3316 .probe = sh_eth_drv_probe, 3317 .remove = sh_eth_drv_remove, 3318 .id_table = sh_eth_id_table, 3319 .driver = { 3320 .name = CARDNAME, 3321 .pm = SH_ETH_PM_OPS, 3322 .of_match_table = of_match_ptr(sh_eth_match_table), 3323 }, 3324 }; 3325 3326 module_platform_driver(sh_eth_driver); 3327 3328 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3329 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3330 MODULE_LICENSE("GPL v2"); 3331